ABSTRACT

Multilevel dcdc converters making use of high frequency transformers are suitable for integration in solid-state solutions for applications in electric power distribution systems. This paper presents a simplified switching scheme for threelevel full-bridge dcdc converters that enables zero-voltage and zero current switching of all the main power devices. It describes the main operational modes and design equations of the converter as well as provides simulation and experimental results to demonstrate the feasibility of the proposed ideas.

The technique of zero voltage switching in modern power conversion is explored. Several ZVS topologies and applications, limitations of the ZVS technique, and a generalized design procedure are featured. Two design examples are presented: a 50 Watt DC/DC converter, and an off-line 300 Watt multiple output power supply. This topic concludes with a performance comparison of ZVS converters to their square wave counterparts, and a summary of typical applications.

TABLE OF CONTENTS
1. INTRODUCTION 2. OVERVIEW OF ZVZCS 2.1 ZERO VOLTAGE SWITCHING OVERVIEW 2.2 ZERO VOLTAGE SWITCHING VS CONVENTIONAL SQUARE WAVE 3. PROPOSED ZVZCS CONVERTER 3.1 POWER DIAGRAM 4. CONTROL CIRCUIT FOR PROPOSED SYSTEM 5. DRIVER CIRCUIT FOR THE PROPOSED SYSTEM 6. THEORITICAL BACKGROUND OF THE PROPOSED SYSTEM 6.1 CONVERTER OPERATIONAL MODES 6.2 DESIGN EQUATIONS 6.3 CONVERTER LOSSES 6.4 SOFT SWITCHING RANGE 7. EXPERIMENTAL RESULTS

8. ZVS DESIGN EQUATIONS AND ZVS DIFFERENCES 9. ZVS BENFITS 10. APPLICATIONS CONCLUSION LIST OF FIGURES REFERENCES

1. INTRODUCTION

Advances in resonant and quasi-resonant power conversion technology propose alternative solutions to a conflicting set of square wave conversion design goals; obtaining high efficiency operation at a high switching frequency from a high voltage source. Currently, the conventional approaches are by far, still in the production mainstream. However, an increasing challenge can be witnessed by the emerging resonant technologies, primarily due to their lossless switching merits. The intent of this presentation is to unravel the details of zero voltage switching via a comprehensive analysis of the timing intervals and relevant voltage and current waveforms. The concept of quasi-resonant, lossless switching is not new, most noticeably patented by one individual and publicized by another at various power conferences Numerous efforts focusing on zero current switching ensured converters . In theory, the on, off first perceived as the likely candidate for tomorrows generation of high frequency power transitions occur at a time in the resonant cycle

where the switch current is zero, facilitating zero current, hence zero power switching. And while true, two obvious concerns can impede the quest for high efficiency operation with high voltage inputs. By nature of the resonant tank and zero current switching limitation, the peak switch current is significantly higher than its square wave counterpart. In fact, the peak of the full load switch current is a minimum of twice that of its square wave kin. In its off state, the switch returns to a blocking a high voltage every cycle. When activated by the next drive pulse the MOSFET output capacitance (Goss) is discharged by the FET, contributing a significant power loss at high frequencies and high voltages. Instead, both of these losses are avoided by implementing a zero voltage switching technique. High-voltage high-power isolated dcdc converters have several potential uses in the electric utility industry, such as interfaces for high-power distributed generation, renewable resources, energy storage, dc interlinks, and solid state power substations . Traditionally, switching devices with high-voltage blocking capability, such as thyristors and gate turn-off thyristors (GTOs) are used since they are more compatible with voltage levels seen in utility applications. The main disadvantage of these devices is that they switch very slowly, and in the case of thyristors, an external circuit is required for turn-OFF. Faster switching devices such as MOSFETs and (low voltage) insulated-gate bipolar transistors (IGBTs) bring many advantages in terms of system size and dynamic response but are unable to withstand large voltages. In order to take advantage of these smaller faster devices, several multilevel topologies have been proposed in order to reduce the voltage seen by individual switching devices.

The main multilevel topologies diode clamped, flying capacitor, and cascade provide for reliable division of voltage across the switching devices. High efficiency is required for any high-voltage solid-state solution intended to replace fundamental-frequency transformers in utility applications since existing transformer technology can be as high as 99% efficient. Peak losses in switching converters occur during the switching instants, and these losses increase with increasing switching frequency. Many soft-switching topologies have been proposed to reduce these switching losses, with quasi-resonant phase-shifted zero-voltage switching (ZVS) and zero-voltage zero-current switching (ZVZCS) drawing particular interest since they do not cause added current or voltage stresses to the converter components. Of the two, ZVZCS is preferred due to the reduction of the circulating current and the wideload operation ability. Over time, researchers combined these soft-switching topologies with multilevel topologies to provide superior performance at high voltage. Diode-clamped multilevel converters are of interest since they have fewer capacitors than flying-capacitor converters and do not require multiple independent voltage sources as do cascade multilevel converter. ZVS and ZVZCS three-level (3L) half bridge (HB) converters have been proposed, but these converters face the disadvantage that they only apply half the dc-bus voltage to the primary of the transformer. Greater power transfer can be achieved with a full-bridge (FB) topology, but it is a challenge to establish a proper switching scheme to achieve soft-switching operation for all the main power devices. So far, this has been accomplished for ZVS 3L FBs and for ZVZCS three-phase 3L converters. This paper presents a simple control strategy that reduces control complexity, device voltage stresses and achieves soft switching for all main power devices for the

3L FB ZVZCS converter topology. In addition, this converter has reduced circulating currents, wider load operation compared to the ZVS 3L FB, and the control can be implemented with existing phase shifted pulse width-modulated (PWM) controllers.

2. OVERVIEW OF ZVZCS 2.1 ZERO VOLTAGE SWITCHING OVERVIEW

Zero voltage switching can best be defined as conventional square wave power conversion during the switchs on-time with resonant switching transitions. For the most part, it can be considered as square wave power utilizing a constant off-time control which varies the conversion frequency, or on-time to maintain regulation of the output voltage. For a given unit of time, this method is similar to fixed frequency conversion which uses an adjustable duty cycle. Regulation of the output voltage is accomplished by adjusting the effective duty cycle, performed by varying the conversion frequency. This changes the effective on-time in a ZVS design. The foundation of this conversion is simply the volt-second product equating of the input and output. It is virtually identical to that of square wave power conversion, and vastly.

2.2

ZERO

VOLTAGE

SWITCHING

VS

CONVENTIONAL

SQUARE WAVE

Unlike the energy transfer system of its electrical dual, the zero current switched converter. During the ZVS switch off-time, the L-C tank circuit resonates. This traverses the voltage across the switch from zero to its peak, and back down again to zero. At this point the switch can be reactivated, and lossless zero voltage switching facilitated. Since the output capacitance of the MOSFET switch (Co& has been discharged by the resonant tank, it does not contribute to power loss or dissipation in the switch. Therefore, the MOSFET transition losses go to zero regardless of operating frequency and input voltage. This could represent a significant savings in power, and result in a substantial improvement in efficiency. Obviously, this attribute makes zero voltage switching a suitable candidate for high frequency, high voltage converter designs. Additionally, the gate drive requirements are somewhat reduced in a ZVS design due to the lack of the gate to drain (Miller) charge, which is deleted when V& equals zero. The technique of zero voltage switching is applicable to all switching topologies; the buck regulator and its derivatives (forward, half and full bridge), the fly back, and boost converters, to name a few. This presentation will focus on the continuous output current, buck derived topologies.

3. PROPOSED ZVZCS CONVERTER

The goal of the design is to produce a dcdc converter that achieves soft switching for all the main switches, reduces the voltage stresses across each main switch, and controls the voltage on the secondary as per an FB step-down converter is the circuit topology and the operational waveforms of the proposed converter. The resistance Rload is the load equivalent resistance and might represent, for example, the inverter interfacing a distribution system. The intermediate voltage stages typically available in a 3L converter (i.e., }Vdc/2) allow a better approximation of a sinusoid thus resulting in a reduction in harmonic levels for the inverter case, but this feature is not applicable to the dcdc converter in this paper since the output voltage Vout , fixed at a constant dc level, is greater than the intermediate levels typical of dcac 3L converters. If the intermediate voltages were used, the voltage at the input of the diode-bridge rectifier would be less than Vout and the rectifier would not conduct, so no power would be delivered to the load. Table I gives the proposed switching states and identifies the voltage levels VS at the output of the transformer for each switching state. A + symbol indicates that the switch is ON during the switching state, while a symbol indicates that the switch is OFF. The switching frequency is fixed and each switch is ON for exactly half a switching cycle, but the timing of the turn-ON and turn-OFF of each switch is controlled so that the dc-bus voltage is applied to the transformer for the desired time as with phase-shifted PWM [9][11]. Using Table I and recognizing that the rectifier causes the voltage at the output filter to be positive regardless of the polarity of the transformer voltage, the reader can realize that the system has the same general operating modes as a buck converter and will have the same differential equations. The switching scheme, though it does not allow the intermediate voltage levels, does achieve soft switching for all the main devices, as will be shown in Section III.

Furthermore, the loss of intermediate switching states is consistent with other 3L soft-switched designs. As previously discussed, the rectifier diodes Drec1Drec4 Change the transformer voltage so that a positive voltage is applied to the output filter regardless of the polarity of the transformer voltage; thus, the converters operation can be defined in terms of half cycles with the voltage and current seen by the output filter Lf Co being the same for each half cycle. If the converter is in state 1 for duration D Tsw /2, where D represents the duty cycle and is a fraction between 0 and 1, then the average voltage at the rectifier will be Vout = D Vdc n where n is the turns ratio of the transformer. This provides the desired dc voltage conversion and shows that the system operates as a transformerized buck converter. Section III will show how the switching scheme achieves soft switching. Examining Table I and Fig. 1(a) reveals that diagonal switches receive the same control signals. The switching scheme can be simplified by controlling the devices in pairs, so that each pair S1 and S8, S2 and S7, S3 and S6 , and S4 and S5receives the same control signal. It can be further noted that the switching order and duration is identical to phase-shifted PWMfor a twolevel FB [11], so existing phase-shifted PWMcontrollers can be used to control the converter. This is an advantage compared to other 3L FB soft-switching topologies which require complex switching control schemes, such as double-phase-shifted control. The proposed 3L FB converter operates at twice the power of the standard (1)

two-level (2L) FB or 3L HB topologies in, since the 2L FB is limited to half the dcbus voltage for the same switch ratings while the 3L HB only applies half the dc-bus voltage to the transformer. The 3L FB has the advantage of being able to handle the same dc-bus voltage as the 3L HB, while applying the full dc-bus voltage to the transformer like the 2L FB. The proposed converter has an advantage over hybrid multilevel topologies in that it applies the full dc-bus voltage to the load for the entire operating range. The proposed converter has an advantage over ZVS-only 3L FB converters because ZVZCS converters have a wider soft-switching range than ZVS converters. Altogether, the proposed converter offers a high-voltage high-power solution that gives soft switching to all the main switches, reduces the voltage stress applied to the main switches thus allowing the use of devices with faster switching speeds, and reduces the complexity of the switching controller so that existing technology can be used for the switching controller.

3.1 POWER DIAGRAM

PO W E R D IAG R AM

S1
C 2

D 1

1 0nF

S5

D 5

4 C 7

10 nF

D 1 T 1 D 3 1 D 3

S2

1 S6 C 5

2 3 0/1 0 0 V

50 0 0 M fd / D 20 0 V 4

D C 4

7 C 8 L 1 T 2

1 D 6 D D C 3 1 0 Q 3 D 1 8 4

S3

S7

10 0 :3 0 10 K H z

S4

S8

IR 4 PC 3 0 WD X 8N o s FR 3 0 6 X 1 0 N o s

4. CONTROL CIRCUIT FOR PROPOSED SYSTEM

+12 V +12 V
16 R 1 7 R D 1 2 6 2 T T U R D N H RG 1 S 1 4 8 SV C TC H C G 5T 1 4 D U 2 V D D Q Q 5 Q D Q Q D C 3D 20 50 71 42 11 0 13 2 64 12 L R 9

+12 V
14 U 3 3 A D L QK D Q G N 1 3 1 5 2 D D V C

+12 V
1 2 7 3 14 U 4 A

S1
4 0 8 1

3 E O 5 U5 R GN

4 6 R S

CV

D C D 4

Q5 D4

14

0C 1 L 7 K G N D

+12 V
U 2

5 6

14

U 4

S4
4 0 8 1

15 13

C C 1

+1 2 V
16 15 U 6 V 1 4 QD D Q Q 5 Q D Q Q D C 0 5D 3 20 50 71 42 11 0 13 2 64 12 L R 1 1

14

U 1

B D D 1 9 1 D 14 3 1 2 3 4 0 8 7 U 1 1 4 D 2 4 0 8 1 7 3 8 9 14 U 1 0 4 C

V C

L QK D Q G N 1

S2

0 8 R S

D D

1 97 C L K 14 N D 3 U 4

G4 8

S3
1

13

7 C D

5. DRIVER CIRCUIT FOR THE PROPOSED CIRCUIT

OPTO -COUPLER CIRCUIT
1 2 v D C 1 2 v A C

330ohm
1

1 K

2 . 2 K

1 0 0 o h m G A T E

1 0 K 1 0 K 1 0 0 o h m

1 0 0 o h m

1 0 0 0 m F

MCT2E

1 2 v

D C

1 2 v

A C

330ohm
1

1 K

2 . 2 K

1 0 0 o h m G A T E

1 0 K 1 0 K 1 0 0 o h m

1 0 0 o h m

1 0 0 0 m F

MCT2E

1 2 v

D C

1 2 v

A C

330ohm
1

1 K

2 . 2 K

1 0 0 o h m G A T E

1 0 K 1 0 K 1 0 0 o h m

1 0 0 o h m

1 0 0 0 m F

MCT2E

1 2 v

D C

1 2 v

A C

330ohm
1

1 K

2 . 2 K

1 0 0 o h m G A T E

1 0 K 1 0 K 1 0 0 o h m

1 0 0 o h m

1 0 0 0 m F

MCT2E

1 2 v

D C

1 2 v

A C

330ohm
1

1 K

2 . 2 K

1 0 0 o h m G A T E

1 0 K 1 0 K 1 0 0 o h m

1 0 0 o h m

1 0 0 0 m F

MCT2E

1 2 v

D C

1 2 v

A C

330ohm
1

1 K

2 . 2 K

1 0 0 o h m G A T E

1 0 K 1 0 K 1 0 0 o h m

1 0 0 o h m

1 0 0 0 m F

MCT2E

6. THEORETICAL BACKROUND OF THE PROPOSED SYSTEM 6.1.CONVERTER OPERATIONAL MODES

The following analysis assumes that the switching devices are ideal, the output filter is large enough to act as a constant current source for the entire period, and the blocking capacitor is large enough to act as a constant voltage source while the current is being reset. Operational Mode 1: t0 t < t1 : Switches S1 and S8 have been ON for a (relatively) long time and Cb0 is charged to Vcb0p.At t = 0, switches S2 and S7 begin conducting and (Vdc Vcb0p ) is applied to the primary of the transformer. As a result, the primary current rapidly rises from 0 to the reflected output current Ip0 = Io/n ..(1)

1)

where Ip0 is the peak value of the primary side current going into the transformer, Io is the current through Lf , and n is the turns ratio of the transformer. The voltage applied to the transformer leakage inductor Llk during this period is Vdc (VCb0) = Vdc + VCb0 , .(2) and the duration of this period is t1 0 = t1 = Llk Ip0/(Vdc + VCb0) ... (3)

Since this period is so short, vcb0 is assumed to be constant throughout the period. The load current is not completely supplied by Vdc during this period, so the excess current freewheels through the secondary rectifier diodes Drec1Drec4

2)

Operational Mode 2: t1 t < t2 : The freewheeling mode ends when the primary current reaches Ip0 at t1 and

diodes Drec3 and Drec4 stop conducting. The output filter is connected in series with the leakage inductance of the transformer through Drec1 andDrec2 , and acts to keep the primary current constant at Ip0 . Power is transferred from Vdc to the load during this mode. The duration of this mode is related to the voltage conversion ratio by the duty cycle parameter D, which is given by

V0 / Vdc= D/n=(tON)/(Tsw /2)/n =(t2 t1 )/(Tsw /2)/n Since interval t1 is so short, tON is set equal to t2 and D = t2/Tsw /2 The blocking capacitor is charged from Vcb0p to +Vcb0p by Ip0 during this mode.

... (4)

. . (5)

3)

Operational Mode 3: t2 t < t3 : Switches S1 and S8 are turned OFF at t2 . Capacitors C1 and C8 are charged

and C4 and C5 are discharged by ip , which is still held constant at Ip0 by the large output filter inductance. When C4 and C5 are completely discharged at t3 , the primary current begins to circulate through devices S2 and S7 and diodes Dc1 and Dc4 . Switches S4 and S5 can be gated ON under complete ZVS at any time after t3 . Since this mode is so short, vcb0 is assumed to remain constant at Vcb0p for the duration of this mode. Each of the parallel capacitors conducts Ip0/2 during this mode and has a change of voltage of Vdc/2. Using the same value Cr for capacitors C1, C4, C5 , and C8 , the duration of this mode is t3 t2 = Cr Vdc/Ip0 ... (6)

4)

Operational Mode 4: t3 t < t4 : As the primary current circulates through S2, S7,Dc1 , and Dc4 , the blocking capacitor voltage Vcb0p is applied to the transformer and the primary current begins to decrease. As soon as the primary current falls below Ip0 , the output current begins to freewheel through the output rectifier diodes, disconnecting the primary side of the circuit from the load and short circuiting the transformer magnetizing inductance. Thus, the reset time is dependent on theleakage inductance

T reset = t4 t3 = Llk Ip0/Vcb0p

... (7)

FIG .1

5)

Operational Mode 5: t4 t < Tsw /2: Upon reaching zero, the current is prevented from flowing in the negative

direction by the diodes D2 and D7 . The output current continues to freewheel through the output rectifier diodes. The voltage Vcb0p appears across the output terminals AB, so S1 and S8 have to block (Vdc + Vcb0p )/2. At Tsw /2, S2 and S7 turn OFF under ZCS, and shortly afterward, S3 and S6 turn ON under ZCS. Since S4 and S5 are already ON, S3 and S6 conduct, and (Vdc + Vcb0p ) is applied to the primary of the transformer, beginning operational mode 6. Modes 610 are similar to modes 15 except for the reversal of the voltage and current signs.

FIG .2.

6.2. DESIGN EQUATIONS

The design of the converter involves determining values for Cdc1, Cdc2, Css1, Css2, C1, C4, C5, C8, Cb0, Llk , and the output filter. The output filter should be large enough to maintain the load current for the entire switching period Tsw , while the transformer leakage inductance Llk should be minimized in order to minimize the reset time. Beyond these restrictions, transformer and filter design principles also apply. Capacitors Cdc1 and Cdc2 are essential for the proper voltage division across the switching devices .Consequently, they should be selected with identical values using tight tolerance parts. In practice, the dc-bus capacitors will be required to maintain the voltage through changes in the input voltage Vdc and through voltage spikes caused by parasitic inductances, so a large value may be required. Smaller

capacitors with good high-frequency response may be placed in parallel with the bulk dc-bus capacitors in order to handle high-frequency ripple due to parasitic components. Capacitors Css1 and Css2 are also identical. Fig. 2 shows that they conduct during mode 3 and its mirror, mode 8. These capacitors must maintain a near-constant voltage during the entire cycle; thus, they should be selected so that they do not experience more than a 5%voltage change during mode 3. Each capacitor conducts Ip0/2 during mode 3, and its nominal voltage is Vdc/2. Therefore, the capacitor value required for a 5%ripple is Css= Ip0 (t3 t2 )/0.05 Vdc ..(8)

This can be simplified using (6), so that Css= Cr/0.05 = 20 Cr (9)

The size of the parallel capacitors, Cr , is determined by the minimum requirement to achieve ZVS during turn-OFF, which requires that the parallel capacitors must be large enough to hold the voltage close to zero during the current falltime of the device tf i, which can be determined from the data sheet . Once this parameter has been determined, Cr can be calculated as follows: Cr = tf i Ip0/Vdc ..(10)

A large value of Vcb0p is desirable in order to quickly reset the primary current during mode 4, but the OFF devices; see (Vdc + Vcb0p )/2 at the end of mode 2. Thus, the value of Vcb0p should be limited to one-fifth the dc-bus voltage in order to limit the voltage stress on the devices. Capacitor Cb0 is charged from

Vcb0p to +Vcb0p during mode 2 by ip at a value of Ip0 . The blocking capacitor will reach its largest value when the converter is transferring maximum rated power and ip is at Ip0,max. In order to meet the voltage restriction outlined earlier for these conditions, Cb0 should be chosen as Cb0=5Ip0.max Dmax/4 fsw Vdc (11)

where Ip0,max is themaximum value of the steady-state primary current expected during normal operation, Dmax is the value of the duty cycle at maximum power transfer, and fsw is the switching frequency. Since Vcb0p is directly proportional to Ip0 , any value of ip less than Ip0,max will result in a value of Vcb0p less than Vdc/5. The voltage Vcb0p for any value of Ip0 less than Ip0,max or any D less than Dmax is Vcb0p=Ip0D/4 fsw Cb0 (12)

6.3 CONVERTER LOSSES

The losses in the FB can be divided into two components: switching and conduction losses. Switching losses of the lagging leg switches the inner four switches S2, S3, S6 , and S7are negligible since they switch under ZCS; likewise, the switching losses of the leading switchesthe outer four switches S1, S4, S5 , and S8during turn-ON are negligible since the voltage across the devices is reduced to zero before switching. The losses in the leading devices during turn-OFF, however, are dependent on the size of the parallel capacitor. As the current

through the devices falls to zero, the difference between the device current and the primary current flows through the parallel capacitor causes a rise in voltage, and thus, the switch has a small amount of switching loss. The energy lost in each ZVS turnOFF event is given by Ezvs,OFF=I2p0t2fi/48 Cr ..(13)

Switches S1, S4, S5 , and S8 each undergo ZVS turn-OFF once per switching cycle, so the ZVS turn-OFF losses are Pzvs,OFF=4Ezvs,OFF fsw .(14)

Since mode 1 is so short, it is lumped together with mode 2 to determine the conduction losseswhile power is being transferred to the load. During this period, S1, S2,D2,D7, S7, S8 , and Cb0 are conducting the primary current Ip0 . The conduction losses for these devices during this time are P1,2=[(2Von,diode + 4 Von,IGBT) Ip0 + RESR,C b0 I p02] D/2 .(15) Mode 3 is the ZVS transition, so the losses in S1, S4, S5 , and S8 during this mode are represented by (13) and (14). Components S2,D2,D7, S7 , and Cb0 are still conducting during this mode, however, and sustain losses of P3 = [(2 VON,diode + 2 VON,IGBT) Ip0 + RESR,C b0 Ipo X Ipo] Cr fsw Vdc//Ip0 .... (16)

During mode 4, S2,D2,D7, S7, Cb0,Dc1 , and Dc4 are all conducting while the current is reset. The losses during this mode are P4 =[(4 VON,diode + 2 VON,IGBT) Ip0/2+ RESR,C b0x I p0/3]2_ f2sw Llk Cb0/D .. (17)

There are no conduction losses during mode 5 since the current through the FB is zero. The conduction losses in modes 6 and 7 are identical to those in modes 1 and 2 and are given by (15). Similarly, the conduction losses in modes 8 and 9 are given by (16) and (17), respectively. Mode 10, like mode 5, has no conduction loss. The total losses for the ZVZCS FB are PT = Pzvs,OFF + 2 (P1,2 + P3 + P4 ) .... (18)

6.4 SOFT-SWITCHING RANGE

ZVS is accomplished when Ip0 discharges the parallel capacitors across the leading switches during mode 3. The length of mode 3, referred to as the dead time, limits the maximum duty cycle that can be commanded by the controller, which, in turn, limits the maximum voltage that can be achieved on the secondary and the maximum power that can be delivered to the load. Since ZVS, and hence the dead time, occurs twice per half cycle, the maximum duty cycle is Dmax=12tdead/Tsw/2. .(19)

Once the dead time is fixed, there is a minimum value of the load current under which ZVS no longer occurs since the leading switches will be switched before the parallel capacitors are completely discharged. This minimum load current is given by Ip0,min=CrVdc/tdead .. (20)

The dead time must not only be selected to maximize the load current range for which ZVS occurs but must also minimize the reduction of the duty cycle. The precise value of the dead time will vary depending on the needs of the application, i.e., whether the application will require high duty cycles or whether it will require a large soft-switching range. ZCS is accomplished when the blocking capacitor voltage drives the primary current to zero before the state change that occurs at Tsw /2. The current begins to be reset at t2 = D Tsw /2, so the total time available to reset the current is Treset,max=(1D)Tsw/2 ..(21)

ZCS will be achieved if the reset period from (6) is less than Treset,max, and using the value for Vcb0p from (12), 4fsw b0 Llk/D (1 D) Tsw/2 ..(22)

It can be seen from this equation that achieving ZCS is independent of the load current, though the voltage across Cb0 may become very large if the primary current exceeds the maximum load current used in (10) to calculate the value of the blocking capacitor. There is a limit on the range of duty cycles for which ZCS occurs.

7. EXPERIMENTAL RESULTS
To demonstrate the proposed converter, a 100 V:30V, 100-W 10-kHz scaled down prototype was designed. IRG4PC30KD IGBTs were used for the switching devices S1S8 , with HFA25TB60 HEXFRED diodes as the antiparallel and series diodes D1D8 . In the prototype, Cree CSD10060 A silicon carbide and IR 10ETF06 silicon schottky diodes in parallel were used for the rectifier. The capacitors utilized for the dc-bus,Cdc, were 2.2 F electrolytics, the clamping capacitors, Css, were 1 F polypropylene, and the parallel capacitors C1, C4, C5 , and C8 were 4.7 nF ceramic. The output filter inductance and capacitance were selected to be large in order to emulate an ideal current source, as per the assumptions given in the derivations in Section III. The output filter inductor was 1.7 mH and the output filter capacitor was 710 F. The PSpice simulation operational waveforms are shown in Fig.3

The simulated waveforms are nearly the same as the theoretical waveforms except for a slight slope in the steadystate primary current caused by the current ripple in the output filter inductor. There was ringing in the primary current after resetting that was also seen in VPrimary for the same time period, which was due to the LC interaction of the leakage inductance with the capacitance of the series diodes D2,D3,D6 , and D7 . The ZVS of S1 during turn-OFF is shown in Fig. 4(a), where it was noticed that the voltage stress across the switch was limited to Vdc/2 = 100 V. This was not complete ZVS turn-OFF, since the voltage across the switch rises during turn-OFF,

reaching 50 V before the device finishes turning OFF. This is consistent with the analysis given in Section III-B. By contrast, S4 has complete zero-voltage turn-ON, since the voltage is reduced to zero before the device is switched, as shown in Fig. 4(b). The ZCS of S2 is shown in Fig. 4(c), which shows that the current falls before the device is switched.

Fig. 4 - Zero Voltage Switched Buck Regulator

Figures shows a plot of the efficiency of the bridge as a function of the load current. The efficiency dropped off significantly as the current increased. This drop is expected since conduction losseswhich are proportional to currentare the dominant losses in the soft-switching converter. The conduction losses are increased due to the larger number of devices in series, but this can be mitigated by using lower-rated devices with a lower ON-state voltage drop compared to what would be needed for a 2L design. The efficiency of the bridge at full load (10 A) was 93%, which was a 4.3% drop off from the light load (1 A) efficiency of 97.3%. The experimental operational waveforms for both full load (10 A) and light load (1 A). Large spikes were seen in both the primary current and the primary voltage at the instant that the dc-bus was applied to the transformer. These spikes are caused by

the rectifier diodes in two ways. First, the full source voltage Vdc is applied to the leakage inductance during mode 1 since the rectifier shorts the secondary side of the transformer while the load current is freewheeling through it. The two rectifier diodes that are not involved in the current cycle (Drec3 and Drec4 for the positive cycle) turn OFF when the current provided by the source is equal to the load current, but this turn-OFF does not happen instantaneously. The full source voltage Vdc is still applied to the leakage inductance while the diodes turn OFF, which results in a current overshoot in addition to the diode reverse recovery currents, which is the second contribution the rectifier diodes make to the current overshoot. Once the diodes turn OFF, this current is forced to decrease to Ip0 by Lf , resulting in a voltage spike as the current through Llk changes rapidly. The current and voltage oscillate as this transient dies down oscillations are the result of interactions between mainly the transformer leakage inductance and diode capacitance [28]. The spikes can be reduced by using rectifier diodes with faster turnOFF times and smaller reverse recovery currents (like SiC Schottky diodes). The voltage and current waveforms for the rectifier on a 2L ZVZCS converter implemented in both Si and SiC. The top waveform shows the primary-side transformer voltage, the second waveform shows the secondary side transformer voltage, the third waveform shows the voltage across Drec4 , and the bottom waveform shows the transformer current reflected to the secondary side. It can be seen from comparing the two waveforms that using a SiC device, which has a smaller reverse recovery current and a faster turn-OFF time, results in a smaller current overshoot and a shorter delay between the rise of the primary side voltage and the rise of the secondary side voltage. The slope in the primary voltage was due to the blocking capacitor voltage, which was added to VAB. Since the blocking capacitor

charges to a higher value at higher currents, the slope in the voltage is more evident at higher loading conditions. The slope in the current was due to the ripple of the output filter inductor, and was approximately 1 A. This ripple was the same for large or small currents, but it was not as evident in the full-load condition since the scaling of the current is higher. The soft switching of the devices. Fig. 8 shows the zero-voltage turn-OFF of S8 at both full and light loads. As was the case in the simulation data, the voltage across the device reached half the final voltage by the time the device finished switching OFF in the full-load case, which was used in (9) to select the parallel capacitances. Since the current is smaller at lighter loads, the capacitor voltage was lower when the device switches OFF, resulting in reduced turn-OFF losses. The same phenomenon was noted in , where the voltage across S8 took considerably longer to reach zero at light loads than at full load. This is consistent with the limit belowwhich the ZVZCS converter will not achieve ZVS for the leading switches, as given by (20). For this system with a Cr of 4.7 nF, the limit on Ip0 is 0.47 A. The converter is operating at Ip0 = 1 A for Fig. 8(a), but this is approaching the ZVS soft-switching limit and some losses occur near the end of the dead time since the capacitor still has a small charge when the device turns ON and the current through it begins to rise for the next cycle. These losseswill increase as the load current decreases and there is less primary current available to discharge the parallel capacitances, as discussed in Section III-D. The steady-state collectoremitter voltage is shown in this figure and is limited to 100 V, or half the dc input voltage. T he ZCS turn-ON of S2 . The voltage rises quickly at both light and heavy loads, but the current rises more quickly at heavy loads. The rate at which the current falls was nearly the same for both the full- and

light-load cases. The current at turn-ON rises very rapidly due to the large applied voltage. Still, the current does not rise until the voltage across the switch is at zero in both cases, so soft switching is still achieved even at heavy loads. The ZCS turn-OFF of S2 , and the current is at zero for a long time before S2 is turned OFF in both the light- and heavy-load cases. This shows that the switch achieves soft switching at turn-OFF. The reset time was approximately 1.4 s, consistent with what was seen in the simulations. The blocking capacitor was charged to a smaller voltage at lighter loads, and therefore, Ip did not have as high a di/dt as at full load. There was less current to reset, however, so the total reset time remained approximately constant.

7. ZVS DESIGN EQUATIONS

A zero voltage switched Buck regulator will be used to develop the design equations for the various voltages, currents and time intervals associated with each of the conversion periods which occur during one complete switching cycle. The circuit schematic, component references, and relevant polarities are shown in Fig. 4.Typical design procedure guidelines andshortcuts will be employed during the analysisfor the purpose of brevity. At the onset, all components will be treated as though they were ideal which simplifies the generation of the basic equations and relationships. As this section progresses, losses and non-ideal characteristics of the components will be added to the formulas. The timing summary will expound upon the equations for a precise analysis.

8. ZVS DIFFERENCES
Variable frequency operation (in general)

Higher off-state voltages in single switch, unclamped topologies Relatively new technology - users must climb the learning curve

Conversion frequency is inversely proportional to load current A more sophisticated control circuit may be required

9.ZVS BENEFITS
Zero power Lossless switching transitions Reduced EMI / RFI at transitions No power loss due to discharging Goss No higher peak currents, (ie. ZCS) same as square wave systems High efficiency with high voltage inputs at any frequency.

Can incorporate parasitic circuit and component L & C

10. APPLICATIONS
Reduced gate drive requirements (no Miller effects) Short circuit tolerant In the electric utility industry, Such as interfaces for high-power distributed generation, Renewable resources, Energy storage, Dc interlinks, And solid state power substation. Reduced gate drive requirements Short circuit tolerant

FUTURE ENHANCEMENT

Future research would include designing a prototype to implement an active clamp to reset the current thus eliminating the series diodes and the losses associated with them. This would have the added benefit of reducing the spikes from the rectifier diodes

CONCLUSION

This paper proposed a 3L ZVZCS converter with a simplified switching scheme for use in solid-state solutions. The converter was shown to have the advantages of soft switching and reduced voltage stresses across the devices, allowing higher voltage operation. The operation of the 3L FB ZVZCS converter was analyzed. Experimental results further demonstrated the feasibility of the proposed ideas. Future research would include designing a prototype to implement an active clamp to reset the current thus eliminating the series diodes and the losses associated with them. This would have the added benefit of reducing the spikes from the rectifier diodes when the dc voltage is applied during modes 1 and 6.

LIST OF FIGURES
1.POWER DIAGRAM - 2.3

2.DRIVER CIRCUIT FOR PROPOSED CIRCUIT 2.4 3.CONVERTER OPERATIONAL MODES - 2.5.1 4.PSPICE OPERATIONAL WAVEFORMS -3.1 5.ZERO SWITCHED VOLTAGE REGULATOR 3.1

REFERENCES

F.

BLAABJERG,

Z.

CHEN,

AND

S.

B.

KJAER,

POWER

ELECTRONICS AS EFFICIENT INTERFACE IN DISPERSED POWER GENERATION SYSTEMS, IEEE TRANS. POWER ELECTRON., VOL. 19, NO. 5, PP. 11841194, SEP. 2004.

J.

D.

LEEPER

AND

J.

T.

BARICH,

TECHNOLOGY

FOR

DISTRIBUTED GENERATION IN A GLOBAL MARKET PLACE, IN PROC. AMER. POWER CONF., 1998, VOL. 1 L. M. TOLBERT AND F. Z. PENG, MULTILEVEL CONVERTERS AS A UTILITY INTERFACE FOR RENEWABLE ENERGY SYSTEMS, IN PROC. 2000 POWER ENG. SOC. SUMMER MEETING, 2000, VOL. 2 F. ZHANG, F. Z. PENG, AND Z. QIAN, STUDY OF THE MULTILEVEL CONVERTERS IN DCDC APPLICATIONS, IN PROC. 2004 IEEE ANNU. POWER ELECTRON. SPEC. CONF. (PESC 2004)

A. MEDURY, J. CARR, J. BALDA, H. MANTOOTH, AND T. FUNAKI, THREE-LEVEL ZVZCS AND ZVS HALF-BRIDGE CONVERTERS: A

COMPARATIVE EVALUATION, IN PROC. 4TH POWER CONVERS. CONF., APR. 2007, PP. 892898.