BEHAVIORAL MODEL OF PIPELINE ADC BY USING SIMULINK@

Erkan Bilhan, Pedro C. Estrada -Gutierrez, Ari Y. Valero-Lopez, Franco Maloberti

Texas A&M University Department of Electrical Engineering College Station, Texas 77840 U.S.A. bilhan @ee.tamu.edu
ABSTRACT
The presented work concentrates on behavioral modeling of pipeline ADCs. For this purpose the parameters that affect the operation of basic pipeline ADC blocks are investigated. The non-ideal parameters of these blocks are modeled by using MATLAE4@ and SIMULINK?

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INTRODUCTION

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Early stages of analog design circuits foresee the validation of the selected architecture and the definition of the basic blocks' specifications. These steps are performed with a behavioral analysis of systems: an investigation at the transistor level is often premature. Even if possible, it is quite time consuming. Behavioral description can be achieved by the use of different highlevel languages [ 13. This paper employs the MATLAB@ and SIMULINK@environment. However, other solutions (like HDL-A or Labview) can be used as well. Specifically, we study the behavioral model and derive performances of a pipeline ADC. It consists of cascaded identical stages. Each stage processes the input signal and produces a digital word plus a residual voltage for the next stage. The resolution of a single stage may vary according to the design specifications. In our case we used IS-biVstage (Figure 1) that is normally used together with the digital correction technique [2]. The transfer function of a stage is as below:
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Figure 1. Pipeline ADC block diagram and stage transfer curve This work accounts for all these non-idealities and permits to estimate the accuracy and the speed performances of the conversion before the design.

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A sample and hold amplifier precedes the pipeline chain. Each of the pipe stages comprises four main blocks: a sub-ADC, sub-DAC, residue amplifier and subtractor. Generally an MDAC realizes the last three. The accuracy of the converter critically depends on the non-idealities of the actual components used. Such non-idealities come from the limited matching of components, the finite gain and gain bandwidth of amplifiers.

11.

SAMPLE/HOLDAMPLIFIER

A Sample and Hold (SBrH) block is a critical part of an ADC. Its function is to sample and then retain the input signal long enough for the A/D converter to complete a conversion without significant error.

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Figure 2. Basic Sample and Hold circuit

0-7803-6742-1/01/$10.0002001 IEEE

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We have modeled a S&H block considering the non-idealities of clock jitter and acquisition timelslew rate. A basic S&H circuit is shown in Figure 2. The clock jitter is modeled during the sampling instance, which is when the clock is asserted. The acquisition time is defined as the time the S&H takes to charge or discharge from one sampling point to another within half a clock period. When the clock signal goes high, the S&H samples the input and the data is stored in the Chid capacitor. The opamp with the unity gain functions as a buffer. After the clock switches to low, the output holds onto the voltage stored in the Chid capacitor. The acquisition voltage depends on the slew rate of the opamp at the output. When the slew rate is limited or there is a large output capacitance, it may cause the output to fall short from the desired input level. This will cause signal degradation and as such affect the performance of the whole system. Clock jitter is the difference of time from its ideal rising clock edge. This difference occurs randomly before or after its ideal rising edge. The specification of the model is limited to kTJ2 (T,=sampling period). From the description above, the model will have to be able to interpolate between two points. The two points may lie between a past and present point or a present and future point. The actual jitter in the system is usually within an acceptable range of error. With this assumption and considering that the input signal frequency is reasonably slow, it is best to use linear interpolation because of its simplicity. The acquisition is the time the circuit takes given a certain time constant to achieve the sampling point. The final value of current sampling may not be equal to the input value if the time constant is large. The
S&H model includes a memory block to remember the

different regions: linear and overdrive. The model is able to determine the region of operation and to apply the proper behavioral model. The hysteresis is included to model the metastability error present in the comparator due to signals whose magnitude is very close to the comparator reference. Fixed offset voltage and random offset voltage are added to the input. Fixed offset voltage accounts the intrinsic offset of the comparator and causes a shift in the threshold voltage of the amplifier. The random offset accounts for the random variations in the reference voltage. Figure 3 shows the SIMULINK@model of the comparator. The signal can follow two different paths depending on the operation region of the comparator. In linear mode the signal is amplified, limiteaand latched, whereas in the overdrive mode the signal goes from the initial voltage to the final voltage in an exponential fashion. This exponential behavior introduces the speed limitation of the comparator into the model.

Figure 3. Comparator macromodel

IV.

MDAC MODEL

last value as the initial point to calculate the final point due to acquisition time. In this model it was assumed that charging or discharging of the capacitor occurs during first half of clock period. Thus the time in this case is T,/2. The acquisition time equation is modeled as a simple RC circuit. The study of the effect of non-linearities associated to the on-resistance of the switch is also possible but it's not done here to limit the simulation time.
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The performance of a pipeline ADC critically depends on the performance of the MDAC amplifier. used to generate the residue voltage for the next stage. Figure 4 shows the typical switched capacitor MDAC configuration used in a 1.5 bit per stage architecture [3]. Phi,

COMPARATOR
Figure 4.MDAC Configuration During the first phase (Phi,) capacitors C1 and C2 are charged to the input voltage while during the second phase (Phiz) C2 is connected in feedback and C, is connected to a proper reference voltage determined by the digital output of the sub-ADC. Successive cells operate with complementary phases so that while the

The comparator is one of the most widely used blocks in analog to digital converters. It is the block that ultimately links the analog signal to a digital representation. One of the most popular comparator implementations for high-speed has one or two stages of preamplification followed by a latch. The comparator model is comprised of two stages, a preamplifier and a latch (with hysteresis). The amplifier can operate in two

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Figure 5. MDAC Configuration for sequential two stages first stage generates the residue voltage the next stage samples it (see Figure 5). The performance of a stage depends on how precisely they can generate the residue for the next stage. In other words the settling of the amplifiers output voltage to the right value in a half clock cycle determines the precision of the next stage. The ideal transfer function of amplifier is given in (1). There are four basic error sources: Capacitor matching and open loop gain, gain bandwidth, and the slew-rate of the amplifier. If the capacitor mismatch is accounted the ideal residue function has to be modified as follows:

equal or higher than 205 times of their overdrive voltage (Vd). So the slew-rate is effective only for large input voltages. During the slewing condition the output voltage changes proportionally to the maximum current that can be driven from amplifier. For other cases the amplifiers operate in linear condition (LOP), in which the speed of the charge transfer is determined by gain bandwidth of amplifier. The circuit in Figure 5 is modeled as in Figure 6 by using a single pole approximation for the amplifiers, to investigate the discussed limitation on the converters performance. The current sources model either the slewing condition (I=I-) or the normal operation (I=g,V,,). Equation (2) gives the system equations describing the circuits behavior for all operating conditions of amplifier. This equation was solved for the four different situations summarized in Table 1 depending on the operating condition of amp-I and amp2. A behavioral model is developed that uses the solutions of the system equations. The simulation results are discussed in the next section.

More complex is the modeling of the finite gain, gainbandwidth and slew-rate of the amplifier. Finite open loop gain modifies the gain of the feedback system and this will introduce an error to the residue value. The gain-bandwidth and slew-rate determines the speed of the operation. If the time for residue generation is smaller than the settling time of the amplifier the residue does not settle to the proper voltage and it introduces an error to the voltage sampled by the next stage. The amplifiers, shown in Figure 5, operate in slewing condition (SLW) if the voltage at their input is

Figure 6. Circuit model used to analyze the MDAC given in Fig. 5 Table 1: Operating conditions for amplifier and solution

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V.

SIMULATIONRESULTS

The discussed model above was used to simulate a 1.5biVstage 10-bits pipeline ADC at 100 MHz with digital correction. Several simulations were performed considering variation of a non-ideal parameter while the rest of the i \ ; ! blocks were considered ideal. The rest of the nonidealities in the same block were only considered constant. This analysis shows the effect of every nonideality isolated from the rest of the parameters. First, results for the Sample and Hold are shown in Tables 2 and 3. Table 2 shows the effect of reducing the time constant or acquisition time of the S&H. Table 3 considers the effect of jitter noise. The values in the jitter column represent in percentage of the clock frequency, the maximum jitter noise possible for that simulation. We can see that the system is very sensitive starting from certain value. Table 2. Maximum INL and DNL for different values of acquisition time (Tau) Tau [s] le-5 5e-5 1e-4 5e-4 le-3 Max INL [LSB] 0 0.5574 0.9734 1.1738 2.0879 Max DNL [LSB] 0 0.1893 0.1986 1.1957 2.3934

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Figure 7. INL and DNL plots for offset in comparator.

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Figure 8. INL and DNL plots for speed in comparator.

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Table 3. Maximum INL and DNL vs. Jitter Jitter [Yo] 10 25 35 45 49 Max INL [LSB] 0.1237 0.974 1 1.7428 2.3782 3.1284 Max DNL [LSB] 0.0562 0.7236 1.4295 1.9647 2.3863

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Simulations performed under the specified conditions show that the offset of the comparators should be below 250mV, the bandwidth of the comparator larger than .15OMHz and the hysteresis smaller than lV, see figures 7, 8 and 9. From the previous values we can see that the digital correction at the output of the ADC helps to relax the specifications of the building blocks. The offset and hysteresis show values from which the performance of the comparator degrades rapidly, but these values are large enough to provide a very relaxed specification.

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Figure 9. INL and DNL plots for hysteresis in comparator. The capacitor values are chosen as CI=C2=C3=C4=lpF, 2C,,=2CpZ =Cp3 =O.lpF for MDAC simulations. The amplifier parameters such as transconductance ( G d output resistance (1/G) and the maximum current (Imx) are calculated according to the assigned values of AV, GBW and SR.The parameters used for simulations and the performance results in terms of INL are summarized in Table 4.

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Table 4: Simulation results for the MDAC

IO-BIT ADC OUTPUT

5 80

6 80 7 80

700 600 600

100

75

250

3.8779 25.1817 1.4529 60.3555 1.8653 49.7195

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The input-output plot of 10-bit ADC for the lst parameter set is given in Figure 10. Some sparkling codes from Figure 10, and an INL error of 4LSBs from Figure 11 can be observed. The'chosen parameter set can not meet the linearity specification, which is an INL error within OSLSBs. For an optimal solution the values for the parameters AV, GBW, SR should be changed. Table 4 presents some possible combinations (data set from 2 to 7) and the result of simulation. As seen from these results, increasing one parameter while keeping the others constant does not improve the performance further. The contribution of the other parameters to INL is more significant than the parameter that is increased. It can be deducted from simulation results that the limitation factors on performance for the first parameter set are the GBW and SR of the amplifier rather than the AV.For an optimal solution one must seek an increase of these two, GBW, SR parameters.

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Figure 10. ADC Output plot for the first parameter set in Table4.

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REFERENCES
[ l ] F. Maloberti, P. Estrada, A. Valero, P. Malcovati, "Behavioral Modeling and Simulation of Data Converters," IMEKO 2000, September 2000, Viena, Austria [2] Lewis, S.H.; Gray, P.R., "A pipeline SMsample/s 9 bit analog-to-digital converter," IEEE JSSC, vol. SC-22, pp.954-61, Dec 1987 [3] Gunay, Z.S.; Soenen, E.G.; Embabi, S.; SanchezSinencio, E., "A 1.8 V pseudo-differential switchedcapacitor amplifier," Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE, pp. 373 376, 1998

Figure 11. INL and DNL plots for the first parameter set in Table 4

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