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AmirAlimohammad
DepartmentofElectricalandComputerEngineering SanDiegoStateUniversity OfficeFourthfloor,Engineering,403E EMail aalimohammad@mail.sdsu.edu OfficeHoursMondaysandFridays4 5PM ClassScheduleMondaysandFridays5:30 6:45PM ClassLocationGeology,Mathematics&ComputerScience(GMCS) 308
Singlecyclefixedpointprocessordesign
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COMPE470Lab.
Binary system
Assume a binary number X is an ordered sequence of binary digits (bits) X = xn-1 xn-2 x1 x0 Upper case letters represent numerical values or sequences of digits Lower case letters, usually indexed, represent individual digits
X = -2n-1xn-1 + 2ixi
Range of representable numbers with n bits is from 2n1 to 2n1 1
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binarypoint If m=0, the number is an integer and if k=0, the number is purely fractional The value of a number is
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Base conversion
Use the remainders for the integer part Example: Convert 23.37510 to base 2. Start by converting the integer portion:
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B +/ A S
m lbits
lbits
k+lbits
For the convenience of hardware implementation, we prefer to have the product of a multiplication keeping the same length as the multiplicand or the multiplier (assume they have the same length). To achieve this, we normally truncate the least significant bits of the product
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Fixed-point multiplier
module Mul #(parameter WI1 = 4, //first input, integer length WF1 = 4, // first input, fraction length WI2 = 8, // second input, integer length WF2 = 8, //second input, fraction length WIO = 12, // output format, integer length WFO =12) // output format, fraction length (input signed [WI1+WF1-1:0] in1, // multiplier inputs input signed [WI2+WF2-1:0] in2, `` input CLK, output signed [WIO+WFO-1 : 0] out); //multiplier output reg signed [WI1+WF1+WI2+WF2-1:0] temp; always @(posedge CLK) temp <= in1*in2; assign out = {temp[WF1+WF2+WIO-1:WF1+WF2],temp[WF1+WF2-1:(WF1+WF2-WFO+1)]}; endmodule
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c = r[3]; //the 3rd reg value in array r is assigned to c integer count[1:5]; // 5 integers reg var[-15:16]; // 32 1-bit regs
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Memories
Memories are arrays of vectors defined using reg variables
reg [ msb : lsb ] memory1 [ upper : lower ]; reg [7:0] myMem [3:0]; // It defines a memory with 4 locations and each // location contains an 8-bit data
A memory element (word or a row of memory) can be accessed by a memory index as mem[index] // similar ro a bit-select
reg [7:0] array1 [0:255]; wire [7:0] out1 = array1[address];
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XST can use block RAM resources to implement ROMs with synchronous outputs or address inputs
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Dual-port RAM
module dual_port_ram_single_clock(input [(DATA_WIDTH-1):0] dina, dinb, input [(ADDR_WIDTH-1):0] addra, addrb, input WEA, CLK, output reg [(DATA_WIDTH-1):0] douta, doutb) parameter DATA_WIDTH = 8; parameter ADDR_WIDTH = 6; reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0]; // Declare the RAM variable always @ (posedge CLK) begin // Port A if (WEA) begin ram[addra] <= dina; douta <= ram[addra]; end always @ (posedge CLK) begin //Port B doutb <= ram[addrb]; end endmodule
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Initializing BlockRAMs
You can use an initial block to initialize the contents of an inferred memory Initialization is only valid for block RAM resources. If you attempt to initialize distributed RAM, XST ignores the initialization, and issues a warning message Block RAM initial contents can be specified by initialization of the signal describing the memory array in your HDL code You can do this directly in your HDL code, or you can specify a file containing the initialization data You can initialize blockRAMs and ROMs using $readmemh and $readmemb system tasks The initialization work identically in synthesis and simulation
reg [7:0] ram[0:15]; initial begin $readmemb("ram.txt", ram); end
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Levels of representations
HighLevelLanguage Program Compiler AssemblyLanguage Program Assembler MachineLanguage Program
lw lw sw sw
0000 1010 1100 0101
Programmer'sView
$15, $16, $16, $15,
1001 1111 0110 1000
Computer'sView
1010 0000 0101 1100 1111 1001 1000 0110 0101 1100 0000 1010 1000 0110 1001 1111
MachineInterpretation ControlSignalSpec
ALUOP[0:3] <= InstReg[9:11] & MASK
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Sequence of instruction execution is controlled by a program counter register The next instruction to be executed is typically implied as instructions are execute sequentially
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Memory-to-memory architecture
All ALU operands from memory VAX machines
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where opcode indicates the operation of the instruction, opd, ops1, and ops2 are the destination and source registers specifiers, respectively
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Start!
Assume that our processor supports three instructions: ADD, SUB, and MUL These arithmetic operations are implemented using the ALU that you designed The addition (subtraction) is performed in 2s complement format with overflow detection No carry output is required Lets implement (A-B)x(C+D)x(A+D)
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CLK
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Controller
Instruction
ControlSignals Conditions
ctrl
douta
Result
ALU
Datapath
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CLK
Data Memory
doutb
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Memory modules
Use the provided parameteric memory module (number of rows and columns are parametric) Use 1024 as the default value for the number of rows and 18 as the number of columns Use one memory block for the data memory and one memory block for the instructions The operands of the instructions are stored in the data memory We will discuss the controller design in the next lab
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