Monday, 19/09/2011 ELECTRONIC AND ELECTRICAL DEPARTMENT POLYTECHNIC OF SULTAN HAJI AHMAD SHAH 4.0 555 TIMER 4.

1 Introduction The 555 Timer is a monolithic timing circuit that can produce accurate and highly stable time delays or oscillations. Use as mono-stable multi-vibrator, astable multi-vibrator, analog square wave signal generator, achometer frequency meter and others. Basically, 555 timer operate in 2 mode: a. b. Mono-stable Astable multi-vibrator

Figure 1: a 555 Timer and b) 556 timers 4.2 Function of Each Pin Timer Refer To Mono-stable Multi-vibrator

Figure 2: a) Sink current (normally on-load) and b) Source current (normally off-load) PIN 1: GROUND All the measure voltage must refer to this pin. PIN 2: TRIGGER It is used to reset (R) the flip-flop. Output is LOW if voltage at pin 2 > 2/3 VCC. When negative edge trigger pulse is < 1/3 VCC, the output at comparator 2 causes HIGH so the timer output HIGH. PIN 3: OUTPUT The output can be connected between two conditions either pins which pin 3 and pin 1 or pin 3 and pin 8. (Refer to figure 2) When output LOW (figure 2a), current will flow through load that connected between pin 3 and pin 8 to output terminal, know as SINK CURRENT. A current flow through the load that connected between pin 3 and pin 1 (figure 2b), known as SOURCE CURRENT. Maximum current for source current and sink current is 200mA. PIN 4: RESET Reset with a negative pulse (ground). When the reset pin is not used, the pin is connected to +V CC to avoid false trigger. PIN 5: CONTROL VOLTAGE Normally is connected to ground through 0.01F capacitor. If output voltage is connected to pin 5, the output waveform time width can be changed. This capacitor can reduce a noise problem. PIN 6: THRESHOLD VOLTAGE Input for non-inverting pin at comparator 1 to set (S) the flip-flop. When voltage at this pin 2/3 VCC, output at comparator 1 set the FF, output timer LOW. PIN 7: DISCHARGE This pin is connected internally to collector at transistor T1. When output HIGH, T1 OFF (open to ground). 1 | Page

Monday, 19/09/2011 When output LOW, T1 saturated (bypass to ground) the capacitor C discharge through T1.

PIN 8: SUPPLY VOLTAGE, VCC. +5 V to 18V

Figure 2: Simplified functional block diagram of a 555 timer 4.2 Mono-stable Multi-vibrator Known as shoot multi-vibrator. And it has a stable output (LOW state). Pulse generator circuit which the period is calculated from RC network and connected to external of 555 timer.

Figure 3: Mono-stable timer circuit and it waveforms. Time period of output High, (s)

Mono-stable Operation (Refer to figures 2 and 3) When the negative trigger edge of the input (pin 2) falls to slightly less than 1/3Vcc, the lower comparator 2 resets the flip-flop. Since Q has change to LOW, the transistor T1 goes into cutoff (open to ground), allowing the capacitor to charge exponentially through resistor R. At this time, has changed to HIGH. When the capacitor charges greater than 2/3VCC, the comparator 1 sets the flip-flop. The Q output become HIGH and turns ON the transistor T1. Hence the capacitor bypasses to ground and start to discharge. At the same time returns to the low state and the output pulse ends. remains LOW until another input trigger arrives. The complementary output comes out of pin 3. 2 | Page

Monday, 19/09/2011 The width of the rectangular pulse depends on how long it takes to charge the capacitor through resistance R. The longer time constant, the longer it takes for the capacitor voltage to reach 2/3VCC. A 555 timer is connected for mono-stable operation. the width of the output pulse. Solution: ( 4.3 ASTABLE MULTIVIBRATOR ) ( If R = 10k and C = 0.022F. Calculate

Figure 4: Astable-stable timer circuit and waveforms. Known as free running multi-vibrator. And not has a stable output (Low state). This type of timer do not have stable condition, the condition always change. Astable do not need trigger pulse for external to change the output. The period for LOW and HIGH can be calculated based on resistor and capacitor value that connected at external of timer.

Astable Operation (Refer to figures 2 and 4) Let start with the Q is LOW, the transistor T1 is cutoff (open to ground) and the capacitor is charging through R1 and R2. As the Capacitor charges, the threshold voltage (pin 6) increases. The becomes HIGH state. Eventually, the threshold voltage exceeds 2/3Vcc. Then the comparator 1 sets the flip-flop. With Q HIGH, the transistor T1 saturates and bypass to ground. The capacitor starts to discharge through R2 to pin 7 (discharge). When the capacitor voltage drops slightly less than 1/3Vcc the comparator 2 resets the Flip flop. The Q is LOW and the is HIGH, this process continues as long as power supply voltage is applied. The capacitor charge time or The time of output High, ( ) (s), second The capacitor discharge time or The time of output Low, (s), second The time period of output, T ( ) ( ) (s), second The frequency, F (Hz), Hertz ( ) The percentage of duty cycle, %DC ( ( (%) Example: i. ii. An astable 555 timer has R1 = 10k, R2 = 2 k, and C = 0.0047 F. The capacitor charge time, (output high time), TH. The capacitor discharge time, (output low), TL Determine: ) )

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Monday, 19/09/2011 iii. iv. v. Solution: i. The capacitor charge time, (output high time), TH. ( ( ii. ) ) ( ) The period time, T The Frequency, F The percentage of duty cycle, %DC.

The capacitor discharge time, (output low time), TL. ( ) ( )

iii.

The period time, T

iv.

The Frequency, F

v.

The percentage of duty cycle, %DC.

4.4 555/556 Inverting Buffer (Schmitt trigger) or NOT gate

Figure 5: 555 inverting buffer circuit (a NOT gate)

Figure 6: NOT gate symbol The buffer circuit's input has a very high impedance (about 1M) so it requires only a few A, but the output can sink or source up to 200mA. This enables a high impedance signal source (such as an LDR) to switch a low impedance output transducer (such as a lamp). It is an inverting buffer or NOT gate because the output logic state (low/high) is the inverse of the input state: i. Input low (< ) makes output high, +VCC

ii.

Input high (>

) makes output low, 0V

When the input voltage is between and the output remains in its present state. This intermediate input region is a deadspace where there is no response, a property called hysteresis, it is like backlash in a mechanical linkage. This type of circuit is called a Schmitt trigger. If high sensitivity is required the hysteresis is a problem, but in many circuits it is a helpful property. It gives the input a high immunity to noise because once the circuit output has switched high or low the input must change back by at least Vs to make the output switch back.

555/556 Bistable (flip-flop) - a memory circuit

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Monday, 19/09/2011 The circuit is called a bistable because it is stable in two states: output high and output low. It is also known as a 'flip-flop'. Also referred to as a flip-flop It has two inputs: i. Trigger (555 pin 2) makes the output high. Trigger is 'active low', it functions when < 1/3 Vs. ii. Reset (555 pin 4) makes the output low. Reset is 'active low', it resets when < 0.7V. The output changes state when it receives a valid input trigger signal, and remains in that state until another valid trigger signal is received.

Figure 7: 555 bi-stable circuit

4.5 Schmitt Trigger Introduction The Schmitt trigger is a voltage-level detector that is similar to a comparator but with hysteresis. The output of a Schmitt trigger changes state when o When a positive-going input passes the upper trigger point (UTP) voltage. o When a negative-going input passes the lower trigger point (LTP) voltage.

Figure 8: Schmitt trigger symbol 4.5.1 Inverting Schmitt trigger

Figure 9: Inverting Schmitt trigger circuit The resistor R2 provides the positive feedback. The input voltage Vin trigger and changes the states of output voltage Vo (Saturated voltage of opamp output) each time when Vin exceeds voltage levels called upper threshold voltage (UTP) and lower threshold voltage (LTP) shown in figure 12. The switching occurs when Vin = = = , where

, therefore (Refer to figure 10): i. Switching at the output occurs from +Vsat to -Vsat. ( ii. ) ( )

Switching at the output occurs from -Vsat to +Vsat. ( ) ( )

Hysteresis A term that is often used to describe them range of voltages between the UTP and LTP of a Schmitt trigger. (HYSTERISIS = UTP LTP).

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Figure 10: Vo versus Vi hysteresis

Figure 11: Input waveform Vin versus Vo 4.5.2 Non-Inverting Schmitt trigger

Figure 12: Non-Inverting Schmitt trigger circuit ( ( ) )

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Figure 13: Vo versus Vi hysteresis

Figure 14: Input waveform Vin versus Vo

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