NoC - Slides

On-Chip Networks (NoCs)
Simone Pellegrini
Seminar on Embedded System Architectures (Prof. A. Strey) University of Innsbruck simone.pellegrini@uibk.ac.at
December 10, 2009
Outline
1
Introduction NoC Components Network Adapter (NA) Routing node Link NoC Analysis and Solutions Case Studies Xpipes RAW Processor Summary
S. Pellegrini (UIBK)
On-Chip Networks
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On-Chip Interconnects
In System-on-a-Chip(SoC), on-chip interconnects consist of 3 solutions: Bus Single wire shared between several IPs, arbitration logic to guarantee serialization of access requests. Crossbar A switch connecting multiple inputs to multiple outputs in a matrix manner. Point-to-Point Each component has a dedicated interconnection towards other dependent IPs.
CPU
RAM
CPU
MPEG
CPU
RAM
DSP
MPEG
DSP b) Crossbar
DSP RAM
MPEG
a) Bus
c) Point-to-Point
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Scalability Problems
As the number of integrated cores (or IPs) is rapidly increasing, traditional interconnects are starting to show scalability problems
Bus
The increasing number of attached cores increase the capacitive load It can easily become a communication bottleneck
Crossbar/Point-to-point
Does not scale efciently beyond 20 cores Expensive realization costs in terms of chip area
On-Chip Networks
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Scalability Problems
As the number of integrated cores (or IPs) is rapidly increasing, traditional interconnects are starting to show scalability problems
Bus
The increasing number of attached cores increase the capacitive load It can easily become a communication bottleneck
Crossbar/Point-to-point
Does not scale efciently beyond 20 cores Expensive realization costs in terms of chip area
As the trend is SoC systems is to integrate a large number of cores, a more scalable system is needed!
On-Chip Networks
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On-Chip Network Overview

The solution consists of an on-chip data-routing network generally known as Network-on-Chip (NoC) architecture.
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On-Chip Network Overview

The solution consists of an on-chip data-routing network generally known as Network-on-Chip (NoC) architecture. A NoC consists of 3 main components: Network Adapter (NA) Routing node Link
switch
NA
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Network Adapter
Decouples computation (the cores) from communication (the network)
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Network Adapter
Decouples computation (the cores) from communication (the network) handles the end-to-end ow control
Messages are broken into packets
additional routing information encoded into packet headers
Packets are decomposed into its (ow control units) Flits are split into phits (physical units)
i.e. minimum datagram size transmitted in a single link transaction
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Network Adapter
Decouples computation (the cores) from communication (the network) handles the end-to-end ow control
Messages are broken into packets
additional routing information encoded into packet headers
Packets are decomposed into its (ow control units) Flits are split into phits (physical units)
i.e. minimum datagram size transmitted in a single link transaction
Implements a Core Interface (CI) at the core side and a Network interface (NI) at network side.
CI implemented using standard sockets, Open Core Protocol (OCP) and the Virtual Component Interface (VCI) often used in SoCs.
S. Pellegrini (UIBK) On-Chip Networks December, 10 2009 6 / 23
Network (routing)
Delivers messages from a sender IP to a receiver core. A network is dened by its topology and the protocol implemented by it.
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Network Topology
Topologies can be distinguished in 2 categories: Regular most common typology k-ary n-cube k-ary tree k-ary n-dimensional fat tree Where k is the degree of each dimension and n is the number of dimensions. Irregular derived by mixing different forms in a hierarchical, hybrid, or asymmetric way (clustering)
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Network Topology
Topologies can be distinguished in 2 categories: Regular most common typology k-ary n-cube k-ary tree k-ary n-dimensional fat tree Where k is the degree of each dimension and n is the number of dimensions. Irregular derived by mixing different forms in a hierarchical, hybrid, or asymmetric way (clustering)
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Routing Protocol
The protocol concerns the strategy of moving data through the network Implemented in the routing node
Switch connections dictated by the routing algorithm
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Routing Protocol
Two main typology of networks exists: Circuit-switching a circuit from source to destination is set up and reserved until the transfer of data is completed Packet-switching packets are forwarded on a per-hop basis towards the destination core
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Routing Protocol
Two main typology of networks exists: Circuit-switching a circuit from source to destination is set up and reserved until the transfer of data is completed Packet-switching packets are forwarded on a per-hop basis towards the destination core Packet-switching is preferred
optimize link utilization, tolerant to link faults, etc.
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Forward Strategies
Store-and-forward the node stores the complete packet and forwards it based on the information within its header. Wormhole the node looks at the header of the packet (stored in the rst it) to determine its next hop and immediately forwards it. The subsequent its are forwarded as they arrive to the same destination node. Virtual cut-through works like the wormhole routing but before forwarding a packet the node waits for a guarantee that the next node in the path will accept the entire packet.
On-Chip Networks
December, 10 2009
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Forward Strategies
Store-and-forward the node stores the complete packet and forwards it based on the information within its header. Wormhole the node looks at the header of the packet (stored in the rst it) to determine its next hop and immediately forwards it. The subsequent its are forwarded as they arrive to the same destination node. Virtual cut-through works like the wormhole routing but before forwarding a packet the node waits for a guarantee that the next node in the path will accept the entire packet. Wormhole routing is widely used in NoCs as no buffering is required: it attains a minimal packet latency small realization area
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Deterministic/Adaptive Routing
Once we know the destination core, the output port to which the message is forwarded can be done either statically or dynamically: Deterministic routing the path is determined by packet source and destination e.g. source routing and X-Y routing (2D dimension order routing). Adaptive routing the routing path is decided on a per-hop basis dynamic arbitration mechanisms, e.g. based on local/global link congestion.
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Deterministic/Adaptive Routing
Once we know the destination core, the output port to which the message is forwarded can be done either statically or dynamically: Deterministic routing the path is determined by packet source and destination e.g. source routing and X-Y routing (2D dimension order routing). Adaptive routing the routing path is decided on a per-hop basis dynamic arbitration mechanisms, e.g. based on local/global link congestion. Most of the NoCs implement deterministic routing as it is easier (requires less chip area) to implement
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Flow-Control
The network level is also responsible of ensuring the correct operation of the network avoiding (or recovering): Deadlock network resources are suspended waiting for each other to be released Livelock resources constantly change state waiting for other to nish
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Flow-Control
The network level is also responsible of ensuring the correct operation of the network avoiding (or recovering): Deadlock network resources are suspended waiting for each other to be released Livelock resources constantly change state waiting for other to nish Deadlocks can be avoided by using Virtual Channels (VC), multiple logical channels share a single physical channel when one logical channel stalls, the physical node can continue serving other logical channels
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Link
Point-to-point interconnection fast, low power and reliable As chip manufacturing technology scales down, the effects of wires on link delay and power consumption increase
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Link
Point-to-point interconnection fast, low power and reliable As chip manufacturing technology scales down, the effects of wires on link delay and power consumption increase Segmentation insert repeater buffers at a regular distance to keep the delay linearly dependent on the length of the wire Pipelining partition of long wires into pipeline stages is an effective way of increasing throughput
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Optical Interconnects
In future chip interconnects, optical wires will be used The idea consist in integrating the technology used in ber optic wires on the chip surface
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Metrics
Performance
Latency Bandwidth Jitter Power consumption Chip area
Cost
NoC design requires to nd a trade-off between application needs (usually expressed in terms of trafc requirements), area usage and power consumption
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NoC Design
Libraries which give a high level description of NoC components that can be assembled together to suite the application needs Parametrizability at system-level : the ease with which a system-level NoC characteristic can be changed at instantiation time. Granularity of NoC : describe the abstraction level at which a NoC component is described.
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Xpipes
Library of highly parameterised soft macros (network interface, switch and switch-to-switch link) Components are assembled together allowing system designers to explore several NoC designs (e.g. different topologies)
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Xpipes
Library of highly parameterised soft macros (network interface, switch and switch-to-switch link) Components are assembled together allowing system designers to explore several NoC designs (e.g. different topologies)
High degree of parameterisation: network-specic it size, maximum number of hops between any two nodes, etc. block-specic content of routing tables for source-based routing, switch I/O ports, number of virtual channels, etc.
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Xpipes
Network backbone characteristics: wormhole switching technique static routing algorithm called street sign routing emphasis on reliability (distributed error detection techniques are implemented at link level) links are pipelined in order to optimize throughput
segment size can be tailored to desired the clock speed
The delay for a it to traverse from across one link and node is 2N + M cycles where N is number of pipeline stages and M the switch stages
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XpipesCompiler
One of the main advantage of Xpipes over other NoC libraries is the provided tool set, i.e. the XpipesCompiler
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RAW Processor
RAW microprocessor is a general purpose multicore CPU exploit ILP across several CPU cores (called tiles) whose functional units are connected through a NoC design is optimized for low-latency communication NoC characteristics: Four 32-bit full-duplex networks (2 static and 2 dynamic) 2D mesh topology networks are integrated into the processors pipeline
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Networks
Static 2 static networks managed by a single router: 5-stage pipelined routing is performed by programming the static routers in a per-clock-basis
instruction stream generated by a compiler
data words are forwarded to the correct output buffer on arrival (1 clock latency per hop)
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Networks
Static 2 static networks managed by a single router: 5-stage pipelined routing is performed by programming the static routers in a per-clock-basis
instruction stream generated by a compiler
data words are forwarded to the correct output buffer on arrival (1 clock latency per hop) Dynamic 2 dynamic networks based on packet-switching and wormhole routing protocol memory network restricted usage model that uses deadlock avoidance general network usage is instead unrestricted
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Summary
Due to technology scaling computation is getting cheaper. Communication between cores is rapidly becoming the main source of power consumption.
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Summary
Due to technology scaling computation is getting cheaper. Communication between cores is rapidly becoming the main source of power consumption. Network On-Chip is the emerging solution
Embedded SoC systems General purpose CPUs (e.g. Tileras Tile-GX processor, 100 MIPS cores based on RAW design)
On-Chip Networks
December, 10 2009
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Summary
Due to technology scaling computation is getting cheaper. Communication between cores is rapidly becoming the main source of power consumption. Network On-Chip is the emerging solution
Embedded SoC systems General purpose CPUs (e.g. Tileras Tile-GX processor, 100 MIPS cores based on RAW design)
Practical and efcient programmability of NoC-based systems is one of the big challenges.
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December, 10 2009
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Thanks for your attention
Questions?
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December, 10 2009
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On-Chip Networks (NoCs)

December 10, 2009

On-Chip Network Overview

On-Chip Network Overview

Latency Bandwidth Jitter Power consumption Chip area

Thanks for your attention

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