Building a datapath

The basic design

CS240 Computer Organization

Department of Computer Science Wellesley College

Steve and Woz

o We build our first computer

using a simple edgetriggered clocking methodology.

State element 1

Combinational logic

State element 2

clock

one clock cycle

o Every instruction begins execution one clock edge and

completes execution on the next.

Datapath

17-2

Fetch
o To execute an instruction,

we must first fetch it from memory . . . o . . . and then increment the program counter (PC) to point to the next instruction.*

Add 4 Instruction Memory PC Read Address

Instruction

*Design decision: Instructions are four bytes long.

Datapath 17-3

MIPS instruction format*

instruction operation or opcode second register source operand shift amount

op
6 bits

rs
5 bits

rt
5 bits

rd
5 bits

shamt
5 bits

funct
6 bits
function code

first register source operand

register destination operand

*R-type (for register) or R-format include add, sub, and, or, and slt.
Datapath 17-4

add $t0, $s1, $s2

instruction operation or opcode second register source operand shift amount

000000
6 bits

10001
5 bits

10010
5 bits

01000
5 bits

00000
5 bits

100000
6 bits
function code

first register source operand

register destination operand

Datapath

17-5

Control unit signals

Datapath

17-6

Register file (32 words) and ALU

Control Unit(s) 4 RegWrite 5 Read Addr 1 Read Addr 2 Write Addr Write Data Read Data 1 32 overflow zero ALU result ALU control

Instruction

5 5 32

Read Data 2

32

ALU

*An explict RegWrite line is shown as data is not necessarily written back to the register file on every operation.
Datapath 17-7

lw $t0, 1200($t1)
instruction operation or opcode destination register offset

base register

op
6 bits

rs
5 bits

rt
5 bits

constant or address
16 bits

still 32 bits

*And, yes there is a sw reg1, offset_value(reg2).

Datapath 17-8

lw $t0, 1200($t1)
instruction operation or opcode destination register offset

base register

100011
6 bits

01001
5 bits

01000
5 bits

0000 0100 1011 0000

16 bits

still 32 bits

*And, yes there is a sw reg1, offset_value(reg2).

Datapath 17-9

lw $t0, 1200($t1)
Control Unit RegWrite 5 Read Addr 1 Read Addr 2 Write Addr Write Data 16 Read Data 2 Read Data 1 32 32 Address 4 ALU control MemWrite

Instruction
5

ALU

Data Memory
32 Write Data

Read Data

Sign Extend

32

MemRead 32

Datapath 17-10

Major problem dudes

An R-format instruction like add $t1, %t2, %t3 wants . . .
RegWrite
Read Addr 1

Instruction Memory PC Read Address Instruct

ALU control zero

Read Read Addr 2 Data 1 Write Addr Write Data Read Data 2 ALU

and its write data from the ALU

write address from the third operand position

its second operand from Read Addr 2,

Datapath

17-11

While an . . .
I-format instruction like lw $t0, 1200($t2) wants . . .
RegWrite
Read Addr 1

MemWrite ALU control zero

Address ALU Data Memory Read Data Write Data

Instruction Memory PC Read Address Instruct

Read Read Addr 2 Data 1 Write Addr Write Data Read Data 2

write address from the second operand position

Sign 16 Extend

32

its second operand from offset field

MemRead

and its write data from memory

Datapath 17-12

Everyone is happy . . .
. . . by the addition of three muxs (guided by the munificent control unit)
RegDst RegWrite
Read Addr 1

ALUSrc ALU control zero

MemWrite

MemtoReg

Instruction Memory PC Read Address Instruct

Read Read Addr 2 Data 1 Write Addr Write Data Read Data 2 ALU

Address Data Memory Read Data Write Data

Sign 16 Extend

MemRead
32

Datapath 17-13

beq $s1, $s2, 100

instruction operation or opcode first operand second operand location

000100
6 bits

10001
5 bits

10010
5 bits

0000 0000 0010 0101

16 bits

still 32 bits

Datapath 17-14

beq $s1, $s2, 100

Add 4 Shift left 2 ALU control PC Instruction Read Addr 1 zero Read Read Addr 2 Data 1 Write Addr Read Data 2 Write Data ALU To branch control logic Add Branch target address

Sign 16 Extend

32

Datapath 17-15

beq $s1, $s2, 100

Add 4 Shift left 2 ALU control PC Instruction Read Addr 1 zero Read Read Addr 2 Data 1 Write Addr Write Data Read Data 2 ALU To branch control logic Add PCSrc

Sign 16 Extend

32

Datapath 17-16

Combining the fetch and data paths

Add 4
Shift left 2

Add

PCSrc MemWrite MemtoReg

RegDst

RegWrite
Read Addr 1

ALUSrc ALU control zero

Instruction Memory PC Read Address Instruct

Read Read Addr 2 Data 1 Write Addr Write Data Read Data 2 ALU

Address Data Memory Read Data Write Data

Sign 16 Extend

MemRead
32

Datapath 17-17

Now we add control

o . . . by decoding the

instruction to perform ALU, register file, and memory read/write operations, o . . . and to control the flow of data through multiplexer inputs, o . . . and to select proper registers.

Datapath 17-18