NOVEL MULTI-STAGE TRANSMULTIPLEXING DIGITAL DOWN CONVERTER FOR IMPLEMENTATION OF RFID (ISO18000-3 MODE 2) READER/WRITER

Yuichi Nakagawa1 , Masahiro Muraguchi1 , Hideki Kawamura2 , Kyoji Ohashi2 , Kei Sakaguchi3 , Kiyomichi Araki3 Graduate School of Science and Engineering, Tokyo University of Science, 1-14-6 Kudanshita, Chiyoda-ku, Tokyo, 102-0073 Japan, j4306647@ed.kagu.tus.ac.jp The Nippon Signal Co., Ltd., 11 Hiraide-Kogyo-Danchi, Utsunomiya, Tochigi, 321-8651 Japan. 3 Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro-ku, Tokyo, 152-8552 Japan.
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Abstract - Implementation of RFID reader/writer on software dened radio is studied in this paper. The target RFID is ISO18000-3 mode 2 which has 8 reply channels for simultaneous communication with 8 different RFID tags. In the software dened radio architecture, the 8 reply channels are sampled at a single A/D converter and separated by digital down converters, whereas conventional RFID architecture has redundant 8 parallel analog down converters. A novel multi-stage transmultiplexing digital down converter is proposed for efcient implementation of multi-channel digital down converter. Moreover the proposed architecture is implemented on a FPGA evaluation board, and validity of the system is conrmed on a real hardware. Keywords - RFID, ISO18000-3 mode 2, software dened radio, multi-stage transmultiplexing digital down converter, implementation on FPGA I. I NTRODUCTION In recent years, RFID (Radio Frequency IDentication) system becomes popular for development of ubiquitous networks. The RFID system consists of RFID tag which has built-in IC chip and reader/writer to communicate with the tag. The RFID system is expected to play an important role in many applications such as entrance management and physical distribution management[1]. ISO18000-3 mode 2[2], which is one of the standards of RFID, has 8 reply frequency channels for simultaneous communication with 8 different RFID tags. Conventional reader/writer has 8 parallel analog down converters with different local frequencies to realize simultaneous communications[3]. However such an architecture is not desirable because of the circuit size. This paper proposes a solution to the problem by utilizing software dened radio technology[4]. In the software dened radio architecture, the 8 reply channels are sampled at a single A/D converter and separated by Digital Down Converters (DDCs). A new architecture called multi-stage transmultiplexing DDC is proposed in this paper for size and computationally efcient implementation of parallel DDCs. It is an integration of conventional multi-stage FIR lter[5], [6] and transmultiplexer[7], [8]. The multi-stage FIR lter has been developed to realize sharp lter response with small number of taps. By connecting M -tap FIR lter in cascade way, M 2 equivalent taps can be achieved. Moreover, by inserting 1/N -decimator between them, M 2 N

equivalent taps can be realized. In recent days, 3-stage FIR lter is commonly used for computationally efcient DDC as in [4]. Transmultiplexer is used to convert frequency division multiplexing (FDM) signal to time division multiplexing (TDM) signal, and vice versa. A novel digital transmultiplexing architecture based on polyphase lter bank has been proposed for parallel DDCs as in [8]. Unfortunatly, since the channel spacing in the ISO18000-3 mode 2 standard is not uniform, the architecture can not be directly used for this purpose. In the proposed multi-stage transmultiplexing DDC, the transmultiplexer is placed between the stages of FIR lters so that the computational resources of the later stage lter can be shared among the different channels by means of TDM. In this paper, RFID reader/writer for ISO18000-3 mode 2 is designed by using multi-stage transmultiplexing DDC. As a result, 83% reduction of the number of multipliers can be achieved compared with conventional parallel DDCs. Moreover, the proposed architecture was implemented on a FPGA evaluation board, and validity of the system was conrmed on a real hardware. The organization of this paper is as follows. Firstly, Sec.II overviews the architecture of proposed multi-stage transmultiplexing DDC. Sec.III gives details on design of RFID reader/writer for ISO18000-3 mode2 standard including the specications of multi-stage transmultiplexing DDC. Computer simulation and implementation on FPGA of proposed architecture follow them in Sec.IV and Sec.V respectively. Finally, Sec.VI concludes this paper. II. M ULTI - STAGE TRANSMULTIPLEXING DIGITAL DOWN
CONVERTER

First of all, general concept of the proposed multi-stage transmultiplexing DDC is explained in this section. Fig. 1(a) shows block diagram of conventional multi-channel multi-stage DDC, and its evolution to multi-stage transmultiplexing DDC is shown in Fig. 1(b). In the conventional DDC, the input FDM signals are individually down converted by multiplying N different local frequencies, and N parallel multi-stage lters follow them. In this case the multi-stage lters composed of two FIR lters and 1/N -decimator in-between. Since there are N parallel down converters, N times computational resources are required in this architecture. In the proposed DDC as illustrated in Fig. 1(b), the N 1/N decimators in the conventional DDCs are replaced by transmultiplexer where N different channel signals are multiplexed in

1550-2252/$25.00 2007 IEEE

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Channel 1 Filter1 Channel 2 N Filter2

Channel 1 Filter1 Channel 2 Filter1 N Filter2 Filter1 Filter2 Channel 1 N

TDM

FDM

Channel N Filter1

Filter2

Channel N Filter1 First stage

First stage Decimation Second stage

Transmultiplexing

Second stage

(a) Multi-channel multi-stage DDC

(b) Multi-stage transmultiplexing DDC

Fig. 1. Block diagram of proposed and conventional multi-channel DDC.

Channel Channel Channel

#N
FDM

#N t t #2 #1
Fs / N

TDM

#N #1 #2
N Ts

#2 #1 f
Fs Ts

Ts

Ts

Time

Ts

Time

Frequency

Frequency

<Input signal>

<Down conversion + Filteing +1/ N Decimation>

<Transmultiplexing>

Fig. 2. Principles of multi-stage transmultiplexing DDC. time domain. Therefore the computational resources of the second FIR lter can be shared among N different channels. The visual image of this concept is illustrated in Fig. 2. Firstly, the input FDM signals are sampled at time interval of Ts to satisfy the Nyquist rate of the input signals as illustrate in the left side of Fig. 2. It is assumed that there are N frequency channels in this case. Then the signals are down converted to baseband, ltered, and 1/N decimated as in the middle of Fig. 2, where the N different channels are aligned both in frequency and time domain. In the right side of Fig. 2, by introducing transmultiplexer instead of 1/N -decimators the FDM signals can be converted to TDM signals, so that the computational resources for different N channels can be reduced to 1/N while the number of multipliers required per unit time is kept constant1 . The more the number of stages, the more reduction of computational resources can be achieved in the proposed multi-stage transmultiplexing DDC. III. D ESIGN OF RFID READER / WRITER In this section, we will design a RFID reader/writer for ISO18000-3 mode 2 by applying the multi-stage transmultiplexing DDC proposed in Sec.II. A. Conventional RFID reader/writer ISO18000-3 mode 2 is one of the international standards of RFID system. Specications of ISO18000-3 mode 2 are listed
this design, hard coded multiplier is considered in the FIR lter to reduce the circuit size since the lter coefcients are not variable. Therefore the proposed architecture not just reduces the number of multiplier coefcients but it reduces the number of multipliers itself[9].
1 In

Table 1 RFID air interface standards. Parameter name Air interface standard Carrier frequency System Description ISO18000-3 ISO18000-3 mode 1 mode 2 13.56 MHz Passive (load modulation) Ach: 969 kHz Bch:1233 kHz Cch:1507 kHz 423.75Hz Dch:1808 kHz Ech:2086 kHz Fch:2465 kHz Gch:2712 kHz Hch:3013 kHz ASK BPSK Manchester MFM 24.48 kbps 105.9375 kbps

Tag R/W

Subcarrier frequencies

Subcarrier modulation

Data coding Bit rate

in Table 1 with that of mode 1[2]. Both ISO18000-3 mode 1 and mode 2 use the carrier frequency of 13.56 MHz. The mode 2 is a high data rate version of ISO18000-3 which has 8 reply channels for simultaneous communication with 8 different RFID tags in addition to the increased data rate of about 100 kbps. The block diagram of conventional RFID reader/writer of mode 2 is shown in Fig. 3. The reader/writer consists of antenna, transmitter, and receiver, and Micro Processing Unit (MPU). The transmitter transmits energy to activate the passive RFID

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Antenna

RFID tags
Phase Shifter Transmission Command
A/D

Digital down converter

I
Fc
LPF

16 16

I Q

Decimation
Q
LPF

Transmitter <Conventional>
LPF Detection

Ach
LPF A/D

/2
10

Bch
LPF A/D MPU

Local Oscillator for Ach Bch Cch Dch Ech Fch Gch Hch
I Q I Q I Q I Q I Q I Q I Q
Power [dB]

0 -10 -20 -30 -40 -50 -60 -70 -80 -6 -4 -2 0 2 Frequency [MHz] 4 6

Hch Receiver
LPF A/D

Fig. 3. Block diagram of conventional RFID reader/writer. tags as well as transmission commands through 13.56 MHz carrier frequency. In the receiver side, the carrier frequency of 13.56 MHz is rstly removed by diode detector, and then 8 parallel analog down converters are employed to separate the subcarriers. The 8 parallel baseband signals are sampled and decoded in the MPU. In this architecture, the 8 parallel analog down converters are obviously redundant, and not desirable due to the circuit size. B. Software dened radio architecture In the proposed RFID reader/writer, the 8 analog down converters are replaced with DDCs based on software dened radio (SDR) technology as shown in Fig. 4. In the SDR architecture, the 8 reply channels are sampled at a single A/D converter and separated by DDCs. We employed 13.56 MHz for the sampling clock of the A/D converter, since it is a base clock of the RFID system. Fig. 4(a) shows the block diagram of multi-channel DDCs. The IQ-DDC consists of numerically controlled local oscillator, two multipliers, two Low Pass Filters (LPFs), and two decimators. The local oscillator generates sine and cosine signals with a frequency of corresponding subcarrier. The LPF is designed to have a 1dB bandwidth of 254kHz and to have spurious level less than -40dB in the stop band. Fig. 4(b) shows an example of the frequency response of the LPF with single-stage FIR lter. Although the lter satises the requirements, the number of multipliers required in this lter is 420. Therefore, totally (420 2 + 2) 8 = 6736 multipliers are needed for 8-channel IQ-DDCs. It is obviously infeasible for practical implementation. One simple scheme to reduce the computational resources is to employ a symmetric FIR lter. Because of the symmetric property of the lter coefcients, the complexity of the lter can be reduced to a half by sharing the same coefcients. For further reduction of computational resources, the multi-stage transmultilexing DDC is introduced in following subsections. C. Multi-stage DDC In this design, 3-stage DDC is employed and its block diagram is shown in Fig. 5(a). There are three LPFs and two 1/4decimators between the LPFs for each channel. The rst stage is common for all channels, which selects the whole frequency band of the RFID system. The second stage selects the target

(a) Block diagram of multi-channel DDC (b) Frequency response of LPF

Fig. 4. RFID reader/writer based on SDR. Table 2 The number of multipliers in 3-stage DDC. of multipliers FIR lter Symmetric FIR lter DDC architecture 1-Stage 3-Stage 6736 930 3376 498

channel coarsely, and nally the third stage selects the target channel strictly with ne lter response. Frequency responses of each LPF are shown in Fig. 5(b) and total frequency response of three LPFs is shown in Fig. 5(c). As in Fig. 5(b), the pass bandwidth of the lters reduces according to the stages. The third lter has sharpest lter response while has a lot of spurious responses due to the decimation. The second lter selects the main lobe of the third lter while still have spurious responses. The rst lter selects the main lobe of the second lter and negates all spurious responses of the second lter in previous subsection. Finally, as in Fig. 5(c) the total frequency response of three lters satises the requirements of the LPF described in the single-stage lter design. The number of multipliers required for the designed 3-stage DDC is shown in Table 2 with that of single stage architecture. As can be seen, the multi-stage architecture drastically reduces the required multipliers. As a result, 498 multipliers are needed in this design of 3-stage DDC with symmetric FIR LPFs, which is still infeasible for practical implementation. D. Multi-stage transmultiplexing DDC Multi-stage transmultiplexing DDC proposed in Sec.II is introduced for further reduction of computational resources. Fig. 6 shows block diagram of the designed multi-stage transmultiplexing DDC. In this architecture, the different frequency channels are transmultiplexed in front of the second and third lters instead of decimation. By converting FDM into TDM, the computational resources in the lters can be shared in different time for different channels. In the second lter, 2 sets of 4 channels (A-Dch, E-Hch) are transmultiplexed instead of 1/4 decimation. Similarly in the third lter, I/Q signals of 8 channels (A-Hch),

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LPF2 LPF2

4 channel TDM 8 channel IQ TDM <Third Stage> 8channel(I/Q) FDM

/2

TDM
Ach Bch Cch Dch Ech Fch Gch Hch Ach Bch Cch Dch Ech Fch Gch Hch

<First Stage>
I

I Q I Q
LPF3

LPF1

A/D
Q /2

LPF1

LPF2 LPF2

/2

Ech Fch Gch Hch

Fig. 6. 3-stage transmultiplexing DDC.

(a) I A/D Q /2 Local Oscillator (b) 4
LPF2

(c)

Ach

(d)

(e)

(f)

LPF1

Table 3 The number of multipliers in 3-stage transmultiplexing DDC.

I Q

LPF3

Decimation
LPF1

Decimation
LPF2

4 /2 Local Oscillator

LPF3

Bch Cch Dch Ech Fch Gch Hch (a) Block diagram of 3-stage DDC
10 0 -10
Power [dB]
LPF1 LPF2 LPF3

I Q I Q I Q I Q I Q I Q I Q

of multipliers Mixer First LPF Second LPF Third LPF Total

Transmultiplexing without with 34 10 8 tapIQ 8 tapIQ = 16 = 16 10 tap8 chIQ 10 tap2 chIQ = 160 = 40 18 tap8 chIQ 18 tap = 288 = 18 498 84

10 0 -10 -20 -30 -40 -50 -60 -70 -80 -6 -4 -2 0 2 Frequency [MHz] 4 6 -6 -4 -2 0 2 Frequency [MHz] 4 6

-20 -30 -40 -50 -60 -70 -80

to the time sharing of the computational resources. From the result, it can be understood that the number of multipliers are reduced from 498 to 84 in the proposed DDC which is 83 % reduction. IV. C OMPUTER SIMULATION In computer simulation, reply signal of RFID tags with 8 different frequency channels are generated and connected to the designed RFID reader/writer. Frequency spectrum at each test point, (a), (b), (c), (d), (e), and (f) in Fig. 5, is measured and shown in Fig. 7. From these gures, we can understand the process of frequency conversion, ltering, and decimation of multistage DDC. Finally the desired channel is correctly selected in Fig. 7(f), which satises the requirement of spurious level less than -40 dB. To evaluate validity of the proposed DDC, Bit Error Rate (BER) performance are evaluated and shown in Fig. 8. There are three cases; the rst one is an ideal case where the baseband signal is directly connected to the decoder, the second one is a case of signal carrier where Ach signal is supplied to the DDC, the third one is a case of multi-carrier where 8 channels are supplied to the DDC. The BER performance of the case of single

(b) Frequency responses

(c) Total frequency response

Fig. 5. 3-stage DDC. i.e. 16 real numbered channels, are transmultiplexed instead of 1/4 decimation. As such 1/4 reduction and 1/16 reduction of circuit size at second and third lters respectively are realized. Further reduction can be achieved by doubling the sampling frequency. The number of multipliers required in the multi-stage DDC with and without transmultiplexing are shown in Table 3. In the proposed multi-stage transmultiplexing DDC, the required multipliers are drastically reduced according to the stages due

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10 0 -10 -20 -30 -40 -50 -60 -70 -80

Power [dB]

Power [dB]

RFID tags

Reader/Writer

-4 -2 0 2 4 6 Frequency [MHz] (b) First frequency conversion

-6

Antenna FPGA board Control PC

10 0 -10 -20 -30 -40 -50 -60 -70 -80

-1.5 -1 -0.5 0 0.5 1 Frequency [MHz] (c) First filtering

1.5

10 0 -10 -20 -30 -40 -50 -60 -70 -80

Power [dB]

Power [dB]

Fig. 9. Overview of the prototype handware. In this system, IDs of 100 RFID tags can be detected within 1 second. VI. CONCLUSION Implementation of RFID reader/writer on software dened radio was studied in this paper. The target RFID is ISO18000-3 mode 2 which has 8 reply channels for simultaneous communication with 8 different RFID tags. In the software dened radio architecture, the 8 reply channels are sampled at a single A/D converter and separated by digital down converters, whereas conventional RFID architecture has redundant 8 parallel analog down converters. A novel multi-stage transmultiplexing digital down converter was proposed for size and computationally efcient implementation of multi-channel digital down converter. Moreover the proposed architecture was implemented on an FPGA evaluation board, and validity of the system was conrmed on a real RFID system. R EFERENCES [1] K. Finkenzeller, RFID Handbook, Wiley, 2003. [2] Information technology AIDC techniques RFID for item management Air interface, Part 3: Parameters for air interface commmunications at 13.56 MHz, ISO/IEC FDIS 18000-3, 2003. [3] H. Kawamura, K. Ohashi, Y. Nakagawa, R. Komori, M. Muraguchi, K. Sakaguchi, and K. Araki, Implementation of RFID (ISO18000-3 mode 2) reader writer on software dened radio, SR2005-74, pp.55-72, 2005. [4] J. H. Reed, Software radio A modern approach to radio engineering, Prentice Hall PTR, 2002. [5] R. E. Crochiere and L. R. Rabiner, Multirate digital signal processing, Prentice Hall, 1983. [6] Y. C. Lim, R. Yang, and B. Liu, The design of cascaded FIR lters, IEEE Int. Symp. Circuits and Systems, vol.2, pp.181184, June, 1996. [7] H. Scheuermann and H. G ckler, A comprehensive suro vey of digital transmultiplexing methods, Proc. IEEE, vol.69, pp.14191450, Nov. 1981. [8] F. J. Harris, C. Dick, and M. Rice, Digital receivers and transmitters using polyphase lter banks for wireless communications, IEEE Trans. Microwave Theory and Tech., vol.51, no.4, pp.13951412, Apr. 2003. [9] Y. C. Lim, R. Yang, and D. Li, Signed power-of-two term allocation scheme for the design of digital lters, IEEE Trans. Circuits and Systems II, vol.46, no.5, pp.577584, May. 1999.

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-0.2 0 0.2 Frequency [MHz] (e) Second filtering

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-1.5 -1 -0.5 0 0.5 1 1.5 Frequency [MHz] (d) Second frequency conversion 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -0.4 -0.2 0 0.2 0.4 Frequency [MHz] (f) Third filtering

Power [dB]

Fig. 7. Frequency spectrum at each test point in Fig. 5(a).

0 10 10-1
Bit error rate
Ideal Single-carrier Multi-carrier

10-2 10-3 10-4 10-5 10-6 0 2 4 6 8 SNR [dB] 10 12

Fig. 8. Bit error rate performance. carrier is completely the same as ideal case. Due to the effect of adjacent channel interference, the BER performance of the case of multi-carrier is slightly degraded than that of the case of single carrier. From these simulation results, the validity of the proposed DDC is conrmed. V. I MPLEMENTATION OF RFID READER / WRITER ON FPGA For evaluation of feasibility of the proposed architecture, the RFID reader/writer was implemented on a FPGA evaluation board with FPGA (Xilinl Virtex-II Pro XC2V P50) and 14bit A/D converter. Overview of the system is shown in Fig. 9. The system consists of the control PC, conventional reader/writer, FPGA evaluation board, and tray-type antenna. The proposed multi-stage transmultiplexing DDC, frame detector, and MFM decoder were implemented on FPGA, while conventional reader/witer was used for transmitter. The base clock for the A/D converter and FPGA was 13.56MHz provided by the conventional reader/writer. In the left side of Fig. 9, there are 100 RFID tags in the tray-type antenna. In the display of control PC, the 64bits ID of each RFID tag is detected and shown.

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