Go ST7787

ST
Sitronix
1. Introduction 2. Features
ST7787
262K Color Single-Chip TFT Controller/Driver
The ST7787 is a single-chip controller/driver for 262K-color, graphic type TFT-LCD. It consists of 720 source line and 320 gate line driving circuits. This chip is capable of connecting directly to an external microprocessor, and accepts Serial Peripheral Interface (SPI), 8-bits/9-bits/16-bits/18-bits parallel interface. Display data can be stored in the on-chip display data RAM of 240x320x18 bits. It can perform display data RAM read/write operation with no external operation clock to minimize power consumption. In addition, because of the integrated power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
Single chip TFT-LCD controller/driver with display data RAM Display resolution: 240(H) x RGB x 320(V) Display data RAM (frame memory): 240 x 320 x 18-bits = 1,382,400 bits Operation Frequency: DC~30MHz (30MHz for 6 bits, 10MHz for 18 bits) Output: - 240ch source outputs (240RGB) - 320ch gate outputs - Common electrode output Display mode (color mode) - Full color mode (idle mode off): 262K-colors - Reduce color mode (idle mode on): 8-colors (1-bit for individual R, G, B color depth) Display resolution option - 240 x 320 Display with 240 x 18-bits x 320 display RAM Supported LC type option - MVA LC type (When LCM[1]=0,LCM[0]=0 ) - Transflective LC type (When LCM[1]=0,LCM[0]=1 ) - Transmissive LC type (When LCM[1]=1,LCM[0]=0 ) Supported data format on display host interface - 12-bits/pixel: RGB= (444) using the 1382k bits frame memory and LUT - 16-bits/pixel: RGB= (565) using the 1382k bits frame memory and LUT - 18-bits/pixel: RGB= (666) using the 1382k bits frame memory Supported MCU Interface - 3-line serial interface - 8-bits, 9-bits, 16-bits, 18-bits interface with 8080-series MCU - 8-bits, 9-bits, 16-bits, 18-bits interface with 6800-series MCU - 6-bits, 16-bits, 18-bits RGB interface with graphic controller Display features - Area scrolling - Partial display mode - Software programmable color depth mode Build-in circuit - DC/DC converter - Adjustable VCOM generation - Non-volatile (NV) memory to store initial register setting - Oscillator for display clock generation - Timing controller - 4 preset gamma curve for =1.0/1.8/2.2/2.5 (supporting Transflective) and 1 preset gamma curve for =2.2 (supporting MVA, Ttransmissive type LC) - Factory default value (contrast, module ID, module version, etc) are stored in NV memory - Line inversion, frame inversion NV Memory - 8-bits for ID1 - 7-bits for ID2 - 8-bits for ID3 - 8-bits for VCOM adjustment Supply voltage range - Analog supply voltage range (VDD to AGND): 2.45V 3.3V - I/O supply voltage range (VDDI to DGND): 1.65V 3.3V Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. 1
ST7787
Output voltage level - Source output voltage range (GVDD to AGND): 3.0V to 5.0V - Power supply range for driver circuit (AVDD to AGND): 5.2V (VDD=2.6V) to 6.0V (VDD=3.0V) - Output range of HIGH level of VCOM (VCOMH to AGND): 2.5V to 5.0V - Output range of LOW level of VCOM (VCOML to AGND): -2.5V to 0.0V - Output range of HIGH level of gate driver (VGH to AGND): +12V to +16.5V - Output range of LOW level of gate driver (VGL to AGND): -14V to 5V Lower power consumption, suitable for battery operated systems - CMOS compatible inputs - Optimized layout for COG assembly - Operate temperature range: -30 to +70
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2008.04.18
ST7787
3. Pad arrangement
Dummy Dummy Dummy G317 Dummy Dummy G319 Dummy Dummy EXTC DGNDO IM0 VDDIO IM1 DGNDO IM2 VDDIO P68 DGNDO RCM0 VDDIO RCM1 DGNDO SRGB VDDIO SMX DGNDO SMY VDDIO IDM DGNDO REV VDDIO RL DGNDO TB VDDIO SHUT DGNDO GS LCM1 LCM0 VDDIO TP0 TP1 TP2 TP3 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 DGNDO Dummy TEST_EN D7 D6 D5 D4 D3 D2 D1 D0 TPO0 TPO1 TPO2 TPO3 TPO4 TPO5 TPO6 TPO7 OSC TE CSX RDX WRX SDA Dummy AUTO RESX DGND D/CX DGND PCLK DGND DE HS VS DGND DGND DGND DGND DGND DGND DGND DGND VDDI VDDI VDDI VDDI VREF VREF VREF REGP REGPT VCC VCC VCC VCC VCC VCC Dummy Dummy VCI1 VCI1 VCI1 VCI1 AGND AGND AGND AGND AGND AGND AGND AGND VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDDO AVDDO AVDDS C1SO C1SO VC1S VC1S VC1S VC1S GVDD GVDD GVDD C11P C11P C11P C11P C11P C11P C11N C11N C11N C11N C11N C11N C12P C12P C12P C12P C12P C12P C12N C12N C12N C12N C12N C12N Dummy Dummy AGND AGND AGND AGND AGND AGND AGND AGND Dummy Dummy VCL VCL VCL VCLO VCLO VCLS C21P C21P C21P C21P C21N C21N C21N C21N C22P C22P C22P C22P C22N C22N C22N C22N C23P C23P C23P C23P C23N C23N C23N C23N Dummy Dummy VGL VGL VGL VGL VGLS Dummy Dummy VGH VGH VGHO VGHO VGHS Dummy Dummy VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VCOML VCOML VCOML VCOML VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM Dummy Dummy VPP VPP VPP VPP Dummy Dummy
View point: bump view Chip size (um): 19384 x 1170 PAD coordinate: pad center Coordinate origin: chip center Chip thickness (um): 300 Bump height (um): 15 Bump hardness (HV): 7525 Pad arrangement (Unit: um): Output: pad No. 1 ~ 1069 = 16 x 97
20 16
G1 Dummy
G3 Dummy
S2
S1 S3
97
45 18
Input: pad No. 1070 ~ 1335 = 55 x 110
Alignment mark (unit: um): (-9533,-248.77)
(9544,-248.77)
S719 Dummy
S718 S720
Dummy G2
Dummy G4
G318 Dummy Dummy Dummy
G320 Dummy Dummy
V1.7
2008.04.18
ST7787
4. Pad Center Coordinates
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PIN Name DUMMY DUMMY DUMMY DUMMY DUMMY G320 G318 G316 G314 G312 G310 G308 G306 G304 G302 G300 G298 G296 G294 G292 G290 G288 G286 G284 G282 G280 G278 G276 G274 G272 G270 G268 G266 G264 G262 G260 G258 G256 G254 G252 X 9612 9594 9576 9558 9540 9522 9504 9486 9468 9450 9432 9414 9396 9378 9360 9342 9324 9306 9288 9270 9252 9234 9216 9198 9180 9162 9144 9126 9108 9090 9072 9054 9036 9018 9000 8982 8964 8946 8928 8910 Y 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 PAD No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PIN Name G250 G248 G246 G244 G242 G240 G238 G236 G234 G232 G230 G228 G226 G224 G222 G220 G218 G216 G214 G212 G210 G208 G206 G204 G202 G200 G198 G196 G194 G192 G190 G188 G186 G184 G182 G180 G178 G176 G174 G172 X 8892 8874 8856 8838 8820 8802 8784 8766 8748 8730 8712 8694 8676 8658 8640 8622 8604 8586 8568 8550 8532 8514 8496 8478 8460 8442 8424 8406 8388 8370 8352 8334 8316 8298 8280 8262 8244 8226 8208 8190 Y 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72
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PAD No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PIN Name G170 G168 G166 G164 G162 G160 G158 G156 G154 G152 G150 G148 G146 G144 G142 G140 G138 G136 G134 G132 G130 G128 G126 G124 G122 G120 G118 G116 G114 G112 G110 G108 G106 G104 G102 G100 G98 G96 G94 G92 X 8172 8154 8136 8118 8100 8082 8064 8046 8028 8010 7992 7974 7956 7938 7920 7902 7884 7866 7848 7830 7812 7794 7776 7758 7740 7722 7704 7686 7668 7650 7632 7614 7596 7578 7560 7542 7524 7506 7488 7470 Y 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 PAD No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 PIN Name G90 G88 G86 G84 G82 G80 G78 G76 G74 G72 G70 G68 G66 G64 G62 G60 G58 G56 G54 G52 G50 G48 G46 G44 G42 G40 G38 G36 G34 G32 G30 G28 G26 G24 G22 G20 G18 G16 G14 G12 X 7452 7434 7416 7398 7380 7362 7344 7326 7308 7290 7272 7254 7236 7218 7200 7182 7164 7146 7128 7110 7092 7074 7056 7038 7020 7002 6984 6966 6948 6930 6912 6894 6876 6858 6840 6822 6804 6786 6768 6750 Y 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72
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PAD No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 PIN Name G10 G8 G6 G4 G2 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY S720 S719 S718 S717 S716 S715 S714 S713 S712 S711 S710 S709 S708 S707 S706 S705 S704 S703 S702 S701 S700 S699 S698 S697 S696 S695 S694 S693 S692 X 6732 6714 6696 6678 6660 6642 6624 6606 6588 6570 6552 6534 6516 6498 6480 6462 6444 6426 6408 6390 6372 6354 6336 6318 6300 6282 6264 6246 6228 6210 6192 6174 6156 6138 6120 6102 6084 6066 6048 6030 Y 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 PAD No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 PIN Name S691 S690 S689 S688 S687 S686 S685 S684 S683 S682 S681 S680 S679 S678 S677 S676 S675 S674 S673 S672 S671 S670 S669 S668 S667 S666 S665 S664 S663 S662 S661 S660 S659 S658 S657 S656 S655 S654 S653 S652 X 6012 5994 5976 5958 5940 5922 5904 5886 5868 5850 5832 5814 5796 5778 5760 5742 5724 5706 5688 5670 5652 5634 5616 5598 5580 5562 5544 5526 5508 5490 5472 5454 5436 5418 5400 5382 5364 5346 5328 5310 Y 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72
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PAD No. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 PIN Name S651 S650 S649 S648 S647 S646 S645 S644 S643 S642 S641 S640 S639 S638 S637 S636 S635 S634 S633 S632 S631 S630 S629 S628 S627 S626 S625 S624 S623 S622 S621 S620 S619 S618 S617 S616 S615 S614 S613 S612 X 5292 5274 5256 5238 5220 5202 5184 5166 5148 5130 5112 5094 5076 5058 5040 5022 5004 4986 4968 4950 4932 4914 4896 4878 4860 4842 4824 4806 4788 4770 4752 4734 4716 4698 4680 4662 4644 4626 4608 4590 Y 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 PAD No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 PIN Name S611 S610 S609 S608 S607 S606 S605 S604 S603 S602 S601 S600 S599 S598 S597 S596 S595 S594 S593 S592 S591 S590 S589 S588 S587 S586 S585 S584 S583 S582 S581 S580 S579 S578 S577 S576 S575 S574 S573 S572 X 4572 4554 4536 4518 4500 4482 4464 4446 4428 4410 4392 4374 4356 4338 4320 4302 4284 4266 4248 4230 4212 4194 4176 4158 4140 4122 4104 4086 4068 4050 4032 4014 3996 3978 3960 3942 3924 3906 3888 3870 Y 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72
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PAD No. 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 PIN Name S411 S410 S409 S408 S407 S406 S405 S404 S403 S402 S401 S400 S399 S398 S397 S396 S395 S394 S393 S392 S391 S390 S389 S388 S387 S386 S385 S384 S383 S382 S381 S380 S379 S378 S377 S376 S375 S374 S373 S372 X 972 954 936 918 900 882 864 846 828 810 792 774 756 738 720 702 684 666 648 630 612 594 576 558 540 522 504 486 468 450 432 414 396 378 360 342 324 306 288 270 Y 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 PAD No. 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 PIN Name S371 S370 S369 S368 S367 S366 S365 S364 S363 S362 S361 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY S360 S359 S358 S357 S356 S355 S354 S353 S352 S351 S350 S349 S348 S347 S346 S345 S344 S343 S342 S341 S340 S339 X 252 234 216 198 180 162 144 126 108 90 72 54 36 18 0 -18 -36 -54 -72 -90 -108 -126 -144 -162 -180 -198 -216 -234 -252 -270 -288 -306 -324 -342 -360 -378 -396 -414 -432 -450 Y 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715
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10
2008.04.18
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PAD No. 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 PIN Name S338 S337 S336 S335 S334 S333 S332 S331 S330 S329 S328 S327 S326 S325 S324 S323 S322 S321 S320 S319 S318 S317 S316 S315 S314 S313 S312 S311 S310 S309 S308 S307 S306 S305 S304 S303 S302 S301 S300 S299 X -468 -486 -504 -522 -540 -558 -576 -594 -612 -630 -648 -666 -684 -702 -720 -738 -756 -774 -792 -810 -828 -846 -864 -882 -900 -918 -936 -954 -972 -990 -1008 -1026 -1044 -1062 -1080 -1098 -1116 -1134 -1152 -1170 Y 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 PAD No. 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 PIN Name S298 S297 S296 S295 S294 S293 S292 S291 S290 S289 S288 S287 S286 S285 S284 S283 S282 S281 S280 S279 S278 S277 S276 S275 S274 S273 S272 S271 S270 S269 S268 S267 S266 S265 S264 S263 S262 S261 S260 S259 X -1188 -1206 -1224 -1242 -1260 -1278 -1296 -1314 -1332 -1350 -1368 -1386 -1404 -1422 -1440 -1458 -1476 -1494 -1512 -1530 -1548 -1566 -1584 -1602 -1620 -1638 -1656 -1674 -1692 -1710 -1728 -1746 -1764 -1782 -1800 -1818 -1836 -1854 -1872 -1890 Y 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715
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11
2008.04.18
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12
2008.04.18
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13
2008.04.18
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14
2008.04.18
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PAD No. 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 PIN Name S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY G1 G3 G5 G7 G9 G11 G13 G15 G17 G19 G21 G23 G25 G27 G29 G31 X -6228 -6246 -6264 -6282 -6300 -6318 -6336 -6354 -6372 -6390 -6408 -6426 -6444 -6462 -6480 -6498 -6516 -6534 -6552 -6570 -6588 -6606 -6624 -6642 -6660 -6678 -6696 -6714 -6732 -6750 -6768 -6786 -6804 -6822 -6840 -6858 -6876 -6894 -6912 -6930 Y 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.715 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 PAD No. 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 PIN Name G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 G59 G61 G63 G65 G67 G69 G71 G73 G75 G77 G79 G81 G83 G85 G87 G89 G91 G93 G95 G97 G99 G101 G103 G105 G107 G109 G111 X -6948 -6966 -6984 -7002 -7020 -7038 -7056 -7074 -7092 -7110 -7128 -7146 -7164 -7182 -7200 -7218 -7236 -7254 -7272 -7290 -7308 -7326 -7344 -7362 -7380 -7398 -7416 -7434 -7452 -7470 -7488 -7506 -7524 -7542 -7560 -7578 -7596 -7614 -7632 -7650 Y 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72
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15
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PAD No. 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 PIN Name G113 G115 G117 G119 G121 G123 G125 G127 G129 G131 G133 G135 G137 G139 G141 G143 G145 G147 G149 G151 G153 G155 G157 G159 G161 G163 G165 G167 G169 G171 G173 G175 G177 G179 G181 G183 G185 G187 G189 G191 X -7668 -7686 -7704 -7722 -7740 -7758 -7776 -7794 -7812 -7830 -7848 -7866 -7884 -7902 -7920 -7938 -7956 -7974 -7992 -8010 -8028 -8046 -8064 -8082 -8100 -8118 -8136 -8154 -8172 -8190 -8208 -8226 -8244 -8262 -8280 -8298 -8316 -8334 -8352 -8370 Y 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 PAD No. 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 PIN Name G193 G195 G197 G199 G201 G203 G205 G207 G209 G211 G213 G215 G217 G219 G221 G223 G225 G227 G229 G231 G233 G235 G237 G239 G241 G243 G245 G247 G249 G251 G253 G255 G257 G259 G261 G263 G265 G267 G269 G271 X -8388 -8406 -8424 -8442 -8460 -8478 -8496 -8514 -8532 -8550 -8568 -8586 -8604 -8622 -8640 -8658 -8676 -8694 -8712 -8730 -8748 -8766 -8784 -8802 -8820 -8838 -8856 -8874 -8892 -8910 -8928 -8946 -8964 -8982 -9000 -9018 -9036 -9054 -9072 -9090 Y 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72
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16
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PAD No. 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 PIN Name G273 G275 G277 G279 G281 G283 G285 G287 G289 G291 G293 G295 G297 G299 G301 G303 G305 G307 G309 G311 G313 G315 G317 G319 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY EXTC DGNDO IM0 VDDIO IM1 DGNDO IM2 VDDIO P68 X -9108 -9126 -9144 -9162 -9180 -9198 -9216 -9234 -9252 -9270 -9288 -9306 -9324 -9342 -9360 -9378 -9396 -9414 -9432 -9450 -9468 -9486 -9504 -9522 -9540 -9558 -9576 -9594 -9612 -9585 -9505 -9425 -9345 -9265 -9185 -9105 -9025 -8945 -8865 -8785 Y 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 344.72 486.72 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 PAD No. 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 PIN Name DGNDO RCM0 VDDIO RCM1 DGNDO SRGB VDDIO SMX DGNDO SMY VDDIO IDM DGNDO REV VDDIO RL DGNDO TB VDDIO SHUT DGNDO GS LCM1 LCM0 VDDIO TP0 TP1 TP2 TP3 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 DGNDO X -8705 -8625 -8545 -8465 -8385 -8305 -8225 -8145 -8065 -7985 -7905 -7825 -7745 -7665 -7585 -7505 -7425 -7345 -7265 -7185 -7105 -7025 -6945 -6865 -6785 -6705 -6625 -6545 -6465 -6385 -6305 -6225 -6145 -6065 -5985 -5905 -5825 -5745 -5665 -5585 Y -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28
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PAD No. 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 PIN Name DUMMY TEST_EN D7 D6 D5 D4 D3 D2 D1 D0 TPO0 TPO1 TPO2 TPO3 TPO4 TPO5 TPO6 TPO7 OSC TE CSX RDX WRX SDA DUMMY AUTO RESX DGND D/CX DGND PCLK DGND DE HS VS DGND DGND DGND DGND DGND X -5505 -5425 -5345 -5265 -5185 -5105 -5025 -4945 -4865 -4785 -4705 -4625 -4545 -4465 -4385 -4305 -4225 -4145 -4065 -3985 -3905 -3825 -3745 -3665 -3585 -3505 -3425 -3345 -3265 -3185 -3105 -3025 -2945 -2865 -2785 -2705 -2640 -2575 -2510 -2445 Y -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 PAD No. 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 PIN Name DGND DGND DGND VDDI VDDI VDDI VDDI VREF VREF VREF REGP REGPT VCC VCC VCC VCC VCC VCC DUMMY DUMMY VCI1 VCI1 VCI1 VCI1 AGND AGND AGND AGND AGND AGND AGND AGND VDD VDD VDD VDD VDD VDD VDD VDD X -2380 -2315 -2250 -2170 -2105 -2040 -1975 -1895 -1830 -1765 -1685 -1605 -1525 -1460 -1395 -1330 -1265 -1200 -1120 -1040 -960 -895 -830 -765 -685 -620 -555 -490 -425 -360 -295 -230 -150 -85 -20 45 110 175 240 305 Y -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28
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PAD No. 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 PIN Name VDD VDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDDO AVDDO AVDDS C1SO C1SO VC1S VC1S VC1S VC1S GVDD GVDD GVDD C11P C11P C11P C11P C11P C11P C11N C11N C11N C11N C11N C11N C12P C12P C12P C12P C12P C12P C12N X 370 435 515 580 645 710 775 840 905 970 1035 1100 1180 1245 1310 1375 1440 1505 1585 1650 1715 1795 1860 1925 1990 2055 2120 2200 2265 2330 2395 2460 2525 2605 2670 2735 2800 2865 2930 3010 Y -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 PAD No. 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 PIN Name C12N C12N C12N C12N C12N DUMMY DUMMY AGND AGND AGND AGND AGND AGND AGND AGND DUMMY DUMMY VCL VCL VCL VCLO VCLO VCLS C21P C21P C21P C21P C21N C21N C21N C21N C22P C22P C22P C22P C22N C22N C22N C22N C23P X 3075 3140 3205 3270 3335 3415 3495 3575 3640 3705 3770 3835 3900 3965 4030 4110 4190 4270 4335 4400 4465 4530 4595 4675 4740 4805 4870 4950 5015 5080 5145 5225 5290 5355 5420 5500 5565 5630 5695 5775 Y -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28
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PAD No. 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 PIN Name C23P C23P C23P C23N C23N C23N C23N DUMMY DUMMY VGL VGL VGL VGL VGLS DUMMY DUMMY VGH VGH VGHO VGHO VGHS DUMMY DUMMY VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VCOML VCOML VCOML VCOML VCOM X 5840 5905 5970 6050 6115 6180 6245 6325 6405 6485 6550 6615 6680 6745 6825 6905 6985 7050 7115 7180 7245 7325 7405 7485 7550 7615 7680 7745 7810 7875 7940 8020 8085 8150 8215 8280 8345 8410 8475 8555 Y -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 PAD No. 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 PIN Name VCOM VCOM VCOM VCOM VCOM VCOM VCOM DUMMY DUMMY VPP VPP VPP VPP DUMMY DUMMY X 8620 8685 8750 8815 8880 8945 9010 9090 9170 9250 9315 9380 9445 9525 9605 Y -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28 -450.28
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5. Block diagram
GVDD VREF VCI1
320 Gate buffer 720 Source buffer Voltage reference
Level shifter DAC Gamma circuit Gate decoder Level Shifter
Data Latch
VCOMH
Gamma Table
Vcom generator
VCOM VCOML
Display Ram 240 x 18 x 320
Display control
OSC
Color conversion LUT table
C11P
Instruction register
Mutiple OTP Booster 1/2/4
C11N C12P C12N C21P C21N C22P C22N
RGB I/F
MCU IF
C23P C23N
SMY SMX EXTC P68 IM [2:0] DC/X (SCL) CSX RDX WRX GS SRGB RCM [1:0] LCM [1:0]
SDA VSYNC HSYNC DE PCLK SHUT TB RL REV IDM
D[17:0]
VDD VDDI AVDD VCL VGH VGL
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6. Pin description 6.1 Power supply pin
Name VDD VDDI VPP AGND DGND I/O I I I I I Description Power supply for analog, digital system and booster circuit Power supply for I/O system Power supply for OTP circuit System ground for analog system and booster circuit System ground for I/O system and internal digital system Count 10 4 4 16 11 Connect pin VDD VDDI VPP GND GND
6.2 Interface logic pin

Name P68 I/O I Description -8080/6800 MCU interface mode select -P68=1, select 6800 MCU parallel interface -P68=0, select 8080 MCU parallel interface -If not used, please fix this pin at VDDI or DGND level -Selection for MCU parallel interface or serial interface -If not used, please connect this pin to VDDI or DGND IM2 MCU & SPI interface mode selection 0 SPI interface 1 MCU parallel interface -This signal will reset the device and it must be applied to properly initialize the chip -Signal is active low -Chip select input pin (Low is enable) -This pin can be permanently fixed Low in MCU interface mode only -Display data/command selection pin in MCU interface -D/CX=1: display data -D/CX=0: command data -In serial interface, this is used as SCL -If not used, please connect this pin to VDDI or DGND -Read enable in 8080 MCU parallel interface -Read/write operation enable pin in 6800 MCU parallel interface -If not used, please connect this pin to VDDI or DGND -Write enable in MCU parallel interface - Read/write operation enable pin in 8080 MCU parallel interface -If not used, please connect this pin to VDDI or DGND -In RGB interface, WRX are not used and should be connected to VDDI -When RCM1, RCM0=1X (RGB interface), this pin is used as serial input/output pin. -When RCM1, RCM0=0X (MCU interface), this pin is not used and please connect to VDDI or DGND level. The serial input/output pin in MCU interface mode is D0. -Monitoring pin of internal oscillator clock and is turned ON/OFF by S/W command -When this pin is inactive (function OFF), this pin is DGND level -If not used, please keep this pin open -When RCM=1 (RGB interface), D[17:0] are used as RGB interface data bus -When RCM=0 (MCU interface), D[17:0] are used as MCU parallel interface data bus -D0 is the serial input/output signal in serial interface mode -In serial interface, D[17:1] are not used and should be connected to VDDI or DGND -Tearing effect output pin to synchronies MCU to frame writing, activated by S/W command -External VSYNC signal input pin with MCU interface. -When this pin is not inactive, this pin is low -If not used, please open this pin -Pixel clock signal in RGB interface mode -If not used, please fix this pin at VDDI or DGND -Vertical sync. Signal in RGB interface mode -If not used, please fix this pin at VDDI or DGND -Horizontal sync. Signal in RGB interface mode -If not used, please fix this pin at VDDI or DGND -Data enable signal in RGB interface mode Count 1 Connect pin GND/VDDI
IM0~IM2
GND/VDDI
RESX CSX
I I
1 1
MCU MCU
D/CX (SCL)
MCU
RDX (E)
MCU
WRX
MCU
SDA
MCU DGND/VDDI
OSC
D[17:0]
I/O
18
MCU
TE
I/O
MCU
PCLK VS HS DE
I I I I
1 1 1 1
RGB interface RGB interface RGB interface RGB interface
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-If not used, please fix this pin at VDDI or DGND Note1. If CSX is connected to ground in parallel interface mode, there will be no abnormal visible effect on the display module. Also there will be no restriction on using the parallel Read/Write protocols, power On/Off sequences or other functions. Furthermore there will be no influence to the power consumption of the display module. Note2. When in 8-line parallel mode (IM2 , IM1, IM0 =001) then if some data or signal appears on D[17:8] then it will have no influence to the system. (D[17:8] can be connected to1 or 0) Note3. When CSX=1, there is no influence to the parallel and serial interface. Note4. 1 = VDDI level, 0 = DGND level.
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6.3 Mode selection pin
Name I/O Description -To use extended command set, please connect this pin to VDDI -During normal operation, please open this pin (internal Rpull-down=2M ) EXTC Enable/disable modification of extend command 0 Only use default command set Use extended command table 1 (command register can be modify by user) -Gamma arrangement selection pin when LCM[1]=0,LCM[0]=0 GS GC[7:0] Reg. LCM1 0 0 01H 1 1 02H 04H GS I 08H 01H 02H 1 X X X X X 0 0 04H 1 1 08H X 0 1 X Transmissive(TM) N/A Transflective(TR) 1.8 0 0 1 X X X X X 0 1 Transmissive(TM) N/A Transflective(TR) 1.8 Transflective(TR) 2.5 Transflective(TR) 1.0 Transflective(TR) 1.0 Transflective(TR) 2.5 MVA Transflective(TR) Curve 2.2 1 VDDI/GND LCM0 0 1 LC Type MVA Transflective(TR) Curve 2.2 Gamma Count Connect pin
EXTC
VDDI/GND
IDM
LCM1, LCM0
-Normal mode and Idle mode selection pin -Please refer RGB interface for detail usage IDM Enable/disable idle mode 0 Normal display (can be changed to Idle mode by S/W) 1 Idle mode enable -Liquid crystal (LC) type selection pins LCM[1:0] Selection of LC type 0 0 MVA 0 1 Transflective 1 0 Transmissive 1 1 Reserved -RGB or MCU interface mode selection pins RCM[1:0] Selection of MCU or RGB interface 00 0 MCU Interface 01 1 MCU Interface 10 2 RGB Interface (1) 11 3 RGB Interface (2) -RGB arrangement selection pin for color filter design SRGB RGB arrangement S1, S2, S3 filter order = R, G, B 0 S1, S2, S3 filter order = B, G, R 1 -Please refer chapter 14 for detail using -Scanning direction of source output selection pin SMX Scanning direction of source output 0 S1 -> S720 1 S720 -> S1 -Please refer chapter 14 for detail using -Scanning direction of gate output selection pin SMY Scanning direction of gate output 0 G1 -> G320
VDDI/GND
VDDI/GND
RCM1, RCM0
VDDI/GND
SRGB
VDDI/GND
SMX
VDDI/GND
SMY
VDDI/GND
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1 G320 -> G1 -Please refer chapter 14 for detail using -Polarity of source output selection pin REV Polarity of source output 0 Data not reverse 1 Data reverse -Please refer RGB interface for detail using -If not used, please fix this pin at VDDI or DGND -Display On/Off control pin In RGB interface SHUT Display On/Off 0 Display On 1 Display Off -Please refer RGB interface for detail using -If not used, please fix this pin at VDDI or DGND -Scanning direction of source output selection pin in RGB interface RL SMX Scanning direction of source output 0 0 S1 -> S720 0 1 S720 -> S1 1 0 S720 -> S1 1 1 S1 -> S720 -Please refer RGB interface for detail using -If not used, please fix this pin at VDDI or DGND level -Scanning direction of gate output selection pin in RGB interface TB SMY Scanning direction of gate output 0 0 G1 -> G320 0 1 G320 -> G1 1 0 G320 -> G1 1 1 G1 -> G320 -Please refer RGB interface for detail using -If not used, please fix this pin at VDDI or DGND -Enable/disable the automatic power-on sequence AUTO Automatic power-on sequence enable/disable 0 Reserved 1 Enable (auto mode) -Enable/disable the test mode TEST_EN Test mode enable/disable 0 Disable 1 Enable
REV
VDDI/GND
SHUT
VDDI/GND
RL
VDDI/GND
TB
VDDI/GND
AUTO
VDDI
TEST_EN
VDDI/GND
6.4 Driver output pin

Name S1 to S720 G1 to G320 VCI1 AVDD AVDDO AVDDS VC1S C1SO VCL VCLO VCLS VGH VGHO I/O O O I/O I O I I O I O I I O -Source driver output pins -Gate driver output pins -A reference voltage for step-up circuit 1 -Connect a capacitor for stabilization. -Power input pin for analog circuit block -In normal usage, connect it to AVDD -A power output pin that the voltage is generated from power block -Output of booster 1 circuit -Connect a capacitor for stabilization. - A reference voltage for step-up circuit 2 - A reference voltage for analog circuit including gamma, source and gate - Output of regulator in 2x boost system -Power input pin for VCOM circuit -In normal usage, connect it to VCL -A power output pin of step-up circuit 4 -When VCOML is higher than AGND, VCL=AGND -Connect a capacitor for stabilization - A reference voltage for step-up circuit 2 -Power input pin for gate driver circuit -In normal usage, connect it to VGH -Positive output pin of the step-up circuit 2 Description Count 720 320 4 7 2 1 4 2 3 2 1 2 2 Connect pin Capacitor Capacitor AVDD AVDD Capacitor C1S Capacitor VCL VCL VGH Capacitor
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VGHS VGL VGLO VGLS VREF I I O I O -Connect a capacitor for stabilization - A reference voltage for step-up circuit 2 -Power input pin for gate driver circuit -In normal usage, connect it to VGL -Negative output of the step-up circuit 2 -Connect a capacitor for stabilization - A reference voltage for step-up circuit 2 -Reference voltage for power circuit block. -Connect a capacitor for stabilization -A standard level for grayscale voltage generator -Connect a capacitor for stabilization. -When internal GVDD generator is not used, connect an external power supply (AVDD-0.5V) -Positive voltage output of VCOM -Connect a capacitor for stabilization -Negative voltage output of VCOM -Connect a capacitor for stabilization -A power supply for the TFT-LCD common electrode 1 2 2 1 3 VGH Capacitor VGL VGL Capacitor
GVDD
Capacitor
VCOMH VCOML VCOM C11P, C11N C12P, C12N C21P, C21N C22P, C22N C23P, C23N VDDIO DGNDO VCC REGP REGPT
O O O
8 8 8
Capacitor Capacitor Common electrode Step-up Capacitor
-Capacitor connecting pins for step-up circuit 1 (for AVDD)
24
-Capacitor connecting pins for step-up circuit 2 (for VGH, VGL, VCL)
24
Step-up Capacitor
O O O O
-VDDI voltage output level for monitoring -DGND voltage output level for monitoring -Monitoring pin of internal digital reference voltage -Connect a capacitor fir stabilization Test pin
8 9 6 2
Capacitor Open
6.5 Test pin

Name TPI, TPO Dummy I/O I/O Description -Test pins. In regular usage, please open these pins -These pins are dummy (have no function inside) -Can allow signal traces pass through under these pads on TFT glass Count 12 24 Connect pin Open Open
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7. Driver electrical characteristics 7.1 Absolute operation range
Item Symbol Rating Unit Supply voltage VDD - 0.3 ~ +4.6 V Supply voltage (Logic) VDDI - 0.3 ~ +4.6 V Supply voltage (Digital) VCC -0.3 ~ +4.6 V Driver supply voltage VGH-VGL -0.3 ~ +30.0 V Logic Input voltage range VIN 0.5 ~ VDDI + 0.5 V Logic Output voltage range VO 0.5 ~ VDDI + 0.5 V Operating temperature range TOPR -30 ~ +70 Storage temperature range TSTG -55 ~ +125 Note: If one of the above items is exceeded its maximum limitation momentarily, the quality of the product may be degraded. Absolute maximum limitation, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the recommend range.
7.2 ESD protection level

Test Condition C = 100 pF, R = 1.5k ohm. 3 times zapping/each pin, 1sec/per zapping C = 200 pF, R = 0.0 ohm. Machine Model 3 times zapping/each pin, 1sec/per zapping Note: connecter pin is DATA BUS, Power, CSX, RDX, WRX, RESX, TE. Model Human Body Model Protection Level 2500 for each pin 3000 for connecter pin 250 for each pin Unit V V
7.3 Latch-up protection level

The device will not latch up at trigger current level less than 100 mA.
7.4 Light Sensitivity

The operation of the IC will not be materially altered by incident light.
7.5 DC characteristic
Parameter Power & operation voltage System voltage Interface operation voltage Digital operating voltage Gate driver high voltage Gate driver low voltage Gate driver supply voltage I/O operating voltage OTP operation voltage Input / Output Logic-high input voltage Logic-low input voltage Logic-high output voltage Logic-low output voltage Logic-high input current Logic-low input current Input leakage current VCOM voltage VCOM high voltage VCOM low voltage VCOM amplitude Source driver Source output range Gamma reference voltage Source output settling time Output deviation voltage (Source output channel) Symbol VDD VDDI VCC VGH VGL | VGH-VGL | VPP VIH VIL VOH VOL IIH IIL IIL VCOMH VCOML VCOMAC Vsout GVDD Tr Vdev Below with 99% precision Sout >=4.2V, Sout<=0.8V 4.2V>Sout>0.8V Operating voltage Condition Operating voltage I/O supply voltage Digital supply voltage Min 2.45 1.65 1.65 10 -14 19 1.65 7.5 0.7VDDI VSS 0.8VDDI VSS -1 -0.1 2.5 -2.5 4.0 0.1 3.0 10 7.8 VDDI 0.3VDDI VDDI 0.2VDDI 1 +0.1 5.0 0.0 6.0 AVDD-0.1 5.0 14 20 15 Specification TYP Max 2.78 1.8/2.78 3.3 3.3 2.0 16.5 -5 30 3.3 Unit V V V V V V V V V V V V uA uA uA V V V V V us mV mV Note 1,2,3 Note 1,2,3 Note 1,2,3 Note 1,2,3 Note 1,2,3 Note 1,2,3 Note 1,2,3 Note 3 Note 3 Note 3 Note 4 Note 3 Note 4,5 Note 4,5 Related Pins Note 2 Note 2 Note 2 Note 3 Note 3 Note 3
IOH = -1.0mA IOL = +1.0mA VIN = VDDI or VSS IOH = -1.0mA Ccom=12nF Ccom=12nF |VCOMH-VCOML|
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Output offset voltage Step-up circuit Internal reference voltage 1st step-up (VDDx2) voltage 1st step-up (VDDx2) drop voltage VOFSET VREF AVDD VDDx2,dorp I AVDD = 2.5mA (include panel loading) 4.95 6.0 4% 35 mv % V % Note 6 Note 3 Note 3 Note 3
Linear range VLinear 0.2 AVDD-0.2 V Note 1: VDDI=1.65 to 3.3V, VDD=2.45 to 3.3V, AGND=DGND=0V, Ta=-30 to 70 Note 2, 3, 4: When the measurements are performed with LCD module, measured points are like below. Note 3: P68, CSX, RDX, WRX, D[17:0], D/CX, RESX, TE, PCLK, VS, HS, EXTC, GS, IDM, SCL, LCM[1:0], RCM[1:0], IM[2:0], SRGB, SMX, SMY, REV, SHUT, RL, TB and Test pins Note 5, Source channel loading= 2.2kohm , 10pF/channel, Gate channel loading=0.8kohm , 50pF/channel. Note 6, The Max. value is between measured point of note 4 and gamma setting value.
Fig. 7.5.1 Example of measured point on the panel
Fig. 7.5.2 Tr: the source output stabling time.
Fig. 7.5.3 Source output deviation (channel to channel).
-When Sout >=4.2V, Sout<=0.8V Max (S1, S2, S3, . , S720) Min (S1, S2, S3, . , S720) <= 20mV -When 4.2V>Sout>0.8V Max (S1, S2, S3, . , S720) Min (S1, S2, S3, . , S720) <= 6mV -Example When Sout level is 3.95V (Gray scale voltage) Max (S1, S2, S3, . , S720) = 3.96V Min (S1, S2, S3, , S720) = 3.944V Sout deviation =Max (S1, S2, S3, . , S720) Min (S1, S2, S3, . , S720) = 10mV <- Out of Spec
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7.6 Power consumption
Operation mode Inversion mode One Line -Normal mode One Line -Partial + Idle mode (40 lines) -Sleep-in mode One Line N/A Note 2 Note 3,4 N/A 1 1 1 2.5 0.65 9uA 1 1 1 2.8 0.8 9uA Image Note 1 Current consumption Typical Maximum IDDI IDD IDDI IDD (uA) (mA) (uA) (mA) 1 2.6 1 3.0
Notes: 1. All pixels black. 2. Grayscale from top to bottom. 3. Black & white checker board 8 by 8 4. Absolute worst case patterns: all pixels black.
Typical case: TA = 25 VDD = 2.78 V VDDI = 1.80 V Worst Case: TA = -30 to 70 VDD = 2.45 V to 3.3 V VDDI = 1.65 V to 3.3 V Includes process variance.
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8. Timing chart 8.1 Parallel interface characteristics: 18, 16, 9 or 8-bits bus (8080-series MCU interface)
Fig. 8.1.1 Parallel interface timing characteristics (8080-series MCU interface) Symbol Parameter Min Max TAST Address setup time 10 D/CX TAHT Address hold time (Write/Read) 10 TCHW Chip select H pulse width 0 TCS Chip select setup time (Write) 15 TRCS Chip select setup time (Read ID) 45 CSX TRCSFM Chip select setup time (Read RAM) 355 TCSF Chip select wait time (Write/Read) 10 TCSH Chip select hold time 10 TWC Write cycle 66 WRX TWRH Control pulse H duration 20 TWRL Control pulse L duration 20 TRC Read cycle (ID) 160 RDX (ID) TRDH Control pulse H duration (ID) 90 TRDL Control pulse L duration (ID) 45 TRCFM Read cycle (FM) 450 RDX (FM) TRDHFM Control pulse H duration (RAM) 90 TRDLFM Control pulse L duration (RAM) 355 TDST Data setup time 20 TDHT Data hold time 20 D[17:0] TRAT Read access time (ID) 40 TRATFM Read access time (FM) 340 TODH Output disable time 20 80 Note 1: VDDI=1.65 to 3.3V, VDD=2.45 to 3.3V, AGND=DGND=0V, Ta=-30 to 70 Signal Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description -
-(3-transfer for one pixel)
-(15Mhz)
When read ID data When read from frame memory
For maximum CL=30pF For minimum CL=8pF
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Fig. 8.1.2 Rising and falling timing for input and output signal
Fig.8.1.3 Chip selection (CSX) timing
Fig. 8.1.4 Write-to-read and read-to-write timing
NOTE: The rising time and falling time (Tr, Tf) of input signal and fall time are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals.
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8.2 Parallel interface characteristics: 18, 16, 9 or 8-bits bus (6800-series MCU interface)
TCHW CSX
VIH VIL
TCHW TCS TRCS/TRCSFM TCSH TCSF
D/CX
VIH VIL
TAST /WX
VIH VIL
TAHT
TWC E
VIL VIH
TWRL TWRH
D[17:0] write
VIH VIL
TDST
TDHT
RX
VIL
VIH
TRDH/TRDHFM E
VIL VIH
TRDL/TRDLFM
TRC/TRCFM TODH
TRAT/TRATFM D[17:0] read

VIH VIL
Fig. 8.2.1 Parallel interface timing characteristics (6800-series MCU interface) Symbol Parameter Min Max Unit Description TAST Address setup time 10 ns D/CX TAHT Address hold time (Write/Read) 10 ns TCHW Chip select H pulse width 0 ns TCS Chip select setup time (Write) 15 ns TRCS Chip select setup time (Read ID) 45 ns CSX TRCSFM Chip select setup time (Read FM) 355 ns TCSF Chip select wait time (Write/Read) 10 ns TCSH Chip select hold time 10 ns TWC Write cycle 66 ns WRX -(15Mhz) TWRH Control pulse H duration 20 ns TWRL Control pulse L duration 20 ns TRC Read cycle (ID) 160 ns RDX (ID) When read ID data TRDH Control pulse H duration (ID) 90 ns TRDL Control pulse L duration (ID) 45 ns TRCFM Read cycle (FM) 450 ns When read from frame RDX (FM) TRDHFM Control pulse H duration (FM) 90 ns memory TRDLFM Control pulse L duration (FM) 355 ns TDST Data setup time 20 ns TDHT Data hold time 20 ns For maximum CL=30pF D[17:0] TRAT Read access time (ID) 40 ns For minimum CL=8pF TRATFM Read access time (FM) 340 ns Output disable time 20 80 ns TODH Note 1: VDDI=1.65 to 3.3V, VDD=2.45 to 3.3V, AGND=DGND=0V, Ta=-30 to 70 Note 2: The rising time and falling time (Tr, Tf) of input signal and fall time are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. Signal
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8.3 Serial interface characteristics (3-line serial)
CSX
VIH VIL
TCHW TSCYCW/TSCYCR TCSS TCSH

VIH VIL
SCL
TSLW/TSLR TSHW/TSHR TSDS TSDH
TSCC
SDA
VIH VIL
TACC
TOH
VIH VIL
VIH VIL
SDA (DOUT)
Fig. 8.3.1 3-line serial interface timing Signal CSX Symbol TCSS TCSH TSCC TCHW TSCYCW TSHW TSLW TSCYCR TSHR TSLR TSDS TSDH TACC TOH Parameter Min Max Chip select setup time 60 Chip select hold time 60 Chip select setup time 20 Chip select setup time 40 Serial clock cycle (Write) 66 SCL H pulse width (Write) 20 SCL L pulse width (Write) 20 Serial clock cycle (Read) 150 SCL H pulse width (Read) 60 SCL L pulse width (Read) 60 Data setup time 10 Data hold time 10 Access time 10 Output disable time 15 Table 8.3: 3-line Serial Interface Characteristics Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description
SCL
SDA (DIN) (DOUT)
For maximum CL=30pF For minimum CL=8pF
Note 1: VDDI=1.65 to 3.3V, VDD=2.45 to 3.3V, AGND=DGND=0V, Ta=-30 to 70 Note 2: The rising time and falling time (Tr, Tf) of input signal and fall time are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals.
8.4 Vertical synchronizing signal timing characteristic
Fig. 8.4 Vertical synchronizing signal timing Symbol Parameter Min Max Unit tVCYC VSYNC Cycle 1F+2H VSYNC tVLW VSYNC Pulse L Width 1H 1F-1H tVHW VSYNC Pulse H Width 3H -Standing up standing fall time of the input signal(tr,tf) is provided for by 15ns or less. -The signal level is provided for based on 30% and 70% of VDDI-DGND -This is provided for while external VSYNC is synchronizing. -F indicates the time of one frame in internal synchronizition. -H indicates the time in internal synchronizition for one line. Signal Description
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9. Function description 9.1 Interface type selection
The selection of given interfaces are done by setting P68, IM2, IM1, and IM0 pins as shown in following table. P68 0 0 0 0 1 1 1 1 P68 0 0 0 0 1 1 IM2 0 1 1 1 1 0 1 1 1 1 IM2 0 1 1 1 1 1 1 IM1 0 0 1 1 0 0 1 1 IM1 0 0 1 1 0 0 IM0 0 1 0 1 0 1 0 1 IM0 0 1 0 1 0 1 Interface 3-line serial interface 8080 8-bit parallel 8080 16-bit parallel 8080 9-bit parallel 8080 18-bit parallel 3-line serial interface 6800 8-bit parallel 6800 16-bit parallel 6800 9-bit parallel 6800 18-bit parallel Interface 3-line serial interface 8080 8-bit parallel 8080 16-bit parallel 8080 9-bit parallel 8080 18-bit parallel 6800 8-bit parallel 6800 16-bit parallel Read back selection Via the read instruction RDX strobe (8-bit read data and 8-bit read parameter) RDX strobe (16-bit read data and 8-bit read parameter) RDX strobe (9-bit read data and 8-bit read parameter) RDX strobe (18-bit read data and 8-bit read parameter) Via the read instruction E strobe (8-bit read data and 8-bit read parameter) E strobe (16-bit read data and 8-bit read parameter) E strobe (9-bit read data and 8-bit read parameter) E strobe (18-bit read data and 8-bit read parameter) RDX Note1 RDX RDX RDX RDX E E WRX Note1 WRX WRX WRX WRX WRX WRX D/CX SCL D/CX D/CX D/CX D/CX RS RS RS RS Read back selection D[17:1]: unused, D0: SDA D[17:8]: unused, D7-D0: 8-bit data D[17:16]: unused, D15-D0: 16-bit data D[17:9]: unused, D8-D0: 9-bit data D17-D0: 18-bit data D[17:8]: unused, D7-D0: 8-bit data D[17:16]: unused, D15-D0: 16-bit data D[17:9]: unused, D8-D0: 9-bit data D17-D0: 18-bit data
1 1 1 0 6800 9-bit parallel E WRX 1 1 1 1 6800 18-bit parallel E WRX Note 1. Unused pins can be open, or connected to DGND or VDDI.
9.2 8080-series MCU parallel interface (P68=0)

The MCU can use on of following interfaces: 11-lines with 8-data parallel interface, 12-lines with 9-data parallel interface, 19-lines with 16-data parallel interface or 21-lines with 18-data parallel interface. The chip-select CSX (active low) enables/disables the parallel interface. RESX (active low) is an external reset signal. WRX is the parallel data write, RDX is the parallel data read and D[17:0] is parallel data. The graphics controller chip reads the data at the rising edge of WRX signal. The D/CX is the data/command flag. When D/CX=1, D[17:0] bits are either display data or command parameters. When D/C=0, D[17:0] bits are commands. The 6800-series bi-directional interface can be used for communication between the micro controller and LCD driver chip. The selection of this interface is done when P68 pin is in low state (DGND). Interface bus width can be selected with IM2, IM1 and IM0. The interface functions of 8080-series parallel interface are given in following table. RDX WRX D/CX Read back selection 0 1 Write 8-bit command (D7 to D0) 8-bit 1 1 Write 8-bit display data or 8-bit parameter (D7 to D0) 0 1 0 0 parallel 1 1 Read 8-bit display data (D7 to D0) 1 1 Read 8-bit parameter or status (D7 to D0) 0 1 Write 8-bit command (D7 to D0) 16-bit 1 1 Write 16-bit display data or 8-bit parameter (D15 to D0) 0 1 0 1 parallel 1 1 Read 16-bit display data (D15 to D0) 1 1 Read 8-bit parameter or status (D7 to D0) 0 1 Write 8-bit command (D7 to D0) 9-bit 1 1 Write 9-bit display data or 8-bit parameter (D8 to D0) 0 1 1 0 parallel 1 1 Read 9-bit display data (D8 to D0) 1 1 Read 8-bit parameter or status (D7 to D0) 0 1 Write 8-bit command (D7 to D0) 18-bit 1 1 Write 18-bit display data or 8-bit parameter (D17 to D0) 0 1 1 1 parallel 1 1 Read 18-bit display data (D17 to D0) 1 1 Read 8-bit parameter or status (D7 to D0) Note: applied for command code: DAh, DBh, DCh, 04h, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh P68 IM2 IM1 IM0 Interface
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9.2.1 Write cycle sequence
Fig. 9.2.1 8080-series WRX protocol Note: WRX is an unsynchronized signal (It can be stopped).
Fig. 9.2.2 8080-series parallel bus protocol, write to register or display RAM
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9.2.2 Read cycle sequence
The read cycle (RDX high-low-high sequence) means that the host reads information from display via interface. The driver sends data (D[17:0]) to the host when there is a falling edge of RDX and the host reads data when there is a rising edge of RDX.
Fig. 9.2.3 8080-series RDX protocol Note: RDX is an unsynchronized signal (It can be stopped).
Read parameter
Read display data
D[17:0] RESX 1
CMD
DM
PA
CMD
DM & data
Data
Data
CSX
D/CX
RDX
WRX
D[17:0]
CMD
DM
PA
CMD
DM & data
Data
Data
Host D[17:0] Host to LCD Driver D[17:0] LCD to Host
CMD Hi-Z
Hi-Z
CMD Hi-Z
Hi-Z
DM
PA1
DM & data
PAN-2
PAN-1
CMD: write command code PA: parameter or display data
Signals on D[17:0], D/CX, R/WX, E pins during CSX=1 are ignored.
Fig. 9.2.4 8080-series parallel bus protocol, read data from register or display RAM
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9.3 6800-Series Parallel Interface (P68=1)
The MCU uses a 11-lines 8-data parallel interface or 12-lines 9-data parallel interface or 19-lines 16-data parallel interface or 21-lines 18-data parallel interface. The chip-select CSX(active low) enables and disables the parallel interface. RESX (active low) is an external reset signal. The R/WX is the Read/Write flag and D[17:0] is parallel data. The Graphics Controller Chip reads the data at the falling edge of E signal when R/WX= 1 and Writes the data at the falling of the E signal when R/WX=0. The D/CX is the data/command flag. When D/CX=1, D[17:0] bits are display RAM data or command parameters. When D/C= 0, D[17:0] bits are commands. The 6800-series bi-directional interface can be used for communication between the micro controller and LCD driver chip. The selection of this interface is done when P68 pin is high state (VDDI). Interface bus width can be selected with IM2, IM1 and IM0. The interface functions of 6800-series parallel interface are given in Table 9.3.1. Table 9.3.1 The function of 6800-series parallel interface P68 IM2 IM1 IM0 Interface D/CX R/WX E Function 0 0 Write 8-bit command (D7 to D0) 1 0 Write 8-bit display data or 8-bit parameter (D7 to D0) 1 1 0 0 8-bit Parallel 1 1 Read 8-bit Display data (D7 to D0) 1 1 Read 8-bit parameter or status (D7 to D0) 0 0 Write 8-bit command (D7 to D0) 1 0 Write 16-bit display data or 8-bit parameter (D15 to D0) 1 1 0 1 16-bit Parallel 1 1 Read 16-bit Display data (D15 to D0) 1 1 Read 8-bit parameter or status (D7 to D0) 0 0 Write 8-bit command (D7 to D0) 1 0 Write 9-bit display data or 8-bit parameter (D8 to D0) 1 1 1 0 9-bit Parallel 1 1 Read 9-bit Display data (D8 to D0) 1 1 Read 8-bit parameter or status (D7 to D0) 0 0 Write 8-bit command (D7 to D0) 1 0 Write 18-bit display data or 8-bit parameter (D17 to D0) 1 1 1 1 18-bit Parallel 1 1 Read 18-bit Display data (D17 to D0) 1 1 Read 8-bit parameter or status (D7 to D0) Note: applied for command code: DAh, DBh, DCh, 04h, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh.
9.3.1 Write cycle sequence

The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write cycle (E low-high-low sequence) consists of 3 control (D/CX, E, R/WX) and data signals (D[17:0]). D/CX bit is a control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is low (=0) and vice versa it is data (=1).
Fig. 9.3.1 6800-Series Write Protocol
Note: E is an unsynchronized signal (It can be stopped)
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Fig. 9.3.2 6800-series parallel bus protocol, write to register or display RAM
9.3.2 Read cycle sequence

The write cycle means that the host reads information (command or/and data) to the display via the interface. Each read cycle (E low-high-low sequence) consists of 3 control (D/CX, E, R/WX) and data signals (D[17:0]). D/CX bit is a control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is low (=0) and vice versa it is data (=1).
Fig. 9.3.3 6800-series read protocol Note: E is an unsynchronized signal (It can be stopped)
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Read parameter Read display data D[17:0] RESX 1
S CMD DM PA CMD DM & data Data Data P
CSX
D/CX
R/WX
D[17:0]
CMD
DM
PA
CMD
DM & data
Data
Data
Host D[17:0] Host to LCD Driver D[17:0] LCD to Host
CMD Hi-Z
Hi-Z
CMD Hi-Z
Hi-Z
DM
PA1
DM & data
PAN-2
PAN-1
CMD: write command code PA: parameter or display data
Signals on D[17:0], D/CX, R/WX, E pins during CSX=1 are ignored.
Fig. 9.3.4 6800-series parallel bus protocol, read data form register or display RAM
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9.4 Serial interface
The selection of this interface is done by IM2. See the Table 9.4.1. Table 9.4.1 Serial Interface Type Selection P68 IM2 IM1 IM0 Interface - 0 - - 3-line Serial interface
Read back selection Via the read instruction (8-bit, 24-bit and 32-bit read parameter)
The serial interface is a 3-lines/ 9-bits bi-directional interface for communication between the micro controller and the LCD driver chip. The 3-lines serial use: CSX (chip enable), SCL (serial clock) and SDA (serial data input/output) Serial clock (SCL) is used for interface with MCU only, so it can be stopped when no communication is necessary.
9.4.1 Command Write Mode

The write mode of the interface means the micro controller writes commands and data to the LCD driver. 3-lines serial data packet contains a control bit D/CX and a transmission byte is transfrerred by the D/CX pin. If D/CX is low, the transmission byte is interpreted as a command byte. If D/CX is high, the transmission byte is stored in the display data RAM (Memory write command), or command register as parameter. Any instruction can be sent in any order to the DRIVER. The MSB is transmitted first. The serial interface is initialized when CSX is high. In this state, SCL clock pulse or SDA data have no effect. A falling edge on CSX enables the serial interface and indicates the start of data transmission.
3-Line Serial Data Stream Format

Transmission byte (TB) may be a Command or a Data
MSB
LSB
D/CXD7 D6 D5 D4 D3 D2 D1 D0
TB TB TB
D/CXD7 D6 D5 D4 D3 D2 D1 D0 D/CXD7 D6 D5 D4 D3 D2 D1 D0 D/CXD7 D6 D5 D4 D3 D2 D1 D0
Fig. 9.4.1 Serial interface data Stream format
When CSX is high, SCL clock is ignored. During the high time of CSX the serial interface is initialized. At the falling edge of CSX, SCL can be high or low (see Fig 6.1.1.2). SDA is sampled at the rising edge of CSX. D/CX indicates, whether the byte is command code (D/CX=0) or parameter/RAM data (D/CX=1). It is sampled when first rising edge of SCL (3-lines serial interface) . If CSX stays low after the last bit of command/data byte, the serial interface expects the D/CX bit (3-lines serial interface) at the next rising edge of SCL.
Fig. 9.4.2 3-line serial interface write protocol (write to register with control bit in transmission)
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9.4.2 Read Functions
The read mode of the interface means that the micro controller reads register value from the Driver. To do the micro controller first has to send a command (Read ID or register command) and then the following byte is transmitted in the opposite direction. After that CSX is required to go to high before a new command is send (see the below figure). The Driver samples the SDA (input data) at rising edge of SCL, but shifts SDA (output data) at the falling edge of SCL. Thus the micro controller is supported to read at the rising edge of SCL. After the read status command has been sent, the SDA line must be set to tri-state no later than at the falling edge of SCL of the last bit. 3-line serial protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read):
3-line serial protocol (for RDDID command: 24-bit read)
3-line Serial Protocol (for RDDST command: 32-bit read)
Fig. 9.4.4 3-line serial interface read protocol
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9.5 Data Transfer Break and Recovery
If there is a break in data transmission by RESX pulse, while transferring a Command or Frame Memory Data or Multiple Parameter command Data, before Bit D0 of the byte has been completed, then DRIVER will reject the previous bits and have reset the interface such that it will be ready to receive command data again when the chip select line (CSX) is next activated after RESX have been High state. See the following example
If there is a break in data transmission by CSX pulse, while transferring a Command or Frame Memory Data or Multiple Parameter command Data, before Bit D0 of the byte has been completed, then DRIVER will reject the previous bits and have reset the interface such that it will be ready to receive the same byte re-transmitted when the chip select line (CSX) is next activated. See the following example
If 1, 2 or more parameter command is being sent and a break occurs while sending any parameter before the last one and if the host then sends a new command rather than re-transmitting the parameter that was interrupted, then the parameters that were successfully sent are stored and the parameter where the break occurred is rejected. The interface is ready to receive next byte as shown below.
Fig.9.5.3 Write interrupts recovery (serial interface) If a 2 or more parameter command is being sent and a break occurs by the other command before the last one is sent, then the parameters that were successfully sent are stored and the other parameter of that command remains previous value.
Host (MCU to driver)
Fig. 9.5.1 Serial bus protocol, write mode interrupted by RESX
Host (MCU to driver)
Fig. 9.5.2 Serial bus protocol, write mode interrupted by CSX
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Fig. 9.5.4 Write interrupts recovery (both serial and parallel Interface )
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9.6 Data transfer pause
It will be possible when transferring a Command, Frame Memory Data or Multiple Parameter Data to invoke a pause in the data transmission. If the Chip Select Line is released after a whole byte of a Frame Memory Data or Multiple Parameter Data has been completed, then DRIVER will wait and continue the Frame Memory Data or Parameter Data Transmission from the point where it was paused. If the Chip Select Line is released after a whole byte of a command has been completed, then the Display Module will receive either the commands parameters (if appropriate) or a new command when the Chip Select Line is next enabled as shown below. This applies to the following 4 conditions: 1) Command-Pause-Command 2) Command-Pause-Parameter 3) Parameter-Pause-Command 4) Parameter-Pause-Parameter
9.6.1 Serial interface pause
Fig. 9.6.1 Serial interface pause protocol (pause by CSX)
9.6.2 Parallel interface pause
Fig. 9.6.2 Parallel bus pause protocol (paused by CSX)
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9.7 Data Transfer Modes
The Module has three kinds Color modes for transferring data to the display RAM. These are 12-bit Color per pixel, 16-bit Color per pixel and 18-bit Color per pixel. The data format is described for each interface. Data can be downloaded to the Frame Memory by 2 methods.
9.7.1 Method 1
The Image data is sent to the Frame Memory in successive Frame writes, each time the Frame Memory is filled, the Frame Memory pointer is reset to the start point and the next Frame is written.
9.7.2 Method 2
Image Data is sent and at the end of each Frame Memory download, a command is sent to stop Frame Memory Write. Then Start Memory Write command is sent, and a new Frame is downloaded.
Note: 1) These apply to all data transfer Color modes on both serial and parallel interfaces. 2) The frame memory can contain both odd and even number of pixels for both methods. Only complete pixel data will be stored in the frame memory.
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9.8 Data Color Coding 9.8.1 8-bit Parallel Interface (IM2, IM1, IM0=100) Different display data formats are available for three Colors depth supported by listed below. - 4k Colors, RGB 4,4,4-bit input, - 65k Colors, RGB 5,6,5-bit input,. - 262k Colors, RGB 6,6,6-bit input, 9.8.1.1 8-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=03h There are 2 pixels (6 sub-pixels) per 3-bytes.
Note1. The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data. Note 2.3-times transfer is used to transmit 1 pixel data with the 12-bit color depth information. Note 3. - = Don't care - Can be set to '0' or '1'
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9.8.1.2 8-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH=05h There are 1 pixel (3 sub-pixels) per 2-bytes.
RESX IM[2:0] CSX D/CX
1 100
WRX RDX R/WX E

6800-series control pins 1 8080-series control pins 0
D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 0 1 1 0 0
R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 Pixel n 16 bits
G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0
R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 Pixel n+1 16 bits
G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0
Look-up table for 65k color data mapping (16 bits to 18 bits)
18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green and MSB=Bit 4, LSB=Bit 0 for Red and Blue data. Note 2.2-times transfer is used to transmit 1 pixel data with the 16-bit color depth information. Note 3. - = Don't care - Can be set to '0' or '1'
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9.8.1.3 8-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH=06h There are 1 pixel (3 sub-pixels) per 3-bytes.
1 100
WRX RDX R/WX E

D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 0 1 1 0 0
R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 -
G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 Pixel n 18 bits
B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 -
R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 Pixel n+1 18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3. - = Don't care - Can be set to '0' or '1'
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9.8.2 16-Bit Parallel Interface (IM2,IM1, IM0=101) Different display data formats are available for three colors depth supported by listed below. - 4k colors, RGB 4,4,4-bit input - 65k colors, RGB 5,6,5-bit input - 262k colors, RGB 6,6,6-bit input
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9.8.2.1 16-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=03h There are 1 pixel (3 sub-pixels) per 1 bytes, 12-bit/pixel.
Note1. The data order is ad follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data. Note 2.1-times transfer (D11 to D0) is used to transmit 1 pixel data with the 12-bit color depth information. Note 3. - = Don't care - Can be set to '0' or '1'
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Note1. The data order is ad follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for Red and Blue data. Note 2.1-times transfer (D15 to D0) is used to transmit 1 pixel data with the 16-bit color depth information. Note 3. - = Don't care - Can be set to '0' or '1'
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Note1. The data order is ad follows, MSB=D15, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data. Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3. - = Don't care - Can be set to '0' or '1'
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9.8.3 9-Bit Parallel Interface (IM2, IM1, IM0=110) Different display data formats are available for three colors depth supported by listed below. - 262k colors, RGB 6,6,6-bit input 9.8.3.1 Write 9-bit data for RGB 6-6-6-bit input (262k-color) There are 1 pixel (6 sub-pixels) per 3 bytes, 18-bit/pixel.
1 110
WRX RDX R/WX E

D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 0 1 1 0 0
R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 Pixel n
G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0
R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 Pixel n+1
G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 5 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0
18 bits
18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
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9.8.4 18-Bit Parallel Interface (IM2, IM1, IM0=111) Different display data formats are available for three colors depth supported by listed below. - 4k colors, RGB 4,4,4-bit input - 65k colors, RGB 5,6,5-bit input - 262k colors, RGB 6,6,6-bit input.
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9.8.4.1 18-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=03h There are 1 pixel (3 sub-pixels) per 1 byte, 12-bit/pixel.
1 111
WRX RDX R/WX E

D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 0 1 1 0 0
R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 Pixel n 12 bits
R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 Pixel n+1 12 bits
R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 B3, Bit 3 B3, Bit 2 B3, Bit 1 B3, Bit 0 Pixel n+2
R4, Bit 3 R4, Bit 2 R4, Bit 1 R4, Bit 0 G4, Bit 3 G4, Bit 2 G4, Bit 1 G4, Bit 0 B4, Bit 3 B4, Bit 2 B4, Bit 1 B4, Bit 0 Pixel n+3
Look-Up Table for 4096 Color data mapping (12 bits to 18 bits)
18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
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9.8.4.2 18-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH=05h There are 1 pixel (3 sub-pixels) per 1 byte, 16-bit/pixel.
1 111
WRX RDX R/WX E

0 0 1 0 1 1 0 0
R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 Pixel n 16 bits
R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 Pixel n+1 16 bits
R3, Bit 4 R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 5 G3, Bit 4 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 B3, Bit 4 B3, Bit 3 B3, Bit 2 B3, Bit 1 B3, Bit 0 Pixel n+2
R4, Bit 4 R4, Bit 3 R4, Bit 2 R4, Bit 1 R4, Bit 0 G4, Bit 5 G4, Bit 4 G4, Bit 3 G4, Bit 2 G4, Bit 1 G4, Bit 0 B4, Bit 4 B4, Bit 3 B4, Bit 2 B4, Bit 1 B4, Bit 0 Pixel n+3
Look-up table for 65k color data mapping (16 bits to 18 bits)
18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for Red and Blue data. Note 2.1-times transfer is used to transmit 1 pixel data with the 16-bit color depth information. Note 3. - = Don't care - Can be set to '0' or '1'
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1 111
WRX RDX R/WX E

0 0 1 0 1 1 0 0
R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 Pixel n 18 bits
R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 5 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 Pixel n+1 18 bits
R3, Bit 5 R3, Bit 4 R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 5 G3, Bit 4 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 B3, Bit 5 B3, Bit 4 B3, Bit 3 B3, Bit 2 B3, Bit 1 B3, Bit 0 Pixel n+2
R4, Bit 5 R4, Bit 4 R4, Bit 3 R4, Bit 2 R4, Bit 1 R4, Bit 0 G4, Bit 5 G4, Bit 4 G4, Bit 3 G4, Bit 2 G4, Bit 1 G4, Bit 0 B4, Bit 5 B4, Bit 4 B4, Bit 3 B4, Bit 2 B4, Bit 1 B4, Bit 0 Pixel n+3
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Read, Green and Blue data. Note 2.1-times transfer (D17o D0) is used to transmit 1 pixel data with the 18-bit color depth information. Note 3. - = Don't care - Can be set to '0' or '1'
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9.8.5 3-line serial Interface Different display data formats are available for three colors depth supported by the LCM listed below. 4k colors, RGB 4-4-4-bit input 65k colors, RGB 5-6-5-bit input 262k colors, RGB 6-6-6-bit input 9.8.5.1 Write data for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=03h
Note 1. pixel data with the 12-bit color depth information Note 2. The most significant bits are: Rx3, Gx3 and Bx3 Note 3. The least significant bits are: Rx0, Gx0 and Bx0 Note 4. X = Don't care - Can be set to '0' or '1'
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9.8.5.2 Write data for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH=05h
Note 1. pixel data with the 16-bit color depth information Note 2. The most significant bits are: Rx4, Gx5 and Bx4 Note 3. The least significant bits are: Rx0, Gx0 and Bx0 Note 4. X = Don't care - Can be set to '0' or '1' 9.8.5.3 Write data for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH=06h
Note 1. pixel data with the 18-bit color depth information Note 2. The most significant bits are: Rx5, Gx5 and Bx5 Note 3. The least significant bits are: Rx0, Gx0 and Bx0 Note 4. X = Don't care - Can be set to '0' or '1'
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9.9 RGB interface 9.9.1 General Description The module uses 6, 16 and 18-bit parallel RGB interface which includes: VS, HS, DE, PCLK, D[17:0]. The interface is activated after Power On sequence (See section Power On/Off Sequence) Pixel clock (PCLK) is running all the time without stopping and it is used to entering VS, HS, DE and D[17:0] states when there is a rising edge of the PCLK. The PCLK cannot be used as continues internal clock for other functions of the display module e.g. Sleep In mode etc. Vertical synchronization (VS) is used to tell when there is received a new frame of the display. This is negative (0, low) active and its state is read to the display module by a rising edge of he PCLK signal. Horizontal synchronization (HS) is used to tell when there is received a new line of the frame. This is negative (0, low) active and its state is read to the display module by a rising edge of the PCLK signal. Data Enable (DE) is used to tell when there is received a RGB information that should be transferred on the display. This is a positive (1, high) active and its state is read to the display module by a rising edge of the PCLK signal. D[17:0] (18-bit: R5-R0, G5-G0 and B5-B0; 16-bit: R4-R0, G5-G0 and B4-B0) are used to tell what is the information of the image that is transferred on the display (When DE=1 and there is a rising edge of PCLK). D[17:0] can be 0 (low) or 1 (high). These lines are read by a rising edge of the PCLK signal.
The PCLK cycle is described in the following figure.
PCLK
VS, HS, DE D[17:0]
The host changes D[17:0], VS,HS and DE lines when there is a falling edge of the PCLK
The driver read the D[17:0], VS,HS and DE lines when there is a rising edge of the PCLK
Fig. 9.9.1 PCLK cycle
Note: PCLK is an unsynchronized signal (It can be stopped).
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9.9.2 General Timing Diagram
Fig. 9.9.2 RGB general timing diagram The image information must be correct on the display, when the timings are in range on the interface. However, the image information can be incorrect on the display, when timings are not out of range on the interface (Out of the range timings cannot on the host side). The correct image information must be displayed automatically (by the display module) on the next frame (vertical sync.) when there is returned from out of the range to in range interface timing.
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9.9.3 Updating Order on Display Active Area (Normal Display Mode On + Sleep Out) There is defined different kind of updating orders for display. These updating orders are controlled by H/W (SMX, SMY) and S/W (MX, MY, MV) bits.
Fig. 9.9.3 Updating order when MADCTLs MX=0 and MY=0
Vertical active counter (0 ~ 319) Vertical active counter (0 ~ 319)
Vertical active counter (0 ~ 319) Vertical active counter (0 ~ 319)
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Table 9.9.1 Rules for Updating Order Condition Horizontal Counter Return to 0 Increment by 1 Return to 0 Return to 0 Vertical Counter Return to 0 No change Increment by 1 Return to 0
An active VS signal is received Signal Pixel information of the active area is received An active HS signal between two active area lines The Horizontal counter is larger than 239 and the Vertical counter is larger than 319 Note 1. Pixel order is RGB on the display. Note 2. Data streaming direction from the host to the display is described in the following figure.
Fig. 9.9.3 Data streaming order for RGB interface 9.9.4 RGB Interface Bus Width set All 4-kinds of bus width can be available during RGB interface mode (selected by COLMOD (3Ah) command for 6-bit, 16-bit and 18-bit data width) VIPF[3:0] 0101 0110 VIPF[3:0] D17 R4 R5 D17 D16 R3 R4 D16 D15 R2 R3 D15 D14 R1 R2 D14 D13 R0 R1 D13 D12 x R0 D12 D11 G5 G5 D11 D10 G4 G4 D10 D9 G3 G3 D9 D8 G2 G2 D8 D7 G1 G1 D7 D6 G0 G0 D6 D5 B4 B5 D5 D4 B3 B4 D4 D3 B2 B3 D3 D2 B1 B2 D2 D1 B0 B1 D1 D0 x B0 D0 Bus width 16-bit data 18-bit data Bus width
x x x x x x x x x x R5 R4 R3 R2 R1 x x x x x x x x x x G5 G4 G3 G2 G1 x x x x x x x x x x B5 B4 B3 B2 B1 Note 1: When VIPF[3:0]=1110, 6-bit data width of 3-times transfer is used to transmit 1 pixel data with depth information. Note 2: Only VIPF[3:0]= 0101 , 0110 and 1110 are valid on RGB I/F, Others are invalid. Note 3. x Dont care, but need to set VDDI or DGND level. 1110
R0 x x 6-bit G0 x x data B0 x x the 18-bit color
9.9.5 RGB Interface Mode Set Table 9.9.5.1 RGB Interface Mode Set RGB I/F PCLK DE VS Mode RGB Mode 1 Used Used Used RGB Mode 2 Used Used Used
HS Used Used
Video Data bus D[17:0] Used Used
Register for Blanking Porch setting Not Used Used
Reference clock for Display Internal Oscillator Internal Oscillator
There are 2-kinds of RGB mode which is selected by RCM1 & RCM0 hardware pins. In RGB Mode 1 (RCM1, RCM0 = 10), writing data to frame memory is done by PCLK and Video Data Bus (D[17:0]), when DE is high state. The external synchronization signals (PCLK, VS and HS) are used for internal display signals. So, controller (host) must always transfer PCLK, VS, HS and DE signals to IC. In RGB Mode 2 (RCM1, RCM0 = 11), blanking porch setting of VS and HS signals are defined by RGBBPCTR (B5h) command. DE pin is used for data making. When DE pin is high, valid data is directly stored to frame memory. In the contrast, if DE pin is low the data of frame memory will keep same status.
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Table 9.9.5.2 MCU & RGB Interface Comparisons table
Function
Mode selection 1
Mode selection 2 Motion /Still selection Input data Input signal
RCM1, RCM0 "0x" 8080/ 6800 IF + SPI I/F MCU Mode IMx= IMx="00" 8080/ 6800 IF SPI I/F Motion or Still Still picture picture
D[17:0] CSX WRX (R/WX), RDX (E) Refer the WRX cycle Refer Internal Oscillator D0 D/CX = SCL CSX Refer SCL Refer Internal Oscillator
RCM1, RCM0
"11" RGB I/F + SPI I/Mode selection 1/F RGB Mode 1 RGB Mode 2 ICM='0' ICM='1' RGB-1 I/F + SPI I/F Motion or Still picture D[17:0] PCLK VS, HS, DE Refer PCLK Refer PCLK Still picture SDA H/W pin enable D/CX = SCL CSX Refer SCL Refer Internal Oscillator ICM='0' ICM='1' RGB-2 I/F + SPI I/F Motion or Still picture D[17:0] PCLK VS, HS, DE Refer PCLK Refer PCLK Still picture SDA H/W pin enable D/CX = SCL CSX Refer SCL Refer Internal Oscillator "10"
GRAM Write cycle GRAM Read Cycle Command setting SMX, SMY, SRGB TE Function Normal / Partial mode Idle Mode (IDM H/W pin) Display On/ Off (SHUT H/W pin) Data inverter setting (REV H/W pin)
D[7:0] D0 SDA SDA SDA SDA -If those register not change, those H/W pins are always valid. If those registers be changed, should be follow registers setting. -When Power On or H/W reset, those function follow H/W pins setting first. -By command setting -By command setting -By command setting -By command setting -By command setting -By Command setting -By IDM H/W pin -IDM On/OFF (39h/28h) are disable -By SHUT H/W pin -SLPIN(10h), SLPOUT(11h), Display On/OFF (29h/28h) are disable -By REV H/W pin -INVON/OFF (21h/20h) are disable -When DE='0' area, the data of GRAM will keep the same status. -By H/W pin -No commands conflict -Control by RGBBPCTR (B5h)
-By command setting -Dont care in this mode, but should be set to VDDI or DGND
DE H/W pin RL H/W pin TB H/W pin Blanking porch Colors format
-Dont care in this mode, but should be set to VDDI or DGND
-Dont care in this mode -Control by IFPF[2:0] of COLMOD(3A)
-The data latched by rising edge of PCLK when DE=1 -When display data coming the DE signal should be VDDI level -Dont care in this mode, but should be set to VDDI or DGND -Control by DE signal -Control by VIPF[3:0] of COLMOD(3A)
Note 1: RCM1 and RCM0 are H/W setting pins. Note 2: In RGB + SPI I/F (RCM="1x"), VS, HS, DE, PCLK and D[17:0] are Hi-Z by Driver and can be stop for Host, when ICM='1'. Note 3: In RGB + SPI I/F (RCM="1x"), the data deliver via GRAM Note 4: When Power on Driver IC should be detect SMX, SMY, SRGB H/W setting Note 5: When Power on Driver IC should be detect RCM1, RCM0 H/W setting and get into the I/F mode. Note 6: When Power on Driver IC should be detect LCM1, LCM0 H/W setting and get into the setting mode.
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9.9.6 RGB Interface Timing Diagram 9.9.6.1 General Timings for RGB I/F
Fig. 9.9.6 General timing of RGB interface Table 9.9.6.1 General Timing for RGB I/F Item Symbol Condition Min Specification Type. Max Unit ns ns ns ns ns ns ns ns ns ns
Pixel low pulse width TPCLKLT 12 Pixel high pulse width TPCLKHT 12 Vertical Sync. set-up time TVSST 15 Vertical Sync. hold time TVSSHT 15 Horizontal Sync. set-up time THSST 15 Horizontal Sync. hold time TVSSHT 15 Data Enable set-up time TDEST 15 Data Enable hold time TDEHT 15 Data set-up time TDST 15 Data hold time TDHT 15 Note 1: VDDI=1.65 to 3.3V, VDD=2.45 to 3.3V, AGND=DGND=0V, Ta=-30 to 70 (to +85 no damage) Note 2: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. Note 3. Data lines can be set to High or Low during blanking time Dont care. Note 4. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. Note 5. HP is multiples of eight PCLK.
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VS n frame n+1 frame n+2 frame
HS
PCLK
DE *
DE ** don't care Data
Frame data frame data DE * = RGB mode 1 DE ** = RGB mode 2 frame data RAM write command (2Ch) address set command (2Ah, 2Bh) data transfer (ICM="1") data transfer (ICM="1")
Fig. 9.9.7 RAM access via SPI interface in RGB mode Note: DP=0, EP=0, HSP=0 and VSP=0 of RGBCTR (B0h) command.
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9.9.6.2 RGB Interface Mode 1 Timing Diagram
Fig. 9.9.8 RGB mode 1 timing diagram Note: DP=0, EP=0, HSP=0 and VSP=0 of RGBCTR (B0h) command.
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Fig. 9.9.9 Vertical and horizontal timing of RGB interface
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Table 9.9.6.2 Vertical and Horizontal Timing for RGB I/F Item Vertical Timing Vertical cycle period Vertical low pulse width Vertical front porch Vertical back porch Vertical data start line Vertical blanking period Vertical active area Vertical refresh rate Horizontal Timing Horizontal cycle period Horizontal low pulse width Horizontal front porch Horizontal back porch Horizontal data start point Horizontal blanking period Horizontal active area Symbol TVP TVS TVFP TVBP TVBL TVDISP TVRR THP THS THFP THBP THS + THBP ff HS + fHBP TVS + TVBP TVS + TVBP + TVFP Frame rate Condition Min 326 2 2 2 4 6 61.75 272 2 2 2 30 1.0 32 320 65 Specification Typ. Max 330 4 4 4 8 10 68.25 512 256 256 256 256 Unit HS HS HS HS HS HS HS Hz PCLK PCLK PCLK PCLK PCLK us PCLK PCLK ns MHz
THBL 256 THDISP 240 TPCLKCYC 33.3 174 Pixel clock cycle TVRR=65Hz fPCLKCYC 5.8 30.0 Note 1. VDDI=1.65 to 3.3V, VDD=2.45 to 3.3V, AGND=DGND=0V, Ta=-30 to 70 (to +85 no damage) Note 2. Data lines can be set to High or Low during blanking time Dont care. Note 3. HP is multiples of eight PCLK.
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9.9.6.3 RGB Interface Mode 2 Timing Diagram
V back porch (TVS+TVBP) VS
1 frame (TVP) V front porch (TVFP)
HS
DE 1"
HS H back porch (THS+THBP) PCLK
1 line (THP) Valid data (THDISP) H front porch (THFP)
DE 1"
Data bus
Invalid
D1 D2 D3
Dn
Invalid
Latch data
Invalid
D1 D2 D3
Dn
Fig. 9.9.10 RGB mode 2 timing diagram
Fig. 9.9.11 RGB mode 2 vertical timing diagram
Note: DP=0, EP=0, HSP=0 and VSP=0 of RGBCTR (B0h) command.
Horizontal timing for RGB I/F

HS THS+THBP=10 PCLK D[17:0] Invalid THP= 260 PCLK PCLK THDISP=240 PCLK
THFP=10 PCLK Invalid
Fig. 9.9.12 RGB mode 2
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Fig. 9.9.13 RGB mode 2 idle mode timing diadram
Note: DP=0, EP=0, HSP=0 and VSP=0 of RGBCTR (B0h) command.
Fig. 9.9.14 Vertical and Horizontal in RGB interface
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Table 9.9.6.3 Vertical and Horizontal Timing for RGB I/F Item Vertical Timing Vertical cycle period Vertical low pulse width Vertical front porch Vertical back porch Vertical data start line Vertical blanking period Vertical active area Vertical refresh rate Horizontal Timing Horizontal cycle period Horizontal low pulse width Horizontal front porch Horizontal back porch Horizontal data start point Horizontal blanking period Horizontal active area Pixel clock cycle THBL THDISP TPCLKCYC fPCLKCYC Symbol TVP TVS TVFP TVBP TVBL TVDISP TVRR THP THS THFP THBP THS + THBP ff HS + fHBP TVS + TVBP TVS + TVBP + TVFP Frame rate Condition Min 323 1 1 1 2 3 61.75 243 1 1 1 1 0.196 3 33.3 5.1 Specification Type. Max 324 1 3 4 320 65 260 4 1023 1023 1023 1023 68.25 511 63 63 63 63 256 196 30 Unit HS HS HS HS HS HS HS Hz PCLK PCLK PCLK PCLK PCLK us PCLK PCLK ns MHz
10 20 240 182 5.48
TVRR=65Hz
Note 1. VDDI=1.65 to 3.3V, VDD=2.45 to 3.3V, AGND=DGND=0V, Ta=-30 to 70 (to +85 no damage) Note 2. Data lines can be set to High or Low during blanking time Dont care. Note 3. HP is multiples of eight PCLK.
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9.9.6.4 Power On Sequence on RGB Mode 2 The Driver operates power up and display ON by VDD, VDDI, SHUT, VS, HS, DE, PCLK on RGB mode 2 as show as following figure.
VDD VDDI VDD RESX SHUT PCLK HS DE
TVDD-VDDI
TRS-SH
TVDD-SH TPCLK-SH
1 VS
10
11
12
13
14
15
Display high voltage Display Source output Vcom output Gate output Internal counter Internal oscillator
TSH-LCD TSH-ON Blanking display (over 1 frame)
Display on Normal display Normal display Normal display
Fig. 9.9.15 Power-ON sequence in RGB mode 2 Table 9.9.6.4 Power ON AC Characteristics Characteristics Symbol Min VDD On to VDDI On TVDD-VDDI 0 VDDI/VDD on to falling edge of SHUT TVDD-SH 1 RESX to falling of SHUT TRS-SH 10 Signals input to falling edge of SHUT * TCLK-SH 1 Falling edge of SHUT to LCD power ON TSH-LCD Falling edge of SHUT to Display start TSH-ON Note 1: Signals mean VS, HS, DE and PCLK signal. Note 2: DP=0, EP=0, HSP=0 and VSP=0 of RGBCTR (B0h) command.
Typ
Max
120 10
Unit ns ms us PCLK ms VS
Remark
Note1
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9.9.6.5 Power OFF Sequence on RGB Mode 2 The Driver operates power off and display OFF by VDD, VDDI, SHUT, VS, HS and DE on RGB mode 2 as show as following figure.
TVDD-VDDI
RESX SHUT TOFF-VDD PCLK HS DE VS TSH-OFF
Display high voltage Display Source output Vcom output Gate output Internal counter Internal oscillator
Display on Normal display Normal display Normal display 0V 0V
Display off
Blanking display (over 1 frame)
Fig. 9.9.16 Power-OFF seqnence in RGB mode 2
Table 9.9.6.5 Power OFF AC Characteristics Characteristics Symbol Min VDDI On to VDD On TVDD-VDDI 0 Signals input to VDDI/VDD off TSH-OFF 1 Rising edge of SHUT to Display off TSH-OFF 2 Note 1: Signals mean VS, HS, DE and PCLK signal. Note 2: DP=0, EP=0, HSP=0 and VSP=0 of RGBCTR (B0h) command.
Typ
Max
Unit ns us VS
Remark Note1
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9.9.7 RGB Data Color Coding 9.9.7.1 16-bit/pixel Color Order on the RGB Interface
PCLK
Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit5, LSB=Bit0 for Green data and MSB=Bit4, LSB=Bit0 for Red and Blue data. Note 2. - Dont care, but need set to VDDI or DGND level.
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9.9.7.2 18-bit/pixel Color Order on the RGB Interface
PCLK
Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit5, LSB=Bit0 for Red, Green and Blue data. Note 2. - Dont care, but need set to VDDI or DGND level.
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9.9.7.3 6-bit/pixel Color Order on the RGB Interface
RESX
1 10or 11 1 1 1
RCM[1:0] VS HS DE
WRX PCLK D17 D16

-
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 -
G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 Pixel n 18 bits
B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 -
R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 Pixel n+1 18 bits
G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 -
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit5, LSB=Bit0 for Red, Green and Blue data. Note 2. - Dont care, but need set to VDDI or DGND level.
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9.10 Display Data RAM 9.10.1 Configuration The display module has an integrated 240x320x18-bit graphic type static RAM. This 1382,400-bit memory allows to store on-chip a 240xRGBx320 image with an 18-bpp resolution (262K-color). There will be no abnormal visible effect on the display when there is a simultaneous Panel Read and Interface Read or Write to the same location of the Frame Memory.
Fig. 9.10.1 Display data RAM organization
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9.10.2 Memory to Display Address Mapping 9.10.2.1 When using 240RGB x 320 resolution (SMX=SMY=SRGB=0)
Pixel 1 Pixel 2 -------Pixel 239 Pixel 240
Gate Out
Source Out
S1 RGB=0
S2
S3 RGB=1
S4 RGB=0
S5
S6 -------- S715 S716 S717 S718 S719 S720 RGB=1 RGB=0 RGB=1 RGB=0 SA ML=' 0 ' ML=' 1 ' B1 -------- R238 G238 B238 R239 G239 B239 0 319 -------1 318 -------2 317 -------3 316 -------4 315 -------5 314 -------6 313 -------7 312 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -------312 7 -------313 6 -------314 5 -------315 4 -------316 3 -------317 2 -------318 1 -------319 0 238 239 -------1 0 -------RGB Order RGB=1
1 2 3 4 5 6 7 8 | | | | | 313 314 315 316 317 318 319 320
RA MY=' 0 ' MY=' 1 ' 0 319 R0 1 318 2 317 3 316 4 315 5 314 6 313 7 312 | | | | | | | | | | | | | | | 312 7 313 6 314 5 315 4 316 3 317 2 318 1 319 0 MX=' 0 ' CA MX=' 1 '
G0
B0
R1
G1
| | | | |
| | | | |
| | | | |
| | | | |
0 239
1 238
Note RA = Row Address, CA = Column Address SA = Scan Address MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command MV =Scan direction parameter, D4 parameter of MADCTL command RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command
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9.10.3 Normal Display On or Partial Mode On, Vertical Scroll Off 9.10.3.4 When using 240RGB x 320 resolution
In this mode, contents of the frame memory within an area where column pointer is 00h to EFh and page pointer is 00h to 13Fh is displayed. To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0).
1). Example for Normal Display On (MX=MY=ML=0 ,SMX=SMY=0)

Scan Order
00h 00 10 20 30 40 50 60 01h 01 11 21 31 41 51 ---- ---- ---- ---- ---- EEh EFh 02 03 0W 0X 0Y 0Z 1 12 13 1W 1X 1Y 1Z 2 22 2X 2Y 2Z 3 32 3X 3Y 3Z | 42 4X 4Y 4Z | 5Y 5Z | 6Z | | | 240 x 320 x18 bit Fram e RAM | | SZ | UY UZ | V2 VX VY VZ | W2 WX WY WZ | X2 XX XY XZ 318 Y2 Y3 YW YX YY YZ 319 Z2 Z3 ZW ZX ZY ZZ 320
240 Columns
240 Columns
00h 01h 02h | | | | | | | | | | | | 13Dh 13Eh 13Fh
00 10 20 30 40 50 60
01 11 21 31 41 51
02 03 12 13 22 32 42
0W 0X 0Y 1W 1X 1Y 2X 2Y 3X 3Y 4X 4Y 5Y
0Z 1Z 2Z 3Z 4Z 5Z 6Z
240 R G B x 320
LCD Panel
S0 U0 V0 W0 X0 Y0 Z0 SZ UZ VZ WZ XZ YZ ZZ
S0 U0 V0 W0 X0 Y0 Z0
U1 V1 W1 X1 Y1 Z1
U1 V1 W1 X1 Y1 Z1
V2 W2 X2 Y2 Y3 Z2 Z3
VX WX XX YW YX ZW ZX
UY VY WY XY YY ZY
G1 G2 G3 | | | | | | | | | | | | G318 G319 G320
Display area =320 lines
2). Example for Partial Display On (PSL[7:0]=04h,PEL[7:0]=13Bh, MX=MV=ML=0 ,SMX=SMY=0)

Scan Order
00h 00 10 20 30 40 50 60 01h 01 11 21 31 41 51 ---- ---- ---- ---- ---- EEh EFh 02 03 0W 0X 0Y 0Z 1 12 13 1W 1X 1Y 1Z 2 22 2X 2Y 2Z 3 32 3X 3Y 3Z | 42 4X 4Y 4Z | 5Y 5Z | 6Z | | | 240 x 320 x18 bit Fram e RAM | | SZ | UY UZ | V2 VX VY VZ | W2 WX WY WZ | X2 XX XY XZ 318 Y2 Y3 YW YX YY YZ 319 Z2 Z3 ZW ZX ZY ZZ 320
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240 Columns
240 Columns
00h 01h 02h | | | | | | | | | | | | 13Dh 13Eh 13Fh
00 10 20 30 40 50 60
01 11 21 31 41 51
02 12 22 32 42
03 13
0W 0X 0Y 1W 1X 1Y 2X 2Y 3X 3Y 4X 4Y 5Y
0Z 1Z 2Z 3Z 4Z 5Z 6Z
240 RGB x 320 LCD Panel S0 U0 V0 W0 X0 Y0 Z0 SZ UZ VZ WZ XZ YZ ZZ
S0 U0 V0 W0 X0 Y0 Z0
U1 V1 W1 X1 Y1 Z1
U1 V1 W1 X1 Y1 Z1
V2 W2 X2 Y2 Y3 Z2 Z3
UY VY WY XY YY ZY
G1 G2 G3 | | | | | | | | | | | | G318 G319 G320
Non-Display area =4 lines
Display area =312 lines
Non-Display area =4lines
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9.10.4 Vertical Scroll Mode
There is vertical scrolling, which are determined by the commands Vertical Scrolling Definition (33h) and Vertical Scrolling Start Address (37h).
Fig. 9.10.2 Difference between Scrolling and original
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9.10.4.1 When using 240RGB x 320 resolution
When Vertical Scrolling Definition Parameters (TFA+VSA+BFA)=320. In this case, scrolling is applied as shown below.
1). Example for TFA =3, VSA=315, BFA=2, SSA=4, ML=0: Scrolling
240 Columns Scan Order
00h 00 10 20 30 40 50 60 01h 01 11 21 31 41 51 ---- ---- ---- ---- ---- EEh EFh 02 03 0W 0X 0Y 0Z 12 13 1W 1X 1Y 1Z 22 2X 2Y 2Z 32 3X 3Y 3Z 42 4X 4Y 4Z 5Y 5Z 6Z 240 x 320 x18 bit Fram e RAM S0 U0 V0 W0 X0 Y0 Z0 SZ UZ VZ WZ XZ YZ ZZ
240 Columns
00h 01h 02h | | | | | | | | | | | | 13Dh 13Eh 13Fh
U1 V1 W1 X1 Y1 Z1
V2 W2 X2 Y2 Y3 Z2 Z3
UY VY WY XY YY ZY
1 2 3 | | | | | | | | | | | | 318 319 320
SSA
00 10 20 40 50 60
01 11 21 41 51
02 03 12 13 22 42
0W 0X 0Y 1W 1X 1Y 2X 2Y 4X 4Y 5Y
0Z 1Z 2Z 4Z 5Z 6Z
240 R G B x 320
LCD Panel
S0 U0 V0 W0 X0 30 Y0 Z0 U1 V1 W1 X1 31 Y1 Z1 UY VY WY XY 3Y YY ZY SZ UZ VZ WZ XZ 3Z YZ ZZ
V2 W2 X2 32 Y 2 Y3 Z 2 Z3
VX WX XX 3X YW Y X ZW Z X
G1 G2 G3 | | | | | | | | | | | | G318 G319 G320
TFA
2). Example for TFA =3, VSA=315, BFA=2, SSA=4, ML=1: Scrolling: TFA and BFT are exchanged
240 Columns Scan Order 240 Columns
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VSA
BFA
00h 01h 02h | | | | | | | | | | | | 13Dh 13Eh 13Fh
00h 00 10 20 30 40 50 60
01h 01 11 21 31 41 51
S0 U0 V0 W0 X0 Y0 Z0
U1 V1 W1 X1 Y1 Z1
---- ---- ---- ---- ---- EEh EFh 02 03 0W 0X 0Y 0Z 320 12 13 1W 1X 1Y 1Z 319 22 2X 2Y 2Z 318 32 3X 3Y 3Z | 42 4X 4Y 4Z | 5Y 5Z | 6Z | | | 240 x 320 x18 bit Fram e RAM | | SZ | UY UZ | V2 VX VY VZ | W2 WX WY WZ | X2 XX XY XZ 3 Y2 Y3 YW YX YY YZ 2 Z2 Z3 ZW ZX ZY ZZ 1
00 10 W0 20 30 40 50 60
01 11 W1 21 31 41 51
02 03 12 13 W2 22 32 42
0W 0X 0Y 1W 1X 1Y WX WY 2X 2Y 3X 3Y 4X 4Y 5Y
240 R G B x 320
LCD Panel
SSA
S0 U0 V0 X0 Y0 Z0
U1 V1 X1 Y1 Z1
V2 X2 Y2 Y3 Z2 Z3
VX XX YW YX ZW ZX
UY VY XY YY ZY
0Z G1 1Z G2 W Z G3 2Z | 3Z | 4Z | 5Z | 6Z | | | | | SZ | UZ | VZ | XZ G318 YZ G319 ZZ G320
BFA
VSA
TFA
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9.10.5 Vertical Scroll Example
Case 1: TFA + VSA + BFA320 N/A. Do not set TFA + VSA + BFA320. In that case, unexpected picture will be shown. Case 2: TFA + VSA + BFA=320 (Scrolling) Example1) When MADCTL parameter ML=0, TFA=0, VSA=320, BFA=0 and VSCSAD=80.
Example2) When MADCTL parameter ML=1, TFA=30, VSA=290, BFA=0 and VSCSAD=80.
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9.11 Address Counter The address counter sets the addresses of the display data RAM for writing and reading. Data is written pixel-wise into the RAM matrix of DRIVER. The data for one pixel or two pixels is collected (RGB 6-6-6-bit), according to the data formats. As soon as this pixel-data information is complete the Write access is activated on the RAM. The locations of RAM are addressed by the address pointers. The address ranges are X=0 to X=239 (EFh) and Y=0 to Y=319 (13Fh). Addresses outside these ranges are not allowed. Before writing to the RAM a window must be defined into which will be written. The window is programmable via the command registers XS, YS designating the start address and XE, YE designating the end address. For example the whole display contents will be written, the window is defined by the following values: XS=0 (0h) YS=0 (0h) and XE=239 (EFh), YE=319 (13Fh). In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps around to YS and X increments to address the next column. In horizontal addressing mode (V=0), the X-address increments after each byte, after the last X-address (X=XE), X wraps around to XS and Y increments to address the next row. After the every last address (X=XE and Y=YE) the address pointers wrap around to address (X=XS and Y=YS). For flexibility in handling a wide variety of display architectures, the commands CASET, RASET and MADCTL (see section 10 command list), define flags MX and MY, which allows mirroring of the X-address and Y-address. All combinations of flags are allowed. Section 9.12 show the available combinations of writing to the display RAM. When MX, MY and MV will be changed the data bust be rewritten to the display RAM. For each image condition, the controls for the column and row counters apply as section. 9.12 below: Condition When RAMWR/RAMRD command is accepted Complete Pixel Read / Write action The Column counter value is larger than End Column (XE) The Column counter value is larger than End Column (XE) and the Row counter value is larger than End Row (YE) Column Counter Return to Start Column (XS) Increment by 1 Return to Start Column (XS) Return to Start Column (XS) Row Counter Return to Start Row (YS) No change Increment by 1 Return to Start Row (YS)
9.12. Memory Data Write/ Read Direction The data is written in the order illustrated above. The Counter which dictates where in the physical memory the data is to be written is controlled by Memory Data Access Control Command, bits B5 (MV), B6 (MX), B7 (MY) as described below.
Fig. 9.12.1 Data streaming order
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9.12.1 When 240RGBx320
MADCTL (36h)
Physical row point
MV 0 0 0 0 1 1 1 1
MX 0 0 1 1 0 0 1 1
MY 0 1 0 1 0 1 0 1
CASET Direct to Physical Column Pointer Direct to Physical Column Pointer Direct to (239-Physical Column Pointer) Direct to (239-Physical Column Pointer) Direct to Physical Row Pointer Direct to (319-Physical Row Pointer) Direct to Physical Row Pointer Direct to (319-Physical Row Pointer)
RASET Direct to Physical Row Pointer Direct to (319-Physical Row Pointer) Direct to Physical Row Pointer Direct to (319-Physical Row Pointer) Direct to Physical Column Pointer Direct to Physical Column Pointer Direct to (239-Physical Column Pointer) Direct to (239-Physical Column Pointer)
Note: Data is always written to the Frame Memory in the same order, regardless of the Memory Write Direction set by MADCTL bits B7 (MY), B6 (MX), B5 (MV). The write order for each pixel unit is
One pixel unit represents 1 column and 1page counter value on the Frame Memory.
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9.12.2 Frame Data Write Direction According to the MADCTL parameters (MV, MX and MY)
MADCTL Display Data Parameter Direction MV Normal 0 MX 0 MY 0
Image in the Image in the Driver Host (DDRAM) (MPU)
H/W position (0,0) X-Y address (0,0) X: CASET Y: RASET H/W position (0,0) X-Y address (0,0) X: CASET
F
Y-Mirror 0 0 1
F F
F
X-Mirror 0 1 0
Y: RASET H/W position (0,0)
B B
X-Y address (0,0) X: CASET Y: RASET
F
X-Mirror Y-Mirror 0 1 1
F
H/W position (0,0)
F
X-Y address (0,0) X: CASET
F
X-Y Exchange 1 0 0
B
H/W position (0,0) X-Y address (0,0) X: RASET
Y: RASET
F
X-Y Exchange Y-Mirror 1 0 1
Y: CASET H/W position (0,0) X-Y address (0,0) X: RASET Y: CASET H/W position (0,0)
F F
F
X-Y Exchange X-Mirror 1 1 0
B B
X-Y address (0,0) X: RASET Y: CASET
F
X-Y Exchange X-Mirror Y-Mirror 1 1 1
H/W position (0,0)
F B
X-Y address (0,0) X: RASET
Y: CASET
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9.13 Tearing Effect Output Line The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled or disabled by the Tearing Effect Line Off & On commands. The mode of the Tearing Effect signal is defined by the parameter of the Tearing Effect Line On command. The signal can be used by the MPU to synchronize Frame Memory Writing when displaying video images. 9.13.1 Tearing Effect Line Modes Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only:
tvdh= The LCD display is not updated from the Frame Memory tvdl= The LCD display is updated from the Frame Memory (except Invisible Line see below) Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking Information, there is one V-sync and 320 H-sync pulses per field.
thdh= The LCD display is not updated from the Frame Memory thdl= The LCD display is updated from the Frame Memory (except Invisible Line see above)
Note: During Sleep In Mode, the Tearing Output Pin is active Low.
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9.13.2 Tearing Effect Line Timings The Tearing Effect signal is described below:
Table 9.13.1 AC characteristics of Tearing Effect Signal Idle Mode Off (Frame Rate = 58.9 Hz) Symbol Parameter min max unit tvdl Vertical Timing Low Duration 13 tvdh Vertical Timing High Duration 1000 thdl Horizontal Timing Low Duration 33 thdh Horizontal Timing Low Duration 25 NOTE: The timings in Table 9.3.1 apply when MADCTL ML=0 and ML=1 500 ms s s s
description
The signals rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.
The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to avoid Tearing Effect:
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9.13.3 Example 1: MPU Write is faster than panel read. MCU to memory 1st TE output signal time Memory to LCD 1st Image on LCD Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical sync pulse of the Tearing Effect Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame refresh has a complete new image: 320nd time 320nd time
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9.13.4 Example 2: MPU write is slower than panel read.
The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync pulse of the Tearing Effect Output Line. This allows time for the image to download behind the Panel Read pointer and finishing download during the subsequent Frame before the Read Pointer catches the MPU to Frame memory write position.
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9.14 Preset Values ST7787 will set preset values on our production line for each display module. Any of these preset values do not need customers SW support.
9.15 Power ON/OFF Sequence The power on/off sequence is illustrated below:
9.15.1 Uncontrolled Power Off The uncontrolled power off means a situation when e.g. there is removed a battery without the controlled power off sequence. There will not be any damages for the display module or the display module will not cause any damages for the host or lines of the interface. 2. At an uncontrolled power off the display will go blank and there will not be any visible effects within (TBD) second on the display (blank display) and remains blank until Power On Sequence powers it up.
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9.16 Power Level Definition 9.16.1 Power Level 6 level modes are defined they are in order of Maximum Power consumption to Minimum Power Consumption: 1. Normal Mode On (full display), Idle Mode Off, Sleep Out. In this mode, the display is able to show maximum 262,144 colors. 2. Partial Mode On, Idle Mode Off, Sleep Out. In this mode part of the display is used with maximum 262,144 colors. 3. Normal Mode On (full display), Idle Mode On, Sleep Out. In this mode, the full display area is used but with 8 colors. 4. Partial Mode On, Idle Mode On, Sleep Out. In this mode, part of the display is used but with 8 colors. 5. Sleep In Mode In this mode, the DC: DC converter, Internal oscillator and panel driver circuit are stopped. Only the MCU interface and memory works with VDDI power supply. Contents of the memory are safe. 6. Power Off Mode In this mode, both VDD and VDDI are removed. Note: Transition between modes 1-5 is controllable by MCU commands. Mode 6 is entered only when both Power supplies are removed.
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9.16.2 Power Flow Chart Normal display mode on = NOR ON Partial display mode on = PTL ON Idle mode off = IDM OFF Idle mode on = IDM ON Sleep out = SLP OUT Sleep in = SLP IN
NOR ON PTL ON Sleep out Normal display mode on Idle mode off IDM OFF IDM ON SLP IN SLP OUT IDM OFF SLP IN SLP OUT Power on sequence HW reset SW reset
Sleep in Normal display mode on Idle mode off
NOR ON PTL ON
IDM ON
Sleep out Normal display mode on Idle mode on
Sleep in Normal display mode on Idle mode on
Sleep out Partial display mode on Idle mode off IDM ON IDM OFF
SLP IN SLP OUT
Sleep in Partial display mode on Idle mode off IDM ON IDM OFF
PTL ON NOR ON
Sleep out Partial display mode on Idle mode on
SLP IN SLP OUT
Sleep in Partial display mode on Idle mode on
PTL ON NOR ON
Note 1: There is not any abnormal visual effect when there is changing from one power mode to another power mode. Note 2: There is not any limitation, which is not specified by this spec, when there is changing from one power mode to another power mode.
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9.17 Reset
9.17.1 Reset Table (240RGB x320)

Item Frame memory Sleep In/Out Display On/Off Display mode (normal/partial) Display Inversion On/Off VSYNCIN VSYNCOUT Display Idle Mode On/Off Column: Start Address (XS) Column: End Address (XE) Row: Start Address (YS) After Power On Random In Off Normal Off On Off Off 0000h 00Efh 0000h After Hardware Reset No Change In Off Normal Off On Off Off 0000h 00EFh 0000h After Software Reset No Change In Off Normal Off On Off Off 0000h 00EFh (239d) (when MV=0) 013Fh (319d) (when MV=1) 0000h 013Fh (319d) (when MV=0) 00EFh (239d) (when MV=1) GC0 No Change 0000h 013Fh Off 0000h 0140h 0000h 0000h Off 0 (Mode1) No Change No Change 08h No Change No Change 00h 00h 00h 38h NV value NV value
Row: End Address (YE) Gamma setting RGB for 4k and 65k Color Mode Partial: Start Address (PSL) Partial: End Address (PEL) Scroll: Vertical scrolling Scroll: Top Fixed Area (TFA) Scroll: Scroll Area (VSA) Scroll: Bottom Fixed Area (BFA) Scroll Start Address (SSA) Tearing: On/Off Tearing Effect Mode *3) Memory Data Access Control (MY/MX/MV/ML/RGB) Interface Pixel Color Format RDDPM RDDMADCTL RDDCOLMOD RDDIM RDDSM RDDSDR ID1 ID2 ID3
013Fh GC0 See Section 9.19 0000h 013Fh Off 0000h 0140h 0000h 0000h Off 0 (Mode1) 0/0/0/0/0 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h 38h NV value NV value
013Fh GC0 See Section 9.19 0000h 013Fh Off 0000h 0140h 0000h 0000h Off 0 (Mode1) 0/0/0/0/0 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h 38h NV value NV value
Notes 1. There will be no abnormal visible effects on the display when S/W or H/W Reset is applied. Notes:2. Powered-On Reset finishes within 10s after both VDD & VDDI are applied. Notes:3. TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only.
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9.17.2 Module Input/Output Pins 9.17.2.1 Output or Bi-directional (I/O) Pins
Output or Bi-directional pins TE D7 to D0 (Output driver) After Power On Low High-Z (Inactive) After Hardware Reset Low High-Z (Inactive) After Software Reset Low High-Z (Inactive)
Note: There will be no output from D7-D0 during Power On/Off sequence, Hardware Reset and Software Reset.
9.17.2.2 Input Pins

Input pins RESX CSX D/CX WRX RDX D7 to D0 P/SX During Power On Process See 9.15 Input invalid Input invalid Input invalid Input invalid Input invalid Input invalid After Power On Input valid Input valid Input valid Input valid Input valid Input valid Input valid After Hardware Reset Input valid Input valid Input valid Input valid Input valid Input valid Input valid After Software Reset Input valid Input valid Input valid Input valid Input valid Input valid Input valid During Power Off Process See 9.15 Input invalid Input invalid Input invalid Input invalid Input invalid Input invalid
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9.17.3 Reset Timing
Table 9.18.3.1 Reset input timing VSS=0V, VDDI=1.65V to 1.95V, VDD=2.45V to 2.9V,Ta = -30 to 70) Symbol Parameter Related Pins MIN TYP tRESW *1) Reset low pulse width RESX 30 tREST *2) Reset complete time 120 -
MAX -
Note -
Unit us ms
Note 1) Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below. Note 2. During the resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120 ms, when Reset Starts in Sleep Out mode. The display remains the blank state in Sleep In mode) and then return to Default condition for H/W reset. Note 3. During Reset Complete Time, ID2 and VCOMOF value in OTP will be latched to internal register during this period. This loading is done every time when there is H/W reset complete time (tREST) within 120ms after a rising edge of RESX. Note 4. Spike Rejection also applies during a valid reset pulse as shown below:
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9.18 Color Depth Conversion Look Up Tables 9.18.1 4096 and 65536 Color to 262,144 Color Look Up Table Outputs Color Frame Memory Data (6-bit) R005 R004 R003 R002 R001 R000 R015 R014 R013 R012 R011 R010 R025 R024 R023 R022 R021 R020 R035 R034 R033 R032 R031 R030 R045 R044 R043 R042 R041 R040 R055 R054 R053 R052 R051 R050 R065 R064 R063 R062 R061 R060 R075 R074 R073 R072 R071 R070 R085 R084 R083 R082 R081 R080 R095 R094 R093 R092 R091 R090 R105 R104 R103 R102 R101 R100 R115 R114 R113 R112 R111 R110 R125 R124 R123 R122 R121 R120 R135 R134 R133 R132 R131 R130 R145 R144 R143 R142 R141 R140 R155 R154 R153 R152 R151 R150 R165 R164 R163 R162 R161 R160 R175 R174 R173 R172 R171 R170 R185 R184 R183 R182 R181 R180 R195 R194 R193 R192 R191 R190 R205 R204 R203 R202 R201 R200 R215 R214 R213 R212 R211 R210 R225 R224 R223 R222 R221 R220 R235 R234 R233 R232 R231 R230 R245 R244 R243 R242 R241 R240 R255 R254 R253 R252 R251 R250 R265 R264 R263 R262 R261 R260 R275 R274 R273 R272 R271 R270 R285 R284 R283 R282 R281 R280 R295 R294 R293 R292 R291 R290 R305 R304 R303 R302 R301 R300 R315 R314 R313 R312 R311 R310
Default value after H/W Reset 000000 000011 000101 000111 001001 001011 001101 001111 010001 010011 010101 010111 011001 011011 011101 011111 100001 100011 100101 100111 101001 101011 101101 101111 110001 110011 110101 110111 111001 111011 111101 111111
RGBSET Parameter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RED
Look Up Table Input Data 4k Color 65k Color 0000 00000 0001 00001 0010 00010 0011 00011 0100 00100 0101 00101 0110 00110 0111 00111 1000 01000 1001 01001 1010 01010 1011 01011 1100 01100 1101 01101 1110 01110 1111 01111 10000 10001 10010 10011 10100 10101 10110 10111 Not Used 11000 11001 11010 11011 11100 11101 11110 11111
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Color Look Up Table Outputs Frame Memory Data (6-bit) G005 G004 G003 G002 G001 G000 G015 G014 G013 G012 G011 G010 G025 G024 G023 G022 G021 G020 G035 G034 G033 G032 G031 G030 G045 G044 G043 G042 G041 G040 G055 G054 G053 G052 G051 G050 G065 G064 G063 G062 G061 G060 G075 G074 G073 G072 G071 G070 G085 G084 G083 G082 G081 G080 G095 G094 G093 G092 G091 G090 G105 G104 G103 G102 G101 G100 G115 G114 G113 G112 G111 G110 G125 G124 G123 G122 G121 G120 G135 G134 G133 G132 G131 G130 G145 G144 G143 G142 G141 G140 G155 G154 G153 G152 G151 G150 G165 G164 G163 G162 G161 G160 G175 G174 G173 G172 G171 G170 G185 G184 G183 G182 G181 G180 G195 G194 G193 G192 G191 G190 G205 G204 G203 G202 G201 G200 G215 G214 G213 G212 G211 G210 G225 G224 G223 G222 G221 G220 G235 G234 G233 G232 G231 G230 G245 G244 G243 G242 G241 G240 G255 G254 G253 G252 G251 G250 G265 G264 G263 G262 G261 G260 G275 G 274 G273 G272 G271 G270 G285 G 284 G283 G282 G281 G280 G295 G 294 G293 G292 G291 G290 G305 G 304 G303 G302 G301 G300 G315 G 314 G313 G312 G311 G310 Default value after H/W Reset 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 RGBSET Parameter 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Look Up Table Input Data 4k Color 65k Color 0000 000000 0001 000001 0010 000010 0011 000011 0100 000100 0101 000101 0110 000110 0111 000111 1000 001000 1001 001001 1010 001010 1011 001011 1100 001100 1101 001101 1110 001110 1111 001111 010000 010001 010010 010011 010100 010101 010110 010111 Not Used 011000 011001 011010 011011 011100 011101 011110 011111
GREEN
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Color Look Up Table Outputs Frame Memory Data (6-bit) G325 G324 G323 G322 G321 G320 G335 G334 G333 G332 G331 G330 G345 G344 G343 G342 G341 G340 G355 G354 G353 G352 G351 G350 G365 G364 G363 G362 G361 G360 G375 G374 G373 G372 G371 G370 G385 G384 G383 G382 G381 G380 G395 G394 G393 G392 G391 G390 G405 G404 G403 G402 G401 G400 G415 G414 G413 G412 G411 G410 G425 G424 G423 G422 G421 G420 G435 G434 G433 G432 G431 G430 G445 G444 G443 G442 G441 G440 G455 G454 G453 G452 G451 G450 G465 G464 G463 G462 G461 G460 G475 G474 G473 G472 G471 G470 G485 G484 G483 G482 G481 G480 G495 G494 G493 G492 G491 G490 G505 G504 G503 G502 G501 G500 G515 G514 G513 G512 G511 G510 G525 G524 G523 G522 G521 G520 G535 G534 G533 G532 G531 G530 G545 G544 G543 G542 G541 G540 G555 G554 G553 G552 G551 G550 G565 G564 G563 G562 G561 G560 G575 G574 G573 G572 G571 G570 G585 G584 G583 G582 G581 G580 G595 G594 G593 G592 G591 G590 G605 G604 G603 G602 G601 G600 G615 G614 G613 G612 G611 G610 G625 G624 G623 G622 G621 G620 G635 G634 G633 G632 G631 G630 Default value after H/W Reset 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 RGBSET parameter 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Look Up Table Input Data 4k Color 65k Color 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 Not Used 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111
GREEN
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Color Look Up Table Outputs Frame Memory Data (6-bit) B005 B004 B003 B002 B001 B000 B015 B014 B013 B012 B011 B010 B025 B024 B023 B022 B021 B020 B035 B034 B033 B032 B031 B030 B045 B044 B043 B042 B041 B040 B055 B054 B053 B052 B051 B050 B065 B064 B063 B062 B061 B060 B075 B074 B073 B072 B071 B070 B085 B084 B083 B082 B081 B080 B095 B094 B093 B092 B091 B090 B105 B104 B103 B102 B101 B100 B115 B114 B113 B112 B111 B110 B125 B124 B123 B122 B121 B120 B135 B134 B133 B132 B131 B130 B145 B144 B143 B142 B141 B140 B155 B154 B153 B152 B151 B150 B165 B164 B163 B162 B161 B160 B175 B174 B173 B172 B171 B170 B185 B184 B183 B182 B181 B180 B195 B194 B193 B192 B191 B190 B205 B204 B203 B202 B201 B200 B215 B214 B213 B212 B211 B210 B225 B224 B223 B222 B221 B220 B235 B234 B233 B232 B231 B230 B245 B244 B243 B242 B241 B240 B255 B254 B253 B252 B251 B250 B265 B264 B263 B262 B261 B260 B275 B274 B273 B272 B271 B270 B285 B284 B283 B282 B281 B280 B295 B294 B293 B292 B291 B290 B305 B304 B303 B302 B301 B300 B315 B314 B313 B312 B311 B310 Default value after H/W Reset 000000 000011 000101 000111 001001 001011 001101 001111 010001 010011 010101 010111 011001 011011 011101 011111 100001 100011 100101 100111 101001 101011 101101 101111 110001 110011 110101 110111 111001 111011 111101 111111 RGBSET parameter 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Look Up Table Input Data 4k Color 65k Color 0000 00000 0001 00001 0010 00010 0011 00011 0100 00100 0101 00101 0110 00110 0111 00111 1000 01000 1001 01001 1010 01010 1011 01011 1100 01100 1101 01101 1110 01110 1111 01111 10000 10001 10010 10011 10100 10101 10110 10111 Not Used 11000 11001 11010 11011 11100 11101 11110 11111
BLUE
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9.19 Sleep Out-Command and Self-Diagnostic Functions of the Display Module 9.19.1 Register Loading Detection Sleep Out-command (See section 10.1.12 Sleep Out (11h)) is a trigger for an internal function of the display module, which indicates, if the display module loading function of factory default values from E-memory (similar device) to registers of the display controller is working properly. There are compared factory values of the E-memory and register values of the display controller by the display controller. If those both values (E-memory and register values) are same, there is inverted (=increased by 1) a bit, which is defined in command 10.1.10 Read Display Self-Diagnostic Result (0Fh) (=RDDSDR) (The used bit of this command is D7). If those both values are not same, this bit (D7) is not inverted (= increased by 1). The flow chart for this internal function is following:
Power on sequence HW reset SW reset
Sleep In (10h)
Sleep Out Mode
Sleep In Mode
RDDSDRs D7=0
Sleep Out (11h)
Loads values from E-memory to registers
Compares E-memory and register values
No
Are E-memory and register values same ?
Yes D7 inverted
Note: There is not compared and loaded register values, which can be changed by user (00h to AFh and DAh to DDh), by the display module.
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9.20 External Light Source The operation of the module can meet customers Environmental reliability requirements. 9.21 Oscillator The chip has on-chip oscillator that does not require external components. This oscillator output signal is used for system clock generation for internal display operation. 9.22 System Clock Generator The timing generator produces the various signals to driver the internal circuitty. Internal chip operation is not affected by operations on the data bus. 9.23 Instruction Decoder and Register The instruction decoder indentifies command words arriving at the interface and routes the following data bytes to their destination. The command set can be found in Command section. 9.24 Source Driver The source driver block includes 240x3 source outputs (S1 to S720), which should be connected directly to the TFT-LCD. The source output signals are generated in the data processing block after the data is read out of the RAM and latched, which represent the simulatance selected rows. 9.25 Gate Driver The gate driver block include 320 chanel gate output (G1 to G320) which should be connected directly to the TFT-LCD. 9.25.1 Gate Driver 9.25.1.1 Normal mode
1 2 3 4 5 6 7 8 9 10 11 12
S1-S396 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12
VGH VGL
Fig. 9.25.1 Gate Driver Output Option 1
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10. Command 10.1 System function Command List and Description Table 10.1.1 System Function command List (1)
Instruction Refer D/CX WRXRDX D17-8
NOP 10.1.1 SWRESET 10.1.2 0 0 0 1 1 1 1 0 1 1 1 1 1 0 RDDPM 10.1.5 1 1 0 1 1 0 1 1 0 RDDIM 10.1.8 1 1 0 RDDSM 10.1.9 1 1 0 RDDSDR 10.1.10 1 1 -: Dont care
D7
0 0 0 --ID17 ID27 ID37 0 --BSTON ST23
D6
D5
D4
0 0 0 --ID14 ID24 ID34 0 --MV IFPF0
D3
0 0 0 --ID13 ID23 ID33 1 --ML IDMON
D2
D1
D0
(Hex)
Function
-
1 1 1 1 - 1 1 1 1 1
RDDID
10.1.3
1 1 1 1
RDDST
10.1.4
0 0 0 0 0 0 ----ID16 ID15 ID26 ID25 ID36 ID35 0 0 ----MY MX IFPF2 IFPF1
0 0 0 (00h) No Operation 0 0 1 (01h) Software reset (04h) Read Display ID 1 0 0 ------Dummy read ID12 ID11 ID10 ID1 read ID22 ID21 ID20 ID2 read ID32 ID31 ID30 ID3 read 0 0 1 (09h) Read Display Status ------Dummy read RGB MH ST24 PTLON SLOUTNORON -
VSSON ST14 INVON ST12 GCS1 GCS0 TELOM HSON
1 1 - 1 1 - 1 1 - 1 1 - 1 1 - 1 1
RDD 10.1.6 MADCTL
1
1
RDD 10.1.7 COLMOD
Read Display Power 0 0 0 0 1 0 1 0 (0Ah) Mode ----------------Dummy read BSTON IDMON PTLON SLPOUT NORON DISON D1 D0 0 0 0 0 1 0 1 1 (0Bh Read Display MADCTL ----------------Dummy read MX MY MV ML RGB MH D1 D0 00h Read Display Pixel 0 0 0 0 1 1 0 0 (0Ch) Format ----------------Dummy read VIPF3 VIPF2 VIPF1 VIPF0 D3 IFPF2 IFPF1 IFPF0 Read Display Image 0 0 0 0 1 1 0 1 (0Dh) Mode ----------------Dummy read VSSON D6 INVON D4 D3 GCS2 GCS1 GCS0 Read Display Signal 0 0 0 0 1 1 1 0 (0Eh) Mode ----------------Dummy read TEON TELOM HSON VSON PCKON DEON D1 D0 00h Read Display 0 0 0 0 1 1 1 1 (0Fh) Self-diagnostic result --------BRD --D3 --D2 --D1 --D0 Dummy read RELD FUND ATTD
ST11 DISON TEON GCS2 VSON PCKON DEON ST0
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Table 10.1.2 System Function command List (2)
Instruction Refer D/CX WRX RDX D17-8
SLPIN SLPOUT PTLON NORON INVOFF INVON GAMSET 10.1.11 10.1.12 10.1.13 10.1.14 10.1.15 10.1.16 10.1.17 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 1 1 1 1 0 1 0 1 1
D7
0 0 0 0 0 0 0 GC7 0 0 0 --XS7 --XE7 0 --YS7 --YE7 0
D6
0 0 0 0
D5
0 0 0 0
D4
1 1 1 1 0 0 0 GC4 0 0 0 --XS4 --XE4 0 --YS4 --YE4 0
D3
0 0 0 0 0 0 0 GC3 1 1 1 --XS3 --XE3 1 --YS3 --YE3 1
D2
0 0 0 0
D1
0 0 1 1
D0
0 1 0 1
(Hex)
(10h) (11h) (12h) (13h)
Function
Sleep in & booster off Sleep out & booster on Partial mode on Partial mode off Normal mode
- - - 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - -
DISPOFF 10.1.18 DISPON 10.1.19
CASET
10.1.20
RASET
10.1.21
RAMWR
10.1.22
RAMRD
10.1.23
0 0 0 (20h) Display inversion off Normal 0 0 1 (21h) Display inversion on 1 1 0 (26h) Gamma curve select GC2 GC1 GC0 0 0 0 (28h) Display off 0 0 1 (29h) Display on 0 1 0 (2Ah) Column address set ----XS8 Xaddress start: 0XSEF XS2 XS1 XS0 00h MV=0 ----XE8 Xaddress end: XSXEEF XE2 XE1 XE0 AFh MV=0 0 1 1 (2Bh) Row address set ----YS8 Xaddress start: 0YS13F YS2 YS1 YS0 00h MV=0 ----YE8 Xaddress end: YSYE13F YE2 YE1 YE0 DBh MV=0 1 0 0 (2Ch) Memory write Write data * Bit asignment varies with the selected interface Write data 0 0 1 0 1 1 1 0 (2Eh) Memory read ----------------Dummy read Read data * Bit asignment varies with the selected interface Read data
0 1 0 1 0 1 GC6 GC5 0 1 0 1 0 1 ----XS6 XS5 ----XE6 XE5 0 1 ----YS6 YS5 ----YE6 YE5 0 1
-: Dont care
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Table 10.1.3 System Function command List (3)
Instruction Refer D/CXWRXRDX D17-8
0 1 PTLAR 10.1.25 1 1 1 0 1 1 1 1 1 1 0 0 1 0 1 0 1 1 0 0 0 1 0 OTP_process 10.1.34 1 1 0 RDID1 10.1.35 1 1 0 1 1 0 1 1
D7
0 --PSL7 --PEL7 0 --TFA7 --VSA7 --BFA7 0 0 --0 MY 0 --SSA7 0 0 0 0
D6
0 --PSL6 --PEL6 0 --TFA6 --VSA6 --BFA6 0 0 --0 MX 0 --SSA6 0 0 0 0
D5
1 --PSL5 --PEL5 1 --TFA5 --VSA5 --BFA5 1 1 --1 MV 1 --SSA5 1 1 1 1
D4
1 --PSL4 --PEL4 1 --TFA4 --VSA4 --BFA4 1 1 --1 ML 1 --SSA4 1 1 1 1
D3
0 --PSL3 --PEL3 0 --TFA3 --VSA3 --BFA3 0 0 --0 RGB 0 --SSA3 1 1 1
D2
0 --PSL2 --PEL2 0 --TFA2 --VSA2 --BFA2 1 1 --1 MH 1 --SSA2 0 0 0 1
D1
D0
(Hex)
Function
SCRLAR
10.1.26
TEOFF TEON MADCTL
10.1.27 10.1.28 10.1.29
VSCSAD IDMOFF IDMON COLMOD
10.1.30 10.1.31 10.1.32 10.1.33

1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 --- PSL8 PSL1 PSL0 --- PEL8 PEL1 PEL0 1 1 --- TFA8 TFA1 TFA0 --- VSA8 VSA1 VSA0 --- BFA8 BFA1 BFA0 0 0 0 1 --M 1 0 ----1 1 --- SSA8 SSA1 SSA0 0 0 0 1 1 0 1 1
(30h) Partial start/end address set 00h Partial start address 0,1,2,.,219 00h 00h Partial end address 0,1,2,.,219 F0h (33h) Scroll area set Top fixed area 0,1,2,.,219 Vertical scroll area 0,1,2,.,219 Bottom fixed area 0,1,2,.,219 (34h) Tearing effect line off (35h) Tearing effect mode set & on M="0": Mode 1, M="1": Mode 2 (36h) Memory data access control soft rst (37h) Scroll start address of RAM SSA=0,1,2,.,319 00h (38h) Idle mode off (39h) Idle mode on (3Ah) Interface pixel format soft rst (3Fh) CAh OTP-Process
VIPF3 VIPF2 VIPF1 VIPF0
--1
IFPF2 IFPF1IFPF0
1
0 1
1
0 1
0
0 0
0
0 1
1
0 1
0
0 0
1
INI 1
0
0 0
(DAh) Read ID1 Dummy read
1 1
--ID17 1 --ID27 1
--ID16 1 --ID26 1
--ID15 0 --ID25 0
--ID14 1 --ID24 1
--ID13 1 --ID23 1
---
---
---
RDID2
10.1.36
ID12 ID11 ID10 Read parameter 0 1 1 (DBh) Read ID2 ------Dummy read ID22 ID21 ID20 Read parameter 1 0 0 (DCh) Read ID3
RDID3
10.1.37
--ID37
--ID36
--ID35
--ID34
--ID33
---
---
---
Dummy read
Read parameter -: Dont care Note 1. After the H/W reset by RESX pin or S/W reset by SWRESET command, each internal register becomes default state (Refer RESET TABLE section) Note 2. Undefined commands are treated as NOP (00 h) command. Note 3. B0 to D9 and DE to FF are for factory use of driver supplier. Note 4. Commands 10h, 12h, 13h, 20h, 21h, 26h, 28h, 29h, 30h, 33h, 36h (ML parameter only), 37h, 38h and 39h are updated during V-sync when Module is in Sleep Out Mode to avoid abnormal visual effects. During Sleep In mode, these commands are updated immediately. Read status (09h), Read Display Power Mode (0Ah), Read Display MADCTL (0Bh), Read Display Pixel Format (0Ch), Read Display Image Mode (0Dh), Read Display Signal Mode (0Eh and Read Display Self Diagnostic Result (0Fh) of these commands are updated immediately both in Sleep In mode and Sleep Out mode.
ID32 ID31 ID30
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10.2 Panel Function Command List and Description
Table 10.2.1 Panel Function Command List (2)
Instruction Refer D/CX WRX RDX D23-8 D7
0 RGBCTR 10.2.1 1 0 1 FRMCTR1 10.2.2 1 1 0 1 FRMCTR2 10.2.3 1 1 0 1 1 FRMCTR3 10.2.4 1 1 1 1 0 INVCTR 10.2.5 1 0 1 RGB PRCTR 10.2.6 1 1 1 0 DISSET5 10.2.7 1 1 VSYNCOUT 10.2.8 VSYNCOIN 10.2.9 0 0
D6
0 --0 0
D5
1 --0 1
D4
1 ICM 0 1
D3
0 DP 0 0
D2
0 EP 0 0
D1
0 HSP 0 0
D0
0 VSP 0 1
(Hex) Function (B0h) Set Display I/F mode
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 --0 1
Polarity set
(B1h)
In normal mode full colors
--- RTNA[6] RTNA[5] 0 0 1 ------0 0 0 ------0 0 0 1 0 1 --- RTNB[6] RTNB[5] 0 --0 --0 1 0 --0 --0 0 1 --0 --0 1
RTNA[4] RTNA[3] RTNA[2] RTNA[1] RTNA[0]
1 0 1 1 0 Blanking porch setting FPA[4] FPA[3] FPA[2] FPA[1] FPA[0] 0 0 0 1 0 BPA[4] BPA[3] BPA[2] BPA[1] BPA[0] 0 0 0 1 0 1 0 0 1 0 (B2h) In idle mode 8-colors
RTNB[4] RTNB[3] RTNB[2] RTNB[1] RTNB[0]
0 Blanking porch setting
FPB[4] FPB[3] FPB[2] FPB[1] FPB[0] 1 0 0 0 0 BPB[4] BPB[3] BPB[2] BPB[1] BPB[0] 1 0 0 0 0 1 0 0 1 1
(B3h)
In partial mode + full colors
--- RTNC[6] RTNC[5] RTNC[4] RTNC[3] RTNC[2] RTNC[1] RTNC[0] 0 0 1 1 0 1 1 0 Blanking porch setting ------FPC[4] FPC[3] FPC[2] FPC[1] FPC[0] line inversion 0 0 0 1 0 0 0 0 ------BPC[4] BPC[3] BPC[2] BPC[1] BPC[0] 0 0 0 1 0 0 0 0 --- RTND[6] RTND[5] RTND[4] RTND[3] RTND[2] RTND[1] RTND[0] 0 0 1 1 1 0 0 0 ------FPD[4] FPD[3] FPD[2] FPD[1] FPD[0] Blanking porch setting frame inversion 0 0 0 1 0 0 0 0 ------BPD[4] BPD[3] BPD[2] BPD[1] BPD[0] 0 0 0 1 0 0 0 0 1 0 1 1 0 1 0 0 (B4h) Display inversion ----------NLA NLB NLC control 0 0 0 0 0 0 1 0 1 0 1 1 0 1 0 1 (B5h) --------VFP[3] VFP[2] VFP[1] VFP[0] 0 0 0 0 0 0 0 0 --------VBP[3] VBP[2] VBP[1] VBP[0] RGB I/F Blanking porch 0 0 0 0 0 0 1 0 setting --------HFP[3] HFP[2] HFP[1] HFP[0] 0 0 0 0 1 0 0 1 --------HBP[3] HBP[2] HBP[1] HBP[0] 0 0 0 0 1 0 0 1 Display function 1 0 1 1 0 1 1 0 (B6h) setting --0 --0 1 1 --0 --0 0 0 NO1 0 --0 1 1 NO0 0 --0 1 1 SDT1 0 PTG1 0 1 1 SDT0 0 PTG0 0 1 1 EQ1 1 PT1 1 0 0 EQ0 0 PT0 0 0 1 External VSYNC disable External VSYNC (BDh) enable
(BCh)
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Instruction Refer D/CXWRXRDX D17-8 D7 0 1 -1 PWCTR1 10.2.10 --1 1 -0 0 1 -1 -VGH3 1 1 PWCTR2 10.2.11 -1 --1 1 -0 0 1 -1 --1 1 -0
1 PWCTR3 10.2.12 1 1 1 0 PWCTR4 10.2.13 1 1 1 1 1 0 1 PWCTR5 10.2.14 1
D6 1 -0 1 VGH2 0 -0 1 -0
STEP1A _SEL2
D5 0 -0 0 VGH1 1 -0 0 -0
STEP1A _SEL1
D4 0 VRH4 1 0 VGH0 1 -0 0 -0
STEP1A _SEL0
D3 0 VRH3 0 0 VGL3 1 -0 0 -0
--0
---
D2 0 VRH2 0 0 VGL2 0 GOT2 0 0 APA2 0`

STEP2A _SEL2
D1 0 VRH1 0 0 VGL1 0 GOT1 0 1 APA1 0

STEP2A _SEL1
D0 0 VRH0 0 1 VGL0 0 GOT0 0 0 APA0 1

STEP2A _SEL0
(Hex) Function (C0h)
Power control setting
(C1h) BBh setting

Power control
(C2h)
1 1 1 1 1 1 1 1 1
---------------
STEP1A_ SEL3
1 1 0
--
0
LDO5 _SEL2
1
LDO5 _SEL1
1
LDO5 _SEL0
0
STEP4A _SEL2
0
STEP4A _SEL1
1
STEP4A _SEL0
0
STEP1AP _SEL2
0
STEP1AP _SEL1
1
STEP1AP_ SEL0
0
---
0
STEP2AP _SEL2
1
STEP2AP _SEL1
1
STEP2AP _SEL0
In normal mode full color
0 --1 -0
STEP1B _SEL3
0 --1 -0
STEP1B _SEL2
0 --0 -0
STEP1B _SEL1
0 --0 -0
STEP1B _SEL0
0 --0 -0 --0 ------0 -0 --0 -----
0
STEP4AP _SEL2
0
STEP4AP _SEL1
0
STEP4AP _SEL0
0 0 APB2 0
STEP2A _SEL2
0 1 APB1 0
STEP2A _SEL1
0 1 APB0 1
STEP2B _SEL0
(C3h)
0 -----1 -0
STEP1C _SEL3
0 --STEP1BP _SEL2
0 --STEP1BP _SEL1
0 --STEP1AP _SEL0
0
STEP4B _SEL2
0
STEP4B _SEL1
0
STEP4B _SEL0
In Idle mode (8-colors)
0
STEP2BP _SEL2
0
STEP2BP _SEL1
0
STEP2BP _SEL0
0 --1 -0
STEP1C _SEL2
0 --0 -0
STEP1C _SEL1
0 --0 -0
STEP1C _SEL0
0
STEP4BP _SEL2
0
STEP4BP _SEL1
0
STEP4BP _SEL0
1 1 1 1
------
0 1 APC2 0
STEP2C _SEL2
0 0 APC1 0
STEP2C _SEL1
0 0 APC0 1
STEP2C _SEL0
(C4h)
In partial mode + Full colors
1 ------1
--
0 --STEP1CP _SEL2
1 --STEP1CP _SEL1
1 --STEP1CP _SEL0
0
STEP4C _SEL2
1
STEP4C _SEL1
1
STEP4C _SEL0
1 1 1 0 1 VMCTR1 10.2.15 1
1 1 1 1 1 1
-----------------
0
STEP2CP _SEL2
1
STEP2CP _SEL1
1
STEP2CP _SEL0
0 --0 VMH6 0 0
nVM0
0 --1 VMH 5 1 1
---
0 --1 VMH4 0 0
---
---0 VMH3 1 1
--
0
STEP4CP _SEL2
0
STEP4CP _SEL1
0
STEP4CP _SEL0
-----1 0 0 --
0 1 VMH2 0 0
---
0 0 VMH1 0 0
---
0 1 VMH0 0 0
---
(C5h)
VMH_ VMH_ VMH_ VMH_ VMH_ VMH_ VMH_ COLOR8M6 COLOR8M5 COLOR8M4 COLOR8M3 COLOR8M2 COLOR8M1 COLOR8M0
VCOM control 1
0 VMCTR2 10.2.16 1 1
1 1 1
0 0 0 0 --
-1 VMA5 0 0
-1 VMA4 1 0
-0 VMA3 0 0
-1 VMA2 1 0
-1 VMA1 1
VMA _IDMON01
-0 VMA0 0
VMA _IDMON00
(C6h)
VCOM control 2
VMA VMA _IDMON05 _IDMON04
VMA VMA _IDMON03 _IDMON02
----: Dont care Note 1: C0h to CFh are fixed for about power controller. Note 2: The C9h to CFh are reserved for further using.
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Instruction Refer D/CXWRXRDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 0 1 0 0 0 0 WRID1 10.2.17 ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 1 WRID2 10.2.18 0 ID26 ID25 ID24 ID23 ID22 ID21 ID20 1 1 0 1 0 1 1 1 0 0 0 1 1 1 0 1 0 0 1 0 WRID3 10.2.19 ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 OTP-Load 10.2.20 1 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1 1 1 1 0 1 1 1 1 0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 OTP-Prog 10.2.21 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 1 0 1 1 1 0 1 0 1 1 0 1 0 -: Dont care Note 1: The D1h to D8h registers are fixed for about ID code setting. Note 2: The D9h, DEh and DFh registers are used for NV Memory function controller. (Ex: write, clear, etc.) (Hex) Function (D0h) Reserved for future using
(D1h) LCM version code

OTP ID2 set the LCM version code.
(D2h) Customer Project code

OTP ID3 set the project code.
DEh OTP-Read command 75h DFh CAh OTP prog. Command 00h Protection sequence:CA AAh 00AA A5 A5 5A A5h 5Ah
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Instruction Refer D/CXWRXRDX D17-8
0 1 1 1 1 1 GAMCTRP1 10.2.22 1 1 1 1 1 1 1 0 1 1 1 1 1 GAMCTRN1 10.2.23 1 1 1 1 1 1 1 0 Vcom_multi_mode10.2.24 1
D7
1 0
---
D6
1 0
---
D5
1
---
D4
0
---
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
MVA_EN ---
(Hex) Function 0 0 0 0 (E0h) Set Gamma correction RFP0[3] RFP0[2] RFP0[1] RFP0[0]
0 1 0 1 0 0 1 0
PKP0[3] PKP0[2] PKP0[1] PKP0[0]
D3
D2
D1
D0
0
---
0
---
0
---
0
---
0
---
0 --0
---
0 --0
---
0 --0
---
PKP1[4] PKP1[3] PKP1[2] PKP1[1] PKP1[0] 1 1 0 0 1 PKP2[4] PKP2[3] PKP2[2] PKP2[1] PKP2[0] 1 1 1 0 0 PKP3[4] PKP3[3] PKP3[2] PKP3[1] PKP3[0]
0
---
0
---
0
---
1 1 1 1 0
---
1 1 1 1 1 0 0
0
0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 1 1
1 0 0 1 0 0 1 1 0 0 0 0 0 1 0 0 1 0 0 1 1 0 1 1
1 1 0 0 1 1 0 1 1 1 0 1 0 1 1 0 0 1 1 0 1 0 1 1 (FBh) Vcom multi mode Negative Polarity (E1h) Set Gamma correction Postiive Polarity
PKP4[4] PKP4[3] PKP4[2] PKP4[1] PKP4[0] PKP5[4] PKP5[3] PKP5[2] PKP5[1] PKP5[0] PKP6[4] PKP6[3] PKP6[2] PKP6[1] PKP6[0] PKP7[4] PKP7[3] PKP7[2] PKP7[1] PKP7[0] PKP8[3] PKP8[2] PKP8[1] PKP8[0] RFP1[3] RFP1[2] RFP1[1] RFP1[0] OSP1[2] OSP1[1] OSP1[0]
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0 1
---
0 1
---
0 1
---
0 0
---
0 0 0 1 1 1 1 1 1 1 1 0 0
---
RFN0[3] RFN0[2] RFN0[1] RFN0[0] PKN0[3] PKN0[2] PKN0[1] PKN0[0]
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0 1 1 1 1 1 1 0
---
PKN1[4] PKN1[3] PKN1[2] PKN1[1] PKN1[0] PKN2[4] PKN2[3] PKN2[2] PKN2[1] PKN2[0] PKN3[4] PKN3[3] PKN3[2] PKN3[1] PKN3[0] PKN4[4] PKN4[3] PKN4[2] PKN4[1] PKN4[0] PKN5[4] PKN5[3] PKN5[2] PKN5[1] PKN5[0] PKN6[4] PKN6[3] PKN6[2] PKN6[1] PKN6[0] PKN7[4] PKN7[3] PKN7[2] PKN7[1] PKN7[0] PKN8[3] PKN8[2] PKN8[1] PKN8[0] RFN1[3] RFN1[2] RFN1[1] RFN1[0] OSN1[2] OSN1[1] OSN1[0]
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0
---
0 1 --
0 1
0 1 1 1
0 0 1 1
1 1
1 Vcom 1 _Mu_mode 1 1
-: Dont care Note 1: E0-E7 registers are fixed for about Gamma adjusting.
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10.1.1 NOP (00h)
00H Inst / Para NOP Parameter D/CX WRX RDX 0 1 D17-8 D7 0 NOP (No Operation) D6 D5 D4 D3 0 0 0 0 No Parameter D2 0 D1 0 D0 0 (Code) (00h) -
NOTE: - Dont care
-This command is empty command. It does not have effect on the display module. Description -However it can be used to terminate RAM data write or read as described in RAMWR (Memory Write), RAMRD (Memory Read) and parameter write commands. Restriction
Status
Availability Yes Yes Yes Yes Yes Default Value N/A N/A N/A
Register Availability
Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status
Default
Power On Sequence S/W Reset H/W Reset
Flow Chart
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10.1.2 SWRESET (01h): Software Reset
01H Inst / Para SWRESET Parameter
NOTE: - Dont care
D/CX WRX RDX 0 1
D17-8 -
D7 0
SWRESET (Software Reset) D6 D5 D4 D3 0 0 0 0 No Parameter
D2 0
D1 0
D0 1
(Code) (01h) -
Description
-When the Software Reset command is written, it causes a software reset. It resets the commands and parameters to their S/W Reset default values and all source & gate outputs are set to VSS (display off). (See default tables in each command description) Note: The Frame Memory contents are not affected by this
command.
-It will be necessary to wait 120msec before sending new command following software reset. -The display module loads all display supplier s factory default values to the registers during 120msec. Restriction -If Software Reset is applied during Sleep Out mode, it will be necessary to wait 120msec before sending Sleep Out command. -Software Reset command cannot be sent during Sleep Out sequence.
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Yes Yes Default Value N/A N/A N/A
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status
Default
SWRESET (01h)
Legend
Command
Display whole blank screen
Parameter
Display
Flow Chart
Set Commands to S/W Default Value
Action Mode Sequential
Sleep In Mode
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10.1.3 RDDID (04h): Read Display ID
04H Inst / Para
RDDID (Read Display ID)

D/CX WRX RDX 0 1 1 1 1 1 1 1 1 1 D17-8 D7 0 ID17 ID27 ID37 D6 0 ID16 ID26 ID36 D5 0 ID15 ID25 ID35 D4 0 ID14 ID24 ID34 D3 0 ID13 ID23 ID33 D2 1 ID12 ID22 ID32 D1 0 ID11 ID21 ID31 D0 0 ID10 ID20 ID30 (Code) (04h) Dummy
RDDID 1st Parameter 2nd Parameter 3rt Parameter 4th Parameter
NOTE: - Dont care
-This read byte returns 24-bit display identification information. -The 1st parameter is dummy data -The 2nd parameter (ID17 to ID10): LCD modules manufacturer ID. Description -The 3rd parameter (ID27 to ID20): LCD module/driver version ID -The 4th parameter (ID37 to UD30): LCD module/driver ID.
NOTE: Commands RDID1/2/3(DAh, DBh, DCh) read data correspond to the parameters 2,3,4 of the command 04h, respectively.
Restriction
Status
Availability Yes Yes Yes Yes Yes Default Value ID1 N/A N/A N/A ID2 N/A N/A N/A ID3 N/A N/A N/A
Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Status
Default
Serial I/F Mode

RDDID (04h)
Parallel I/F Mode

RDDID (04h) Host Driver Legend
Command
Dummy Clock
Dummy Read
Parameter
Display
Flow Chart
Send ID1[7:0]
Send ID1[7:0]
Action Mode
Send ID2[7:0]
Send ID2[7:0]
Sequential transfer
Send ID3[7:0]
Send ID3[7:0]
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10.1.4 RDDST (09h): Read Display Status
09H Inst / Para RDDST
1st Parameter 2nd Parameter 3rd Parameter 4th Parameter 5th Parameter
NOTE: - Dont care
D/CX WRX RDX 0 1

1 1 1 1 1 1 1 1 1 1

D17-8 -
D7 0
-
RDDST (Read Display Status) D6 D5 D4 D3 0 0 0 1

MY IFPF2 ST14 GCS0
D2 0
-
D1 0
-
D0 1
-
(Code) (09h)
-
MX IFPF1 INVON TELOM
MV IFPF0 ST12 HSON
BSTON ST23 VSSON GCS1
ML RGB MH ST24 IDMON PTLON SLOUT NORON ST11 DISON TEON GCS2 VSON PCKON DEON ST0
This command indicates the current status of the display as described in the table below:
Bit BSTON MY MX MV ML Description Booster Voltage Status Row Address Order (MY) Column Address Order (MX) Row/Column Exchange (MV) Scan Address Order (ML) Value 1 =Booster on, 0 =Booster off 1 =Decrement, (Bottom to Top, when MADCTL (36h) D7=1) 0 =Increment, (Top to Bottom, when MADCTL (36h) D7=0) 1 =Decrement, (Right to Left, when MADCTL (36h) D6=1) 0 =Increment, (Left to Right, when MADCTL (36h) D6=1) 1 = Row/column exchange, (when MADCTL (36h) D5=1) 0 = Normal, (when MADCTL (36h) D5=0) 1 =Decrement, (LCD refresh Top to Bottom, when MADCTL (36h) D4=1) 0=Increment, (LCD refresh Bottom to Top, when MADCTL (36h) D4=0) 1 =BGR, (When MADCTL (36h) D3=1) 0 =RGB, (When MADCTL (36h) D3=0) 1 =Decrement, (LCD refresh Left to Right, when MADCTL (36h) D2=1) 0 =Increment, (LCD refresh Right to Left, when MADCTL (36h) D2=0) 0 0 011 = 12-bit / pixel, 101 = 16-bit / pixel, 110 = 18-bit / pixel, others are no define 1 = On, 0 = Off 1 = On, 0 = Off 1 = Out, 0 = In 1 = Normal Display, 0 = Partial Display 1 = Scroll on,0 = Scroll off 0 1 = On, 0 = Off 0 0 1 = On, 0 = Off 1 = On, 0 = Off 0 = mode1, 1 = mode2 1 = On, 0 = Off 1 = On, 0 = Off 1 = On, 0 = Off 1 = On, 0 = Off 0
GCS[2:0] 000 001 010 (LCM=[01]) 011 000 (LCM=[01]) 001 010 TR LCtype
RGB MH
RGB/ BGR Order (RGB) Horizontal Order
Description
ST24 ST23 IFPF2 IFPF1 IFCPF0 IDMON PTLON SLPOUT NORON VSSON ST14 INVON ST12 ST11 DISON TEON TELOM HSON VSON PCLKON DEON ST0
GS
For Future Use For Future Use Interface Color Pixel Format Definition Idle Mode On/Off Partial Mode On/Off Sleep In/Out Display Normal Mode On/Off Vertical Scrolling Status Horizontal Scroll Status Inversion Status All Pixels On (Not Used) All Pixels Off (Not Used) Display On/Off Tearing effect line on/off Tearing effect line mode Horizontal Sync. (HS, RGB I/F) Vertical Sync, (VS, RGB I/F) Pixel Clock (PCLK, RGB I/F) Data Enable (DE, RGB I/F) For Future Use
GC[7:0] 01h 02h 04h 08h 1 01h 02h 04h
=1.0 =2.5 =2.2 =1.8 =2.2 =1.8 =2.5
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Note: ST0, ST5, ST9, ST11-ST15, ST19, ST23, ST24 are set to 0, when RGB I/F.
Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Availability Yes Yes Yes Yes Yes Default Value (ST31 to ST0) ST[23-16] ST[15-8] 0110-0001 0000-0000 0xxx-0001 0000-0000 0110-0001 0000-0000
Default
ST[31-24] 0000-0000 0xxx0xx00 0000-0000
ST[7-0] 0000-0000 0000-0000 0000-0000
Serial I/F Mode

RDDST (09h)
Parallel I/F Mode

RDDST (09h) Host Driver
Dummy Clock
Dummy Read
Legend
Command
Send ST[31:24]
Send ST[31:24]
Flow Chart
Send ST[23:16] Send ST[23:16]
Parameter
Display
Action Mode Sequential transfer
Send ST[15:8]
Send ST[15:8]
Send ST[7:0]
Send ST[7:0]
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10.1.5 RDDPM (0Ah): Read Display Power Mode
0AH Inst / Para RDDPM
1st Parameter 2nd Parameter
D/CX WRX RDX 0 1

1 1 1 1
D17-8 -
RDDPM (Read Display Power Mode) D7 D6 D5 D4 D3 0 0 0 0 1
D2 0
D1 1
D1
D0 0
D0
(Code) (0Ah)
-
BSTON IDMON PTLON SLPOUT NORON DISON
NOTE: - Dont care, can be set to VDDI or DGND level
Bit
BSTON IDMON
Description
Booster Voltage Status Idle Mode On/Off Partial Mode On/Off Sleep In/Out Display Normal Mode On/Off Display On/Off Not Used Not Used 1 =Booster on, 0 =Booster off 1 = Idle Mode On, 0 = Idle Mode Off 1 = Partial Mode On, 0 = Partial Mode Off 1 = Sleep Out, 0 = Sleep In 1 = Normal Display, 0 = Partial Display 1 = Display On, 0 = Display Off 0 0
Value
Description
PTLON SLPON NORON DISON D1 D0
Restriction
Status
Availability Yes Yes Yes Yes Yes Default Value (D7 to D0) 08h 08h 08h
Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset
Default
Serial I/F Mode

RDDPM (0Ah)
Parallel I/F Mode

RDDPM (0Ah) Host Driver
Legend
Command
Parameter
Display
Flow Chart
Send D[7:0]
Dummy Read
Action Mode
Send D[7:0]
Sequential transfer
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10.1.6 RDDMADCTL (0Bh): Read Display MADCTL
0BH Inst / Para RDDMADCTL
D/CX 0
1 1
WRX
RDX 1

RDDMADCTL (Read Display MADCTL) D17-8 D7 D6 D5 D4 D3 0 0 0 0 1 MY MX MV ML RGB
D2 0
MH
D1 1
D1
D0 1
D0
(Code) (0Bh)
-
1 1
Bit
MX MY
Description
Row Address Order Column Address Order Row/Column Order (MV) Vertical Refresh Order RGB/BGR Order Horizontal order Not Used Not Used
Description
MV ML RGB MH D1 D0
Value 1 = Bottom to Top (When MADCTL B7=1) 0 = Top to Bottom (When MADCTL B7=0) 1 = Right to Left (When MADCTL B6=1) 0 = Left to Right (When MADCTL B6=0) 1 = Row/column exchange (MV=1) 0 = Normal (MV=0) 1 =LCD Refresh Bottom to Top 0 =LCD Refresh Top to Bottom 1 =BGR, 0=RGB 1 =LCD Refresh Right to Left 0 =LCD Refresh Left to Right 0 0
Restriction
Status
Availability Yes Yes Yes Yes Yes Default Value (D7 to D0) 00h No change 00h
Default
Legend
Serial I/F Mode

RDDMADCTL (0Bh)
Parallel I/F Mode

Command RDDMADCTL (0Bh)
Host Driver
Parameter
Display
Flow Chart
Send D[7:0]
Dummy Read
Action Mode
Send D[7:0]
Sequential transfer
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10.1.7 RDDCOLMOD (0Ch): Read Display Pixel Format
0CH Inst / Para RDDCOLMOD
D/CX 0
1 1
WRX
RDX 1

D17-8 -
RDDCOLMOD (Read Display Pixel Format) D7 D6 D5 D4 D3 D2 0 0 0 0 1 1

VIPF3 VIPF2 VIPF1 VIPF0 D3 IFPF2
D1 0
IFPF1
D0 0
IFPF0
(Code) (0Ch)
-
1 1
NOTE: - Dont care, can be set to VDDI or DGND level This command indicates the current status of the display as described in the table below:
IFPF[2:0] 011 101 110 111 3 5 6 7 MCU Interface Color Format 12-bit/pixel 16-bit/pixel 18-bit/pixel No used
Description Others are no define and invalid

VIFPF[2:0] 0101 0110 0111 1110 5 6 7 14 RGB Interface Color Format 16-bit/pixel (1-times data transfer) 18-bit/pixel (1-times data transfer) No used 18-bit/pixel (3-times data transfer)
Others are no define and invalid
Restriction
Status
Availability Yes Yes Yes Yes Yes Default Value IFPF[2:0] 0110 (18 bits/pixel) No Change 0110 (18 bits/pixel) VIPF[3:0] 0110 (18 bits/pixel) No Change 0110 (18 bits/pixel)
Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status
Default
Legend
Serial I/F Mode

RDDCOLMOD (0Ch)
Parallel I/F Mode

Command RDDCOLMOD (0Ch)
Host Driver
Parameter
Display
Flow Chart
Send D[7:0]
Dummy Read
Action Mode
Send D[7:0]
Sequential transfer
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10.1.8 RDDIM (0Dh): Read Display Image Mode
0DH Inst / Para RDDIM
D/CX WRX RDX 0 1

1 1 1 1

D17-8 -
RDDIM (0Dh): Read Display Image Mode D7 D6 D5 D4 D3 D2 0 0 0 0 1 1

VSSON
D1 0
GCS1
D0 1
GCS0
(Code) (0Dh)
-
D6
INVON
D4
D3
GCS2

This command indicates the current status of the display as described in the table below: Bit VSSON D6 INVON D4 D3 Description Vertical Scrolling On/Off Horizontal Scrolling On/Off Inversion On/Off All Pixels On All Pixels Off Value 1 = Vertical scrolling is On, 0 = Vertical scrolling is Off 0 (Not used) 1 = Inversion is On, 0 = Inversion is Off 0 (Not used) 0 (Not used)
GS
GC[7:0] Reg.
LCM1 0 0
LCM0 0 1 0 1 X X X X X 0 1 0 1 X
LC Type MVA Transflective(TR)
Gamma
01H 1 1 Description 02H 04H 08H 01H 02H 1 X X X X X 0 0 04H 1 1 08H X Transmissive(TM) N/A 0 Transmissive(TM) N/A
Curve 2.2
Transflective(TR) 1.8 Transflective(TR) 2.5 Transflective(TR) 1.0 Transflective(TR) 1.0 Transflective(TR) 2.5 MVA Transflective(TR) Curve 2.2
Transflective(TR) 1.8
Note 1: While LCM[1:0]=00 Note 2: Even GCS[2:0] value is be changeable from read status, the gamma curve of Transmissive and MVA only
=2.2. Restriction
Status Availability Yes Yes Yes Yes Yes Default Value(D7 to D0) 0000_0001 (01h) 0000_0001 (01h) 0000_0001 (01h)
Default
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Legend
Serial I/F Mode

RDDIM (0Dh)
Parallel I/F Mode

Command RDDIM (0Dh)
Host Driver
Parameter
Display
Flow Chart
Send D[7:0]
Dummy Read
Action Mode
Send D[7:0]
Sequential transfer
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10.1.9 RDDSM (0Eh): Read Display Signal Mode
0EH Inst / Para RDDSM
1st Parameter 2
nd
RDDSM (0Eh): Read Display Signal Mode D/CX WRX 0

1 1 1 1
RDX 1

D17-8 -
D7 0
TEON
D6 0
TELOM
D5 0
HSON
D4 0
VSON
D3 1
PCKON
D2 1
DEON
D1 1
D1
D0 0
D0
(Code) (0Eh)
-
Parameter
Bit
TEON TELOM HSON
Description
Tearing Effect Line On/Off Tearing effect line mode Horizontal Sync. (RGB I/F) On/Off Vertical Sync. (RGB I/F) On/Off Pixel Clock (PCLK, RGB I/F) On/Off Data Enable (DE, RGB I/F) On/Off Not Used Not Used 1 = On, 0 = Off 1 = mode1, 0 = mode2 1 = On, 0 = Off 1 = On, 0 = Off 1 = On, 0 = Off 1 = On, 0 = Off 1 = On, 0 = Off 1 = On, 0 = Off
Value
Description
VSON PCKON DEON D1 D0
Restriction
Status
Availability Yes Yes Yes Yes Yes Default Value(D7~D0) 00h 00h 00h Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset
Default
Legend
Serial I/F Mode

RDDSM (0Eh)
Parallel I/F Mode

Command RDDSM (0Eh)
Host Driver
Parameter
Display
Flow Chart
Send D[7:0]
Dummy Read
Action Mode
Send D[7:0]
Sequential transfer
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10.1.10 RDDSDR (0Fh): Read Display Self-Diagnostic Result
0FH Inst / Para RDDSDR
D/CX 0
1 1
WRX
RDX 1

RDDSDR (0Fh): Read Display Self-Diagnostic Result D17-8 D7 D6 D5 D4 D3 D2 0 0 0 0 1 1

RELD FUND ATTD BRD D3 D2
D1 1
D1
D0 1
D0
(Code) (0Fh)
-
1 1
Bit RELD FUND ATTD BRD D3 D2 D1 D0 Description Register Loading Detection Functionality Detection Chip Attachment Detection Display Glass Break Detection Not Used Not Used Not Used Not Used Value See section 9.19 See section 9.19 1 1 0 0 0 0
Description
Restriction
Status
Availability Yes Yes Yes Yes Yes Default Value(D7~D0)
Default
Legend
Serial I/F Mode

RDDSDR (0Fh)
Parallel I/F Mode

Command RDDSDR (0Fh)
Host Driver
Parameter
Display
Flow Chart
Send D[7:0]
Dum my Read
Action Mode
Send D[7:0]
Sequential transfer
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10.1.11 SLPIN (10h): Sleep In
10H Inst / Para SLPIN st 1 Parameter D/CX 0 WRX
RDX 1
D17-8 -
SLPIN (Sleep In) D7 D6 D5 D4 0 0 0 1 No parameter
D3 0
D2 0
D1 0
D0 0
(Code) (10h) -
-This command causes the LCD module to enter the minimum power consumption mode. -In this mode the DC/DC converter is stopped, Internal display oscillator is stopped, and panel scanning is stopped.
Sleep In VDDI VDD Gate Output Source Output 0V 0V Blanking display (over 1frame display) * 0V STOP STOP DISCHARGE 0V or VDD 0V or VDD 0V 0V or VDD 0V 1.6V-3.0V 2.6V-3.0V STOP
VCOM Output
Description
Internal counter Internal Oscillator DC charge in capacitors VGH VGL AVDD IC Internal reset
* Note: complete 1 frame display (ex: continue 2-falling edges of VS)
-MCU interface and memory are still working and the memory keeps its contents
-This command has no effect when module is already in sleep in mode. Sleep In Mode can only be exit by the Sleep Out Command (11h). -It will be necessary to wait 120msec before sending next command , this is to allow time for the supply Restriction voltages and clock circuits to stabilize. -It will be necessary to wait 120msec after sending Sleep Out command (when in Sleep In Mode) before Sleep In command can be sent.
Status Availability Yes Yes Yes Yes Yes Default Value Sleep in mode Sleep in mode Sleep in mode
Default
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-It takes about 120msec to get into Sleep In mode (booster off state) after SLPIN command issued. -The results of booster off can be check by RDDST (09h) command Bit31.
SPLIN (10h)
Legend Stop DC/DC Converter Stop Internal Oscillator Sleep In

Command
Flow Chart
Display whole blank screen (Automatic No effect to DISP ON/OFF Command)
Parameter
Display
Drain charge from LCD
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10.1.12 SLPOUT (11h): Sleep Out
11H Inst / Para SLPOUT 1st Parameter D/CX 0 WRX
RDX 1
D17-8 -
SLPOUT (Sleep Out) D7 D6 D5 D4 0 0 0 1 No Parameter
D3 0
D2 0
D1 0
D0 1
(Code) (11h) -
-This command turns off sleep mode. -In this mode the DC/DC converter is enabled, Internal display oscillator is started, and panel scanning is started.
Sleep Out VDDI VDD Internal Oscillator AVDD VGL STOP 0V or VDD 0V 0V or VDD STOP 0V STOP 0V 0V STOP 0V 0V
Memory Contents Memory Contents
1.6V-3.0V 2.6V-3.0V Start
Description
VGH Internal counter IC Internal reset Gate Output Source Output VCOM Output
Start
Blanking display (over 1fram e display) * If DISPON 29h is set * Note: complete 1 frame display (ex: continue 2-falling edges of VS)
-This command has no effect when module is already in sleep out mode. Sleep Out Mode can only be exit by the Sleep In Command (10h). -It will be necessary to wait 120msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. -DRIVER loads all default values of extended and test command to the registers during this 120msec and Restriction there cannot be any abnormal visual effect on the display image if those default and register values are same when this load is done and when the DRIVER is already Sleep Out mode. -DRIVER is doing self-diagnostic functions during this 120msec. See also section 9.20. -It will be necessary to wait 120msec after sending Sleep In command (when in Sleep Out mode) before Sleep Out command can be sent
Status Availability Yes Yes Yes Yes Yes Default Value Sleep in mode Sleep in mode Sleep in mode
Default
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-It takes 120msec to become Sleep Out mode (booster on mode) after SLPOUT command issued. -The results of booster on can be checked by RDDST (09h) command Bit31.
SLPOUT (11h) Legend Start Internal Oscillator Display whole blank screen for 2 frames (Automatic No effect to DISP ON/OFF
Command
Parameter
Display
Flow Chart
Start DC-DC Converter Charge Offset voltage for LCD Panel
Display Memory contents in accordance with the current command

table settings
Sleep Out
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10.1.13 PTLON (12h): Partial Display Mode On
12H Inst / Para PTLON st 1 Parameter D/CX 0 WRX
RDX 1
PTLON (12h): Partial Display Mode On D17-8 D7 D6 D5 D4 D3 D2 0 0 0 1 0 0 No Parameter
D1 1
D0 0
(Code) (12h) -
-This command turns on Partial mode. The partial mode window is described by the Partial Area command (30h) Description -To leave Partial mode, the Normal Display Mode On command (13H) should be written. -There is no abnormal visual effect during mode change between Normal mode On <-> Partial mode On. Restriction This command has no effect when Partial mode is active.
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Yes Yes Default Value Normal Mode On Normal Mode On Normal Mode On
Default
Flow Chart See Partial Area (30h)
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10.1.14 NORON (13h): Normal Display Mode On
13H Inst / Para NORON st 1 Parameter D/CX 0 WRX
RDX 1
NORON (Normal Display Mode On) D17-8 D7 D6 D5 D4 D3 0 0 0 1 0 No Parameter
D2 0
D1 1
D0 1
(Code) (13h) -
-This command returns the display to normal mode. -Normal display mode on means Partial mode off, Scroll mode Off. Description -Exit from NORON by the Partial mode On command (12h) -There is no abnormal visual effect during mode change from Normal mode On to Partial mode On. Restriction -This command has no effect when Normal Display mode is active.
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Yes Yes Default Value Normal Mode On Normal Mode On Normal Mode On
Default
Flow Chart -See Partial Area and Vertical Scrolling Definition Descriptions for details of when to use this command
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9.1.15 INVOFF (20h): Display Inversion Off
20H Inst / Para INVOFF st 1 Parameter D/CX 0 WRX
RDX 1
IVNOFF (Normal Display Mode Off) D17-8 D7 D6 D5 D4 D3 0 0 1 0 0 No Parameter
D2 0
D1 0
D0 0
(Code) (20h) -
-This command is used to recover from display inversion mode. -This command makes no change of contents of frame memory. -This command does not change any other status.
(Example)
Top-Left (0,0)
Memory
Display
Description
Restriction -This command has no effect when module is already inversion off mode.
Status Availability Yes Yes Yes Yes Yes Default Value Display Inversion off Display Inversion off Display Inversion off
Default
Legend Display Inversion On Mode

Command
Parameter
Display
Flow Chart
INVOFF (20h) Action Mode Display Inversion OFF Sequential transfer
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10.1.16 INVON (21h): Display Inversion On
21H Inst / Para INVON st 1 Parameter D/CX 0 WRX
RDX 1
IVNOFF (Display Inversion On) D17-8 D7 D6 D5 D4 D3 0 0 1 0 0 No Parameter
D2 0
D1 0
D0 1
(Code) (21h) -
-This command is used to enter into display inversion mode -This command makes no change of contents of frame memory. -This command does not change any other status. -To exit from Display Inversion On, the Display Inversion Off command (20h) should be written.
(Example)
Top-Left (0,0)
Description
Memory
Display
Restriction -This command has no effect when module is already Inversion On mode.
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Yes Yes Default Value Display Inversion off Display Inversion off Display Inversion off
Default

Command
Parameter
Display
Flow Chart
INVON (21h) Action Mode Display Inversion OFF Sequential transfer
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10.1.17 GAMSET (26h): Gamma Set
26H Inst / Para GAMSET
1st Parameter
D/CX 0
1
WRX

RDX 1 1
D17-8 -
D7 0
GC7
GAMSET (Gamma Set) D6 D5 D4 0 1 0

GC6 GC5 GC4
D3 0
GC3
D2 1
GC2
D1 1
GC1
D0 0
GC0
(Code) (26h)
-This command is used to select the desired Gamma curve for the current display. A maximum of 4 curves can be selected. The curves are defined in section 9.17 The curve is selected by setting the appropriate bit in the parameter as described in the Table. GS GC[7:0] Reg. LCM1 0 0 01H 1 1 02H 04H Description 08H 01H 02H X X X 0 0 04H 1 1 08H
Note: All other values are undefined.
LCM0 0 1 0 1 X X X X X 0 1 0 1 X
LC Type MVA Transflective(TR)
Gamma
Curve 2.2 Transmissive(TM) N/A Transflective(TR) 1.8 Transflective(TR) 2.5 Transflective(TR) 1.0 Transflective(TR) 1.0 Transflective(TR) 2.5 MVA Transflective(TR) Curve 2.2 Transmissive(TM) N/A Transflective(TR) 1.8
1 X X
-Values of GC [7:0] not shown in table above are invalid and will not change the current selected Gamma Restriction curve until valid is received.
Status Availability Yes Yes Yes Yes Yes Default Value 01h 01h 01h
Default
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---------------GAMSET (26h) Parameter
Display
Legend
Com and
Flow Chart
1st Parameter: GC[7:0]
New Gamma Curve Loaded
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10.1.18 DISPOFF (28h): Display Off
28H Inst / Para DISPOFF st 1 Parameter D/CX 0 WRX
RDX 1
D17-8 -
DISPOFF (Display Off) D7 D6 D5 D4 0 0 1 0 No Parameter
D3 1
D2 0
D1 0
D0 0
(Code) (28h) -
-This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is disables and blank page inserted. -This command makes no change of contents of frame memory. -This command does not change any other status. -There will be no abnormal visible effect on the display. -Exit from this command by Display On (29h)
(Example)
Top-Left (0,0)
Memory
Display
Display OFF VDDI 1.6V-3.0V 2.6V-3.0V STOP 0V 0V Blanking display (over 1 frame display) * 0V STOP
Description
VDD Gate Output Source Output VCOM Output Internal counter Internal Oscillator VGH VGL AVDD IC Internal reset
Restriction -This command has no effect when module is already in Display Off mode.
Status Availability Yes Yes Yes Yes Yes Default Value Display off Display off Display off
Default
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Command
Parameter
Display
Flow Chart
DISPOFF (28h) Action Mode Display Inversion OFF Sequential transfer
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10.1.19 DISPON (29h): Display On
29H Inst / Para DISPON st 1 Parameter D/CX 0 WRX
RDX 1
D17-8 -
DISPON (Display On) D7 D6 D5 D4 0 0 1 0 No Parameter
D3 1
D2 0
D1 0
D0 1
(Code) (29h) -
-This command is used to recover from DISPLAY OFF mode. Output from the Frame Memory is enabled. -This command makes no change of contents of frame memory. -This command does not change any other status.
(Example)
Top-Left (0,0)
Memory
Display
Display ON VDDI 1.6V-3.0V Blanking display (over 1 frame display) * STOP 0V 0V STOP Start
Memory Contents Memory Contents
Description
VDD Gate Output Source Output VCOM Output Internal counter Internal Oscillator VGH VGL AVDD IC Internal reset
2.6V-3.0V
Restriction -This command has no effect when module is already in Display On mode.
Status Availability Yes Yes Yes Yes Yes Default Value Display off Display off Display off
Default
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Legend Display OFF Mode
Command
Parameter
Display
Flow Chart
DISPON (29h) Action Mode Display ON Mode Sequential transfer
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10.1.20 CASET (2Ah): Column Address Set
2AH Inst / Para GAMSET
1st Parameter 2nd Parameter 3rd Parameter 4th Parameter
D/CX 0
1 1 1 1
WRX

RDX 1
1 1 1 1
D17-8 -
CASET(Colume Address Set)_ D7 D6 D5 D4 D3 0 0 1 0 0

XS7 XE7 XS6 XE6 XS5 XE5 XS4 XE4 XS3 XE3
D2 1
XS2 XE2
D1 1
XS1 XE1
D0 0
XS8 XS0 XE8 XE0
(Code) (2Ah)
-This command is used to define area of frame memory where MCU can access. -This command makes no change on the other driver status. -The value of XS [8:0] and XE [8:0] are referred when RAMWR command comes. -Each value represents one column line in the Frame Memory. (Example)
XS[8:0] XE[8:0]
Description
Xaddress start: 0XSEF MV=0 Restriction Xaddress end: XSXEEF MV=0

Status Availability Yes Yes Yes Yes Yes
1. 240x320 memory base 2Status

Power On Sequence S/W Reset H/W Reset Default Value XS[8:0] 0000h 0000h 0000h XE[8:0] 00EFh 00EFh 00EFh
Default
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Partial Mode
CASET (2Ah)
1st & 2nd Parameter: XS[8:0] 3rd & 4th Parameter: XE[8:0]
RASET (2Bh)
Flow Chart
1st & 2nd Parameter: YS[8:0] 3rd & 4th Parameter: YE[8:0]
Legend RAMWR (2Ch)

Command
Parameter Image Data D1[17:0],D2[17:0]Dn[17:0]

Display
Action Mode
Any Command
Sequential
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10.1.21 RASET (2Bh): Row Address Set
2BH Inst / Para RASET (2Bh)
D/CX 0
1 1 1 1
WRX

RDX 1
1 1 1 1
D17-8 -
D7 0
RASET (Row Address Set) D6 D5 D4 D3 0 1 0 1

YS6 YE6 YS5 YE5 YS4 YE4 YS3 YE3
D2 0
YS2 YE2
D1 1
YS1 YE1
D0 1
YS8 YS0 YE8 YE0
(Code) (2Bh)
YS7 YE7
This command is used to define area of frame memory where MCU can access. This command makes no change on the other driver status. The value of YS [8:0] and YE [8:0] are referred when RAMWR command comes. Each value represents one column line in the Frame Memory.
Example
Description
YS[8:0]
YE[8:0]
Xaddress start: 0YS13F MV=0 Restriction Xaddress end: YSYE13F MV=0

1. 240x320 memory base 2Status

Power On Sequence S/W Reset H/W Reset Default Value YS[8:0] 0000h 0000h 0000h YE[8:0] 013Fh 013Fh 013Fh
Default
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Partial Mode
CASET (2Ah)
1st & 2nd Parameter: XS[8:0] 3rd & 4th Parameter: XE[8:0]
RASET (2Bh)
Flow Chart
1st & 2nd Parameter: YS[8:0] 3rd & 4th Parameter: YE[8:0] Legend RAMWR (2Ch)
Command
Parameter Image Data D1[17:0],D2[17:0]Dn[17:0]

Display
Action Mode Any Command Sequential
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10.1.22 RAMWR (2Ch): Memory Write
2CH Inst / Para RAMWR 1st Parameter D/CX 0 1 1 1 WRX

Nth Parameter
RDX 1 1 1 1
D17-8 D17-8
RAMWR (Memory Write) D7 D6 D5 D4 0 0 1 0 D7 D6 D5 D4
D3 1 D3
D2 1 D2
D1 0 D1
D0 0 D0
(Code) (2Ch) -
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
-This command is used to transfer data from MCU to frame memory. -This command makes no change to the other driver status. -When this command is accepted, the column register and the row register are reset to the Start Column/Start Row positions. Description -The Start Column/Start Row positions are different in accordance with MADCTL setting. (See section 9.12) -Then D[23:0] is stored in frame memory and the column register and the row register incremented as section 9.10.2. -Sending any other command can stop Frame Write.
Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Yes Yes Default Value Contents of memory is set randomly Contents of memory is not cleared Contents of memory is not cleared
Default
Legend RAMWR (2Ch)

Command
Parameter
Flow Chart
Image Data D1[17:0],D2[17:0]Dn[17:0]
Display
Action Mode
Any Command
Sequential
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10.1.23 RAMRD (2Eh): Memory Read
2Eh Inst / Para RAMRD
D/CX 0
1 1 1 1
WRX
RDX 1

D17-8 D17-8
RAMRD (Memory Read) D7 D6 D5 D4 D3 0 0 1 0 1
D2 1
D1 1
D0 0
(Code) (2Eh)
(N+1)th Parameter
1 1 1 1
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
D17-8
-This command is used to transfer data from frame memory to MCU. -This command makes no change to the other driver status. -When this command is accepted, the column register and the row register are reset to the Start Column/Start Row positions. -The Start Column/Start Row positions are different in accordance with MADCTL setting. (See section 9.12) Description -Then D[23:0] is read back from the frame memory and the column register and the row register incremented as section 9.10.2. -Frame Read can be canceled by sending any other command. -See section 9.8 Data color coding for color coding (18-bit cases), when there is used 8, 9, 16 and 18-bit data lines for image data. -In all color modes, the Frame Read is always 18- bits and there is no restriction on length of parameters. Restriction -Memory read is only possible via the SPI and parallel interface
Status Availability Yes Yes Yes Yes Yes Default Value Contents of memory is set randomly Contents of memory is not cleared Contents of memory is not cleared
Default
RAMRD (2Eh) Legend Dummy Read

Command
Parameter
Flow Chart
Image Data D1[17:0],D2[17:0]Dn[17:0]
Display
Any Command
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10.1.24 PTLAR (30h): Partial Area
30H Inst / Para PTLAR
D/CX WRX 0
1 1 1 1

RDX D17-8 1 1 1 1 1 -
D7 0
-PSL7 -PEL7
PTLAR (Partial Area) D6 D5 D4 D3 0 1 1 0

-PSL6 -PEL6 -PSL5 -PEL5 -PSL4 -PEL4 -PSL3 -PEL3
D2 0
-PSL2 -PEL2
D1 0
-PSL1 -PEL1
D0 0
PSL8 PSL0 PEL8 PEL0
(Code) (30h)
-This command defines the partial modes display area. -There are 4 parameters associated with this command, the first defines the Start Row (PSL) and the second the End Row (PEL), as illustrated in the figures below. PSL and PEL refer to the Frame Memory row address counter.
-If End Row > Start Row, when MADCTL ML=0
Start Row PSL [8:0] Non-displaying Area
Partial Display Area PEL [8:0] End Row Non-displaying Area
-If End Row > Start Row, when MADCTL ML=1

End Row PEL [8:0] Non-displaying Area
Description
Partial Display Area PSL [8:0] Start Row Non-displaying Area
-If End Row < Start Row, when MADCTL ML=0

End Row Non-displaying Area PSL [8:0] Start Row PEL [8:0] Partial Display Area
-If End Row = Start Row then the Partial Area will be one row deep. Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Default Value PSL[7:0] PE[8] 0000h 0h 0000h 0h 0000h 0h Availability Yes Yes Yes Yes Yes
Status
Default
PSL[8] 0h 0h 0h
PEL[7:0] 0000h 0000h 0000h
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1. To Enter Partial Mode
PTYLAR (30h)
1st & 2nd Parameter: PSEL[8:0] 3rd & 4th Parameter: PEL[8:0]
2. To Exit Partial Mode

Partial Mode DISPOFF (28h)
Optional to prevent tearing effect image display Legend

Command
NORON (13h) Partial Mode OFF
Flow Chart
PTLON (12h) RAMRW (2Ch) Partial Mode Image Data D1[17:0],D2[17:0] Dn[17:0]
Parameter
Display
Action Mode Sequential transfer DISON (29h)
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10.1.25 SCRLAR (33h): Scroll Area
33H Inst / Para PTLAR
1st Parameter 2 Parameter 3rd Parameter 4th Parameter 5th Parameter 6th Parameter
nd
D/CX WRX RDX D17-8 0 1 1 1 1 1 1 1

D7 0
--TFA7
SCRLAR (Scrolll Area) D6 D5 D4 D3 0 1 1 0

--TFA6
D2 0
--TFA2
D1 1
--TFA1
D0 1
TFA8 TFA0 VSA8 VSA0 BFA8 BFA0
(Code) (33h)
1 1 1 1 1 1
--TFA5
--TFA4
--TFA3
--VSA7
--VSA6
--VSA5
--VSA4
--VSA3
--VSA2
--VSA1
--BFA7
--BFA6
--BFA5
--BFA4
--BFA3
--BFA2
--BFA1
-This command defines the Vertical Scrolling Area of the display. When MADCTL ML=0 st nd The 1 & 2 parameter TFA [8:0] describes the Top Fixed Area (in No. of lines from Top of the Frame Memory and Display). rd th The 3 & 4 parameter VSA [8:0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address) The first line appears immediately after the bottom most line of the Top Fixed Area. th th The 5 & 6 parameter BFA [8:0] describes the Bottom Fixed Area (in No. of lines from Bottom of the Frame Memory and Display). TFA, VSA and BFA refer to the Frame Memory row address.
Top-Left (0,0)
Top Fixed Area TFA [8:0] Scroll Fixed Area VSFA [8:0] Bottom Fixed Area BFA [8:0] First line read from
Description
When MADCTL ML=1 st nd The 1 & 2 parameter TFA [8:0] describes the Top Fixed Area (in No. of lines from Bottom of the Frame Memory and Display). rd th The 3 & 4 parameter VSA [8:0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address) The first line appears immediately after the top most line of the Top Fixed Area. th th The 5 & 6 parameter BFA [8:0] describes the Bottom Fixed Area (in No. of lines from Top of the Frame Memory and Display).
Top-Left (0,0)
Bottom Fixed Area BFA [8:0] Scroll Fixed Area VSFA [8:0] Top Fixed Area TFA [8:0] First line read from frame memory
See Section 9.10.4 for details of the Memory to Display Mapping. Restriction -In Vertical Scroll Mode, MADCTL parameter MV should be set to 0-this only affects the Frame Memory Write. TFA[8:0]+VSA[8:0]+BFA[8:0] must equal to 320 or abnoemal display will be observed.
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Status
Default
TFA8 0h 0h 0h
TFA[7:0] 00h 00h 00h
Default Value VFA8 VFA[7:0] 1h 40h 1h 40h 1h 40h
BFA8 0h 0h 0h
BFA[7:0] 00h 00h 00h
1. To Enter Vertical Scroll Mode

Normal Mode SCRLAR (33h)
Legend
Command
Parameter
Display
1st & 2nd Parameter: TFA[8:0] 3rd & 4th Parameter VSA[8:0] 5th & 6th Parameter BFA[8:0] CASET (2Ah) 1st & 2nd Parameter XS[7:0] 3rd & 4th Parameter XE[7:0]
Redefines the Frame memory Window that

the scroll data will be define
RASET (2
1st & 2nd Parameter YS[7:0]
Flow Chart
Only required for non-rolling scrolling
3rd & 4th Parameter YE[7:0] MADCTL (36h) Parameter: MY,MX,MV,ML,RGB RAMRW (2Ch) Scroll Image Data VSCSAD (37h)
1st & 2nd Parameter SS A[7:0] 1
Optional It may be necessary to redefine the Frame Memory Write Direction.
Scroll Mode
NOTE: The Frame Memory Window size must be defined correctly otherwise undesirable image will be displayed.
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Legend
2. Continuous Scroll
Command
Normal Mode CASET (2Ah) 1st 3

rd
Parameter
Display
&2nd Parameter XS[7:0] & 4 Parameter XE[7:0] RASET (2Bh)

th
1st & 2nd Parameter YS[7:0] 3rd & 4th Parameter YE[7:0] RAMRW (2Ch) Only required for non-rolling scrolling Scroll Image Data VSCSAD (37h) 1st & 2nd Parameter SSA[7:0] 1
3. To Exit Vertical Scroll Mode

Scroll Mode DISOFF (28h) NORON (13h) / PTLON (12h) Scroll Mode OFF RAMRW (2Ch) OptionTo prevent Tearing Effect Image Display
Image Data D1[17:0],D2[17:0] Dn[17:0] DISON (29h)
NOTE: Scroll Mode can be exit by both the Normal Display Mode On (13h) and Partial Mode On (12h) commands.
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10.1.26 TEOFF (34h): Tearing Effect Line OFF
34H Inst / Para TEOFF 1st Parameter D/CX 0 WRX
RDX 1
TEOFF (Tearing Effect Line OFF) D17-8 D7 D6 D5 D4 D3 0 0 1 1 0 No Parameter
D2 1
D1 0
D0 0
(Code) (34h) -
Description -This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line. Restriction -This command has no effect when Tearing Effect output is already OFF.
Status Availability Yes Yes Yes Yes Yes Default Value OFF OFF OFF
Default
Legend
Command
TE Line Output ON Parameter

Display
Flow Chart
TE
Action TE Line Output OFF
Mo
Sequential transfer
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10.1.27 TEON (35h): Tearing Effect Line ON
35H Inst / Para TEON 1st Parameter D/CX 0 1 WRX

RDX 1 1
D17-8 -
TEON (Tearing Effect Line ON) D7 D6 D5 D4 D3 0 0 1 1 0

0 0 0 0 0
D2 1
0
D1 0
0
D0 1
TELOM
(Code) (35h)
-This command is used to turn ON the Tearing Effect output signal from the TE signal line. -This output is not affected by changing MADCTL bit ML. -The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect Output Line. (-=Dont Care).
When TELOM(M)=0:
The Tearing Effect Output line consists of V-Blanking information only.

tvdl tvdh
Description
Vertical time scale

When TELOM M=1:
The Tearing Effect Output line consists of both V-Blanking and H-Blinking information.
tvdl tvdh
Vertical time scale
Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low. Restriction -This command has no effect when Tearing Effect output is already OFF.
Status Availability Yes Yes Yes Yes Yes Default Value Tearing effect off & TELOM=0 Tearing effect off & TELOM=0 Tearing effect off & TELOM=0
Default Flow Chart
Legend TE Line Output OFF

Command
Parameter TEON (35h)

Display
Action 1 Parameter: (M)

st
Mode Sequential
TE Line Output ON
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10.1.28 MADCTL (36h): Memory Data Access Control
36H Inst / Para
MADCTL (Memory Data Access Control)

D/CX 0 1 WRX

MADCTL
1st Parameter
RDX 1 1
D17-8 -
D7 0
MY
D6 0
MX
D5 1
MV
D4 1
ML
D3 0
RGB
D2 1
MH
D1 1
0
D0 0
0
(Code) (36h)
-This command defines read/ write scanning direction of frame memory. -This command makes no change on the other driver status. -Bit Assignment
Bit MY MX MV ML NAME Row Address Order Column Address Order Row/Column Exchange Vertical Refresh Order DESCRIPTION These 3bits controls MCU to memory write/read direction. (See Section 9.12) LCD vertical refresh direction control 0 = LCD vertical refresh Top to Bottom 1 = LCD vertical refresh Bottom to Top Color selector switch control 0 =RGB color filter panel, 1 =BGR color filter panel LCD horizontal refresh direction control 0 = LCD horizontal refresh Left to right 1 = LCD horizontal refresh right to left
RGB
RGB-BGR ORDER
MH
Horizontal Refresh Order
ML: Vertical Refresh Order

Top-Left (0,0)
Memory
Sent First Sent 2nd Sent 3rd
Display
ML=0
Sent Last
Description
Top-Left (0,0)
Memory
Sent Last
Display
ML=1
Sent 3rd Sent 2nd Sent First
RGB: RGB-BGR Order RGB=0 Driver IC

RGB RGB SIG1 RG B RGB SIG2 RGB RGB SIG240 RGB RG B
SIG1
RGB=1 Driver IC
RG B R GB SIG2 RG R G BB SIG240
SIG1 RGB BGB R RG
SIG2 RGB B RGB B
SIG240 RGB B RGB B
SIG1
SIG2
SIG240 BGR BG BGR R
BGR BG BGR R
BGR B GR BGR R
LCD Panel
LCD Panel
Ver. 1.7
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MH: Horizontal refresh Order
Top-Left (0,0)
Memory
Top-Left (0,0)
Memory
ML=0
ML=1
Sent 3rd Sent 2nd Sent First
Sent Last
Sent Last
Sent 3rd
Sent First Sent 2nd
Description
Top-Left (0,0)
Display
Top-Left (0,0)
Display
Restriction D1 and D0 of the 1st parameter are set to 00 internally.

Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value MY=0,MX=0,MV=0,ML=0,RGB=0, MH=0 No Change MY=0,MX=0,MV=0,ML=0,RGB=0, MH=0 Legend
Command
Default Flow Chart
MADCTL (36h) Parameter

Display 1st Parameter: MY, MX, ML, RGB, MH
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10.1.29 VSCSAD (37h): Vertical Scroll Start Address of RAM
37H Inst / Para VSCSAD
VSCSAD (Vertical Scroll Start Address of RAM)

D/CX 0 1 1 WRX

RDX 1 1 1
D17-8 -
D7 0
SSA7
D6 0
SSA6
D5 1
SSA5
D4 1
SSA4
D3 0
SSA3
D2 1
SSA2
D1 1
SSA1
D0 1
SSA8 SSA0
(Code) (37h)
-This command is used together with Vertical Scrolling Definition (33h). These two commands describe the scrolling area and the scrolling mode. -The Vertical Scrolling Start Address command has one parameter which describes which line in the Frame Memory will be written as the first line after the last line of the Top Fixed Area on the display as illustrated below: -This command Start the scrolling. -Exit from V-scrolling mode by commands Partial mode On (12h) or Normal mode On (13h).
When MADCTL ML= 0

Example: When Top Fixed Area=Bottom Fixed Area=00, Vertical Scrolling Area=320 and Vertical Scrolling Pointer SSA= 3.
(Example)
Top-Left (0,0) Scan address
Memory
0 1 2 3 318 319 G1 G2 G3 G4 | | G319 G320
Display
Description
SSA[7:0] Scroll start address
When MADCTL ML = 1 Example: When Top Fixed Area= Bottom Fixed Area=00, Vertical Scrolling Area=320 and SSA= 3
(Example)
Top-Left (0,0) Scan address
Memory
319 318 3 2 1 0 G1 G2 G3 G4 | | G319 G320
Display
SSA[7:0] Scroll start address
NOTE: -When new Pointer position and Picture Data are sent, the result on the display will happen at the next Panel Scan to avoid tearing effect. -SSA refers to the Frame Memory scan address.
-Since the value of the Vertical Scrolling Start Address is absolute (with reference to the Frame Memory), it must not enter the fixed area (defined by Vertical Scrolling Definition (33h)- otherwise Restriction undesirable image will be displayed on the Panel. SSA[7:0] is based on 1-line unit. -SSA[7:0] = 0000h, 0001h, 0002h, 0003h, , 00A1h
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes No No Yes
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
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Default
Status Power On Sequence S/W Reset H/W Reset Default Value 0000h 0000h 0000h
Flow Chart See Vertical Scrolling Definition (33h) description.
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10.1.30 IDMOFF (38h): Idle Mode Off
38H Inst / Para IDMOFF 1st Parameter D/CX 0 WRX
IDMOFF (Idle Mode Off) RDX 1 D17-8 D7 D6 D5 0 0 1 No Parameter D4 1 D3 1 D2 0 D1 0 D0 0 (Code) (38h) -
-This command is used to recover from Idle mode on. -There will be no abnormal visible effect on the display mode change transition. Description -In the idle off mode, 1. LCD can display 4096, 65k or 262k colors. 2. Normal frame frequency is applied. Restriction -This command has no effect when module is already in idle off mode.
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Yes Yes Default Value Idle Mode Off Idle Mode Off Idle Mode Off
Default Flow Chart
Legend
Command
Idle mode on
Parameter
Display
IDMOFF (38h)
Action Mode
Idle mode off Sequential transfer
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10.1.31 IDMON (39h): Idle Mode On
39H Inst / Para IDMOFF 1st Parameter D/CX 0 WRX
IDMON (Idle Mode On) RDX 1 D17-8 D7 D6 D5 0 0 1 No Parameter D4 1 D3 1 D2 0 D1 0 D0 1 (Code) (39h) -
-This command is used to enter into Idle mode on. -There will be no abnormal visible effect on the display mode change transition. -In the idle on mode, 1. Color expression is reduced. The primary and the secondary colors using MSB of each R,G and B in the Frame Memory, 8 color depth data is displayed. 2. 8-Color mode frame frequency is applied. 3. Exit from IDMON by Idle Mode Off (38h) command
(Example)
Top-Left (0,0)
Mem ory
Display
Description
Color Black Blue Red Magenta Green Cyan Yellow White
R5 R4 R3 R2 R1 R0 0xxxxx 0xxxxx 1xxxxx 1xxxxx 0xxxxx 0xxxxx 1xxxxx 1xxxxx
G5 G4 G3 G2 G1 G0 0xxxxx 0xxxxx 0xxxxx 0xxxxx 1xxxxx 1xxxxx 1xxxxx 1xxxxx
B5 B4 B3 B4 B1 B0 0xxxxx 1xxxxx 0xxxxx 1xxxxx 0xxxxx 1xxxxx 0xxxxx 1xxxxx
Restriction This command has no effect when module is already in idle on mode.
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes No No Yes Default Value Idle Mode Off Idle Mode Off Idle Mode Off
Default
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Legend
Command
Idle mode on
Parameter
Display
Flow Chart
IDMOFF (38h)
Action Mode
Idle mode off Sequential transfer
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10.1.32 COLMOD (3Ah): Interface Pixel Format
3AH Inst / Para D/CX WRX COLMOD 0 1st Parameter 1 RDX 1 1 D17-8 COLMOD (3Ah): Interface Pixel Format D7 0
VIPF3
D6 0
VIPF2
D5 1
VIPF1
D4 1
VIPF0
D3 1
D3
D2 0
IFPF2
D1 1
IFPF1
D0 0
IFPF0
(Code) (3Ah)
This command is used to define the format of RGB picture data, which is to be transferred via the MCU interface (IFPF) and RGB interface (VIPF). The formats are shown in the table:
Others are no define and invalid
IFPF[2:0] 011 101 110 3 5 6 MCU Interface Color Format 12-bit/pixel 16-bit/pixel 18-bit/pixel RGB Interface Color Format 16-bit/pixel (1-time data transfer) 18-bit/pixel (1-time data transfer) 8-bit/pixel (3-times data transfer)
Description Others are no define and invalid

VIPF[3:0] 0101 0110 1110 5 6 14
Note1: In 12-bit/Pixel, 16-bit/Pixel or 18-bit/Pixel mode, the LUT is applied to transfer data into the Frame Memory. Note2: When RGB I/F the 12-bit/pixel dont care
Restriction There is no visible effect until the Frame Memory is written to.
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes No No Yes Default Value IFPF[2:0] VIPF[3:0] 0110(18-bit/Pixel) No Change 0110(18-bit/Pixel) 0110(18-bit/Pixel) No Change 0110(18-bit/Pixel)
Default
Legend 18-bit/Pixel Mode

Command
Parameter COLMOD (3Ah)

Display
Flow Chart
1st Parameter: P[2:0]=111
16-bit/Pixel Mode
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10.1.33 OTP-Process (3Fh): OTP-Process
3FH Inst / Para GMCTRP1 1 Parameter rd 2 Parameter
st
D/CX 0 1 1
WRX
- - -
RDX 1 1 1
D17-8 -
D7 D6 0 1 0 0 1 0
OTP-Process D5 D4 D3 1 0 0 1 0 0 1 1 0
D2 1 0 0
D1 1 1 INI
D0 1 0 0
(Code) (3Fh) CAh
-While EXTC is fixed to L.

Description Please set INI to 1 for enable OTP
rogramming -While EXTC is fixed to L Please set INI to 0 for disable OTP programing -If this register not using the register need be reserved. Restriction -After adjust the C5H command(VcomH voltage) and C6H command(VcomAC voltage), VPP connect 7.5V.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Default Value Not Fixed 00h 00h Legend
Command
Availability Yes Yes Yes Yes Yes
Default
-----------------OTP-process (FAh)
Parameter
Display
Flow Chart
1st Parameter:
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10.1.34 RDID1 (Dah): Read ID1 Value
DAH Inst / Para RDID1
1st Parameter 2
nd
RDID1 (Read ID1 Value) D/CX 0

1 1
WRX
RDX 1

D17-8 -
D7 1
ID17
D6 1
ID16
D5 0
ID15
D4 1
ID14
D3 1
ID13
D2 0
ID12
D1 1
ID11
D0 0
ID10
(Code) (Dah)
-
1 1
Parameter
-This read byte returns 8-bit LCD modules manufacturer ID st -The 1 parameter is dummy data Description nd -The 2 parameter (ID17 to ID10): LCD modules manufacturer ID. nd NOTE: See command RDDID (04h), 2 parameter. Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out
Availability Yes Yes No No Yes Default Value FF FF FF
Default
Serial I/F Mode

RDID1 (DAh)
Partial I/F Mode

RDID1 (DAh) Host Driver
Legend
Command
Parameter
Display
Flow Chart
Send 2nd parameter: ID1[7:0]
Dummy Read
Action Mode
Sequential transfer
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10.1.35 RDID2 (DBh): Read ID2 Value
DBH Inst / Para RDID2
1st Parameter 2
nd

1 1
WRX
RDX 1

D17-8 -
D7 1
ID27
D6 1
ID26
D5 0
ID25
D4 1
ID24
D3 1
ID23
D2 0
ID22
D1 1
ID21
D0 1
ID20
(Code) (DBh)
-
1 1
Parameter
-This read byte returns 8-bit LCD module/driver version ID st -The 1 parameter is dummy data nd -The 2 parameter (ID26 to ID20): LCD module/driver version ID Description -Parameter Range: ID=80h to FFh NOTE: See command RDDID (04h), 3 parameter. Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out
rd
Default
Flow Chart
Serial I/F Mode
RDID2 (DBh)
Partial I/F Mode

RDID2 (DBh) Host Driver
Legend
Command
Parameter
Display
S : end 2nd parameter ID2[7:0]
Dummy Read
Action Mode
Sequential transfer
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10.1.36 RDID3 (DCh): Read ID3 Value
DCH Inst / Para RDID3
1st Parameter 2
nd

1 1
WRX
RDX 1

D17-8 -
D7 1
ID37
D6 1
ID36
D5 0
ID35
D4 1
ID34
D3 1
ID33
D2 1
ID32
D1 0
ID31
D0 0
ID30
(Code) (DCh)
-
1 1
Parameter
-This read byte returns 8-bit LCD module/driver ID. st -The 1 parameter is dummy data Description -The 2nd parameter (ID37 to ID30): LCD module/driver ID.
NOTE: See command RDDID (04h), 4th parameter.
Restriction
Status
Normal Mode On, Idle Mode Off, Sleep Out
Default
Serial I/F Mode

RDID3 (DCh)
Part
RDID3 (DCh) Host Driver
Legend
Command
Parameter
Display
Flow Chart
Dummy Read
Action Mode
Sequential transfer
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10.2.1 RGBCTR (B0h): RGB signal control
B0H Inst / Para
RGBCTR (RGB signal control)

D/CX 0 1 WRX

RGBCTR
1st Parameter
RDX 1 1
D17-8 -
D7 1
0
D6 0
0
D5 1
0
D4 1
ICM
D3 0
DP
D2 0
EP
D1 0
HSP
D0 0
VSP
(Code) (B0h)
NOTE: - Dont care
-Set the operation status on the RGB interface. The setting becomes effective as soon as the command is received.
-ICM: GRAM Write/Read frequency and data input select on the RGB interface
ICM 0 1
Write cycle PCLK SCL Write/ Read frequency and input data select Read cycle PCLK Internal oscillator Data input D[17:0] SDA
Description
Symbol DP EP HSP VSP Name PCLK polarity set Enable polarity set Hsync polarity set Vsync polarity set Clock polarity set for RGB Interface 1 = data fetched at the falling edge 0 = data fetched at the rising edge 1 = Low enable for RGB interface 0 = High enable for RGB interface 1 = High level sync clock 0 = Low level sync clock 1 = High level sync clock 0 = Low level sync clock
Restriction -If this register not using the register need be reserved.
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Yes Yes Default Value DP/EP/HSP/VSP
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status ICM
Default
-----------------RGBCTR (B0h)
Legend
Command
Parameter
Display
Flow Chart
1 Parameter: ICM, DW, DP, EP, HSP, VSP
st
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10.2.2 FRMCTR1 (B1h): Frame Rate Control (In normal mode/ Full colors)
B1H Inst / Para FRMCTR1
1st Parameter 2 Parameter 3th Parameter
nd
D/CX 0
1 1
WRX

RDX 1
1 1
D17-8
-
D7
1 -------
FRMCTR1 (Frame Rate Control) D6 D5 D4 D3

0
RTNA[6]
D2
0
RTNA[2] FPA[2] BPA[2]
D1
0
D0
1
1
RTNA[5]
1
0
(Code) (B1h)
-
-----
-----
NOTE: - Dont care
-Set the frame frequency of the full colors normal mode. -The frame frequency need to meet 60Hz 5% in this mode.
RTNA[6:0]
0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 1010010 1010011 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
Description
Frame Rate 90 88 86 84 82 80 78 77 75 74 72 71 70 68 67 66 65 63 62 61 60 59 59 57 57 56 55 54 53 53 52 51 51 50 49 48 48 47 47 46 45 45 44 44
RTNA[6:0]
1010100 1010101 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 1100000 1100001 1100010 1100011 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 1101101 1101110 1101111 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
1111111
Frame Rate 43 43 42 42 41 41 40 40 40 39 39 38 38 37 37 37 36 36 36 35 35 35 34 34 34 33 33 33 32 32 32 32 31 31 31 31 30 30 30 30 29 29 29 29
Note: OSC output fre. Is 1.2MHz, FPA=02H and BPA=02H
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FPA[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Timing 0 line 1 line 2 lines 3 lines 4 lines 5 lines 6 lines 7 lines 8 lines 9 lines 10 lines 11 lines 12 lines 13 lines 14 lines 15 lines 16 lines 17 lines 18 lines 19 lines 20 lines 21 lines 22 lines 23 lines 24 lines 25 lines 26 lines 27 lines 28 lines 29 lines 30 lines 31 lines BPA[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Timing 0 line 1 line 2 lines 3 lines 4 lines 5 lines 6 lines 7 lines 8 lines 9 lines 10 lines 11 lines 12 lines 13 lines 14 lines 15 lines 16 lines 17 lines 18 lines 19 lines 20 lines 21 lines 22 lines 23 lines 24 lines 25 lines 26 lines 27 lines 28 lines 29 lines 30 lines 31 lines
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Yes Yes Default Value FPA 02h 02h 02h
Default
RTNA 36h 36h 36h
BPA 02h 02h 02h
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------------FRMCTR1 (B1h) Legend
Command
Parameter
Display 1st Parameter: 2nd Parameter: 3rd Parameter::
Flow Chart
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10.2.3 FRMCTR2 (B2h): Frame Rate Control (In Idle mode/ 8-colors)
1st Parameter 2nd Parameter 3th Parameter
D/CX 0
1 1 1
WRX

RDX 1
1 1 1
D17-8
-
FRMCTR2 (Frame Rate Control) D7 D6 D5 D4 D3

1 ------0
RTNB[6] -----
D2
0
RTNB[2] FPB[2] BPB[2]
D1
1
D0
0
(Code)
1
RTNB[5] -----
1
0
(B2h)
-
NOTE: - Dont care
-Set the frame frequency of the Idle mode. -The frame frequency need to meet 60Hz 5% in this mode.
RTNB[6:0]
0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 1010010 1010011 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
Frame Rate 87 85 83 81 79 78 76 74 73 71 70 69 67 66 65 64 63 62 60 59 58 58 57 56 55 54 53 52 52 51 50 50 49 48 47 47 46 46 45 44 44 43 43 42
RTNB[6:0]
1010100 1010101 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 1100000 1100001 1100010 1100011 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 1101101 1101110 1101111 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
Frame Rate 42 41 41 40 40 40 39 39 38 38 37 37 37 36 36 36 35 35 35 34 34 34 33 33 33 32 32 32 31 31 31 31 30 30 30 30 29 29 29 29 28 28 28 28
Description
1111111
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FPB[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Timing
0 line 1 line 2 lines 3 lines 4 lines 5 lines 6 lines 7 lines 8 lines 9 lines 10 lines 11 lines 12 lines 13 lines 14 lines 15 lines 16 lines 17 lines 18 lines 19 lines 20 lines 21 lines 22 lines 23 lines 24 lines 25 lines 26 lines 27 lines 28 lines 29 lines 30 lines 31 lines
BPB[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Timing
0 line 1 line 2 lines 3 lines 4 lines 5 lines 6 lines 7 lines 8 lines 9 lines 10 lines 11 lines 12 lines 13 lines 14 lines 15 lines 16 lines 17 lines 18 lines 19 lines 20 lines 21 lines 22 lines 23 lines 24 lines 25 lines 26 lines 27 lines 28 lines 29 lines 30 lines 31 lines
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Yes Yes Default Value FPB 02H 02H 02H
Default
RTNB 38H 38H 38H
BPB 02H 02H 02H
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------------FRMCTR1 (B2h) Legend
Command
Parameter
Display 1st Parameter: 2nd Parameter: 3rd Parameter
Flow Chart
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10.2.3 FRMCTR3 (B3h): Frame Rate Control (In Partial mode/ full colors)
1st Parameter 2nd Parameter 3rd arameter 4th Parameter 5th Parameter 6th Parameter
D/CX 0
1 1 1 1 1 1
WRX

RDX 1
1 1 1 1 1 1
D17-8
-
D7
1 ---
FRMCTR3 (Frame Rate Control) D6 D5 D4 D3

0
RTNC[6] RTND[6] -
D2
0
RTNC[2] FPC[2] BPC[2] RTND[2] FPD[2] BPD[2]
D1
1
D0
1
1
RTNC[5] RTND[5] -
1
0
(Code) (B3h)
-
NOTE: - Dont care
-Set the frame frequency of the Partial mode/ full colors. -When the display is frame inversion the frame frequency need to meet 65Hz 5% in this mode. -When the display is line inversion the frame frequency need to meet 70Hz 5% in this mode.
RTNC[6:0]
0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 1010010 1010011 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
Frame Rate 87 85 83 81 79 77 76 74 73 71 70 68 67 66 65 63 62 61 60 59 58 57 56 55 54 54 53 52 51 51 50 49 49 48 47 47 46 45 45 44 44 43 43 42
RTNC[6:0]
1010100 1010101 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 1100000 1100001 1100010 1100011 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 1101101 1101110 1101111 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 1111111 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
Frame Rate 42 41 41 40 40 39 39 39 38 38 37 37 36 36 36 35 35 35 34 34 34 33 33 33 32 32 32 32 31 31 31 30 30 30 30 29 29 29 29 28 28 28 28 28
Description
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RTND[6:0]
0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 1010010 1010011 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
Frame Rate 867 85 83 81 79 77 75 74 72 71 69 68 67 66 64 63 62 61 60 59 58 57 56 55 55 54 53 52 51 51 50 49 49 48 47 47 46 45 45 44 44 43 43 42
RTND[6:0]
1010100 1010101 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 1100000 1100001 1100010 1100011 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 1101101 1101110 1101111 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
Frame Rate 42 41 41 40 40 39 39 38 38 38 37 37 36 36 36 35 35 35 34 34 34 33 33 33 32 32 32 32 31 31 31 30 30 30 30 29 29 29 29 28 28 28 28 28
1111111
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Yes Yes
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Status
Default
RTNC 36h 36h 36h
FPC 02h 02h 02h
Default Value BPC RTND 02h 38h 02h 38h 02h 38h
FPD 02h 02h 02h
BPD 02h 02h 02h
------------FRMCTR1 (B3h)
Legend
Command
Parameter
Display 1st Parameter: 2nd Parameter: 3rd Parameter: . . 6th Parameter:
Flow Chart
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10.2.5 INVCTR (B4h): Display Inversion Control
B4H Inst / Para INVCTR
1st Parameter NOTE: - Dont care
D/CX 0
1
WRX

RDX 1
1
INVCTR (Display Inversion Control) D17-8 D7 D6 D5 D4 D3 D2 1 0 1 1 0 1 0 0 0 0 0 NLA
D1 0
NLB
D0 0
NLC
(Code) (B4h)
02h
-Display Inversion mode control -NLA: Inversion setting in full colors normal mode (Normal mode on)
NLA 0 1 NLB 0 1 NLC 0 1 Inversion setting in full Colors normal mode Line Inversion Frame Inversion Inversion setting in Idle mode Line Inversion Frame Inversion Inversion setting in full Colors partial mode Line Inversion Frame Inversion
-NLB: Inversion setting in Idle mode (Idle mode on)

Description
-NLC: Inversion setting in full colors partial mode (Partial mode on / Idle mode off)
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Yes Yes Default Value NLC 0d 0d 0d
Default
NLA 0d 0d 0d
NLB 1d 1d 1d
B4h 02h 02h 02h
------------INVCTR (B4h)
Legend
Command
Parameter
] Display
Flow Chart
1st Parameter:
NLA, NLB, NLC
Ver. 1.7
171
2008.04.18
ST7787
10.2.6 RGBBPCTR (B5h): RGB Interface Blanking Porch setting
B5H Inst / Para RGBBPCTR
D/CX 0
1 1 1 1
WRX

RDX 1
1 1 1 1
RGBPSET (RGB Interface Blanking Porch setting) D17-8 D7 D6 D5 D4 D3 D2 D1 1 0 1 1 0 1 0

--------------------------------VFP[3] VBP[3] HFP[3] HBP[3] VFP[2] VBP[2] HFP[2] HBP[2] VFP[1] VBP[1] HFP[1] HBP[1]
D0
1 VFP[0] VBP[0] HFP[0] HBP[0]
(Code) (B5h)
-
NOTE: - Dont care
-Set the blanking porch in the RGB interface

Description -The detail settings are designed by driver maker. Restriction -If this register not using the register need be reserved.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Status Default Value VBP[3:0] HFP[3:0] 02H 09H 02H 09H 02H 09H
Availability Yes Yes Yes Yes Yes
Default
VFP[3:0] 00H 00H 00H
HBP[3:0] 09H 09H 09H
------------RGBBPCTR1 (B5h)
Legend
Command
Parameter
Display 1st Parameter: 2nd Parameter: 3rd Parameter: 4th Parameter:
Flow Chart
Ver. 1.7
172
2008.04.18
ST7787
10.2.7 DISSET5 (B6h): Display Function set 5
B6H Inst / Para DISSET5
1st Parameterr 2nd Paramete NOTE: - Dont care
DISSET (Display Function set 5)

D/CX 0
1 1
WRX

RDX 1
1 1
D17-8 -
D7
1 -----
D6
0 -----
D5
1 NO1 ---
D4
1 NO0 ---
D3
0 STD1 PTG1
D2
1 STD0 PTG0
D1
1 EQ1 PT1
D0
0 EQ0 PT0
(Code) (B6h)
02h 02h
-1st parameter: Set output waveform relation. -NO[1:0]: Set the amount of non-overlap of the gate output
NO[1:0]
00 01 10 11 0 1 2 3 Amount of non-overlap of the gate output Refer the Internal oscillator Refer the PCLK 2 clock cycle 8 clock cycle 4 clock cycle 16 clock cycle 8 clock cycle 32 clock cycle 10 clock cycle 40 clock cycle
-SDT[1:0]: Set delay amount from gate signal falling edge of the source output.
SDT[1:0]
-EQ[1:0]: Set the Equalizing period

EQ[1:0]
Gn
Gate Non-overlap period
Description
Gn+1 Sn VCOM
Delay time for source output EQ period
-2nd parameter: Set the output waveform in non-display area. -PTG[1:0]: Determine gate output in a non-display area in the partial mode
PTG[1:0]
00 01 10 11 0 1 2 3 Gate output in a non-display area Normal scan Fix on VGL Fix on VGL Fix on VGL
-PT[1:0]: Determine Source /VCOM output in a non-display area in the partial mode
Source output on non-display area Positive Negative V63 V0 V0 V63 AGND AGND Hi-z Hi-z VCOM output on non-display area Positive Negative VCOML VCOMH VCOML VCOMH AGND AGND AGND AGND
PT[1:0]
00 01 10 11 0 1 2 3
Ver. 1.7
173
2008.04.18
ST7787
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Yes Yes Default Value EQ[1:0] PTG[1:0] 10 00 10 00 10 00
Default
NO[1:0] 00 00 00
STD[1:0] 00 00 00
PT[1:0] 10 10 10
-----------------DISSET5 (B6h)
Legend
Command
Parameter
Display
Flow Chart
1 : st Parameter NO[1:0], STD[1:0], EQ[1:0] 2nd Parameter: PTG[1:0], PT[1:0]
Ver. 1.7
174
2008.04.18
ST7787
10.2.8 VSYNCOUT (BCh):
BCH Inst / Para VSYNCOUT st 1 Parameter
VSYNCOUT
D/CX 0 WRX
RDX 1
D17-8 -
D7
1
D6
0
D5
1
D4
1
D3
1
D2
1
D1
0
D0
0
(Code) (BCh)
No Parameter
NOTE: - Dont care
This command comes off external VSYNC a display synchronous.
Description
Operation shifts to an internal synchronous mode by the VSYNCOUT command while external VSYNC is synchronizing. VSYNCOUT command is recognized frame synchronously. The shift operation becomes the same for the VSYNCOUT command issued within the range of the inside of the figure.
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Yes Yes Default Value OFF OFF OFF
Default
Legend Exxternal VSYNC enable

Command
Parameter
Display
Flow Chart
VSYNCOUT(BCh)
Action Mode
External VSYNC disable
Sequential transfer
Ver. 1.7
175
2008.04.18
ST7787
10.2.9 VSYNCIN (BDh):
BDH Inst / Para VSYNCOUT st 1 Parameter
VSYNCIN
D/CX 0 WRX
RDX 1
D17-8 -
D7
1
D6
0
D5
1
D4
1
D3
1
D2
1
D1
0
D0
1
(Code) (BDh)
No Parameter
NOTE: - Dont care
-The frame to which the command is input finishes sending data by an internal vertical synchronizing signal. Afterward, an external vertical synchronizing signal is waiting for at the rest period. The operation after that becomes external synchronous. Operation enters the rest period when the transmission of data ends for one frame while the external is synchronizing.
Description
wait: Synchronous waiting period. Operation is external VSYNC perceives L level of the VSYNC signal and internal operate and after synchronization t, scans the display for one frame. External VSYNC signal through TE pin. Operation enters the synchronous waiting period again when the display sacanning ends. Restriction -If this register not using the register need be reserved.
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Yes Yes Default Value OFF OFF OFF
Default
Legend Exxternal VSYNC disable

Command
Parameter
Display
Flow Chart
VSYNCOUT(BDh)
Action Mode
External VSYNC enable
Sequential transfer
Ver. 1.7
176
2008.04.18
ST7787
10.2.10 PWCTR1 (C0h): Power Control 1
C0H Inst / Para PWCTR1
1st Parameter
D/CX 0
1
WRX

RDX 1
1
D17-8 -
D7 1
0
PWCTR1 (Power Control 1) D6 D5 D4 D3 1 0 0 0

0 0 VRH4 VRH3
D2 0
VRH2
D1 0
VRH1
D0 0
VRH0
(Code) (C0h)
NOTE: - Dont care
-Set the GVDD and voltage

VRH[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 GVDD 5.00 4.75 4.70 4.65 4.60 4.55 4.50 4.45 4.40 4.35 4.30 4.25 4.20 4.15 4.10 4.05 4.00 3.95 3.90 3.85 3.80 3.75 3.70 3.65 3.60 3.55 3.50 3.45 3.40 3.35 3.25 3.00
Description
-If this register not using the register need be reserved.

Restriction -The deviation value of GVDD between with Measurement and Specification: Max <=50mV
-The deviation value of VCI1 between with Measurement and Specification: Max <= 1%
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Yes Yes Default Value LCM1, LCM0 = 01 TR LC Type VRH[4:0] 10000 10000 10000
Default
Ver. 1.7
177
2008.04.18
ST7787
-----------------PECTR1 (C0h) Legend
Command
Parameter
Display
Flow Chart
1 : st Parameter VRH[4:0]
Ver. 1.7
178
2008.04.18
ST7787
10.2.11 PWCTR2 (C1h): Power Control 2
1st Parameter
nd
D/CX 0
1
WRX

RDX 1
1 1
D17-8 -
D7 1
VGH3

VGH2 VGH1 VGH0 VGL3
D2 0
VGL2 GOT2
D1 0
VGL1 GOT1
D0 1
VGL0 GOT0
(Code) (C1h)
2 Parameter 1 NOTE: - Dont care
--
--
--
--
--
-Set the AVDD, VCL, VGH and VGL supply power level
VGH[2:0]/VGL[2:0]
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VGH
X X X X X 12 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 x
VGL
-5.0 -5.5 -6.0 -6.5 -7.0 -9.0 -9.5 -10.0 -10.5 -11.0 -11.5 -12.0 -12.5 -13.0 -13.5 -14.0
Description -
Unit(V) GOT [2:0]: Define VGH2 level period.

GOT[2:0]
000 001 010 011 100 101 110 111
UC mode OSC clk

0 4 6 9 11 14 16 19
RGB pixel clk

0 16 24 36 44 56 64 76
Note: When VCI1=2.5V, VDD=2.5V,Set-up cycle 1 effective=95%, Set-up cycle 2 effective=98%, -If this register not using the register need be reserved.
Restriction -The deviation value of VGH/ VGL between with Measurement and Specification: Max: VGH-VGL<=1V
-VGH-VGL <= 32V
Ver. 1.7
179
2008.04.18
ST7787
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Yes Yes Default Value VGH[3:0] C0h C0h C0h
Default
GOT[2:0] 00h 00h 00h
VGL[3:0] 80h 80h 80h
-----------------PWCTR2 (C1h)
Legend
Command
Parameter
Display
Flow Chart
1 : st Parameter .2nd Parameter
Ver. 1.7
180
2008.04.18
ST7787
10.2.12 PWCTR3 (C2h): Power Control 3 (in Normal mode/ Full colors)
1st Parameter 2nd Parameter 3rd Parameter 4 Parameter 5 Parameter
th th
D/CX WRX RDX D17-8 0 1 1 1 1 1 1

D7 1
0
STEP1A _SEL3

0
STEP1A _SEL2 LDO5 _SEL2 STEP1AP _SEL2
-
D2 0
APA2
STEP2A _SEL2 STEP4A _SEL2 STEP2PA _SEL2 STEP4PA _SEL2
D1 1
APA1
D0 0
APA0
(Code) (C2h)
1 1 1 1 1
0
-
0
-
0 0
-----
1 -
NOTE: - Dont care
-Set the amount of current in Operational amplifier in normal mode/full colors. -Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver.
APA[2:0] 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7
Amount of Current in Operational Amplifier Operation of the operational amplifier stops Small Medium Low Medium Medium High Large Reserved Reserved
-Set the Booster circuit Step-up cycle in Normal mode/ full colors.
Step1A_SEL[3:0] Step-up cycle in Booster circuit 1 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4
LDO5 [2:0]
000 0
C1S(V)
4.5
0000 0 001 1 4.6 0001 1 010 2 4.7 0010 2 011 3 4.8 0011 3 100 4 4.9 0100 4 101 5 5.0 0101 5 110 6 5.1 0110 6 111 7 X 0111 7 Unit(V) 1000 8 1001 9 1010 10 Description 1011 11 1100 12 1101 13 1110 14 1111 15 Unit:KHz Note:While Step1A_SEL3 setting to 0, the charge pump circuit is selected to Single mode. On the contray to Dual mode.
Step2A_SEL[2:0] Step-up cycle in Booster circuit 2 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 Step4A_SEL[2:0] Step-up cycle in Booster circuit 4 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4
000 001 010 011 100 101 110 111 Unit:KHz
0 1 2 3 4 5 6 7
000 001 010 011 100 101 110 111
0 1 2 3 4 5 6 7
Ver. 1.7
181
2008.04.18
ST7787
1. Set the Booster circuit Step-up cycle during porch area in Normal mode/ full colors.
Step1PA_SEL[2:0] Step-up cycle in Booster circuit 1 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 Step2PA_SEL[2:0] Step-up cycle in Booster circuit 2 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4
000 001 010 011 100 101 110 111 Unit:KHz
0 1 2 3 4 5 6 7
000 001 010 011 100 101 110 111
0 1 2 3 4 5 6 7
Step4PA_SEL[2:0]
000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 Unit:KHz Note: BCLK is Clock frequency for Booster circuit
Step-up cycle in Booster circuit 4 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4
Restriction -If some parameter of the register not use the register need to be reserved.
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Yes Yes Default Value
APA[2:0] Step1A _SEL[3:0] Step2A _SEL[2:0] Ste4A _SEL[2:0] LDO5 _SEL[2:0] Step1PA _SEL[3:0] Step2PA _SEL[2:0] Ste4PA _SEL[2:0]
Default
01h 01h 01h
0Bh 0Bh 0Bh
03h 03h 03h
03h 03h 03h
00h 00h 00h
00h 00h 00h
00h 00h 00h
00h 00h 00h
Legend
-----------------PWCTR3 (C2h)
Command
Parameter
Display
Flow Chart
1st Parameter: APA[2:0] 2nd Parameter: Step1A[3:0] & Step2A[2:0] 3rd Parameter LDO5[2:0] &Step2A[2:0] 4th Parameter Step1PA[2:0] & Step2PA[2:0] 5th Parameter Step4PA[2:0]
Ver. 1.7
182
2008.04.18
ST7787
10.2.13 PWCTR4 (C3h): Power Control 4 (in Idle mode/ 8-colors)
1st Parameter 2nd Parameter 3rd Parameter 4 Parameter 5th Parameter
th
D/CX WRX RDX D17-8 0 1 1 1 1 1 1

D7 1
0
STEP1B _SEL3

0
STEP1B _SEL2
D2 0
APB2
STEP2B _SEL2 STEP4B _SEL2 STEP2PB _SEL2 STEP4PB _SEL2
D1 1
APB1
D0 1
APB0
(Code) (C3h)
1 1 1 1 1
0
STEP1B _SEL1
0
STEP1B _SEL0
0 0
STEP1PB STEP1PB _SEL2 _SEL1
STEP1PB _SEL0
NOTE: - Dont care
-Set the amount of current in Operational amplifier in Idle mode/8 colors. -Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver.
APB[2:0] 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7
-Set the Booster circuit Step-up cycle in Idle mode/8 colors.

Step1B_SEL[3:0] Step-up cycle in Booster circuit 1 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4
0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 Description 1011 11 1100 12 1101 13 1110 14 1111 15 Unit:KHz Note:While Step1B_SEL3 setting to 0, the charge pump circuit is selected to Single mode. On the contray to Dual mode.
Step2B_SEL[2:0] Step-up cycle in Booster circuit 2 OSC/1024 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 Step4B_SEL[2:0] Step-up cycle in Booster circuit 4 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4
000 001 010 011 100 101 110 111
0 1 2 3 4 5 6 7
000 001 010 011 100 101 110 111
0 1 2 3 4 5 6 7
Ver. 1.7
183
2008.04.18
ST7787
1. Set the Booster circuit Step-up cycle during porch area in Idle mode.
Step1PB_SEL[2:0] Step-up cycle in Booster circuit 1 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 Step2PB_SEL[2:0] Step-up cycle in Booster circuit 2 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4
000 001 010 011 100 101 110 111 Unit:KHz
0 1 2 3 4 5 6 7
000 001 010 011 100 101 110 111
0 1 2 3 4 5 6 7
Step4PB_SEL[2:0]
000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 Unit:KHz Note: BCLK is Clock frequency for Booster circuit
APB[2:0] Step1B _SEL[3:0] Step2B _SEL[2:0] Ste4B _SEL[2:0] Step1PB _SEL[3:0] Step2PB _SEL[2:0] Ste4PB _SEL[2:0]
Default
01h 01h 01h
00h 00h 00h
00h 00h 00h
00h 00h 00h
00h 00h 00h
00h 00h 00h
00h 00h 00h
-----------------PWCTR4 (C3h)
Legend
Command
Parameter
Display
Flow Chart
1st Parameter: APB[2:0] 2nd Parameter: Step1B[3:0] & Step2B[2:0] 3rd Parameter Step2B[2:0] 4th Parameter Step1PAB2:0] & Step2PB[2:0] 5th Parameter Step4PB[2:0]
Ver. 1.7
184
2008.04.18
ST7787
10.2.14 PWCTR5 (C4h): Power Control 5 (in Partial mode/ full-colors)
1st Parameter 2nd Parameter 3 Parameter 4 Parameter 5th Parameter NOTE: - Dont care
th rd
D/CX 0
1 1 1 1 1
WRX

RDX 1
1 1 1 1 1
D17-8 -
PWCTR5 (Power Control 5) D7 D6 D5 D4 D3 1 1 0 0 0

0 0 -0 0 STEP1C STEP1C STEP1C STEP1C _SEL3 _SEL2 _SEL1 _SEL0
D2 1
APC2
STEP2C _SEL2 STEP4C _SEL2 STEP2PC _SEL2 STEP4PC _SEL2
D1 0
APC1
D0 0
APC0
(Code) (C4h)
00h
0 0 -
STEP1PC STEP1PC STEP1PC _SEL2 _SEL1 _SEL0
-Set the amount of current in Operational amplifier in Partial mode/ full-colors. -Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver.
APC[2:0] 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7
-Set the Booster circuit Step-up cycle in Partial mode/ full-colors.

Note: BCLK is Clock frequency for Booster circuit
Step1C_SEL[3:0] Step-up cycle in Booster circuit 1 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4
0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 Description 1011 11 1100 12 1101 13 1110 14 1111 15 Unit:KHz Note:While Step1B_SEL3 setting to 0, the charge pump circuit is selected to Single mode. On the contray to Dual mode.
Step2C_SEL[2:0] Step-up cycle in Booster circuit 2 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4 Step4C_SEL[2:0] Step-up cycle in Booster circuit 4 OSC/2048 OSC/1024 OSC/512 OSC/128 OSC/64 OSC/16 OSC/8 OSC/4
000 001 010 011 100 101 110 111
0 1 2 3 4 5 6 7
000 001 010 011 100 101 110 111
0 1 2 3 4 5 6 7
Ver. 1.7
185
2008.04.18
ST7787
1. Set the Booster circuit Step-up cycle during porch area in Partial mode/ full-colors.
Step1PC_SEL[2:0]
000 001 010 011 100 101 110 111 Unit:KHz
0 1 2 3 4 5 6 7
Step2PC_SEL[2:0]
000 001 010 011 100 101 110 111
0 1 2 3 4 5 6 7
Step4PC_SEL[2:0]
000 001 010 011 100 101 110 111 Unit:KHz
0 1 2 3 4 5 6 7
Note: BCLK is Clock frequency for Booster circuit
APC[2:0] Step1C _SEL[3:0] Step2C _SEL[2:0] Ste4C _SEL[2:0] Step1PC _SEL[3:0] Step2PC _SEL[2:0] Ste4PC _SEL[2:0]
Default
01h 01h 01h
0Bh 0Bh 0Bh
03h 03h 03h
03h 03h 03h
00h 00h 00h
00h 00h 00h
00h 00h 00h
-----------------PWCTR4 (C4h)
Legend
Command
Parameter
Display
Flow Chart
1st Parameter: APB[2:0] 2nd Parameter: Step1B[3:0] & Step2B[2:0] 3rd Parameter Step2B[2:0] 4th Parameter Step1PAB2:0] & Step2PB[2:0] 5th Parameter Step4PB[2:0]
Ver. 1.7
186
2008.04.18
ST7787
10.2.15 VMCTR1 (C5h): VCOM Control 1
C5H Inst / Para VMCTR1
1st Parameter 2
nd rd
D/CX WRX RDX D17-8 D7 0 1 1

1 1 1
D6 1
VMH_R6
VMH _IDMON6 ---
VMCTR1 (VCOM Control 1) D5 D4 D3 0 0 0

VMH_R5
VMH _IDMON5 ----
D2 1
VMH_R2
VMH _IDMON2 ----
D1 0
VMH_R1
VMH _IDMON1 ----
D0 1
VMH_R0
VMH _IDMON0 ----
(Code) (C5h)
1 1 1
0 0 nVM0
VMH_R4
VMH _IDMON4 ----
VMH_R3
VMH _IDMON3 ----
Parameter
3 Parameter
NOTE: - Dont care
-Set VCOMH Voltage in normal mode/full colors.

VMH[6:0] 0000000 0 0000001 1 0000010 2 0000011 3 0000100 4 0000101 5 0000110 6 0000111 7 0001000 8 0001001 9 0001010 10 0001011 11 0001100 12 0001101 13 0001110 14 0001111 15 0010000 16 0010001 17 0010010 18 0010011 19 0010100 20 0010101 21 0010110 22 0010111 23 0011000 24 0011001 25 0011010 26 VCOMH
Description
2.500 2.525 2.550 2.575 2.600 2.625 2.650 2.675 2.700 2.725 2.750 2.775 2.800 2.825 2.850 2.875 2.900 2.925 2.950 2.975 3.000 3.025 3.050 3.075 3.100 3.125 3.150
VMH[6:0] 0011011 0011100 0011101 0011110 0011111 0100000
VCOMH 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
0100001
0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101
3.175 3.200 3.225 3.250 3.275 3.300 3.325 3.350 3.375 3.400 3.425 3.450 3.475 3.500 3.525 3.550 3.575 3.600 3.625 3.650 3.675 3.700 3.725 3.750 3.775 3.800 3.825
VMH[6:0] 0110110 54 0110111 55 0111000 56 0111001 57 0111010 58 0111011 59 0111100 60 0111101 61 0111110 62 0111111 63 1000000 64 1000001 65 1000010 66 1000011 67 1000100 68 1000101 69 1000110 70 1000111 71 1001000 72 1001001 73 1001010 74 1001011 75 1001100 76 1001101 77 1001110 78 1001111 79 1010000 80
VCOMH
3.850 3.875 3.900 3.925 3.950 3.975 4.000 4.025 4.050 4.075 4.100 4.125 4.150 4.175 4.200 4.225 4.250 4.275 4.300 4.325 4.350 4.375 4.400 4.425 4.450 4.475 4.500
VMH[6:0] 1010001 81 1010010 82 1010011 83 1010100 84 1010101 85 1010110 86 1010111 87 1011000 88 1011001 89 1011010 90 1011011 91 1011100 92 1011101 93 1011110 94 1011111 95 1100000 96 1100001 97 1100010 98 1100011 99 1100100 100 1100101 101 | 1111111 127
VCOMH
4.525 4.550 4.575 4.600 4.625 4.650 4.675 4.700 4.725 4.750 4.775 4.800 4.825 4.850 4.875 4.900 4.925 4.950 4.975 5.000 Not Permitted
-When the VCOM circuit use VOCMH + VCOMAC -The VCOML is generated from VCOMH-VCOMAC -VcomH voltage also can be adjusted by VMH_IDOMON[6:0] register in Idle mode/8 colors.
VMH _IDOMON[6:0] 0000000 0 0000001 1 0000010 2 0000011 3 0000100 4 0000101 5 0000110 6 0000111 7 0001000 8 0001001 9 0001010 10 0001011 11 0001100 12 0001101 13 0001110 14 0001111 15 0010000 16 0010001 17 0010010 18 0010011 19 0010100 20 0010101 21 0010110 22 VCOMH
2.500 2.525 2.550 2.575 2.600 2.625 2.650 2.675 2.700 2.725 2.750 2.775 2.800 2.825 2.850 2.875 2.900 2.925 2.950 2.975 3.000 3.025 3.050
VMH _IDOMON[6:0] 0011011 27 0011100 28 0011101 29 0011110 30 0011111 31 0100000 32 0100001 33 0100010 34 0100011 35 0100100 36 0100101 37 0100110 38 0100111 39 0101000 40 0101001 41 0101010 42 0101011 43 0101100 44 0101101 45 0101110 46 0101111 47 0110000 48 0110001 49
VCOMH
3.175 3.200 3.225 3.250 3.275 3.300 3.325 3.350 3.375 3.400 3.425 3.450 3.475 3.500 3.525 3.550 3.575 3.600 3.625 3.650 3.675 3.700 3.725
VMH _IDOMON[6:0] 0110110 54 0110111 55 0111000 56 0111001 57 0111010 58 0111011 59 0111100 60 0111101 61 0111110 62 0111111 63 1000000 64 1000001 65 1000010 66 1000011 67 1000100 68 1000101 69 1000110 70 1000111 71 1001000 72 1001001 73 1001010 74 1001011 75 1001100 76
VCOMH
3.850 3.875 3.900 3.925 3.950 3.975 4.000 4.025 4.050 4.075 4.100 4.125 4.150 4.175 4.200 4.225 4.250 4.275 4.300 4.325 4.350 4.375 4.400
VMH _IDOMON[6:0] 1010001 81 1010010 82 1010011 83 1010100 84 1010101 85 1010110 86 1010111 87 1011000 88 1011001 89 1011010 90 1011011 91 1011100 92 1011101 93 1011110 94 1011111 95 1100000 96 1100001 97 1100010 98 1100011 99 1100100 100 1100101 101 | 1111111 127
VCOMH
4.525 4.550 4.575 4.600 4.625 4.650 4.675 4.700 4.725 4.750 4.775 4.800 4.825 4.850 4.875 4.900 4.925 4.950 4.975 5.000 Not Permitted
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0010111 0011000 0011001 0011010 23 24 25 26
3.075 3.100 3.125 3.150
0110010 0110011 0110100 0110101
50 51 52 53
3.750 3.775 3.800 3.825
1001101 1001110 1001111 1010000
77 78 79 80
4.425 4.450 4.475 4.500
-Set VCOMH Voltage in normal mode/full colors. -When nVM0=1, VcomH voltage can be adjusted by VMH_R[6:0] register. -When nVM0=0, VcomH rogram will be setted by OTP register value. -If this register not using the register need be reserved. Restriction -The deviation value of VCOMH/VCOML between with Measurement and Specification: Max<=30mV -The deviation value of VCOMAC between with Measurement and Specification: Max <=50mV
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Yes Yes Default Value nVM0=0, VMH_COLOR8M[6:0] 28h 28h 28h
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset nVM0=0, VMH_R[6:0] 28h 28h 28h
Default
Legend PWCTR4 (C5h)

Command
Parameter
Display
Flow Chart
1st Parameter: VMH_R[6:0] 2nd Parameter: VMH_COLOR8M[6:0] 3rd Parameter nVM0
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188
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10.2.16 VMCTR2 (C6h): VCOM Control 2
C6H Inst / Para VMCTR2
D/CX WRX RDX D17-8 0

1 1

D7
1 0 0
VMCTR2 (VCOM Control 2) D6 D5 D4 D3

1 0 0 0 0 0
D2
1
D1
1
D0
0
(Code) (C6h)
1
1 1
VMA5 VMA4 VMA3 VMA2 VMA1 VMA0 VMA VMA VMA VMA VMA VMA _IDMON5 _IDMON4 _IDMON3 _IDMON2 _IDMON1 _IDMON0
NOTE: - Dont care
-Set VCOMAC Voltage in normal mode/full colors.

VMA[5:0] 000000 0 000001 1 000010 2 000011 3 000100 4 000101 5 000110 6 000111 7 001000 8 001001 9 001010 10 001011 11 001100 12 001101 13 001110 14 001111 15 VMA _IDMON[5:0] 000000 0 000001 1 000010 2 000011 3 000100 4 000101 5 000110 6 000111 7 001000 8 001001 9 001010 10 001011 11 001100 12 001101 13 001110 14 001111 15 VCOMAC 4.000 4.050 4.100 4.150 4.200 4.250 4.300 4.350 4.400 4.450 4.500 4.550 4.600 4.650 4.700 4.750 VCOMAC 4.000 4.050 4.100 4.150 4.200 4.250 4.300 4.350 4.400 4.450 4.500 4.550 4.600 4.650 4.700 4.750 VMA[5:0] 010000 16 010001 17 010010 18 010011 19 010100 20 010101 21 010110 22 010111 23 011000 24 011001 25 011010 26 011011 27 011100 28 011101 29 011110 30 011111 31 VMA _IDMON[5:0] 010000 16 010001 17 010010 18 010011 19 010100 20 010101 21 010110 22 010111 23 011000 24 011001 25 011010 26 011011 27 011100 28 011101 29 011110 30 011111 31 VCOMAC 4.800 4.850 4.900 4.950 5.000 5.050 5.100 5.150 5.200 5.250 5.300 5.350 5.400 5.450 5.500 5.550 VCOMAC 4.800 4.850 4.900 4.950 5.000 5.050 5.100 5.150 5.200 5.250 5.300 5.350 5.400 5.450 5.500 5.550 VMA[5:0] 100000 32 100001 33 100010 34 100011 35 100100 36 100101 37 100110 38 100111 39 101000 40 101001 41 | 111111 63 VCOMAC 5.600 5.650 5.700 5.750 5.800 5.850 5.900 5.950 6.000 Not Permitted
Description -Set VCOMAC Voltage in Idle mode/8 colors.

VMA _IDMON[5:0] 100000 32 100001 33 100010 34 100011 35 100100 36 100101 37 100110 38 100111 39 101000 40 101001 41 | 111111 63 VCOMAC 5.600 5.650 5.700 5.750 5.800 5.850 5.900 5.950 6.000 Not Permitted
Restriction
-If this register not use the register need be reserved. -The deviation value of VCOMAC between with Measurement and Specification: Max <=50mV
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Yes Yes
Default
Default Value LCM1, LCM0 = 01 TR LC Type LCM1, LCM0 = 01 TR LC Type VMA[6:0] VMA_IDMON[5:0] 06h 00h 06h 00h 06h 00h
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-----------------VMCTR4 (C6h) Legend
Command
Parameter
Display
Flow Chart
1st Parameter: VMA[5:0] 2nd Parameter: VMA_IDMON[5:0]
Ver. 1.7
190
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10.2.17 WRID1 (D0h): OTP ID1 set LCM version code D0H OTP ID1 set LCM version code
Inst / Para OTP-read
1 Parameter
st
D/CX 0
1
WRX

RDX 1
1
D17-8 -
D7
1
D6
1
D5
0
D4
1
D3
0
D2
0
D1
0
D0
0
(Code) (D0h)
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
-OTP ID1 set the LCM version code

Description

Restriction -After adjust the C5H command(VcomH voltage) and C6H command(VcomAC voltage), VPP connect
7.5V.
Status Normal Mode On, Idle Mode Ooff, Sleep Out Availability Yes Yes Yes Yes No Default Value N/A N/A N/A
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode Off, Idle Mode On, Sleep Out Sleep In Status
Default
Legend
Command
Parameter
Flow Chart
Display
Ver. 1.7
191
2008.04.18
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10.2.18 WRID2 (D1h): OTP ID2 set LCM version code
D1H Inst / Para OTP-read
1st Parameter
OTP ID2 set LCM version code

D/CX 0
1
WRX

RDX 1
1
D17-8 -
D7
1
D6
1
D5
0
D4
1
D3
0
D2
0
D1
0
D0
1
(Code) (D1h)
ID26
ID25
ID24
ID23
ID22
ID21
ID20
-OTP ID2 set the LCM version code

Description

Restriction -After adjust the C5H command(VcomH voltage) and C6H command(VcomAC voltage), Vpp connect
7.5V.
Default
Legend
Command
Parameter
Flow Chart
Display
Ver. 1.7
192
2008.04.18
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10.2.19 WRID3 (D2h): OTP ID3 set Project code
D2H Inst / Para OTP-read
1st Parameter
OTP ID3 set LCM version code

D/CX 0
1
WRX

RDX 1
1
D17-8 -
D7
1
D6
1
D5
0
D4
1
D3
0
D2
0
D1
1
D0
0
(Code) (D2h)
ID37
ID36
ID35
ID34
ID33
ID32
ID31
ID30
-OTP ID3 set the project code

Description

Restriction -After adjust the C5H command(VcomH voltage) and C6H command(VcomAC voltage), VPP connect
7.5V.
Default
Legend
Command
Parameter
Flow Chart
Display
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193
2008.04.18
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10.2.20 OTP-Load (Deh): OTP read command
DEH Inst / Para OTP-read
1st Parameter
D/CX 0
1
WRX

RDX 1
1
D17-8 -
D7
1
D6
1
OTP-Load D5 D4
0 1
D3
1
D2
1
D1
1
D0
0
(Code) (Deh) (75H)
-Read OTP value

Description After OTP
rogramming, IC will download the OTP value. If you change the VcomH register, you can execute Deh command to re-download OTP. Restriction -If this register not using the register need be reserved.
Status Normal Mode On, Idle Mode Ooff, Sleep Out Availability Yes Yes Yes Yes No Default Value 75h 75h 75h
Default
Legend
Command
Parameter
Flow Chart
Display
Ver. 1.7
194
2008.04.18
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10.2.21 OTP-Prog (DFh): OTP Programimng command
DFH Inst / Para OTP-read
1st Parameter 2nd Parameter 3rd Parameter 4rd Parameter 5rd Parameter
D/CX 0
1 1 1 1 1
WRX

RDX 1
1 1 1 1 1
D17-8 -
D7
1
D6
1
OTP-Prog D5 D4
0 1
D3
1
D2
1
D1
1
D0
0
0 0 1 1 0
1 0 0 0 1
1 0 1 1 0
1 0 0 0 1
0 0 1 0 1
1 0 0 1 0
0 0 1 0 1
1 0 0 1 0
(Code) (DFh) (CAH) (00H) (AAH) (A5H) (5AH)
- OTP download
Description -Set the VcomH voltage in normal mode/full colors and Idle mode/8 colors.
-Set the VcomAC voltage in normal mode/full colors and Idle mode/8 colors. -If this register not using the register need be reserved. Restriction -After adjust the C5H command(VcomH voltage) and C6H command(VcomAC voltage), VPP connect 7.5V.
Status Normal Mode On, Idle Mode Ooff, Sleep Out Availability Yes Yes Yes Yes No Default Value No change No change No change
Default
Legend
Command
Parameter
Display
Flow Chart
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195
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10.2.22 GMCTRP1 (E0h): Gamma (+polarity) Correction Characteristics Setting
E0H
Inst / Para GMCTRP1 1 Parameter nd 2 Parameter rd 3 Parameter th 4 Parameter th 5 Parameter th 6 Parameter th 7 Parameter th 8 Parameter th 9 Parameter th 10 Parameter th 11 Parameter th 12 Parameter th 13 Parameter
st
D/CX WRX RDX D17-8 0 1 1 1 1 1 1 1 1 1 1 1 1 1

- - - - - - - - - - - - - -
GMCTRP0 (Gamma +polarity Correction Characteristics Setting) D7 D6 D5 D4 D3 D2 D1 D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MVA_EN 1 1 0 0 0 0 0 RFP0[3] RFP0[2] RFP0[1] RFP0[0] PKP0[3] PKP0[2] PKP0[1] PKP0[0] PKP1[4] PKP1[3] PKP1[2] PKP1[1] PKP1[0] PKP2[4] PKP2[3] PKP2[2] PKP2[1] PKP2[0] PKP3[4] PKP3[3] PKP3[2] PKP3[1] PKP3[0] PKP4[4] PKP4[3] PKP4]2] PKP4]1] PKP4]0] PKP5[4] PKP5[3] PKP5]2] PKP5]1] PKP5]0] PKP6[4] PKP6[3] PKP6[2] PKP6[1] PKP6[0] PKP7[4] PKP7[3] PKP7[2] PKP7[1] PKP7[0] PKP8[3] PKP8[2] PKP8[1] PKP8[0] RFP1[3] RFP1[2] RFP1[1] RFP1[0] OSP1[2]OSP1[1]OSP1[0] OSP0[4] OSP0[3]OSP0[2]OSP0[1]OSP0[0]
(Code) (E0h)
Register Group
High level adjustment
Negative Polarity
RFP0[3:0] PKP0[3:0] PKP1[4:0] PKP2[4:0] PKP3[4:0] PKP4[4:0]
Set-up Contents
Variable resistor VRHP The voltage of grayscale number 3 is selected by the 16 to 1 selector The voltage of grayscale number 6 is selected by the 32 to 1 selector The voltage of grayscale number 11 is selected by the 32 to 1 selector The voltage of grayscale number 20 is selected by the 32 to 1 selector The voltage of grayscale number 31 is selected by the 32 to 1 selector The voltage of grayscale number 43 is selected by the 32 to 1 selector The voltage of grayscale number 52 is selected by the 32 to 1 selector The voltage of grayscale number 57 is selected by the 32 to 1 selector The voltage of grayscale number 60 is selected by the 16 to 1 selector The voltage of grayscale number 1 is selected by the 16 to 1 selector The voltage of grayscale number 62 is selected by the 7 to 1 selector Variable resistor VRLP
Description
Mid level adjustment
PKP5[4:0] PKP6[4:0] PKP7[4:0] PKP8[3:0] RFP1[3:0] OSP1[2:0]
Low level adjustment
OSP0[4:0]
-When MVA_EN=1, The Gamma correction select to MVA type -When MVA_EN=0, The Gamma correction dont select to MVA type Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Yes Yes
Ver. 1.7
196
2008.04.18
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Default
Status Power On Sequence S/W Reset H/W Reset Default Value Not Fixed Not Fixed Not Fixed Legend
Command
-----------------GMCTRP1 (E0h)
Parameter
Display
Flow Chart
1st Parameter: | 13th Parameter
Ver. 1.7
197
2008.04.18
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10.2.23 GMCTRN1 (E1h): Gamma (-polarity) Correction Characteristics Setting
E1H
Inst / Para GMCTRP1 1 Parameter nd 2 Parameter rd 3 Parameter th 4 Parameter th 5 Parameter th 6 Parameter th 7 Parameter th 8 Parameter th 9 Parameter th 10 Parameter th 11 Parameter th 12 Parameter th 13 Parameter
st
D/CX 0 1 1 1 1 1 1 1 1 1 1 1 1 1
WRX
- - - - - - - - - - - - - -
GMCTRP0 (Gamma +polarity Correction Characteristics Setting) RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 RFN0[3] RFN0[2] RFN0[1] RFN0[0] PKN0[3] PKN0[2] PKN0[1] PKN0[0] PKN1[4] PKN1[3] PKN1[2] PKN1[1] PKN1[0] PKN2[4] PKN2[3] PKN2[2] PKN2[1] PKN2[0] PKN3[4] PKN3[3] PKN3[2] PKN3[1] PKN3[0] PKN4[4] PKN4[3] PKN4]2] PKN4]1] PKN4]0] PKN5[4] PKN5[3] PKN5]2] PKN5]1] PKN5]0] PKN6[4] PKN6[3] PKN6[2] PKN6[1] PKN6[0] PKN7[4] PKN7[3] PKN7[2] PKN7[1] PKN7[0] PKN8[3] PKN8[2] PKN8[1] PKN8[0] RFN1[3] RFN1[2] RFN1[1] RFN1[0] OSN1[2]OSN1[1]OSN1[0] OSN0[4] OSN0[3] OSN0[2]OSN0[1]OSN0[0]
(Code) (E1h)
Register Group
High level adjustment
Negative Polarity
RFN0[3:0] PKN0[3:0] PKN1[4:0] PKP2[4:0] PKN3[4:0] PKN4[4:0]
Set-up Contents
Variable resistor VRHN The voltage of grayscale number 3 is selected by the 16to 1 selector The voltage of grayscale number 6 is selected by the 32 to 1 selector The voltage of grayscale number 11 is selected by the 32 to 1 selector The voltage of grayscale number 20 is selected by the 32 to 1 selector The voltage of grayscale number 31 is selected by the 32 to 1 selector The voltage of grayscale number 43 is selected by the 32 to 1 selector The voltage of grayscale number 52 is selected by the 32 to 1 selector The voltage of grayscale number 57 is selected by the 64 to 1 selector The voltage of grayscale number 60 is selected by the 16 to 1 selector The voltage of grayscale number 1 is selected by the 16 to 1 selector The voltage of grayscale number 62 is selected by the 7 to 1 selector Variable resistor VRLN
Description Mid level adjustment
PKN5[4:0] PKN6[4:0] PKN7[4:0] PKN8[3:0] RFN1[3:0] OSN1[2:0]
Low level adjustment Restriction
OSN0[4:0]
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes Yes Yes Yes Default Value Not Fixed Not Fixed Not Fixed
Default
Ver. 1.7
198
2008.04.18
ST7787
Legend GMCTRP1 (E1h)
Command
Parameter
Display
Flow Chart
1st Parameter: | 13th Parameter
Ver. 1.7
199
2008.04.18
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10.2.24 Vcom multi_mode (FBh):
DEH Inst / Para
Vcom_multi_mode
1st Parameter
D/CX WRX RDX D17-8 0

1

D7
1
D6
1
OTP-Load D5
1
D4
1
D3
1
D2
0
D1
1
D0
1
(Code) (FBh)
1
1
Vcom _multi_mode
-Vcom multi_mode
Description For power saving, please set the Vcom_multi_mode=1. Restriction

Status Normal Mode On, Idle Mode Ooff, Sleep Out Availability Yes Yes Yes Yes No Default Value 7Fh 7Fh 7Fh
Default
Legend
Command
Parameter
Flow Chart
Display
Ver. 1.7
200
2008.04.18
ST7787
11. Display Module Default Position
The default position of the display is always as follow, when MADCTLs (36h) parameter is 00h.
Display driver
The 1st pixel on the display. This is also the 1st access location
RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB
Ver. 1.7
201
2008.04.18
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12. Power structure
12.1. Driver IC Operating voltages Specification
VGH(12V~16.5V) AVDD(4.9V~6.6V)
GVDD(3.0V~5.0V) VDD=(2.45V-3.0V) Charge pump VCOMH(2.5V~5.0V)
Internal Reference Voltage AGND=0V VCOML(-2.5V~0V)
VCL(-3.3V~-2.2V)
VGL(-5V~-14V)
Remark 1. AVDD supply to all power source (exclude VGH, VGL) 2. Source output range: 0.1V ~ AVDD-0.1V 3. Linear Range: 0.2V ~ AVDD-0.2V (For all output voltage, but exclude VGH, VGL) 4. Above operating voltages is min range.
Ver. 1.7
202
2008.04.18
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12.2 Power Booster Circuit 12.2.1 VCI1 generate from VDD regulator
VDD CVDD AVDD Reference Voltage generator Vref
Source Output Circuit Block
S1 | S720
Gray reference Circuit Block (Gamma) AVDD
Vref VC [2:0}
VCI1
Vref AGND VCI1 CVci1 AGND AVDD C11 Boost 1 (x2)VCI1 set-yp 1 BT[2:0] DC[2:0] Or DCT[2:0] AVDD CAVDD VRH [4:0}
GVDD CVCI1
C12
Vref VMH[6:0} + VMOF[6:0]
VCOMH CVMH
AGND VCOM C21 VGH Boost 2,3,4 (x4, x5, x6)VCI1 (x-2, x-4, x-5)VCI1 (x-1)VCI1 VDD
CVGH
VCOML AGND C23 VGL Set-Up 2,3,4 CVGL VCL Vref VMH[6:0} + VMOF[6:0] CVML
VGH BT[2:0] DC[2:0] or DCT[2:0] VGL
Gate output Cirrect Block
G1 | G320
C22 VCL CVCL
VDDI CVDDI
Fig. 12.2.1 Power Booster Structure (1)
Ver. 1.7
203
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12.2.2 EXTERNAL COMPONENTS CONNECTION
Pad Name
VDDI VDD VCC AGND DGND C23P, C23N C22P, C22N C21P, C22N C12P, C12N C11P, C11N AVDD VCI1 VGH VGL VCL VREF GVDD VCOMH VCOML VC1S VGL
Connection
VDDI (Logic Power) VDD (Analog Power) Connect to Capacitor (Max 3V): VCC -------||-------- GND Analog ground (Connect to GND) Digital ground (Connect to GND) Connect to Capacitor: C23P -------||--------C23N Connect to Capacitor: C22P -------||--------C22N Connect to Capacitor: C21P -------||--- -----C21N Connect to Capacitor: C12P -------||--------C12N Connect to Capacitor: C11P -------||--------C11N Connect to Capacitor: AVDD -------||-------- GND Connect to Capacitor: AVDD -------||-------- GND Connect to Capacitor: VGH -------||-------- GND Connect to Capacitor: VGL -------||-------- GND Connect to Capacitor: VCL -------||-------- GND Connect to Capacitor: VREF -------||-------- GND Connect to Capacitor: GVDD -------||-------- GND Connect to Capacitor: VCOMH-------||--------- GND Connect to Capacitor: VCOML -------||-------- GND Connect to Capacitor: VC1S -------||-------- GND Connect to Schottky diode: VGL -------.|-------- GND
Rated (Min) Voltage

10.0V 10.0V 10.0V
Typical capacitance value

1.0 uF 1.0 uF 1.0 uF
25.0V 25.0V 10.0V 10.0V 10.0V 10.0V 10.0V 25.0V 25.0V 10.0V 10.0V 10.0V 10.0V 10.0V 10V 30V
1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0uF Schottky diode
Ver. 1.7
204
2008.04.18
ST7787
13. Gamma structure 13.1 STRUCTURE OF GRAYSCALE AMPLIFIER
The structure of grayscale amplifier is shown as below. 13 voltage levels (VIN0-VIN12) between GVDD and VGS are determined by the high/ mid/ low level adjustment registers. Each mid-adjustment level is split into 64 levels again by the internal ladder resistor network. As a result, grayscale amplifier generates 64 voltage levels ranging from V0 to V63 and outputs one of 64 levels.
Positive frame
GVDD GVDD
Negative frame
30R
30R
RF0P[3:0]
0~2
R 2.5
Step : 1.5R OS0N[3:0] V0
R 2.5 0~2
Step : 1.5R
V63
8R 0~2
RF1P[3:0]
0~3
0R
Step : 2R V1
OS1N[2:0]
Step : 4R
V62 V3 V6 V11 V20 V31 V43 V52 V57 V60 PKN8[3:0] PKN7[4:0] PKN6[4:0] PKN5[4:0] PKN4[4:0] PKN3[4:0] PKN2[4:0] PKN1[4:0] PKN0[3:0] V60 V57 V52 V43
PKP0[3:0] PKP1[4:0] PKP2[4:0] PKP3[4:0] PKP4[4:0] PKP5[4:0] PKP6[4:0] PKP7[4:0] PKP8[3:0]
184R
V31 V20 V11 V6 V3
V62
8R 0~2
V1
0R 0~3
OS1P[2:0]
Step : 4R
RF1N[3:0]
Step : 2R
V63
R 2.5 0~2
V0
R 2.5 0~2
OS0P[3:0]
Step : 1.5R
RF0N[3:0]
Step : 1.5R
30R
30R
Ver. 1.7
205
2008.04.18
ST7787
13.2 Gamma Voltage Formula (Positive/ Negative Polarity)
Grayscale 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Voltage Formula(Positive) VINP0 VINP1 V1-(V1-V3)*(16/30) VIN2 V3-(V3-V6)*(21/60) V3-(V3-V6)*(41/60) VINP3 V6-(V6-V11)*(13/60) V6-(V6-V11)*(26/60) V6-(V6-V11)*(38/60) V6-(V6-V11)*(49/60) VINP4 V11-(V11-V20)*(8/60) V11-(V11-V20)*(16/60) V11-(V11-V20)*(24/60) V11-(V11-V20)*(31/60) V11-(V11-V20)*(38/60) V11-(V11-V20)*(44/60) V11-(V11-V20)*(50/60) V11-(V11-V20)*(55/60) VINP5 V20-(V20-V31)*(6/60) V20-(V20-V31)* (12/60) V20-(V20-V31)* (18/60) V20-(V20-V31)* (24/60) V20-(V20-V31)* (30/60) V20-(V20-V31)* (35/60) V20-(V20-V31)* (40/60) V20-(V20-V31)* (45/60) V20-(V20-V31)* (50/60) V20-(V20-V31)* (55/60) VINP6 V31-(V31-V43)*(5/60) V31-(V31-V43)*(10/60) V31-(V31-V43)*(15/60) V31-(V31-V43)*(20/60) V31-(V31-V43)*(25/60) V31-(V31-V43)*(30/60) V31-(V31-V43)*(35/60) V31-(V31-V43)*(40/60) V31-(V31-V43)*(45/60) V31-(V31-V43)*(55/60) V31-(V31-V43)*(60/60) VINP7 V43-(V43-V52)*(2/18) V43-(V43-V52)*(4/18) V43-(V43-V52)*(6/18) V43-(V43-V52)*(8/18) V43-(V43-V52)*(10/18) V43-(V43-V52)*(12/18) V43-(V43-V52)*(14/18) V43-(V43-V52)*(16/18) VINP8 V52-(V52-V57)*(7/40) V52-(V52-V57)*(15/40) Voltage Formula(Negative) VINN 0 VINN 1 V1-(V1-V3)*(17/30) VINN 2 V3-(V3-V6)*(12/30) V3-(V3-V6)*(22/30) VINN 3 V6-(V6-V11)*(9/40) V6-(V6-V11)*(17/40) V6-(V6-V11)*(25/40) V6-(V6-V11)*(33/40) VINN 4 V11-(V11-V20)*(4/36) V11-(V11-V20)*(8/36) V11-(V11-V20)*(12/36) V11-(V11-V20)*(16/36) V11-(V11-V20)*(20/36) V11-(V11-V20)*(24/36) V11-(V11-V20)*(28/36) V11-(V11-V20)*(32/36) VINN 5 V20-(V20-V32)*(5/60) V20-(V20-V32)* (10/60) V20-(V20-V32)* (15/60) V20-(V20-V32)* (20/60) V20-(V20-V32)* (25/60) V20-(V20-V32)* (30/60) V20-(V20-V32)* (35/60) V20-(V20-V32)* (40/60) V20-(V20-V32)* (45/60) V20-(V20-V32)* (50/60) V20-(V20-V32)* (55/60) VINN6 V32-(V32-V43)*(5/60) V32-(V32-V43)*(10/60) V32-(V32-V43)*(15/60) V32-(V32-V43)*(20/60) V32-(V32-V43)*(25/60) V32-(V32-V43)*(30/60) V32-(V32-V43)*(36/60) V32-(V32-V43)*(42/60) V31-(V31-V43)*(48/60) V31-(V31-V43)*(54/60) VINN 7 V43-(V43-V52)*(5/60) V43-(V43-V52)*(10/60) V43-(V43-V52)*(16/60) V43-(V43-V52)*(22/60) V43-(V43-V52)*(29/60) V43-(V43-V52)*(36/60) V43-(V43-V52)*(44/60) V43-(V43-V52)*(52/60) VINN 8 V52-(V52-V57)*(11/60) V52-(V52-V57)*(22/60)
Ver. 1.7
206
2008.04.18
ST7787
55 56 57 58 59 60 61 62 63 V52-(V52-V57)*(23/40) V52-(V52-V57)*(31/40) VINP9 V57-(V57-V60)*(8/30) V57-(V57-V60)*(18/30) VINP10 V60-(V60-V62)*(13/30) VINP11 VINP12 V52-(V52-V57)*(34/60) V52-(V52-V57)*(47/60) VINN 9 V57-(V57-V60)*(19/60) V57-(V57-V60)*(39/60) VINN 10 V60-(V60-V62)*(14/30) VINN 11 VINN12
Ver. 1.7
207
2008.04.18
ST7787
14. Example Connection with Panel direction and Different Resolution 14.1 Application of connection with panel direction Case 1: (This is default case) - 1 Pixel is at Left Top of the panel - RGB filter order = RGB
st
- Direction default setting (H/W)

G 319 G1 ST7787 (Bump Down) S1 S 720 G 320 G2
SMX = 0 SMY = 0 SRGB = 0 S1 = Filter R S2 = Filter G

G2
00h 01h 02h ------------EDh EEh EFh G1 G3 | | | | | | | | | | | G317 G319 G320
S3 = Filter B
- Display direction control (S/W)
1 st Pixel
G4 | | | | | | | | | | | G318
- X-Mirror control by MX - Y-Mirror control by MY - XY-Exchange control by MV
IC (Bump down) LCD Front side
CF Glass
TFT Glass
Case 2: - 1 Pixel is at Left Top of the panel - RGB filter order = BGR
st

SMX = 0 SMY = 0 SRGB = 1 S1 = Filter B S2 = Filter G

G2
S3 = Filter R
1 st Pixel
G4 | | | | | | | | | | | G318
CF Glass
TFT Glass
Ver. 1.7
208
2008.04.18
ST7787
Case 3: - 1 Pixel is at Righ Bottom of the panel - RGB filter order = RGB
st

SMX = 1 SMY = 1 SRGB = 0 S1 = Filter R S2 = Filter G

G2
S3 = Filter B

G4 | | | | | | | | | | | G318
CF Glass
1 st Pixel
TFT Glass
Case 4: - 1 Pixel is at Righ Bottom of the panel - RGB filter order = BGR
st
G 319 G1 ST7787 (Bump Down) S1 S 720
G 320 G2

SMX = 1 SMY = 1 SRGB = 1 S1 = Filter B
G2
S2 = Filter G S3 = Filter R
1 st Pixel
G4 | | | | | | | | | | | G318

CF Glass
TFT Glass
Ver. 1.7
209
2008.04.18
ST7787
14.2 Application of connection with Different resolution RAM size=240 x 320 x 18-bits (Used) Display size = 240 RGB x 320 1). Example for SMX=SMY=0
G 319
G 320 ST7787 (Bump Down) S 720 S1 G2
G R A M s i z e (240x 320x 18-b i t s ) 00h 02h --- --- --- --- --- EEh EFh 00h 01h 02h | | | | | | | | | | | | | 13Eh 13Fh
(0,0)
G1
D1 D2 -- -- -- -- -G1
D239 D240
G2
(0,0)
(239,319)
G3 | | | | | | | | | | | G317 G319
1 st Pixel
G4 | | | | | | | | | | | G318 G320
(239,319)


SMX = 0 SMY = 0 SRGB = 0
2). Example for SMX=SMY=1
G 319
G 320 ST7787 (Bump Down) S1 S 720 G2
G R A M s i z e (240x 320x 18-b i t s ) 00h 02h --- --- --- --- --- EEh EFh 00h 01h 02h | | | | | | | | | | | | | 13Eh 13Fh
G1
G1
D1 D2 -- -- -- -- --
D239 D240
G2
(0,0)
(239,319)
G3 | | | | | | | | | | | G317 G319
(239,319)
1 st P ixel
G4 | | | | | | | | | | | G318 G320

(0,0) - Direction default setting (H/W)

SMX = 1 SMY = 1 SRGB = 0
Ver. 1.7
210
2008.04.18
ST7787
14.3 MicroProcessor Interface applications 14.3.1 8080-Seriers MCU + SPI Interface (RCM = 00, P68=0, IM2=1) 14.3.1.1 8080-Series MCU Interface for 8-bits data bus (IM1, IM0=00)
Host RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX) RDX(E) D7 to D1 D0 0 0 0 Note: RCM = 0x IM2=0, SPI I/F IM2=1, MCU I/F 00 IM2 D/CX WRX RDX D7 to D1 D0 D15 to D8 D17 to D16 P68 IM1,IM0 IM2 VS, HS, DE PLCK DGND Fig. 14.3.1.1 8080-Series MCU Interface for 8-bits data bus ST7787
14.3.1.2 8080-Series MCU Interface for 16-bits data bus (IM1, IM0=01)
Host RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX) RDX(E) D7 to D1 D0 D15 to D8 0 0 Note: RCM = 0x IM2=0, SPI I/F IM2=1, MCU I/F 01 IM2 D/CX WRX RDX D7 to D1 D0 D15 to D8 D17 to D16 P68 IM1,IM0 IM2 VS, HS, DE PLCK DGND Fig. 14.3.1.2 8080-Series MCU Interface for 16-bits data bus ST7787
Ver. 1.7
211
2008.04.18
ST7787
Host RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX) RDX(E) D8 to D1 D0 0 0 0 Note: RCM = 0x IM2=0, SPI I/F IM2=1, MCU I/F 10 IM2 D/CX WRX RDX D8 to D1 D0 D15 to D9 D17 to D16 P68 IM1,IM0 IM2 VS, HS, DE PLCK DGND Fig. 14.3.1.3 8080-Series MCU Interface for 9-bits data bus ST7787
Host RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX) RDX(E) D7 to D1 D0 D17 to D8 D/CX WRX RDX D7 to D1 D0 D17 to D8 ST7787
0 Note: RCM = 0x IM2=0, SPI I/F IM2=1, MCU I/F 11 IM2
P68 IM1,IM0 IM2 VS, HS, DE PLCK
DGND Fig. 14.3.1.4 8080-Series MCU Interface for 18-bits data bus
Ver. 1.7
212
2008.04.18
ST7787
14.3.2 6800-Seriers MCU + SPI Interface (RCM = 00, P68=1, IM2=1) 14.3.2.1 6800-Series MCU Interface for 8-bits data bus (IM1, IM0=00)
Host RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX) RDX(E) D7 to D1 D0 0 0 1 Note: RCM = 0x IM2=0, SPI I/F IM2=1, MCU I/F 00 IM2 D/CX R/WX E D7 to D1 D0 D15 to D8 D17 to D16 P68 IM1,IM0 IM2 VS, HS, DE PLCK DGND Fig. 14.3.2.1 6800-Series MCU Interface for 8-bits data bus ST7787
Host RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX) RDX(E) D7 to D1 D0 D15 to D8 0 1 Note: RCM = 0x IM2=0, SPI I/F IM2=1, MCU I/F 01 IM2 D/CX R/WX E D7 to D1 D0 D15 to D8 D17 to D16 P68 IM1,IM0 IM2 VS, HS, DE PLCK DGND Fig. 14.3.2.2 6800-Series MCU Interface for 16-bits data bus ST7787
Ver. 1.7
213
2008.04.18
ST7787
Host RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX) RDX(E) D8 to D1 D0 0 0 1 Note: RCM = 0x IM2=0, SPI I/F IM2=1, MCU I/F 10 IM2 D/CX R/WX E D8 to D1 D0 D15 to D9 D17 to D16 P68 IM1,IM0 IM2 VS, HS, DE PLCK DGND Fig. 14.3.2.3 6800-Series MCU Interface for 9-bits data bus ST7787
Host RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX ) RDX(E) D7 to D1 D0 D17 to D8 D/CX R/WX E D7 to D1 D0 D17 to D8 ST7787
1 Note: RCM = 0x IM2=0, SPI I/F IM2=1, MCU I/F 11 IM2
P68 IM1,IM0 IM2 VS, HS, DE PLCK
DGND Fig. 14.3.2.4 6800-Series MCU Interface for 18-bits data bus
Ver. 1.7
214
2008.04.18
ST7787
14.3.3 RGB Interface (RCM = 1) 14.3.3.1 RGBInterface for 6-bits Data Width
Fig. 14.3.3.1 RGB Interface for 6-bits data width
14.3.3.2 RGBInterface for 16-bits Data Width
Ver. 1.7
215
2008.04.18
ST7787
14.3.3.3 RGBInterface for 18-bits Data Width
Ver. 1.7
216
2008.04.18
ST7787
11. Revise History
ST7787 Serial Specification Revision History

Version
0.5B 1.0 1.0 1.1
Date
2007/02/06 2007/3/2 2007/3/2 2007/06/14 Add timing value
Description
Page
Modify Power on and off sequence Add FBH command Modify the operation temperature range Modify the command 3Ah Modify gamma structure Removed the description of 4-line Modify 3SPI Interface description Modify RAMHD typo to RAMRD Modify VIPF[3:0] typo Modify the description of power on/off sequence(9.15) Remove table 9.17.3.1 reset input timing(9.17.3) Modify the figure of reset timing (9.17.3) Modify the waiting time of SWReset to 120ms(10.1.2) Modify the waiting time of SLPout to 120ms(10.1.12) Modify the description of command E0h & E1h Modify power consumption IDDI (Unit) Modify operation temperature range Modify RGB Interface application circuit Modify Power On Sequence on RGB Mode 2 from VDDI VDD to VDD VDDI(9.9.6.4) Modify Power OFF Sequence on RGB Mode 2 from VDDI VDD to VDD VDDI(9.9.6.5) Modify WRX level on RGB mode from VDDI or DGND to VDDI only Modify SCL signal on SPI mode during proch area from clock to Hi level P2 P157 P206 P22 P34 P142 P157 P91 P96 P96 P111 P124 P196, P198 P29 P27~P30, P32~33 P215~216 P73 P74
1.2 1.3
2007/9/6 2007/9/11
1.4
2007/10/2
1.5
2007/11/26
1.6
2008/3/6
1.7
2009/4/18
P22,P215,P216 P40,P44
Ver. 1.7
217
2008.04.18

Go ST7787

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ST

Input: pad No. 1070 ~ 1335 = 55 x 110

Alignment mark (unit: um): (-9533,-248.77)

G318 Dummy Dummy Dummy

G320 Dummy Dummy

320 Gate buffer 720 Source buffer Voltage reference

Level shifter DAC Gamma circuit Gate decoder Level Shifter

Display Ram 240 x 18 x 320

Color conversion LUT table

Mutiple OTP Booster 1/2/4

C11N C12P C12N C21P C21N C22P C22N

SDA VSYNC HSYNC DE PCLK SHUT TB RL REV IDM

VDD VDDI AVDD VCL VGH VGL

6.2 Interface logic pin

RGB interface RGB interface RGB interface RGB interface

6.4 Driver output pin

Capacitor Capacitor Common electrode Step-up Capacitor

-Capacitor connecting pins for step-up circuit 1 (for AVDD)

6.5 Test pin

7.2 ESD protection level

7.3 Latch-up protection level

7.4 Light Sensitivity

Fig. 7.5.1 Example of measured point on the panel

Fig. 7.5.2 Tr: the source output stabling time.

Fig. 7.5.3 Source output deviation (channel to channel).

-(3-transfer for one pixel)

When read ID data When read from frame memory

For maximum CL=30pF For minimum CL=8pF

Fig.8.1.3 Chip selection (CSX) timing

Fig. 8.1.4 Write-to-read and read-to-write timing

TCHW TCS TRCS/TRCSFM TCSH TCSF

TRAT/TRATFM D[17:0] read

TCHW TSCYCW/TSCYCR TCSS TCSH

TSLW/TSLR TSHW/TSHR TSDS TSDH

SDA (DIN) (DOUT)

For maximum CL=30pF For minimum CL=8pF

8.4 Vertical synchronizing signal timing characteristic

9.2 8080-series MCU parallel interface (P68=0)

Read display data

Host D[17:0] Host to LCD Driver D[17:0] LCD to Host

CMD: write command code PA: parameter or display data

Signals on D[17:0], D/CX, R/WX, E pins during CSX=1 are ignored.

9.3.1 Write cycle sequence

Fig. 9.3.1 6800-Series Write Protocol

Note: E is an unsynchronized signal (It can be stopped)

9.3.2 Read cycle sequence

Host D[17:0] Host to LCD Driver D[17:0] LCD to Host

CMD: write command code PA: parameter or display data

Signals on D[17:0], D/CX, R/WX, E pins during CSX=1 are ignored.

9.4.1 Command Write Mode

3-Line Serial Data Stream Format

D/CXD7 D6 D5 D4 D3 D2 D1 D0 D/CXD7 D6 D5 D4 D3 D2 D1 D0 D/CXD7 D6 D5 D4 D3 D2 D1 D0

Fig. 9.4.1 Serial interface data Stream format

3-line serial protocol (for RDDID command: 24-bit read)

3-line Serial Protocol (for RDDST command: 32-bit read)

Fig. 9.4.4 3-line serial interface read protocol

Host (MCU to driver)

Fig. 9.5.1 Serial bus protocol, write mode interrupted by RESX

Host (MCU to driver)

Fig. 9.5.2 Serial bus protocol, write mode interrupted by CSX

9.6.1 Serial interface pause

Fig. 9.6.1 Serial interface pause protocol (pause by CSX)