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A

Compal confidential

JBK00 LA-4093P Schematics Document


Mobile AMD S1G2 CPU with ATI
RX781 & SB700 core logic with M86-M
3

2009-03-25
REV:1.0

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.


SCHEMATICS,MB A4093

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

of

58

Consumer AMD Discrete 17"

Compal
confidential

Thermal Sensor
ADM1032ARMZ

GDDRVRAM
1GMB

BANK 0, 1, 2, 3

P26

Dual Channel

P4

Hyper Transport Link 2.6GHz


16X16

Discrete
ATI M86M

PCI-E Lane*16

P15,16,17,18,19,20

ATI RX781

Finger Print

P28

P43

USB Camera
with Digital MIC

P10, 11, 12, 13, 14

CRT

Clock Generator
SLG8SP626

P8, 9

P4, 5, 6, 7

Fan conn

72QFN

DDR2-SO-DIMM X2

638-PIN uFCPGA 638

P6

page 21,22,23,24

LVDS Panel
Interface

DDR2 667MHz 1.8V


DDR2 800MHz 1.8V

AMD S1G2 CPU

P28

P27
USB2.0 X12

A-Link Express II

USB conn x4

P43

4X PCI-E

HDMI

P29

BT Conn
PCI-E BUS*5

ATI SB700
RTL8111C
10/100/1000

SATA Master-2

P43

SATA Slave

P38

WLAN & TV Tunner

Touch Screen

SATA Slave
P30 31 32 33 34

Dock

P37

RJ45 Conn.

SATA Master-1

Express Card

Mini-Card*2
P36

P43

Azalia

P47

Audio CKT

LPC BUS

AMP & Audio Jack

Codec_92HD71B7

P36

TPA6020A2 P41

P40

LED
P46

ENE
KB926

SPI

JMB380
RTC CKT.

SPI ROM
P38

MDC V1.5

SUBAMP

P42

TPA3007D1

P42

P45

P44

SATA HDD Connector

P30

P35

CardReader
Docking CKT.

P38

1394 Conn.

P38

P38

P45

P46

SATA ODD Connector

CIR

P47

Subwoofer

Int.KBD

Touch Pad CONN.

P35

P42

SATA 2nd HDD Connector


P35

DC/DC Interface CKT.


P48

e-SATA Connector
P43

ACCELEROMETER.
LIS302DLTR

Compal Secret Data

Security Classification

P39

2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATICS,MB A4093
Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

of

58

Voltage Rails
Symbol Note :
@ : means just reserve , no build
+5VS

45@ : means need be mounted when 45 level assy or rework stage.

: means Digital Ground

+3VS

power
plane

RX781R1@ : means just reserve for R1 FRU BOM

+2.5VS
+1.8VS

SBR1 @ : means just reserve for R1 FRU BOM

: means Analog Ground

+1.5VS
+B
+3VL
+5VL

+5VALW
+3VALW
+1.2VALW
+3V_LAN

+1.1VS

+1.8V

+VGA_CORE

+0.9V

M86R1@ : means just reserve for R1 FRU BOM

@ : means just reserve , no build


DEBUG@ : means just reserve for debug.

+1.2V_HT
+CPU_CORE_NB

State

Layout Notes

+CPU_CORE_0

U5

+CPU_CORE_1

M86M
M86M R1
M86R3@
U3

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery


don't exist

RX781
RX781 R1
RX781R3@

U15

SB700
SB700 R1
SBR3@
ZZZ

PCB
O MEANS ON

PCB LA-4093P REV1.0 M/B

X MEANS OFF

I2C / SMBUS ADDRESSING

SMBUS Control Table

DEVICE

HEX

ADDRESS

DDR SO-DIMM 0

A0

10100000

DDR SO-DIMM 1

A4

10100100

CLOCK GENERATOR (EXT.)

D2

11010010

ACCELEROMETER

3A

00111010

SOURCE
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
I2C_CLK

KB926
KB926
RS780M

I2C_DATA
DDC_CLK0
DDC_DATA0

EC SM Bus1 address
Device

HEX

Address

Smart Battery

16H

0001 011X b

A0H

1010 000X b

98H

1001 100X b

24C16
CPU SIC interface

EC SM Bus2 address

DDC_CLK1
DDC_DATA1

Address

SCL0

ADI1032-2 CPU 9AH

1001 101X b

SDA0

ADI1032-1 VGA 98H

1001 100X b

Device

HEX

RS780M
SB700

SCL1

SB700

SDA1
SCL2

SB700

SDA2
4

RS780M

SCL3

SB700

SDA3

X
X
X
X
X
X
X
X
X

BATT

V
X
X
X
X
X
X
X
X

SERIAL
EEPROM

THERMAL
SENSOR
CPU &
ADM1032

X
V
X
X
X
X
X
X
X

V
X
X
X
X
X
X
X
X

SODIMM
I / II

X
X
X
X
X
V
X
X
X

CLK CHIP

X
X
X
X
X
V
X
X
X

Compal Secret Data

Security Classification
2007/08/02

Issued Date

INVERTER

2008/08/02

Deciphered Date

Title

MINI CARD
Slot 2

X
X
X
X
X
X
V
X
X

Date:

HDMI

X
X
V
X
X
X
X
X
X

X
X
X
V
X
X
X
X
X

G-Sensor
3

X
X
X
X
X
V
X
X
X

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

LCD

SCHEMATICS,MB A4093
Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

of

58

VLDT CAP.

+1.2V_HT

250 mil
1
H_CADIP[0..15]

10 H_CADIP[0..15]

H_CADOP[0..15]

H_CADIN[0..15]

10 H_CADIN[0..15]

H_CADON[0..15]

H_CADOP[0..15]
H_CADON[0..15]

10

C1
4.7U_0805_10V4Z

10

C2
4.7U_0805_10V4Z

C3
0.22U_0603_16V4Z

C4
0.22U_0603_16V4Z

C5
180P_0402_50V8J

C6
180P_0402_50V8J

Near CPU Socket


+1.2V_HT
JP1A

H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15

HT LINK

D1
D2
D3
D4

VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3

E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5

L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15

10
10
10
10

H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1

J3
J2
J5
K5

10
10
10
10

H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1

N1
P1
P3
P4

L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1

VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3

L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15

AE2 +VLDT_B 1
C7
AE3
AE4
AE5
AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3

2
4.7U_0805_10V4Z

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

PWM Fan Control circuit

L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1

Y1
W1
Y4
Y3

H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1

10
10
10
10

L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1

R2
R3
T5
R5

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1

10
10
10
10

+5VS

JP2

VLDT=500mA

1
D1
CH751H-40PT_SOD323-2

C8
4.7U_0805_10V4Z

C9
@ 0.1U_0402_16V4Z

1
2

1
2

3
4

GND
GND

ACES_88231-02001
+VCC_FAN

6090022100G_B
1

1
2
5
6

CONN@

CONN@

D Q1

@ D2

G
RLZ5.1B_LL34

SI3456BDV-T1-E3_TSOP6

FAN_PWM

45

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.


SCHEMATICS,MB A4093

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

of

58

Processor DDR2 Memory Interface


PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

JP1C

9 DDR_B_D[63..0]

MEM:DATA

DDR_A_CLK0
+1.8V

R1
1K_0402_1%

DDR_A_CLK#0

C10
1.5P_0402_50V9C

DDR_A_CLK1
1

R2
1K_0402_1%
1

C13
1000P_0402_25V8J

C12
0.1U_0402_16V4Z

+MCH_REF
1

DDR_A_CLK#1

C11
1.5P_0402_50V9C

DDR_B_CLK0
1

DDR_B_CLK#0

C14
1.5P_0402_50V9C

DDR_B_CLK1
1

DDR_B_CLK#1

C15
1.5P_0402_50V9C

+0.9V

+0.9V
JP1B

Place them close to CPU within 1"

+1.8V

R4
1
1
R3

39.2_0402_1%
2
2
39.2_0402_1%
T2

8
8

DDR_A_ODT0
DDR_A_ODT1

8 DDR_CS0_DIMMA#
8 DDR_CS1_DIMMA#

8 DDR_CKE0_DIMMA
8 DDR_CKE1_DIMMA

8 DDR_A_CLK0
8 DDR_A_CLK#0
8 DDR_A_CLK1
8 DDR_A_CLK#1
3

8 DDR_A_MA[15..0]

8 DDR_A_BS#0
8 DDR_A_BS#1
8 DDR_A_BS#2
8 DDR_A_RAS#
8 DDR_A_CAS#
8 DDR_A_WE#

PAD

DDR_A_ODT0
DDR_A_ODT1

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

D10
C10
B10
AD10

VTT1
VTT2
VTT3
VTT4

AF10
AE10

MEMZP
MEMZN

MEM:CMD/CTRL/CLK VTT5
VTT6
VTT7
VTT8
VTT9

H16

RSVD_M1

T19
V22
U21
V19

MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1

T20
U19
U20
V20

MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1

J22
J20

MA_CKE0
MA_CKE1

W10
AC10
AB10
AA10
A10

VTT_SENSE

Y10

MEMVREF

W17

VTT_SENSE

RSVD_M2

B18

MB0_ODT0
MB0_ODT1
MB1_ODT0

W26
W23
Y26

DDR_B_ODT0
DDR_B_ODT1

MB0_CS_L0
MB0_CS_L1
MB1_CS_L0

V26
W25
U22

DDR_CS0_DIMMB#
DDR_CS1_DIMMB#

MB_CKE0
MB_CKE1

J25
H26

DDR_CKE0_DIMMB
DDR_CKE1_DIMMB

DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

N19
N20
E16
F16
Y16
AA16
P19
P20

MA_CLK_H0
MA_CLK_L0
MA_CLK_H1
MA_CLK_L1
MA_CLK_H2
MA_CLK_L2
MA_CLK_H3
MA_CLK_L3

MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CLK_H2
MB_CLK_L2
MB_CLK_H3
MB_CLK_L3

P22
R22
A17
A18
AF18
AF17
R26
R25

N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24

PAD

T1

PAD

T3

+MCH_REF

DDR_B_ODT0 9
DDR_B_ODT1 9
DDR_CS0_DIMMB# 9
DDR_CS1_DIMMB# 9
DDR_CKE0_DIMMB 9
DDR_CKE1_DIMMB 9

DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1

9
9
9
9
9 DDR_B_DM[7..0]

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

R20
R23
J21

MA_BANK0
MA_BANK1
MA_BANK2

MB_BANK0
MB_BANK1
MB_BANK2

R24
U26
J26

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

R19
T22
T24

MA_RAS_L
MA_CAS_L
MA_WE_L

MB_RAS_L
MB_CAS_L
MB_WE_L

U25
U24
U23

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

DDR_B_MA[15..0] 9

9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9

DDR_B_BS#0 9
DDR_B_BS#1 9
DDR_B_BS#2 9
DDR_B_RAS# 9
DDR_B_CAS# 9
DDR_B_WE# 9

DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

A12
B16
A22
E25
AB26
AE22
AC16
AD12

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7

C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12

MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

DDR_A_D[63..0]

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

E12
C15
E19
F24
AC24
Y19
AB16
Y13

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7

G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7

8
1

DDR_A_DM[7..0]

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7

8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8

6090022100G_B
CONN@

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.


SCHEMATICS,MB A4093

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

of

58

+2.5VDDA
VDDA=300mA
L1
3300P_0402_50V7K
1
2
1 FBM_L11_201209_300L_0805
1
1
1
+
4.7U_0805_10V4Z
C17
C18
C19
0.22U_0603_16V4Z
2
2
2
2

+2.5VS

+1.8V

R10
1
R5

2
10K_0402_5%
2
300_0402_5%
B

C16
@ 100U_D2_10VM

C20

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

2 3900P_0402_50V7K

LDT_RST#
H_PWRGD
LDT_STOP#
CPU_LDT_REQ#

R8
169_0402_1%
26 CLK_CPU_BCLK#

C21

2
3900P_0402_50V7K

Address:100_1100

+1.8VS

Place close to CPU wihtin 1.5"


2

R13
R14

+1.2V_HT

R15
300_0402_5%

30

+CPU_CORE_0
R487 10_0402_5%
1
2CPU_VDD0_FB_H
1
2CPU_VDD0_FB_L
R486 10_0402_5%

LDT_RST#

LDT_RST#
1

CPU_SIC
CPU_SID

C22
0.01U_0402_25V4Z
@

2 44.2_0402_1% CPU_HTREF0
2 44.2_0402_1% CPU_HTREF1

1
1

2
1

R21
300_0402_5%

B7
A7
F10
C6

RESET_L
PWROK
LDTSTOP_L
LDTREQ_L

AF4
AF5
AE6

SIC
SID
ALERT_L

R6
P6

HT_REF0
HT_REF1

THERMTRIP_L
PROCHOT_L
MEMHOT_L
THERMDC
THERMDA

W7
W8

56 CPU_VDD1_FB_H
56 CPU_VDD1_FB_L

CPU_VDD1_FB_H
Y6
CPU_VDD1_FB_L AB6

VDD1_FB_H
VDD1_FB_L

VDDNB_FB_H
VDDNB_FB_L

H6
G6

DBRDY
TMS
TCK
TRST_L
TDI

CPU_TEST23_TSTUPD

AD7

TEST23

CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

H10
G9

TEST18
TEST19

+1.8VS

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST27_SINGLECHAIN
1

R25

2 0_0402_5%

E9
E8
AB8
AF7
AE7
AE8
AC8
AF8

TEST21
TEST20
TEST24
TEST22
TEST12
TEST27
TEST9
TEST6

R30
300_0402_5%

+1.8VS

A3
A5
B3
B5
C1

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5

R36
300_0402_5%

11,30 LDT_STOP#
1

CPU_LDT_REQ#

LDT_STOP#

R6

R7

2
@ 0_0402_5%
2
0_0402_5%

ENTRIP2

50

H_THERMTRIP# 32,45

2
300_0402_5%
R11
1
2
@ 0_0402_5%

CPU_PROCHOT#_1.8

+1.8V

H_PROCHOT# 30

PV:change PROCHOT# & delete Q2

PAD
PAD

+CPU_CORE_NB

T22
T21

VDD_NB_FB_H
VDD_NB_FB_L

E10

CPU_DBREQ#

TDO

AE9

CPU_TDO

R484 10_0402_5%
1
2
1
2
R485 10_0402_5%

VDD_NB_FB_H
VDD_NB_FB_L

VDD_NB_FB_H 56
VDD_NB_FB_L 56

Close to CPU

J7
H8

CPU_TEST28_H_PLLCHRZ_P
CPU_TEST28_L_PLLCHRZ_N

TEST17
TEST16
TEST15
TEST14

D7
E7
F7
C7

CPU_TEST17_BP3
CPU_TEST16_BP2
CPU_TEST15_BP1
CPU_TEST14_BP0

TEST7
TEST10

C3
K8

TEST8

C4

TEST29_H
TEST29_L

C9
C8

PAD
PAD
PAD
PAD
PAD
PAD

T5
T6

route as differential
as short as possible
testpoint under package

T7
T8
T10
T12

+1.8V

0718 AMD --> 1K ohm


CPU_SVC
CPU_SVD

R22
R23

CPU_TEST27_SINGLECHAIN
R24
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N

PAD
PAD

T13
T14

CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
CPU_TEST23_TSTUPD

RSVD10
RSVD9
RSVD8
RSVD7
RSVD6

H18
H19
AA7
D5
C5

MV:unmount strap pin

CPU_LDT_REQ# 11,30
6090022100G_B

C24
0.01U_0402_25V4Z
@

1
R9

+1.8V

THERMDC_CPU
THERMDA_CPU

DBREQ_L

TEST28_H
TEST28_L

TEST25_H
TEST25_L

C2
AA6

+1.8V sense no support


W9
Y9

G10
AA9
AC9
AD9
AF9

Q3
1

CPU_SVC 56
CPU_SVD 56

CPU_THERMTRIP#_R
CPU_PROCHOT#_1.8
2
1
R48
300_0402_5%

AF6
AC7
AA8

VDDIO_FB_H
VDDIO_FB_L

CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI

CPU_SVC
CPU_SVD

A6
A4

C23
@ 0.1U_0402_16V4Z

SVC
SVD

VDD0_FB_H
VDD0_FB_L

MV:follow ANT 0E CRB


change R493 to GND
& R492 to +1.8V

H_PWRGD

30,56 H_PWRGD

KEY1
KEY2

F6
E6

@ 30.1_0402_1%
R493 1
2
1
2
+1.8V R492
@ 30.1_0402_1%

R488 10_0402_5%

CLKIN_H
CLKIN_L

56 CPU_VDD0_FB_H
56 CPU_VDD0_FB_L

+CPU_CORE_1
R489 10_0402_5%
1
2CPU_VDD1_FB_H
1
2CPU_VDD1_FB_L

VDDA1
VDDA2

A9
A8

MMBT3904_NL_SOT23-3

M11
W18

CPU_VDD0_FB_H
CPU_VDD0_FB_L

Close to CPU
+1.8VS

F8
F9

CPU_THERMTRIP#_R

26 CLK_CPU_BCLK

JP1D

SI2: remove 100uF

R26
R27
R28
R29
R31
R32
R33
R34
R35
R49

1
1

2
1K_0402_5%
2
1K_0402_5%

2
@ 300_0402_5%

1
2
2
2
2
2
2
2
2
2

2 300_0402_5%
1@ 300_0402_5%
1 300_0402_5%
1@ 300_0402_5%
1@ 300_0402_5%
1@ 300_0402_5%
1@ 300_0402_5%
1@ 300_0402_5%
1@ 300_0402_5%
1@ 300_0402_5%

PV:AMD 4.1 recommend

CONN@

C25
0.01U_0402_25V4Z
@
1

@ C939 0.1U_0402_16V4Z
R175

R814
1

2.09V for Gate


+1.8V

1
D

PV:change to 2.2K

Q127

@ FDV301N_NL_SOT23-3

R19

EC is PU to 5VALW
G

CPU_SIC

2
1
2.2K_0402_5%

+1.8V

+3VS

0.1U_0402_16V4Z
C27
1

2200p change to
1000p for ADT7421

Q129

C26

FDV301N, the Vgs is:


min = 0.65V
Typ = 0.85V
Max = 1.5V

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

SMB_EC_CK1 44,45,46,54

SMB_EC_DA1 44,45,46,54

@ FDV301N_NL_SOT23-3

HDT Connector
JP3
1
3
5
7
9
11
13
15
17
19
21
23

2
U2
1
THERMDA_CPU 2

THERMDC_CPU 3
2
2200P_0402_50V7K
4

VDD

SCLK

SMB_EC_CK2
SMB_EC_DA2

D+

SDATA

D-

ALERT#

GND

THERM#

NOTE: HDT TERMINATION IS REQUIRED


FOR REV. Ax SILICON ONLY.

SMB_EC_CK2 25,45

2
4
6
8
10
12
14
16
18
20
22
24
26

+3VS

U1
HDT_RST#

CONN@ SAMTEC_ASP-68200-07

LDT_RST#
SB_PWRGD 32,45,56 4

@ NC7SZ08P5X_NL_SC70-5

SMB_EC_DA2 25,45

Compal Secret Data

Security Classification
2007/08/02

Issued Date

ADM1032ARMZ-2REEL_MSOP8

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.


SCHEMATICS,MB A4093

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Address:100_1101

Date:

CPU_SID

2
1
2.2K_0402_5%

+1.8V

@ 34.8K_0402_1%~N

@ 20K_0402_5%
R18

2
1
@ 220_0402_5% R37
2
1
@ 220_0402_5% R38
2
1
@ 220_0402_5% R39
2
1
@ 220_0402_5% R40
2
1
300_0402_5% R41

+3VS

Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

of

58

JP1F

VDD(+CPU_CORE) decoupling.
+CPU_CORE_0

+CPU_CORE_1

C30
330U_X_2VM_R6M

C28
330U_X_2VM_R6M

C31
330U_X_2VM_R6M

C29
330U_X_2VM_R6M

Near CPU Socket


+CPU_CORE_0

+CPU_CORE_1
+CPU_CORE_NB

C32
22U_0805_6.3V6M

C33
22U_0805_6.3V6M

C34
22U_0805_6.3V6M

C35
22U_0805_6.3V6M

C36
22U_0805_6.3V6M

C37
22U_0805_6.3V6M

+CPU_CORE_0

C38
22U_0805_6.3V6M

C39
22U_0805_6.3V6M

+1.8V

+CPU_CORE_1

C40
0.22U_0603_16V4Z

C41
0.01U_0402_25V4Z

JP1E

+CPU_CORE_0

C42
180P_0402_50V8J

C43
0.22U_0603_16V4Z

C44
0.01U_0402_25V4Z

C45
180P_0402_50V8J

Under CPU Socket


2

AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4

+CPU_CORE_1

G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11

VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23

K16
M16
P16
T16
V16

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12

VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26

P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2

VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13

Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18

+1.8V

6090022100G_B
Athlon 64 S1
Processor Socket

VDDIO decoupling.

CONN@

+CPU_CORE_NB

decoupling.

+1.8V
+CPU_CORE_NB
1

C46
22U_0805_6.3V6M

C47
22U_0805_6.3V6M

C48

0.22U_0603_16V4Z
2

C49

0.22U_0603_16V4Z
2

C50

C51

180P_0402_50V8J 180P_0402_50V8J
2
2

C52
22U_0805_6.3V6M

C53
22U_0805_6.3V6M

C54
@ 22U_0805_6.3V6M

SI2: reserve 22u

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

6090022100G_B

Under CPU Socket

Athlon 64 S1
Processor Socket

CONN@

Between CPU Socket and DIMM


+1.8V

+0.9V

C55
0.22U_0603_16V4Z

C56
0.22U_0603_16V4Z

C57
0.22U_0603_16V4Z

+1.8V

C60
0.01U_0402_25V4Z

C61
0.01U_0402_25V4Z

C58
0.22U_0603_16V4Z

C62
180P_0402_50V8J

C63
180P_0402_50V8J

C64
180P_0402_50V8J

+0.9V

C65
1
180P_0402_50V8J C66
4.7U_0805_10V4Z

A: Add C165 and C176


to follow AMD Layout
review recommand for
EMI

+1.8V

C: Change to NBO CAP

180PF Qt'y follow the distance between


CPU socket and DIMM0. <2.5inch>

Near Power Supply


1

+ C59
220U_Y_4VM

+1.8V

VTT decoupling.

C67
4.7U_0805_10V4Z

C68
0.22U_0603_16V4Z

C69
0.22U_0603_16V4Z

C70
1000P_0402_25V8J

C71
1000P_0402_25V8J

C72
180P_0402_50V8J

C73
180P_0402_50V8J

Near CPU Socket Right side.


+0.9V

1
1

1
C74
4.7U_0805_10V4Z

1
C75
4.7U_0805_10V4Z

1
C76
4.7U_0805_10V4Z

C77
4.7U_0805_10V4Z

C: Change to NBO CAP

+ C78
220U_Y_4VM
2 @

C79
4.7U_0805_10V4Z

C80
4.7U_0805_10V4Z

C81
0.22U_0603_16V4Z

C82
0.22U_0603_16V4Z

C83
1000P_0402_25V8J

C84
1000P_0402_25V8J

C85
180P_0402_50V8J

C86
180P_0402_50V8J

Near CPU Socket Left side.


Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.


SCHEMATICS,MB A4093

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

of

58

+V_DDR_MCH_REF
+1.8V

DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
1

DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

DDR_A_D4
DDR_A_D5

DDR_A_D[0..63]
DDR_A_DM[0..7]

DDR_A_DM0
DDR_A_DQS[0..7]
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13

DDR_A_D[0..63]

DDR_A_DM[0..7]

DDR_A_DQS[0..7]

DDR_A_MA[0..15]

DDR_A_MA[0..15] 5

DDR_A_DQS#[0..7]

DDR_A_DQS#[0..7]

+1.8V

DDR_A_MA0
DDR_A_BS#1
DDR_A_MA2
DDR_A_MA4

DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
2

DDR_CKE0_DIMMA

5 DDR_CKE0_DIMMA

DDR_A_BS#2

5 DDR_A_BS#2

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

5 DDR_A_BS#0
5 DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

5 DDR_A_CAS#
5 DDR_CS1_DIMMA#

DDR_A_ODT1

5 DDR_A_ODT1

DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
3

DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
9,26,32,39 SMB_CK_DAT0
9,26,32,39 SMB_CK_CLK0
+3VS
4

1
C103
0.1U_0402_16V4Z

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

R43
1K_0402_1%
+V_DDR_MCH_REF

DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3

+V_DDR_MCH_REF 9

R44
1K_0402_1%

DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA

DDR_CKE1_DIMMA 5

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

C88

1
1

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1

C90
C89

C91
C92

C93
C94

1
1

1
1

1
1

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

47_0804_8P4R_5%
RP5
8
1
7
2
6
3
5
4

DDR_CS1_DIMMA#
DDR_A_ODT1
DDR_A_WE#
DDR_A_CAS#

47_0804_8P4R_5%
RP6
8
1
7
2
6
3
5
4

1
C100
1
C99

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

DDR_A_ODT0
DDR_A_MA13
DDR_A_RAS#
DDR_CS0_DIMMA#

47_0804_8P4R_5%
RP7
1
8
2
7
3
6
4
5

1
C102
1
C101

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_ODT0
DDR_A_MA13

47_0804_8P4R_5%
RP4
8
1
7
2
6
3
5
4

C87

DDR_A_BS#0
DDR_A_MA1
DDR_A_MA10
DDR_A_MA3

DDR_A_MA15
DDR_A_MA14

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

47_0804_8P4R_5%
RP3
1
8
2
7
3
6
4
5

DDR_A_MA5
DDR_A_MA8
DDR_A_MA9
DDR_A_MA12

DDR_A_D20
DDR_A_D21

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

DDR_A_D18
DDR_A_D19

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

C96
0.1U_0402_16V4Z

DDR_A_DQS#2
DDR_A_DQS2

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

8
7
6
5

47_0804_8P4R_5%
RP2
8
1
7
2
6
3
5
4

DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA15
DDR_CKE1_DIMMA

DDR_A_CLK0 5
DDR_A_CLK#0 5

C95
1000P_0402_25V8J

DDR_A_D16
DDR_A_D17

1
2
3
4

DDR_A_DM1

DDR_A_D14
DDR_A_D15

+1.8V

+0.9V
RP1
DDR_A_MA6
DDR_A_MA7
DDR_A_MA11
DDR_A_MA14

DDR_A_D10
DDR_A_D11

+1.8V

JP4

C98
C97

1
1

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

47_0804_8P4R_5%

DDR_A_BS#1 5
DDR_A_RAS# 5
DDR_CS0_DIMMA# 5
DDR_A_ODT0 5

DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_CLK1 5
DDR_A_CLK#1 5
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63

P-TWO_A5692B-A0G16-P
CONN@

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.


SCHEMATICS,MB A4093

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

of

58

+1.8V
+1.8V

JP5
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

8 +V_DDR_MCH_REF

C104
1000P_0402_25V8J

DDR_B_D0
DDR_B_D1
1

DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27

5 DDR_CKE0_DIMMB
5 DDR_B_BS#2

DDR_CKE0_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

5 DDR_B_BS#0
5 DDR_B_WE#
5 DDR_B_CAS#
5 DDR_CS1_DIMMB#
5 DDR_B_ODT1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS1_DIMMB#
DDR_B_ODT1
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
8,26,32,39 SMB_CK_DAT0
8,26,32,39 SMB_CK_CLK0
+3VS
4

C119
0.1U_0402_16V4Z

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

+1.8V

+0.9V
DDR_B_D[0..63]
DDR_B_D4
DDR_B_D5
DDR_B_DM0
DDR_B_D6
DDR_B_D7

DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]

DDR_B_D12
DDR_B_D13

DDR_B_D[0..63]

RP8

DDR_B_DM[0..7]

DDR_B_DQS[0..7]

DDR_B_MA[0..15]

DDR_B_DQS#[0..7]

DDR_B_BS#1
DDR_B_MA2
DDR_B_MA0
DDR_B_MA6

1
2
3
4

8
7
6
5

2
C105
1
C106

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C108
1
C107

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C109
1
C110

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C111
1
C112

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C114
1
C113

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C116
1
C115

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C118
1
C117

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

47_0804_8P4R_5%
1

RP9

DDR_B_DM1

DDR_B_MA4
DDR_B_MA14
DDR_B_MA7
DDR_B_MA11

1
2
3
4

DDR_B_BS#2
DDR_CKE0_DIMMB
DDR_CKE1_DIMMB
DDR_B_MA15

8
7
6
5

8
7
6
5

47_0804_8P4R_5%

DDR_B_CLK0 5
DDR_B_CLK#0 5

RP10

DDR_B_D14
DDR_B_D15

1
2
3
4

47_0804_8P4R_5%
DDR_B_D20
DDR_B_D21

RP11
DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
DDR_B_MA12

DDR_B_DM2
DDR_B_D22
DDR_B_D23

8
7
6
5

1
2
3
4

47_0804_8P4R_5%

DDR_B_D28
DDR_B_D29

RP12
DDR_B_BS#0
DDR_B_MA10
DDR_B_MA3
DDR_B_MA1

DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31

8
7
6
5

1
2
3
4

47_0804_8P4R_5%
2

RP13
DDR_CKE1_DIMMB

DDR_B_ODT1
DDR_CS1_DIMMB#
DDR_B_CAS#
DDR_B_WE#

DDR_CKE1_DIMMB 5

DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_ODT0
DDR_B_MA13

1
2
3
4

47_0804_8P4R_5%
RP14
DDR_B_MA13
DDR_B_ODT0
DDR_B_RAS#
DDR_CS0_DIMMB#

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#

8
7
6
5

1
2
3
4

8
7
6
5

47_0804_8P4R_5%

DDR_B_BS#1 5
DDR_B_RAS# 5
DDR_CS0_DIMMB# 5
DDR_B_ODT0 5

DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
3

DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_CLK1 5
DDR_B_CLK#1 5
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
+3VS

PTI_A5652D-A0G16-P
2

CONN@

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATICS,MB A4093
Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

of

58

15 PCIE_GTX_C_MRX_P[0..15]
15 PCIE_GTX_C_MRX_N[0..15]

PCIE_GTX_C_MRX_P[0..15]

PCIE_MTX_C_GRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15]

PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15] 15
PCIE_MTX_C_GRX_N[0..15] 15

U3B

37
37
38
38
37
37
36
36

PCIE_PTX_C_IRX_P0
PCIE_PTX_C_IRX_N0
PCIE_PTX_C_IRX_P1
PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P2
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P3
PCIE_PTX_C_IRX_N3

37 PCIE_PTX_C_IRX_P5
37 PCIE_PTX_C_IRX_N5
30
30
30
30
30
30
30
30

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

AE3
AD4
AE2
AD3
AD1
AD2
V5
W6
U5
U6
U8
U7

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N

AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N15

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N

AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2

PCIE_ITX_PRX_P0
PCIE_ITX_PRX_N0
PCIE_ITX_PRX_P1
PCIE_ITX_PRX_N1
PCIE_ITX_PRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P3
PCIE_ITX_PRX_N3

C152
C153
C154
C155
C156
C157
C158
C159

PCIE_ITX_PRX_P5
PCIE_ITX_PRX_N5

C160 1
C161
1

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5

PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)

AC8
AB8

PART 2 OF 6

PCIE I/F GPP

PCIE I/F SB

SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C
R55
R56

C121 1
C123 1

C125 1

C127 1

C129 1

C131 1

C133 1

C135 1

C137 1

C139 1

C141 1

C143 1

C145 1

C147 1

C149 1

C151 1

C162
C163
C164
C165
C166
C168
C169
C167

1
1
1
1
1
1
1
1

1
1

2
2

C120 1
0.1U_0402_16V7K
C122 1
0.1U_0402_16V7K
C124 1
0.1U_0402_16V7K
C126 1
0.1U_0402_16V7K
C128 1
0.1U_0402_16V7K
C130 1
0.1U_0402_16V7K
C132 1
0.1U_0402_16V7K
C134 1
0.1U_0402_16V7K
C136 1
0.1U_0402_16V7K
C138 1
0.1U_0402_16V7K
C140 1
0.1U_0402_16V7K
C142 1
0.1U_0402_16V7K
C144 1
0.1U_0402_16V7K
C146 1
0.1U_0402_16V7K
C148 1
0.1U_0402_16V7K
C150 1
0.1U_0402_16V7K

2
1

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
2 0.1U_0402_16V7K
0.1U_0402_16V7K
2 0.1U_0402_16V7K
0.1U_0402_16V7K
2
2 0.1U_0402_16V7K
0.1U_0402_16V7K
2
2 0.1U_0402_16V7K
2

1
1

PCIE_ITX_C_PRX_P0
PCIE_ITX_C_PRX_N0
PCIE_ITX_C_PRX_P1
PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P2
PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P3
PCIE_ITX_C_PRX_N3

2
1

1
1
1
1

2
2
2
2
2
2
2
2

1.27K_0402_1%
2K_0402_1%

Polarity inversion

Polarity inversion

Polarity inversion

New Card

37
37
38
38
37
37
36
36

Cardreader

GLAN

PCIE_ITX_C_PRX_P5 37
PCIE_ITX_C_PRX_N5 37
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

TV Tuner

4 H_CADON[0..15]

30
30
30
30
30
30
30
30

H_CADOP[0..15]

H_CADIP[0..15]

H_CADON[0..15]

H_CADIN[0..15]

H_CADIP[0..15]

H_CADIN[0..15]

U3A

+1.1VS

RS780M_FCBGA528
RX781R1@

RS780M Display Port Support (muxed on GFX)


GFX_TX0,TX1,TX2 and TX3
DP0
AUX0 and HPD0
3

WLAN

4 H_CADOP[0..15]

0.1U_0402_16V7K
2 0.1U_0402_16V7K

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

GFX_TX4,TX5,TX6 and TX7


DP1
AUX1 and HPD1

4
4
4
4

H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1

4
4
4
4

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
1 R57

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7

Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

T22
T23
AB23
AA22

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

M22
M23
R21
R20

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1

2 301_0402_1% C23
A24

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22

H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18

H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15

HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N

H24
H25
L21
L20

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N

M24
M25
P19
R18

HT_RXCALP
HT_RXCALN

HT_TXCALP
HT_TXCALN

B24
B25

HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

PART 1 OF 6

HYPER TRANSPORT CPU I/F

D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3

PCIE I/F GFX

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15

RS780M_FCBGA528
RX781R1@

0718 Place within 1"


layout 1:2

H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1

H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1

4
4
4
4

H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1

4
4
4
4

1 R58

2 301_0402_1%

0718 Place within 1"


layout 1:2

NEED CHECK R68 & R69 WITH AMD


Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATICS,MB A4093
Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

10

of

58

PV: follow check list connect to GND


U3C

C180
2.2U_0603_6.3V4Z

G14

DAC_RSET(PWM_GPIO1)

+VDDA18HTPLL

H17

VDDA18HTPLL

+VDDA18PCIEPLL

D7
E7

VDDA18PCIEPLL1
VDDA18PCIEPLL2

D8
A10
C10
C12

14,15,30,36,37,38,44,45

PLT_RST#

SYSRESETb
POWERGOOD
LDTSTOPb
ALLOW_LDTSTOP

26
26

C25
C24

HT_REFCLKP
HT_REFCLKN

E11
F11

REFCLK_P/OSCIN(OSCIN)
REFCLK_N(PWM_GPIO3)

NB_RESET#
NB_PWRGD

CLK_NBHT
CLK_NBHT#

26 NB_OSC_14.318M
+1.1VS

DAC_HSYNC(PWM_GPIO4)
DAC_VSYNC(PWM_GPIO6)
DAC_SCL(PCE_RCALRN)
DAC_SDA(PCE_TCALRN)

PLLVDD(NC)
PLLVDD18(NC)
PLLVSS(NC)

0_0402_5%
2
32 NB_PWRGD
6,30 LDT_STOP#
6,30 CPU_LDT_REQ#

2 NB_PWRGD
300_0402_5%

For SB700 A12 use

A11
B11
F8
E8

A12
D14
B12

R67
1

+1.8VS
1
R371

RED(DFT_GPIO0)
REDb(NC)
GREEN(DFT_GPIO1)
GREENb(NC)
BLUE(DFT_GPIO3)
BLUEb(NC)

1
2
R71
4.7K_0402_5%

1
2
R72
4.7K_0402_5%

26 NBGFX_CLK
26 NBGFX_CLK#

26 CLK_SBLINK_BCLK
26 CLK_SBLINK_BCLK#

+3VS
R88
14

1
10K_0402_5%

AUX_CAL

Strap pin

T2
T1

GFX_REFCLKP
GFX_REFCLKN

U1
U2

GPP_REFCLKP
GPP_REFCLKN

V4
V3

GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN)

B9
A9
B8
A8
B7
A7

I2C_CLK
I2C_DATA
DDC_DATA0/AUX0N(NC)
DDC_CLK0/AUX0P(NC)
DDC_CLK1/AUX1P(NC)
DDC_DATA1/AUX1N(NC)

B10

STRP_DATA

G11

RSVD

C8

TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5)
TXOUT_U3N(NC)

B18
A18
A17
B17
D20
D21
D18
D19

TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)

B16
A16
D16
D17

VDDLTP18(NC)
VSSLTP18(NC)

A13
B13

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

A15
B15
A14
B14

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

C14
D15
C16
C18
C20
E20
C22

LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)

E9
F7
G12

TMDS_HPD(NC)
HPD(NC)

D9
D10

PLL PWR
LVTM

+VDDA18PCIEPLL

L11
1
2
BLM18PG121SN1D_0603

G18
G17
E18
F18
E19
F19

PV: follow check list connect to GND


2

+1.8VS

C_Pr(DFT_GPIO5)
Y(DFT_GPIO2)
COMP_Pb(DFT_GPIO4)

A22
B22
A21
B21
B20
A20
A19
B19

PM

C179
2.2U_0603_6.3V4Z

14 UMA_HSYNC
14 UMA_VSYNC

E17
F17
F15

TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)

PART 3 OF 6

CRT/TVOUT

+VDDA18HTPLL
L10
1
2
BLM18PG121SN1D_0603
1

AVDD1(NC)
AVDD2(NC)
AVDDDI(NC)
AVSSDI(NC)
AVDDQ(NC)
AVSSQ(NC)

CLOCKs

+1.8VS

F12
E12
F14
G15
H15
H14

MIS.

PV: follow check list connect to GND

SUS_STAT#(PWM_GPIO5)

D12

THERMALDIODE_P
THERMALDIODE_N

AE8
AD8

TESTMODE

D13

AUX_CAL(NC)

1
R77

2
0_0402_5%

SUS_STAT# 32
SUS_STAT_R# 14

Strap pin

1
2
R80
1.8K_0402_5%

RS780M_FCBGA528
RX781R1@

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.


SCHEMATICS,MB A4093

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

11

of

58

U3D

MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)

AD16
AE17
AD17

MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)

W12
Y12
AD18
AB13
AB18
V14

MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)

V15
W14

MEM_CKP(NC)
MEM_CKN(NC)

AE12
AD12

SBD_MEM/DVO_I/F

PAR 4 OF 6
AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14

MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)

Y17
W18
AD20
AE21

MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)

W17
AE19

MEM_COMPP(NC)
MEM_COMPN(NC)

IOPLLVDD18(NC)
IOPLLVDD(NC)

AE23
AE24

IOPLLVSS(NC)

AD23

MEM_VREF(NC)

AE18

+1.8VS
+1.1VS

RS780M_FCBGA528
RX781R1@

Compal Secret Data

Security Classification
Issued Date

2007/08/02

Deciphered Date

2008/08/02

Title

Compal Electronics, Inc.


SCHEMATICS,MB A4093

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
C

401621

Wednesday, April 15, 2009

Sheet

12

of

58

U3F

+VDDHT

4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
L22
1
0_0805_5%

2A

+VDDA18PCIE

1
C235
4.7U_0805_10V4Z

1
C246

1
C236

1
C237

1
C238

1
C239

4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

F9
G9
AE11
AD11

+1.8VS

C251
1U_0402_6.3V4Z

J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10

VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15
VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)

VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)
VDD33_1(NC)
VDD33_2(NC)

+1.1VS

+NB_VDDC

PAD-OPEN 4x4m

VDD_CORE=10A

1
+
2

330U_D2E_2.5VM

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

C234

+1.8VS

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

C245

1
C229

C233

1
C228

10U_0805_10V4Z

1
C227

PJP3

C232

1
C226

VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13

10U_0805_10V4Z

1
C225

AE25
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17

1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

C244

+VDDHTTX

2A

2
2
2
2
1
1

0.1U_0402_16V4Z

1
0_0805_5%

VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7

1
1
1
1
2
2

C231

0.1U_0402_16V4Z

L19
2

+1.2V_HT

H18
G19
F20
E21
D22
B23
A23

C220
C219
C222
C221
C224
C223

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2
0.1U_0402_16V4Z

10U_0805_10V4Z

C212

C230

C218

10U_0805_10V4Z

C211

0.1U_0402_16V4Z

C217

2
2
0.1U_0402_16V4Z

+1.1VS

+VDDA11PCIE

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

C243

C216
2

PART 5/6

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17

0.1U_0402_16V4Z

C214

VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7

C242

C215

10U_0805_10V4Z

J17
K16
L16
M16
P16
R16
T16

0.1U_0402_16V4Z

4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VDDHTRX
2
1 2A
0_0805_5%
1
1
1
1
L18

PV:Change C215 from 4.7u to 10u

L17
1
2
FBMA-L11-201209-221LMA30T_0805

VDDA_12=2.5A

U3E

C241

0.1U_0402_16V4Z

1
C210

C240

1
C208

0.1U_0402_16V4Z

1
C207

C247

1
C206

0.1U_0402_16V4Z

1
C209

VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27

L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11

VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34

PART 6/6

GROUND

2A
1

0.1U_0402_16V4Z

L16
2
0_0805_5%

+1.1VS

POWER

A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25

VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

RS780M_FCBGA528

AE10
AA11
Y11
AD10
AB10
AC10
H11
H12

+3VS

RS780M_FCBGA528
RX781R1@

PV: follow check list connect to GND

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATICS,MB A4093
Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

13

of

58

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

RS780 DFT_GPIO5 mux at CRT_VSYNC pull high to 3K


SI2: Change to 3K pull high
2
R101
2
R102

11 UMA_VSYNC

1
3K_0402_5%
1
@ 3K_0402_5%

Enables the Test Debug Bus using GPIO.


1 : Enable (RX780, RS780)
0 : Disable (RX780, RS780)
PIN: RS740-->RS780_AUX_CAL; RX780-->NB_TV_C; RS780--> VSYNC#

+3VS

DFT_GPIO[4:2]: STRAP_PCIE_GPP_CFG[2:0]

These
000 :
001 :
010 :
011 :
100 :
101 :
111 :

RS780 use register to control PCI-E configure

pin straps are used to configure PCI-E GPP mode.


00001
00010
01011
00100
01010
01100
01011

DFT_GPIO1: LOAD_EEPROM_STRAPS
1
@R104
@
R104

11 AUX_CAL

RS780 DFT_GPIO1

D4
2

11 SUS_STAT_R#

2
150_0402_1%
@ CH751H-40PT_SOD323-2
1

PLT_RST#

Selects Loading of STRAPS from EPROM


1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
11,15,30,36,37,38,44,45 default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

RX780 DFT_GPIO1 mux at GREEN(Ball E18) and change pull low form 150 to 3K.

DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb

RS780 use HSYNC to enable SIDE PORT (internal pull high)

11 UMA_HSYNC

2
R107

1
@ 3K_0402_5%

2
R125

1
3K_0402_5%

RX780: Enables the Test Debug Bus using PCIE bus


1 : Disable ( Can still be enabled using nbcfg register access )
0 : Enable
RS780: Enables Side port memory ( RS780 use HSYNC#)
1. Disable (RS780)
0 : Enable (RS780)

+3VS

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATICS,MB A4093
Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

14

of

58

10 PCIE_GTX_C_MRX_P[0..15]
10 PCIE_GTX_C_MRX_N[0..15]
10 PCIE_MTX_C_GRX_P[0..15]
D

10 PCIE_MTX_C_GRX_N[0..15]

PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]

Close to connector

PCIE_MTX_C_GRX_P[0..15]
U5A

PART 1 OF 7

PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P15 AK33
PCIE_MTX_C_GRX_N15 AJ33

PCIE_RX0P
PCIE_RX0N

PCIE_MTX_C_GRX_P14 AJ35
PCIE_MTX_C_GRX_N14 AJ34

PCIE_RX1P
PCIE_RX1N

PCIE_MTX_C_GRX_P13 AH35
PCIE_MTX_C_GRX_N13 AH34

PCIE_RX2P
PCIE_RX2N

PCIE_MTX_C_GRX_P12 AG35
PCIE_MTX_C_GRX_N12 AG34

PCIE_RX3P
PCIE_RX3N

PCIE_MTX_C_GRX_P11 AF33
PCIE_MTX_C_GRX_N11 AE33

PCIE_RX4P
PCIE_RX4N

PCIE_MTX_C_GRX_P10 AE35
PCIE_MTX_C_GRX_N10 AE34

PCIE_RX5P
PCIE_RX5N

P
C
I
E
X
P
R
E
S
S
I
N
T
E
R
F
A
C
E

11,14,30,36,37,38,44,45

PLT_RST#

PCIE_GTX_MRX_P15
PCIE_GTX_MRX_N15

CV9 1
CV10 1

2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P15
2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N15

PCIE_TX1P
PCIE_TX1N

AF31
AF30

PCIE_GTX_MRX_P14
PCIE_GTX_MRX_N14

CV11 1
CV12 1

2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P14
2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N14

PCIE_TX2P
PCIE_TX2N

AF28
AF27

PCIE_GTX_MRX_P13
PCIE_GTX_MRX_N13

CV13 1
CV14 1

2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P13
2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N13

PCIE_TX3P
PCIE_TX3N

AD31
AD30

PCIE_GTX_MRX_P12
PCIE_GTX_MRX_N12

CV15 1
CV16 1

2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P12
2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N12

PCIE_TX4P
PCIE_TX4N

AD28
AD27

PCIE_GTX_MRX_P11
PCIE_GTX_MRX_N11

CV17 1
CV18 1

2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P11
2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N11

PCIE_TX5P
PCIE_TX5N

AB31
AB30

PCIE_GTX_MRX_P10
PCIE_GTX_MRX_N10

CV19 1
CV20 1

2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P10
2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N10

PCIE_TX6P
PCIE_TX6N

AB28
AB27

PCIE_GTX_MRX_P9
PCIE_GTX_MRX_N9

CV21 1
CV22 1

2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P9
2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N9

PCIE_TX7P
PCIE_TX7N

AA31
AA30

PCIE_GTX_MRX_P8
PCIE_GTX_MRX_N8

CV23 1
CV24 1

2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P8
2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N8

PCIE_TX8P
PCIE_TX8N

AA28
AA27

PCIE_GTX_MRX_P7
PCIE_GTX_MRX_N7

CV25 1
CV26 1

2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P7
2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N7

AD35
AD34

PCIE_RX6P
PCIE_RX6N

PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8

AC35
AC34

PCIE_RX7P
PCIE_RX7N

PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7

AB33
AA33

PCIE_RX8P
PCIE_RX8N

PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6

AA35
AA34

PCIE_RX9P
PCIE_RX9N

PCIE_TX9P
PCIE_TX9N

W31
W30

PCIE_GTX_MRX_P6
PCIE_GTX_MRX_N6

CV27 1
CV28 1

2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P6
2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N6

PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5

Y35
Y34

PCIE_RX10P
PCIE_RX10N

PCIE_TX10P
PCIE_TX10N

W28
W27

PCIE_GTX_MRX_P5
PCIE_GTX_MRX_N5

CV29 1
CV30 1

2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P5
2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N5

PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4

W35
W34

PCIE_RX11P
PCIE_RX11N

PCIE_TX11P
PCIE_TX11N

V31
V30

PCIE_GTX_MRX_P4
PCIE_GTX_MRX_N4

CV31 1
CV32 1

2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P4
2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N4

PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3

V33
U33

PCIE_RX12P
PCIE_RX12N

PCIE_TX12P
PCIE_TX12N

V28
V27

PCIE_GTX_MRX_P3
PCIE_GTX_MRX_N3

CV33 1
CV34 1

2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P3
2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N3

PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2

U35
U34

PCIE_RX13P
PCIE_RX13N

PCIE_TX13P
PCIE_TX13N

U31
U30

PCIE_GTX_MRX_P2
PCIE_GTX_MRX_N2

CV35 1
CV36 1

2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P2
2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N2

PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1

T35
T34

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

U28
U27

PCIE_GTX_MRX_P1
PCIE_GTX_MRX_N1

CV37 1
CV38 1

2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P1
2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N1

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0

R35
R34

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

R31
R30

PCIE_GTX_MRX_P0
PCIE_GTX_MRX_N0

CV39 1
CV40 1

2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P0
2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N0

Clock
26 CLK_PCIE_VGA
26 CLK_PCIE_VGA#

AG31
AG30

PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
C

PCIE_TX0P
PCIE_TX0N

AJ31
AJ30

Calibration

PCIE_REFCLKP
PCIE_REFCLKN
SM Bus

AK35
AK34

NC_SMB_DATA
NC_SMBCLK

AM32

PERSTB

PCIE_CALRN

AG26

PCIE_CALRP

AJ27 PCIE_CALRP

NC_DRAM_0
NC_DRAM_1
NC_AC_BATT
NC_FAN_TACH

RV6 1.27K_0402_1%
1
2

RV5
1

2K_0402_1%
2

+PCIE_VDDC

AF3
AG9
AK29
AK14

216-0683008 A11 M86-M_BGA880


M86R1@

Compal Secret Data

Security Classification
2006/09/25

Issued Date

Deciphered Date

2006/09/25

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATICS,MB A4093
Document Number

Rev
C

401621
Wednesday, April 15, 2009

Sheet
1

15

of

58

U5B
PART 2 OF 7

BLM18PG121SN1D_0603
0.1U_0402_16V4Z
2
1
LV2
1
1
1
+1.8VS
CV46
CV45
2
10U_0603_6.3V6M

For M86 HDA Enable

52mA
+DPLL_PVDD

VIP_3

1
RV7

+3VS_DELAY

2
10K_0402_5%
<BOM Structure>

CV47
1U_0402_6.3V4Z

68mA

+1.8VS

BLM18PG121SN1D_0603
+PCIE_PVDD
0.1U_0402_16V4Z
2
1
LV4
1
1
1
CV48
CV49
CV41
10U_0603_6.3V6M

1U_0402_6.3V4Z

10U_0603_6.3V6M

+1.1VS

+MPVDD
1

CV55
0.1U_0402_16V4Z

BLM18PG121SN1D_0603
0.1U_0402_16V4Z
2
1
LV7
1
1
1
CV59
CV60
2

LCD_DDC_DAT
LCD_DDC_CLK

28 LCD_DDC_DAT
28 LCD_DDC_CLK

LCD

345mA

1 1U_0402_6.3V4Z
1
1
CV53
CV54

LV5

PSYNC

100mA
+DPLL_VDDC
CV61
1U_0402_6.3V4Z

10U_0603_6.3V6M
C

25
25
25
25

+3VS_DELAY

THM_ALERT#
RV9

2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

VGA_DDC_DAT

1
RV10
1
RV12
LCD_DDC_DAT
1
RV13
LCD_DDC_CLK
1
RV14
HDMIDAT_VGA
1
RV16
HDMICLK_VGA
1
RV17
CLKREQ_GPIO23
1
RV18
VGA_DDC_CLK

VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3
25
25

2 RV11

45

25

+3VS_DELAY

@
2 RV108

10K_0402_5%
55 VGA_PWSELECT

For PCIE reference clock

2
RV19
XTALIN

OUT

IN

GND

GND

1 CV78

@ 27MHz_16PF_6P27000126

@ 22P_0402_50V8J
RV23
249_0402_1%

1
CV79
2

CV77
2 @ 22P_0402_50V8J

AR16
AP16

2
0.1U_0402_16V4Z

+MPVDD

TX5M_DPB3P
TX5P_DPB3N

AR17
AP17

AN8
AP8
AG1
AH3
AH2
AH1
AJ3
AJ2
AJ1
AK2
AK1
AL3
AL2
AL1
AM3
AM2
AN2
AP3
AR3
AN4
AR4
AP4
AN5
AR5
AP5
AP6
AR6
AN7
AP7
AR7

DVPCNTL__MVP_0
DPA_PVDD
DVPCNTL__MVP_1
DPA_PVSS
DVPCNTL_0
INTEGRATED
DVPCNTL_1
DPB_PVDD
TMDS/DP
DVPCNTL_2
DPB_PVSS
DVPCLK
DVPDATA_0
DPB_VDDR_1
DVPDATA_1 MULTI_GFX
DPB_VDDR_2
DVPDATA_2 EXTERNAL
DPA_VDDR_3
DVPDATA_3 TMDS
DPA_VDDR_4
DVPDATA_4
DVPDATA_5
DPB_VSSR_1
DVPDATA_6
DPB_VSSR_2
DVPDATA_7
DPB_VSSR_3
DVPDATA_8
DPB_VSSR_4
DVPDATA_9
DPB_VSSR_6
DVPDATA_10
DPA_VSSR_5
DVPDATA_11
DPA_VSSR_7
DVPDATA_12
DPA_VSSR_8
DVPDATA_13
DPA_VSSR_9
DVPDATA_14
DPA_VSSR_10
DVPDATA_15
DVPDATA_16
DP_CALR
DVPDATA_17
NC_TPVDDC
DVPDATA_18
NC_TPVSSC
DVPDATA_19
HPD1
DVPDATA_20
DVPDATA_21
DVPDATA_22
R
DVPDATA_23
RB

AM14
AL14

+DPA_PVDD

AH17
AG17

+DPB_PVDD

AN19
AN20
AP19
AR19

+DPB_VDDR

75_0402_1%
2
1
RV28

27M_CLK

XTALIN
XTALOUT

26

+DPLL_VDDC

1.1 PV change 100K to

AR33
AP33

XTALIN
XTALOUT

AG19

DPLL_VDDC

AG21

TS_FDO

RV30
100_0402_1%

MPVDD
MPVSS

100

25
25

DD+

AK4
AM4

DMINUS
DPLUS

PLL
CLOCKS

1U_0402_6.3V4Z
2

HSYNC
VSYNC

AN29
AN30

RSET

AN31

AVDD

AR32

+AVDD

CV68
2

BLM18PG121SN1D_0603
2
1
LV10
+3VS_DELAY

CV69
CV70
1U_0402_6.3V4Z
2
2
0.1U_0402_16V4Z

BLM18PG121SN1D_0603
2
1
+1.8VS
LV11

10mA
1
CV71

1
CV72

2
2
0.1U_0402_16V4Z

1
CV74

1U_0402_6.3V4Z
2

BLM18PG121SN1D_0603
2
1
+1.8VS
LV12

1
CV75

2
2
0.1U_0402_16V4Z

CV73
1U_0402_6.3V4Z

85mA

CV76
10U_0603_6.3V6M

+VDD1DI

2
715_0402_1%

RED

AM29
AL29

GREEN
BLUE

AJ15
AH15
VGA_DDC_DAT
VGA_DDC_CLK

AH14
AG14

BLM18PG121SN1D_0603
2
1
+1.8VS
LV9

+VDD1DI

1
RV24

AJ5
AJ4

CV64
10U_0603_6.3V6M

+A2VDDQ

DDC4DATA_DP4_AUXN
DDC4CLK_DP4_AUXP

CV66
CV67
10U_0603_6.3V6M
2
2
0.1U_0402_16V4Z

10U_0603_6.3V6M

AL21

DDC3DATA_DP3_AUXN
DDC3CLK_DP3_AUXP

CV63
2

A2VDD

R2SET

CV62

65mA

+A2VDDQ

A2VDDQ

AJ21

+A2VDD

10U_0603_6.3V6M

+A2VDD

AK21

BLM18PG121SN1D_0603
2
1
+1.1VS
LV8

70mA

+VDD1DI

AL15
AM15

AH22
AG22

CRT_HSYNC 25,27
CRT_VSYNC 27
1
2
RV15 499_0402_1%
+AVDD

AM21

VDD2DI
VSS2DI

BLM18PG121SN1D_0603
2
1
+1.1VS
LV6

CV65

V2SYNC
H2SYNC

A2VSSQ

27

C
Y
COMP

CV52
10U_0603_6.3V6M

2
150_0402_1%

BLUE

AK19
AK18
AK17

+1.8VS

1U_0402_6.3V4Z
1
RV8

AR29
AP29

AM17
AL17

BLM18PG121SN1D_0603
2
1
LV3

CV57
CV58
0.1U_0402_16V4Z
1
1
1U_0402_6.3V4Z

B
BB

DDC2CLK

THERMAL

0.1U_0402_16V4Z

B2
B2B

+1.8VS

CV44
0.1U_0402_16V4Z

CV56

27

AM18
AL18

200mA

+DPB_VDDR

27

G2
G2B

CV51

GREEN

AM19
AL19

10U_0603_6.3V6M

RED

R2
R2B

CV50

+DPA_VDDR

AR30
AP30

AR28
AP28

G
GB

AP32

200mA

+DPA_VDDR

29

DDC
DP AUX DDC2DATA

BLM18PG121SN1D_0603
2
1
LV1

0.1U_0402_16V4Z

AG15
AH18
AG18
AG6

AVSSQ

CV43

20mA

AN18
AP18
AR18
AN16
AN17
AN15
AN11
AN12
AN13
AN14

VDD1DI
VSS1DI

1U_0402_6.3V4Z

HPD

DDC1DATA
DDC1CLK

CV42
1

AR31
AP31

DAC1

SDA
SCL

A14
B15

10U_0603_6.3V6M

1U_0402_6.3V4Z

DVALID

PCIE_PVDD

+DPA_PVDD
2

AK6
AM6

DAC2

20mA

+DPB_PVDD

TX4M_DPB2P
TX4P_DPB2N

HDMI_TX2-_VGA 29
HDMI_TX2+_VGA 29

AR15
AP15

PSYNC

AM35

RV22
499_0402_1%

YV1

HDMI_TX1-_VGA 29
HDMI_TX1+_VGA 29

TX3M_DPB1P
TX3P_DPB1N

VPCLK0
VIPCLK

AM7

+PCIE_PVDD

+1.8VS

1.1 PV ADD
@
11M_0402_5%

R234 2

XTALOUT

AR11
AP11

AR14
AP14

DPLL_PVDD
DPLL_PVSS

CLKREQ_GPIO23
JMODE_GPIO24
1
1K_0402_5%

TX1M_DPA2P
TX1P_DPA2N

TXCBM_DPB0P
TXCBP_DPB0N

AR20
AP20

25 SCS#_GPIO22

HDMI_TX0-_VGA 29
HDMI_TX0+_VGA 29

VPHCTL

+DPLL_PVDD

10K_0402_5%

AR10
AP10

AJ9
AL7
AK7

VREFG

25 THM_ALERT#
1

HDMI_CLK-_VGA 29
HDMI_CLK+_VGA 29

TX0M_DPA1P
TX0P_DPA1N

TX2M_DPA3P
TX2P_DPA3N

AD12

27M_SSIN

@
2 RV107

SCLK_GPIO10

AN9
AN10

VHAD_0
VHAD_1

+VGA_VREF

GPIO_5

TXCAM_DPA0P
TXCAP_DPA0N

AR12
AP12

GPIO_0
GPIO_1
GENERAL
GPIO_2
PURPOSE
GPIO_3
I/O
GPIO_4
GPIO_5
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BBEN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
GPIO_24_JMODE
GPIO_25_TDI
GPIO_26_TCK
GPIO_27_TMS
GPIO_28_TDO
GEN_A
GEN_B
GEN_C
GEN_D_HPD4
GEN_E
GEN_F
GEN_G

ENBKL
25 SOUT_GPIO8
25 SIN_GPIO9
T4 PAD
25 GPIO_11
25 GPIO_12
25 GPIO_13

VIP / I2C

AG2
AF2
AF1
AE3
AE2
AE1
AD3
AD2
AD1
AD5
AD4
AC3
AC2
AC1
AB3
AB2
AB1
AF5
AF4
AG4
AG3
AD9
AD8
AD7
AB4
AB6
AB7
AB9
AA9
AF8
AF7
AG5
AP9
AR9
AP13
AR13

GPIO_0
GPIO_1

10K_0402_5%

VIP_0
VIP_1
VIP_2
VIP_3
VIP_4
VIP_5
VIP_6
VIP_7

AM9
AL9

AJ7

BLM18PG121SN1D_0603

+VGA_CORE

25

AM12
AL12
AJ12
AH12
AM10
AL10
AJ10
AH10

VGA_DDC_DAT 27
VGA_DDC_CLK 27
HDMIDAT_VGA 29
HDMICLK_VGA 29

1
RV25
1
RV26
1
RV27

2
@ 150_0402_1%
2
@ 150_0402_1%
2
@ 150_0402_1%

CRT
A

HDMI

M86R1@

216-0683008 A11 M86-M_BGA880

Compal Secret Data

Security Classification
26

27M_SSC

1
RV165

2
@ 0_0402_5%

Reserve

27M_SSIN

2006/09/25

Issued Date

2006/09/25

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATICS,MB A4093
Document Number

Rev
C

401621
Sheet

Wednesday, April 15, 2009


1

16

of

58

U5F

320mA
BLM18PG121SN1D_0603
1
2
LV13
1

CV84

AJ26
AH26

CV82

2
10U_0603_6.3V6M

PART 7 OF 7

+LVDDR

1U_0402_6.3V4Z
1

1
2
LV14
1
BLM18PG121SN1D_0603

1U_0402_6.3V4Z
1
CV85

+LVDDC

2
10U_0603_6.3V6M

+LVDDC
1

CV86
2

CV87

2
0.1U_0402_16V4Z

+1.8VS

ControlVARY_BL

AG7

DIGON

AJ6

CV83

2
0.1U_0402_16V4Z

LVDDC+LVDDR=400mA
+1.8VS

LVDDR_1
LVDDR_2

AK27
AL27

LVDDC_1
LVDDC_2

AM24
AN28
AN21
AN24
AN25
AM22
AP21
AP26
AM27
AR21
AR26
AM26
AJ22
AJ24

LVSSR_1
LVSSR_2
LVSSR_3
LVSSR_4
LVSSR_5
LVSSR_6
LVSSR_7
LVSSR_8
LVSSR_9
LVSSR_10
LVSSR_11
LVSSR_12
LVSSR_13
LVSSR_14

AL22
AK22

LPVDD
LPVSS

LVDS channel

+1.8VS

40mA
2

1
LV15
BLM18PG121SN1D_0603

1
CV88

1U_0402_6.3V4Z
1
CV89

2
0.1U_0402_16V4Z

+LPVDD
1

2
RV33

1
10K_0402_5%
VGA_ENVDD 28

TXCLK_UP
TXCLK_UN
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N

AK24
AL24
AN27
AN26
AP27
AR27
AG24
AH24
AK26
AL26

LVDS_BCLK+ 28
LVDS_BCLK- 28
LVDS_B0+ 28
LVDS_B0- 28
LVDS_B1+ 28
LVDS_B1- 28
LVDS_B2+ 28
LVDS_B2- 28

TXCLK_LP
TXCLK_LN
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N

AR22
AP22
AN23
AN22
AP23
AR23
AP24
AR24
AP25
AR25

LVDS_ACLK+ 28
LVDS_ACLK- 28
LVDS_A0+ 28
LVDS_A0- 28
LVDS_A1+ 28
LVDS_A1- 28
LVDS_A2+ 28
LVDS_A2- 28

CV90
2

2
10U_0603_6.3V6M

216-0683008 A11 M86-M_BGA880


M86R1@

Compal Secret Data

Security Classification
2006/09/25

Issued Date

Deciphered Date

2006/09/25

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATICS,MB A4093
Document Number

Rev
C

401621
Wednesday, April 15, 2009

Sheet
1

17

of

58

U5D

+1.8VS

+PCIE_VDDR_M86

PART 5 OF 7

CV99
CV101
CV102
CV109
CV111
CV113

1
1
1
1
1
1
1

2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z

CV93
CV96
CV98
CV100
CV107
CV103
CV104

1
1
1
1
1
1
1
1

BLM18PG121SN1D_0603
+1.8VS

+VDDR4
BLM18PG121SN1D_0603
2
1
LV19

CV125

1
1

CV118

2
10U_0603_6.3V6M
2
1U_0402_6.3V4Z
2
0.1U_0402_16V4Z

CV120

+VDD_CT

1
2

2
10U_0603_6.3V6M
2
1U_0402_6.3V4Z
1
0.1U_0402_16V4Z

+3VS_DELAY
CV131
CV135
+1.8VS

+VDDR5

CV139
1.1 PV ADD
CV144

BLM18PG121SN1D_0603
2
1
LV20
CV152

CV143

1
1
1

2
10U_0603_6.3V6M
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z

VDDR3_1
VDDR3_2
VDDR3_3
VDDR3_4

AP2
AR2

VDDR4_1
VDDR4_2

AN1
AP1

VDDR5_1
VDDR5_2

1.1 PV ADD
+VDDR5
+VDD_MEM_CLK0
+VDD_MEM_CLK1

1
1
1

2
10U_0603_6.3V6M
2
1U_0402_6.3V4Z
2
0.1U_0402_16V4Z

+VDD_MEM_CLK2
+VDD_MEM_CLK3

CV157

1U_0402_6.3V4Z
2

CV158

CV159

2
10U_0603_6.3V6M

BLM18PG121SN1D_0603
2
1
LV23
1
CV166

1
0.1U_0402_16V4Z

B25
B32

VSSRHA_1
VSSRHA_2

B2
L1

VDDRHB_1
VDDRHB_2

C2
L2

VSSRHB_1
VSSRHB_2
BBN_1
BBN_2

U13
V13

BBP_1
BBP_2

1
CV160

1U_0402_6.3V4Z

VDDRHA_1
VDDRHA_2

W13
AA13

+VGA_CORE

+VDD_MEM_CLK0
1

A25
A32

P
O
W
E
R

R26
U26
V25
V26
W25
W26
AA25
AD26
AF26
AA26
AB25
AB26

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
VDDC_33
VDDC_34
VDDC_35
VDDC_36
VDDC_37
VDDC_38
VDDC_39
VDDC_40
VDDC_41
VDDC_42
VDDC_43
VDDC_44

N13
N15
N18
N21
N23
P14
P17
P19
P22
V18
V21
V23
W14
W17
W19
W22
AA15
AA18
AA21
AA23
AB14
AB17
AB19
AB22
AC13
AC15
AC18
AC21
AC23
AE18
AE22
AE19
AE21
R13
R15
R18
R21
R23
U14
U17
U19
U22
V15
W11

VDDCI_1
VDDCI_2
VDDCI_3
VDDCI_4

M12
M24
P11
P25

Back
Bias

BLM18PG121SN1D_0603
2
1
LV21
1

+1.8VS

AE14
AE15
AF12
AE17
+VDDR4

Back Bias Disable


+1.8VS

VDD_CT_5
VDD_CT_6
VDD_CT_7
VDD_CT_8

PCIE_VDDC_1
PCIE_VDDC_2
PCIE_VDDC_3
PCIE_VDDC_4
PCIE_VDDC_5
PCIE_VDDC_6
PCIE_VDDC_7
PCIE_VDDC_8
PCIE_VDDC_9
PCIE_VDDC_10
PCIE_VDDC_11
PCIE_VDDC_12

Memory I/O
Clock

CV148

R11
R25
U11
U25

AR34
AL33
AM33
AN33
AN34
AN35
AP34
AP35

CV161
1U_0402_6.3V4Z

CV168
2

CV173

+PCIE_VDDC

1.2A

1
LV17
CV108
CV110
CV112
CV114
CV115
CV116

2
BLM18PG121SN1D_0603
1
1
1
1
1
1

+VGA_CORE

18A
1
@ CV122
1
@ CV128

2
330U_V_2.5VM_R9M
2
330U_V_2.5VM_R9M

CV123
CV126
CV129

CV132
CV136
CV140
CV145
CV149

1
1
1
1
1

2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M

CV133
CV137
CV141
CV146
CV150
CV153
CV155

+VDDCI 1U_0402_6.3V4Z
1
CV162

1U_0402_6.3V4Z
1
CV163
CV164

2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z

1
1
1
1
1
1
1
1
1

BLM18PG121SN1D_0603
2
1
LV22

CV124
CV127
CV130
CV134
CV138
CV142
CV147
CV151
CV154
CV156

2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z

1
1
1
1
1
1
1
1
1

+VGA_CORE

CV165
2
1U_0402_6.3V4Z

2
10U_0603_6.3V6M

3
2

+3VS
RV34
100K_0402_5%

1U_0402_6.3V4Z
+VDD_MEM_CLK2

From 1.8VS<-->1.1VSP Chip

2
CV171

52

1
0.1U_0402_16V4Z

1
R42

1.1VS_POK

2
0_0402_5%

2
4.7K_0402_5%
CV172
0.1U_0402_16V4Z

1U_0402_6.3V4Z

Q9

2
G
1

1
R403

1
CV170

2N7002_SOT23-3

+VDD_MEM_CLK3
1
CV174

2
10U_0603_6.3V6M

2
CV175

1
0.1U_0402_16V4Z

Compal Secret Data

Security Classification
2006/09/25

Issued Date

Deciphered Date

2006/09/25

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

+1.1VS

2
10U_0603_6.3V6M
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
0.1U_0402_16V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z

QV3
1

+3VS_DELAY

2
G
BLM18PG121SN1D_0603
2
1
LV25
1

+1.8VS

100mA

1
0.1U_0402_16V4Z

+3VS

+1.8VS

2
BLM18PG121SN1D_0603
2
10U_0603_6.3V6M
2
1U_0402_6.3V4Z
2
0.1U_0402_16V4Z

CV167

2
10U_0603_6.3V6M

CV106

+VDD_MEM_CLK1
1

CV169

CV94

SI2301BDS_SOT23

BLM18PG121SN1D_0603
2
1
LV24
1

CV92

1U_0402_6.3V4Z

2
10U_0603_6.3V6M

+1.8VS

1
LV16

216-0683008 A11 M86-M_BGA880

CV121

VDD_CT_1
VDD_CT_2
VDD_CT_3
VDD_CT_4

76mA

LV18
CV117

CV119

432mA
PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7
PCIE_VDDR_8

+1.8VS

AA11
AB11
AD10
AF10

2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z

Memory I/O

CV97

CV105

PCI-Express

CV95

1
330U_V_2.5VM_R9M

VDDR1_1
VDDR1_2
VDDR1_3
VDDR1_4
VDDR1_5
VDDR1_6
VDDR1_7
VDDR1_8
VDDR1_9
VDDR1_10
VDDR1_11
VDDR1_12
VDDR1_13
VDDR1_14
VDDR1_15
VDDR1_16
VDDR1_17
VDDR1_18
VDDR1_19
VDDR1_20
VDDR1_21
VDDR1_22
VDDR1_23
VDDR1_24
VDDR1_25
VDDR1_26
VDDR1_27
VDDR1_28
VDDR1_29

Core

2
CV91

D1
A8
A12
A16
A20
A24
A28
B1
H1
H35
L18
L19
L21
L22
M10
M35
P10
T1
Y1
B35
M1
D35
K10
K12
K24
K26
L14
L15
L17

I/O Internal

3.48A

Compal Electronics, Inc.


SCHEMATICS,MB A4093
Document Number

Rev
C

401621
Wednesday, April 15, 2009

Sheet
1

18

of

58

U5E

Part 6 of 7

A2
A34
C3
C5
A4
C18
A21
C23
C11
C13
C14
A18
A11
C26
C33
F35
R7
G10
F15
H17
G21
D29
A29
G1
F14
J15
E19
E22
E24
D7
G9
F26
G29
D33
M5
G4
E10
E12
F17
G18
G22
F30
J35
J18
H19
J21
F7
J12
J24
J26
K30
J32
F33
K6
K9
K14
K15
K17
K18
K19
K21
K22
M28
K3
L33

PCIE_VSS_1
PCIE_VSS_2
PCIE_VSS_3
PCIE_VSS_4
PCIE_VSS_5
PCIE_VSS_6
PCIE_VSS_7
PCIE_VSS_8
PCIE_VSS_9
PCIE_VSS_10
PCIE_VSS_11
PCIE_VSS_12
PCIE_VSS_13
PCIE_VSS_14
PCIE_VSS_15
PCIE_VSS_16
PCIE_VSS_17
PCIE_VSS_18
PCIE_VSS_19
PCIE_VSS_20
PCIE_VSS_21
PCIE_VSS_22
PCIE_VSS_23
PCIE_VSS_24
PCIE_VSS_25
PCIE_VSS_26
PCIE_VSS_27
PCIE_VSS_28
PCIE_VSS_29
PCIE_VSS_30
PCIE_VSS_31
PCIE_VSS_32
PCIE_VSS_33
PCIE_VSS_34
PCIE_VSS_35
PCIE_VSS_36
PCIE_VSS_37
PCIE_VSS_38
PCIE_VSS_39
PCIE_VSS_40
PCIE_VSS_41
PCIE_VSS_42
PCIE_VSS_43
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65

PCI-Express GND

P33
P34
P35
R27
R28
R29
R32
R33
U29
U32
V29
V32
T33
V34
V35
W29
W32
W33
AA29
AA32
AB29
AB32
Y33
AB34
AB35
AC33
AD29
AD32
AF29
AF32
AD33
AF34
AF35
AG27
AG29
AG32
AG33
AJ29
AJ32
AH33
AL34
AL35
AK32

VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166

P6
M9
M26
K28
M32
N14
N17
N19
N22
N33
N3
R5
U8
P13
P15
P18
P21
P23
P26
P29
P30
R1
U5
P9
R10
R14
R17
R19
R22
V3
AK9
U10
U15
U18
U21
U23
V7
W8
V10
V14
V17
V19
V22
V1
AK12
V9
W10
W15
W18
W21
W23
AA6
AA10
AA14
AA17
AA19
AA22
AB8
AB10
AB13
AB15
AB18
AB21
AB23
AC14
AC17
AC19
AC22
AF9
AD6
AB5
AD24
W5
AF6
AF14
AF21
AF22
AK10
AF17
AF18
AF19
AA3
AG12
AJ14
AH21
D4
AF15
AG10
AN6
AK15
AJ17
AJ18
AJ19
AF24
AN32
AK3
AN3
AR8
AM1
AK30
V11

MECH_1
MECH_2
MECH_3

A35
AR1
AR35

CORE GND
Compal Secret Data

Security Classification

216-0683008 A11 M86-M_BGA880

2006/09/25

Issued Date

Deciphered Date

2006/09/25

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATICS,MB A4093
Document Number

Rev
C

401621
Wednesday, April 15, 2009

Sheet
1

19

of

58

QSA#[7..0]
MAA[12..0]
BA[2..0]
MDA[63..0]

MDB[63..0]

21,22

QSA[7..0]

21,22

QSA#[7..0]

21,22

MAA[12..0]

21,22

BA[2..0]

21,22

MDA[63..0]

21,22

MAB[12..0]

Close to pin N34, N35

BB[2..0]
DQMB#[7..0]

+1.8VS

QSB[7..0]
+1.8VS
QSB#[7..0]

MDB[63..0]

23,24

MAB[12..0]

23,24

BB[2..0]

23,24

DQMB#[7..0]

23,24

QSB[7..0]

23,24

QSB#[7..0]

23,24
D

DQMA#[7..0]

QSA[7..0]

DQMA#[7..0]

RV36
100_0402_1%

RV37
100_0402_1%

+MVREFDA
+MVREFSA

N35
N34
AM34

QSA_0B
QSA_1B
QSA_2B
QSA_3B
QSA_4B
QSA_5B
QSA_6B
QSA_7B

M31
K35
G32
E35
A22
E21
A17
E17

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

RV41
100_0402_1%
+MVREFSB

+MVREFDB

RV42
100_0402_1%

CV178
0.1U_0402_16V4Z

RV43
100_0402_1%

CV179
0.1U_0402_16V4Z

ODTA0
ODTA1

C31
C25

ODTA0
ODTA1

21
22

CLKA0
CLKA1

A33
A26

CLKA0
CLKA1

21
22

CLKA0b
CLKA1b

B33
B26

CLKA0#
CLKA1#

21
22

RASA0b
RASA1b

A31
D24

RASA#0
RASA#1

21
22

CASA0b
CASA1b

C32
H26

CASA#0
CASA#1

21
22

CSA0b_0
CSA0b_1

A30
B30

CSA0#

21

CSA1b_0
CSA1b_1

G24
H24

CSA1#

MVREFDA
MVREFSA

CKEA0
CKEA1

B31
F24

NC_1

WEA0b
WEA1b

C29
D22

+MVREFDB
+MVREFSB

22

CKEA0
CKEA1

21
22

WEA#0
WEA#1

21
22

1
RV44 1
RV45 1
RV46 1
RV47

H15
G14
E14
D14
H12
G12
F12
D10
B13
C12
B12
B11
C9
B9
A9
B8
J10
H10
F10
D9
G7
G6
F6
D6
C8
C7
B7
A7
B5
A5
C4
B4
M3
M2
N2
N1
R3
R2
T3
T2
M8
M7
P5
P4
R9
R8
R6
U4
U3
U2
U1
V2
Y3
Y2
AA2
AA1
U9
U7
U6
V4
W9
W7
W6
W4

DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63

B14
A13

MVREFDB
MVREFSB

2
AM30
2 1K_0402_5%
AA8
2 4.7K_0402_5%
AA7
2 4.7K_0402_5%
AA5
240_0402_1% AH19

TESTEN
TEST_MCLK
TEST_YCLK
MEMTEST
PLLTEST

MEMORY INTERFACE B

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

M30
K34
G31
E34
B22
F21
B17
D17

RV40
100_0402_1%

QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7

+1.8VS

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

+1.8VS

M29
K33
G30
E33
C22
H21
C17
G17

2
DQMAb_0
DQMAb_1
DQMAb_2
DQMAb_3
DQMAb_4
DQMAb_5
DQMAb_6
DQMAb_7

Close to pin A13, B14


1

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
BA2
BA0
BA1

C27
B28
B27
G26
F27
E27
D27
J27
E29
C30
E26
A27
G27
D26
C28
B29

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_A12
MAA_BA2
MAA_BA0
MAA_BA1

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

MEMORY INTERFACE A
read strobe
write strobe

DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63

Part 4 of 7
CV176
0.1U_0402_16V4Z

2
Part 3 of 7

P27
P28
P31
P32
M27
K29
K31
K32
M33
M34
L34
L35
J33
J34
H33
H34
K27
J29
J30
J31
F29
F32
D30
D32
G33
G34
G35
F34
D34
C34
C35
B34
C24
B24
B23
A23
C21
B21
C20
B20
J22
H22
F22
D21
J19
G19
F19
D19
C19
B19
A19
B18
C16
B16
C15
A15
H18
F18
E18
D18
J17
G15
E15
D15

U5G

RV38
100_0402_1%

MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_A12
MAB_BA2
MAB_BA0
MAB_BA1

H2
H3
J3
J5
J4
J6
G5
J9
F3
F4
J1
J2
J7
F1
G2
G3

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
BB2
BB0
BB1

DQMBb_0
DQMBb_1
DQMBb_2
DQMBb_3
DQMBb_4
DQMBb_5
DQMBb_6
DQMBb_7

D12
C10
E7
C6
P3
R4
W3
V8

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

QSB_0
QSB_1
QSB_2
QSB_3
QSB_4
QSB_5
QSB_6
QSB_7

J14
B10
F9
B6
P2
P8
W2
V6

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

QSB_0B
QSB_1B
QSB_2B
QSB_3B
QSB_4B
QSB_5B
QSB_6B
QSB_7B

H14
A10
E9
A6
P1
P7
W1
V5

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

ODTB0
ODTB1

D2
K5

ODTB0
ODTB1

23
24

CLKB0
CLKB1

A3
K1

CLKB0
CLKB1

23
24

CLKB0b
CLKB1b

B3
K2

CLKB0#
CLKB1#

23
24

RASB0b
RASB1b

D3
K7

RASB#0
RASB#1

23
24

CASB0b
CASB1b

C1
K4

CASB#0
CASB#1

23
24

CSB0b_0
CSB0b_1

E1
E2

CSB0#

23

CSB1b_0
CSB1b_1

L3
M4

CSB1#

24

CKEB0
CKEB1

E3
K8

CKEB0
CKEB1

23
24

WEB0b
WEB1b

F2
M6

WEB#0
WEB#1

23
24

read strobe

U5C

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

CV177
0.1U_0402_16V4Z

write strobe

RV39
100_0402_1%

+MVREFSA

+MVREFDA

DRAM_RST

AA4

216-0683008 A11 M86-M_BGA880

216-0683008 A11 M86-M_BGA880


M86R1@

Compal Secret Data

Security Classification
2006/09/25

Issued Date

Deciphered Date

2006/09/25

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATICS,MB A4093
Document Number

Rev
C

401621
Wednesday, April 15, 2009

Sheet
1

20

of

58

BA[2..0]

Close to U6

BA[2..0] 20,22

MAA[12..0]

MAA[12..0] 20,22

Close to U7

+1.8VS
+1.8VS

MDA[31..0]

10U_0603_6.3V6M

MDA[31..0] 20
DQMA#[7..0] 20,22

CV180

QSA[7..0]

QSA[7..0] 20,22

1
CV181

1
CV182

CV183

CV184

CV185

0.01U_0402_16V7K

1
CV186

CV188

1
CV189

2
0.1U_0402_16V4Z

0.1U_0402_16V4Z

BA0
BA1

MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKA0#
CLKA0

K8
J8

CK
CK

K2

CKE

20

CSA0#

L8

CS

20

WEA#0

K3

WE

20

RASA#0

K7

RAS

20

CASA#0

L7

CAS

F3
B3

LDM
UDM

K9

ODTA0
QSA2
QSA#2

+1.8VS

F7
E8

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

+VRAM_REF1

RV50
4.99K_0402_1%

BA2

2
CV200
0.1U_0402_16V4Z

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1
J1
J7

MDA7
MDA5
MDA3
MDA4
MDA0
MDA2
MDA1
MDA6

CV193

1
CV194

1
D

CV195

0.1U_0402_16V4Z

0.1U_0402_16V4Z

MDA18
MDA19
MDA16
MDA21
MDA22
MDA17
MDA23
MDA20

Group2

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

BA0
BA1

L2
L3

BA0
BA1

MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKA0#
CLKA0

K8
J8

CK
CK

CKEA0

K2

CKE

CSA0#

L8

CS

WEA#0

K3

WE

RASA#0

K7

RAS

CASA#0

L7

CAS

DQMA#1
DQMA#3

F3
B3

LDM
UDM

ODTA0

K9

ODT

QSA1
QSA#1

F7
E8

LDQS
LDQS

QSA3
QSA#3

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

+1.8VS

0.1U_0402_16V4Z
1

+1.8VS

CV196

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

U7

Group swap
Group0

2 1U_0402_6.3V4Z
+1.8VS

RV49
4.99K_0402_1%

20

CLKA0#

CLKA0#

20

CLKA0

+VRAM_REF2

CLKA0

RV51
4.99K_0402_1%

BA2

2
RV52
56_0402_5%

HYB18T256161BF-25
@

RV53
56_0402_5%

CV201
0.1U_0402_16V4Z

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

CV197

1
2

QSA0
QSA#0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

ODT
LDQS
LDQS

0.01U_0402_16V7K

Bit swap
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDDL
VSSDL

RV48
4.99K_0402_1%

J1
J7

MDA29
MDA27
MDA31
MDA24
MDA26
MDA30
MDA25
MDA28
MDA11
MDA12
MDA14
MDA8
MDA10
MDA13
MDA9
MDA15

Group3

Group1
C

+1.8VS

0.1U_0402_16V4Z
1

+1.8VS

CV198

CV199

20

CV192

DQMA#2
DQMA#0

10U_0603_6.3V6M

L2
L3

CKEA0

CV191

BA0
BA1

0.1U_0402_16V4Z

1U_0402_6.3V4Z

U6

20

1
CV190

QSA#[7..0] 20,22

0.1U_0402_16V4Z

1
CV187

10U_0603_6.3V6M
1U_0402_6.3V4Z

QSA#[7..0]

0.1U_0402_16V4Z

10U_0603_6.3V6M

DQMA#[7..0]

0.1U_0402_16V4Z

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

2 1U_0402_6.3V4Z
B

HYB18T256161BF-25
@

Add BA2 for 64M*16 VRAM

Add BA2 for 64M*16 VRAM


CV202
470P_0402_50V8J

Compal Secret Data

Security Classification
2006/09/25

Issued Date

Deciphered Date

2006/09/25

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATICS,MB A4093
Document Number

Rev
C

401621
Wednesday, April 15, 2009

Sheet
1

21

of

58

Close to U8
BA[2..0]

BA[2..0] 20,21

MAA[12..0]

+1.8VS

+1.8VS
10U_0603_6.3V6M

MAA[12..0] 20,21

MDA[63..32]

MDA[63..32] 20

DQMA#[7..0]

CV203

DQMA#[7..0] 20,21

1
CV204

0.1U_0402_16V4Z

1
CV205

QSA[7..0]

0.1U_0402_16V4Z

CV206

CV207

CV208

0.01U_0402_16V7K

1
CV209

10U_0603_6.3V6M

CV210

CV211

1
CV212

10U_0603_6.3V6M

0.1U_0402_16V4Z

1
CV213

1
CV214

0.1U_0402_16V4Z

1
CV215

0.01U_0402_16V7K

1
CV216

1
CV217

1
CV218

10U_0603_6.3V6M
1U_0402_6.3V4Z

Close to U9

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
D

QSA[7..0] 20,21

QSA#[7..0]

QSA#[7..0] 20,21

U9
U8

BA0
BA1

L2
L3

BA0
BA1

MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKA1#
CLKA1

K8
J8

CK
CK

20

CKEA1

K2

CKE

20

CSA1#

L8

CS

20

WEA#1

K3

RASA#1

K7

20
20

CASA#1
DQMA#4
DQMA#5
1.1 PV Change

20

RAS

L7

CAS

F3
B3

LDM
UDM

K9

ODTA1

WE

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

MDA47
MDA41
MDA44
MDA40
MDA43
MDA45
MDA42
MDA46
MDA36
MDA35
MDA39
MDA32
MDA33
MDA38
MDA34
MDA37

Group5

Group4

+1.8VS

1.1 PV Change
0.1U_0402_16V4Z
1

ODT

CV219

+1.8VS

1
1.1 PV Change

UDQS
UDQS

+VRAM_REF3

J2

VREF

RV56
4.99K_0402_1%

BA2

2
CV224
0.1U_0402_16V4Z

Add BA2 for 64M*16 VRAM

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKA1#
CLKA1

K8
J8

CK
CK

CKEA1

K2

CKE

CSA1#

L8

CS

WEA#1

K3

WE

RASA#1

K7

RAS

CASA#1

L7

CAS

DQMA#6
DQMA#7

F3
B3

LDM
UDM

ODTA1

K9

ODT

QSA6
QSA#6

F7
E8

LDQS
LDQS

QSA7
QSA#7

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

RV55
4.99K_0402_1%

20
20

CLKA1#

CLKA1#

CLKA1

CLKA1

RV58
56_0402_5%

HYB18T256161BF-25
@

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

+VRAM_REF4

RV59
56_0402_5%

RV57
4.99K_0402_1%

BA2

2
CV223
0.1U_0402_16V4Z

Add BA2 for 64M*16 VRAM

MDA59
MDA60
MDA57
MDA62
MDA63
MDA56
MDA61
MDA58
MDA50
MDA52
MDA48
MDA53
MDA55
MDA51
MDA54
MDA49

0.1U_0402_16V4Z
1

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

Group6

+1.8VS

1
CV222

2
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

Group7

+1.8VS

CV221

B7
A8

MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

+1.8VS

QSA5
QSA#5

RV54
4.99K_0402_1%

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

BA0
BA1

LDQS
LDQS

2 1U_0402_6.3V4Z

1.1 PV Change

+1.8VS

F7
E8

L2
L3

CV220

QSA4
QSA#4

BA0
BA1

2 1U_0402_6.3V4Z

HYB18T256161BF-25
@

CV225
470P_0402_50V8J

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/04/11

Issued Date

Deciphered Date

2009/04/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATICS,MB A4093
Rev
C

401621

Date:

Wednesday, April 15, 2009

Sheet
1

22

of

58

BB[2..0]

MAB[12..0] 20,24

MDB[31..0]

+1.8VS
10U_0603_6.3V6M

1
DQMB#[7..0] 20,24

QSB[7..0]

0.1U_0402_16V4Z

CV226

CV227

CV228

QSB[7..0] 20,24

CV229

0.1U_0402_16V4Z

1
CV230

1
CV231

0.01U_0402_16V7K

1
CV232

10U_0603_6.3V6M

CV233

CV234

10U_0603_6.3V6M

1
CV235

0.1U_0402_16V4Z

1
CV236

CV237

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1
CV238

1U_0402_6.3V4Z

0.01U_0402_16V7K

1
CV239

CV240

CV241

0.1U_0402_16V4Z

0.1U_0402_16V4Z

QSB#[7..0] 20,24

UV7

L2
L3

BA0
BA1

MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKB0#
CLKB0

K8
J8

CK
CK

K2

CKE

CSB0#

L8

CS

20

WEB#0

K3

WE

20

RASB#0

K7

RAS

20

CASB#0

L7

CAS

F3
B3

LDM
UDM

20

DQMB#2
DQMB#0

20

ODT

QSB2
QSB#2

F7
E8

LDQS
LDQS

RV61
4.99K_0402_1%

QSB0
QSB#0

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

+VRAM_REF5

RV63
4.99K_0402_1%

BB2
CV247
0.1U_0402_16V4Z

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1
J1
J7

0.1U_0402_16V4Z
1
CV244

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSS1
VSS2
VSS3
VSS4
VSS5

Group0

Group2

+1.8VS

+1.8VS

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDDL
VSSDL

K9

ODTB0

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

MDB6
MDB4
MDB7
MDB0
MDB2
MDB3
MDB1
MDB5
MDB19
MDB17
MDB22
MDB16
MDB20
MDB18
MDB21
MDB23

L2
L3

BA0
BA1

MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKB0#
CLKB0

K8
J8

CK
CK

CKEB0

K2

CKE

CSB0#

L8

CS

WEB#0

K3

WE

RASB#0

K7

RAS

CASB#0

L7

CAS

DQMB#1
DQMB#3

F3
B3

LDM
UDM

ODTB0

K9

ODT

QSB1
QSB#1

F7
E8

LDQS
LDQS

QSB3
QSB#3

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

+1.8VS

1
CV245

2 1U_0402_6.3V4Z
+1.8VS

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

BB0
BB1

RV60
4.99K_0402_1%

20

CLKB0#

CLKB0#

A3
E3
J3
N1
P9

20

CLKB0

+VRAM_REF6

CLKB0

RV64
56_0402_5%

RV65
56_0402_5%

RV62
4.99K_0402_1%

BB2

2 CV246
0.1U_0402_16V4Z

HYB18T256161BF-25

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

MDB25
MDB28
MDB24
MDB31
MDB29
MDB26
MDB30
MDB27
MDB8
MDB15
MDB9
MDB13
MDB14
MDB10
MDB11
MDB12

0.1U_0402_16V4Z
1
CV242

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

Group3

Group1

+1.8VS

CKEB0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

20

UV8

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

BB0
BB1

0.1U_0402_16V4Z

10U_0603_6.3V6M
1U_0402_6.3V4Z

QSB#[7..0]

Close to UV8

+1.8VS

MDB[31..0] 20

DQMB#[7..0]

Close to UV7

BB[2..0] 20,24

MAB[12..0]

+1.8VS

CV243

2 1U_0402_6.3V4Z

HYB18T256161BF-25

Add BA2 for 64M*16 VRAM

Add BA2 for 64M*16 VRAM

CV248
470P_0402_50V8J
A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/04/11

Issued Date

Deciphered Date

2009/04/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATICS,MB A4093
Rev
C

401621

Date:

Wednesday, April 15, 2009

Sheet
1

23

of

58

BB[2..0]

MAB[12..0] 20,23

MDB[63..32]

+1.8VS
10U_0603_6.3V6M

1
DQMB#[7..0] 20,23

QSB[7..0]

0.1U_0402_16V4Z

CV249

CV250

QSB[7..0] 20,23

1
CV251

CV252

0.1U_0402_16V4Z

CV253

CV254

0.01U_0402_16V7K

1
CV255

10U_0603_6.3V6M

1
CV256

1
CV257

10U_0603_6.3V6M

1
CV258

0.1U_0402_16V4Z

1
CV259

0.1U_0402_16V4Z

CV260

CV261

0.01U_0402_16V7K

1
CV262

1
CV263

1
CV264

10U_0603_6.3V6M
1U_0402_6.3V4Z

QSB#[7..0]

Close to UV10

+1.8VS

MDB[63..32] 20

DQMB#[7..0]

Close to UV9

BB[2..0] 20,23

MAB[12..0]

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

QSB#[7..0] 20,23

UV9

BA0
BA1

MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKB1#
CLKB1

K8
J8

CK
CK

CKEB1

K2

CKE

20

CSB1#

L8

CS

20

WEB#1

K3

WE

20

RASB#1

K7

RAS

20

CASB#1

L7

CAS

DQMB#7
DQMB#5

20

F3
B3
K9

ODTB1
QSB7
QSB#7

F7
E8

RV66
4.99K_0402_1%

B7
A8

RV68
4.99K_0402_1%

BB2

2
CV269

J1
J7

0.1U_0402_16V4Z
1
CV265

2
LDQS
LDQS

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

+VRAM_REF7

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

UV10

Group5

Group7

+1.8VS

ODT

QSB5
QSB#5

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDDL
VSSDL

+1.8VS

LDM
UDM

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

MDB46
MDB45
MDB47
MDB44
MDB41
MDB43
MDB40
MDB42
MDB62
MDB58
MDB61
MDB57
MDB63
MDB56
MDB59
MDB60

+1.8VS

BB0
BB1

L2
L3

BA0
BA1

MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKB1#
CLKB1

K8
J8

CK
CK

CKEB1

K2

CKE

CSB1#

L8

CS

WEB#1

K3

WE

RASB#1

K7

RAS

CASB#1

L7

CAS

DQMB#6
DQMB#4

F3
B3

LDM
UDM

ODTB1

K9

ODT

QSB6
QSB#6

F7
E8

LDQS
LDQS

QSB4
QSB#4

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

1
CV266

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

MDB39
MDB35
MDB32
MDB37
MDB33
MDB36
MDB34
MDB38
MDB51
MDB54
MDB48
MDB55
MDB52
MDB50
MDB53
MDB49

+1.8VS
RV67
4.99K_0402_1%
20

CLKB1#

20

CLKB1

CLKB1#
CLKB1

RV70
56_0402_5%

+VRAM_REF8

RV69
4.99K_0402_1%
RV71
56_0402_5%

BB2

0.1U_0402_16V4Z

CV270
0.1U_0402_16V4Z

HYB18T256161BF-25
@
CV271
470P_0402_50V8J

Add BA2 for 64M*16 VRAM

Add BA2 for 64M*16 VRAM

Group4

Group6

+1.8VS

0.1U_0402_16V4Z
1
CV267

2 1U_0402_6.3V4Z

20

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

L2
L3

BB0
BB1

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

+1.8VS

CV268

2 1U_0402_6.3V4Z

HYB18T256161BF-25
@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/04/11

Issued Date

Deciphered Date

2009/04/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATICS,MB A4093
Rev
C

401621

Date:

Wednesday, April 15, 2009

Sheet
1

24

of

58

STRAPS

Project

GPU

PIN

M82M-XT
D

VRAM_ID[3:0]

DVPDATA
(23,22,21,20)

M86M

Vendor Part Number#

VRAM size

Compal Part Number#

VRAM_ID 3,2,1,0

JBK00 1.0a

512M(x4)

Samsung 64Mx16 1.8V

SA00002MD00

0000

JBK00 1.0

256M(X4)

Samsung 32Mx16 1.8V

SA00002AJ10

0001

512M(x4)

Hynix 64Mx16 1.8V

JBK00 1.0

256M(X4)

Hynix 32Mx16 1.8V

JBK00 1.0

256M(X4)

JBK00 1.0a

512M(x4)

JBK00 1.1
JBK00 1.1
JBK00 1.1

10K_0402_5% @
2
1
RV72

0011

Qimonda 32Mx16 1.8V

SA00002A600

0100

Qimonda 64Mx16 1.8V

SA00002MF00

0101

512M(x8)

Samsung 32Mx16 1.8V

SA00002AJ10

0110

512M(x8)

Hynix 32Mx16 1.8V

SA00002DL00

0111

512M(x8)

Qimonda 32Mx16 1.8V

SA00002A600

1000

1G(x8)

Samsung 64Mx16 1.8V

SA00002MD00

1001

1G(x8)

Hynix 64Mx16 1.8V

1G(x8)

Qimonda 64Mx16 1.8V

1
RV74
@

+1.8VS
VRAM_ID2 16

2
10K_0402_5%

1
2
RV75 10K_0402_5%
@
D

10K_0402_5%
2
1
RV76 @

10K_0402_5%
2
1
RV77 @

+1.8VS

+1.8VS

VRAM_ID1 16

1
RV78

VRAM_ID3 16

2
10K_0402_5%

1
RV79

1010
SA00002MF00

10K_0402_5% @
2
1
RV73

+1.8VS
VRAM_ID0 16

0010
SA00002DL00

2
10K_0402_5%
@

1011

+3VS_DELAY

TX_PWRS_ENB

GPIO0

PCIE FULL TX OUTPUT SWING

10K_0402_5%2

TX_DEEMPH_EN

GPIO1

PCIE TRANSMITTER DE-EMPHASIS ENABLES

10K_0402_5%2

@
1 RV92
@
1 RV93
@
1 RV94

BIF_DEBUG_ACCESS

GPIO4

DEBUG SIGNALS MUXED OUT

BIF_GEN2_EN_A

GPIO5

10K_0402_5%2

@
1 RV95

10K_0402_5%2

PIN

STRAPS

DEBUG_ I2C_ENABLE

GPIO6

DESCRIPTION OF RECOMMENDED SETTING

PCI-E 5.0GT/s or 2.5 GT/s select


Internal use only

BIF_AUDIO_EN

VIP3

ENABLE HD AUDIO

BIF_AUDIO_EN

GPIO8

ENABLE HD AUDIO

RECOMMENDED
M8X

10K_0402_5%2

M86-M ONLY

10K_0402_5%2

M82-M ONLY

10K_0402_5%2

ROMIDCFG[3:0]

BIF_VGA_DIS
BIF_HDMI_EN

GPIO
[9,13,12,11]

SERIAL ROM TYPE OR MEMORY


APERTURE SIZE SELECT

0001

PSYNC

VGA ENABLED===0 is enable

HSYNC

HDMI ENABLE

16

GPIO_1

16

GPIO_5

16

10K_0402_5%2
10K_0402_5%1

@
2 RV101

10K_0402_5%1

2 RV102

SCS#_GPIO22 16

1 RV96 M82@
@
1 RV97
1 RV98
@
1 RV99
512@
1 RV100

10K_0402_5%2

GPIO_0

SOUT_GPIO8 16

GPIO9 = 0 (BIOS_ROM_EN = 0)

SIN_GPIO9 16

GPIO[13:11]

GPIO_11 16

0
0
0
1

GPIO_12 16
GPIO_13 16
PSYNC

16

CRT_HSYNC

16,27

0
0
1
0

MEMORY SIZE
128MB

0
1
0
0

256MB
64MB
512MB

HSYNC for HDMI video

External VGA Thermal Sensor

+3VS_DELAY

RV104@
4.7K_0402_5%

4.7K_0402_5%

0.1U_0402_16V4Z

@ RV103
CV272

+3VS

UV12

16

16

D+

D-

CV273
1
2
2200P_0402_50V7K

VDD

SCLK

D+

SDATA

D-

ALERT#

THERM#

GND

SMB_EC_CK2 6,45
SMB_EC_DA2 6,45
THM_ALERT# 16

ADM1032ARMZ REEL_MSOP8
1.1 PV Modify SA010320120 to SA010320110

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/04/11

Issued Date

Deciphered Date

2009/04/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATICS,MB A4093
Rev
C

401621

Date:

Wednesday, April 15, 2009

Sheet
1

25

of

58

+VDDCLK_IO

+1.2V_HT

R168
1
2
0_0805_5%

0.1U_0402_16V4Z
1
C452

22U_0805_6.3V6M

+3VS_CLK
R167
1
2
0_0805_5%
1

+3VS
1

C453
2

0.1U_0402_16V4Z
1

C454

C455

2
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

C456

C457

2
0.1U_0402_16V4Z

1
C444
22U_0805_6.3V6M

C445
0.1U_0402_16V4Z

C446
0.1U_0402_16V4Z

C447
0.1U_0402_16V4Z

C448
0.1U_0402_16V4Z

C449
0.1U_0402_16V4Z

C450
0.1U_0402_16V4Z

C451
1U_0402_6.3V4Z

+3VS_CLK
1

C458
0.1U_0402_16V4Z

C459
0.1U_0402_16V4Z

C460
0.1U_0402_16V4Z

C461
0.1U_0402_16V4Z

CLK_XTAL_OUT
CLK_XTAL_IN

SI2:follow AMD request modify resistor value


Y2

Routing the trace at least 10mil

GND
8,9,32,39 SMB_CK_CLK0
8,9,32,39 SMB_CK_DAT0
16
16

PA_RS7X0A1

R226
R228

27M_CLK
27M_SSC

+3VS_CLK
1
2
1
2

33_0402_5%
33_0402_5%

11 CLK_SBLINK_BCLK#
11 CLK_SBLINK_BCLK

SB LINK

+VDDCLK_IO

MiniCard_1
MiniCard_2

37 CLK_PCIE_MCARD1#
37 CLK_PCIE_MCARD1
37 CLK_PCIE_MCARD2#
37 CLK_PCIE_MCARD2

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

+3VS_CLK

2 @ 33_0402_5%
2 @ 33_0402_5%

1
1

2
+3VS_CLK MV:Add
8.2K_0402_5%
2
@ 1U_0402_6.3V4Z
1
2
R946
0_0402_5%
1
2
R945
0_0402_5%

R179
@ 8.2K_0402_5%

RS780

CLK_14M_SB 30
MV:unmount
CLK_14M_SIO 44
CLK_NBHT 11
CLK_NBHT# 11 NB

for ICS CLK

1.1V 158R/90.0R

for MP

CLK_CPU_BCLK 6
2

R186
@ 261_0402_1%

CPU
CLK_CPU_BCLK# 6

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55

SCL
SDA
VDD_DOT
SRC_7#/27M
SRC_7/27M_SS
VSS_DOT
SRC_5#
SRC_5
SRC_4#
SRC_4
VSS_SRC
VDD_SRC_IO
SRC_3#
SRC_3
SRC_2#
SRC_2
VDD_SRC
VDD_SRC_IO

VSS_SRC
SRC_1#
SRC_1
SRC_0#
SRC_0
CLKREQ_0#
ATIGCLK_2#
ATIGCLK_2
VSS_ATIG
VDD_ATIG_IO
VDD_ATIG
ATIGCLK_1#
ATIGCLK_1
ATIGCLK_0#
ATIGCLK_0
SB_SRC_1#
SB_SRC_1
VSS_SB_SRC

+3VS_CLK
+VDDCLK_IO

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

1
R174
1
C629

VSS_48
48MHz_0
48MHz_1
VDD_48
XTAL_OUT
XTAL_IN
VSS_REF
REF_0/SEL_HTT66
REF_1/SEL_SATA
REF_2/SEL_27
VDD_REF
VDD_HTT
HTT_0/66M_0
HTT_0#/66M_1
VSS_HTT
PD#
CPU_K8_0
CPU_K8_0#

U10

73

1
R240
R220

OSC_14M_NB

NB_OSC_14.318M 11
2 R380
90.9_0402_1%

22P_0402_50V8J

CLK_48M_USB 32

2
158_0402_1%

22P_0402_50V8J
2

R171/R183 (value may change)

33_0402_5%

R379

+3VS_CLK

14.31818MHZ_20P_6X1430004201
1
C465

NB_OSC_14.318M_R

CLK_XTAL_OUT
CLK_XTAL_IN

C464

SEL_SATA
27M_SEL
+3VS_CLK
+3VS_CLK

R170

CLKREQ_NCARD#
CLKREQ_MCARD2#

VDD_CPU
VDD_CPU_I/O
VSS_CPU
CLKREQ_1#
CLKREQ_2#
VDD_A
VSS_A
VSS_SATA
SRC_6/SATA
SRC_6#/SATA#
VDD_SATA
CLKREQ_3#
CLKREQ_4#
SB_SRC_SLOW#
SB_SRC_0
SB_SRC_0#
VDD_SB_SRC
VDD_SB_SRC_IO

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

CLKREQ_MCARD1#

+3VS_CLK
+VDDCLK_IO

CLKREQ_LAN

CLKREQ_NCARD#
CLKREQ_MCARD2#

CLKREQ_NCARD# 37
CLKREQ_MCARD2# 37

+3VS_CLK

CLK_SBSRC_BCLK 30
CLK_SBSRC_BCLK# 30
+3VS_CLK
1
R372

CLKREQ_MCARD1#

2
10K_0402_5%

SB SRC

1
R324
1
R325
1
R326
1
R390

2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%

+3VS_CLK

PA_RS7X0A1

CLKREQ_MCARD1# 37

+3VS_CLK

+3VS_CLK
+VDDCLK_IO
3

SLG8SP626VTR_QFN72_10x10

SI2: Use new version CLK gen

R181
8.2K_0402_5%

R180
8.2K_0402_5%

+3VS_CLK

+VDDCLK_IO

+3VS_CLK

SEL_SATA

27M_SEL

NBGFX_CLK 11
NBGFX_CLK# 11

NB GFX

CLK_PCIE_VGA 15
CLK_PCIE_VGA# 15

VGA chip(Dis)

NB CLOCK INPUT TABLE


NB CLOCKS

HT_REFCLKN
1

CLKREQ_LAN

configure as SATA output

SEL_SATA

1 *
0 * configure as normal SRC(SRC_6) output
* default

configure as 27M and 27M_SS output

27M_SEL
0
configure as SRC_7 output
* default

CLK_PCIE_MCARD0 38
CLK_PCIE_MCARD0# 38
CLKREQ_LAN 36
CLK_PCIE_LAN 36
CLK_PCIE_LAN# 36
CLK_PCIE_NCARD 37
CLK_PCIE_NCARD# 37

GLAN

configure as single-ended 66MHz output

2007/08/02

Issued Date

0*
configure as differential 100MHz output
* default

New Card

REFCLK_N

14M SE (1.8V)
NC

14M SE (1.1V)
vref

100M DIFF

100M DIFF(IN/OUT)*

GPP_REFCLK

100M DIFF

NC or 100M DIFF OUTPUT

GPPSB_REFCLK

100M DIFF

100M DIFF

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

100M DIFF
100M DIFF

GFX_REFCLK

Compal Secret Data

Security Classification
1

RS780

100M DIFF
100M DIFF

REFCLK_P

Card reader

Use voltage divider resistor R379 & R380 to pull low


NB_OSC_14.318M

RX780

HT_REFCLKP

SCHEMATICS,MB A4093
Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

26

of

58

CRT CONNECTOR
1

+5VS

+R_CRT_VCC

D35

D37

D34

+CRT_VCC
F2

D36
1

2
1

RB491D_SOT23 1A_6VDC_MINISMDC110
C475
0.1U_0402_16V4Z

+3VS
3

JP6

MV: modify bead to NBQ100505T-800Y-N

C471

1
C859
2

1
C469
2

1
C858
2

D_DDCDATA
GREEN_L
HSYNC
BLUE_L
+CRT_VCC
1
C476
2

1
C472
2

VSYNC

6P_0402_50V8K

1
75_0402_1%

1
75_0402_1%

R217

R211

R214

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

RED_L

6P_0402_50V8K

BLUE

BLUE
1
75_0402_1%

16

6P_0402_50V8K

GREEN

6P_0402_50V8K

GREEN

6P_0402_50V8K

16

L47
1
2
NBQ100505T-800Y-N_0402
L48
1
2
NBQ100505T-800Y-N_0402
L49
1
2
NBQ100505T-800Y-N_0402

RED

RED

6P_0402_50V8K

16

DAN217_SC59DAN217_SC59
@
@

DAN217_SC59
@

D_DDCCLK

RED_L

16 GND
17 GND

47

GREEN_L 47
BLUE_L 47

SUYIN_070546FR015S265ZR
CONN@

SI:change CRT Conn.

1.1 PV MODIFY

SI2:change pull high from 6.8K to 2K ohm

+3VS_DELAY

+CRT_VCC

5
1
A

Y
U14

D_DDCDATA 47

Q10B
2N7002DW-7-F_SOT363-6

D_HSYNC

SN74AHCT1G125GW_SOT353-5

1
L84

2
10_0402_5%

HSYNC

1
L83

2
10_0402_5%

VSYNC

+CRT_VCC

+3VS

RS780 DAC_SCL & SDA is 5V tolerance

Q10A
2N7002DW-7-F_SOT363-6 C857
@
470P_0402_50V8J

D_DDCCLK 47

C856
@
2 470P_0402_50V8J

16

5
1
2

CRT_VSYNC

P
OE#

D_DDCCLK

D_VSYNC

U13
SN74AHCT1G125GW_SOT353-5

M82-S DDC3 & DDC4 is 5V tolerance


16 VGA_DDC_CLK

C474

1
2
C477
0.1U_0402_16V4Z

D_HSYNC

1
C470
@

10P_0402_50V8J

D_DDCDATA

10P_0402_50V8J

1
3

16,25 CRT_HSYNC
4

16 VGA_DDC_DAT

P
OE#

R218
2K_0402_5%

R100
2K_0402_5%

1
2
C473
0.1U_0402_16V4Z

+CRT_VCC
+3VS
R238
4.7K_0402_5%
@

R237
4.7K_0402_5%
@

47

D_VSYNC 47

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATICS,MB A4093
Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

27

of

58

+LCDVDD
1

+5VALW
2

R225
470_0805_5%

R224
1M_0402_5%

3 2

+3VS

R222
1
2
100K_0402_5%

Q43
SI2301BDS-T1-E3_SOT23-3

Q144B
2N7002DW-7-F_SOT363-6

80mil

2
R276
2.2K_0402_5%

2
C863
1000P_0402_50V7K
Q144A
1
2N7002DW-7-F_SOT363-6

17 VGA_ENVDD

80mil
+LCDVDD
1

C487
4.7U_0805_10V4Z

C491
0.1U_0402_16V4Z

INVPWR_B+

IO2 GND

USB20_P5

@ PRTR5V0U2X_SOT143-4

32
32

LVDS_BCLK+
LVDS_BCLK-

17 LVDS_BCLK+
17 LVDS_BCLK-

LVDS_BCLK+
2
1
680P_0402_50V7K C870 @
LVDS_BCLK2
1
680P_0402_50V7K C871 @

USB20_P5
USB20_N5

USB20_P5
USB20_N5

17
17
17
17
17
17

SI: Add +5VS jumper

LVDS_B0+
LVDS_B0LVDS_B1+
LVDS_B1LVDS_B2+
LVDS_B2-

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GND

DMIC_DAT
DMIC_CLK

PJP7
PAD-OPEN 2x2m

VIN

GND

VOUT

BP

R891

2
3

EN

RT9193-39GB_SOT23-5

1
@ 0_0402_5%

1
@C923
@
C923
1
@C924
@
C924

2
220P_0402_50V7K
2
220P_0402_50V7K

SI2: Add 220P for EMI

+5VS

SI: Change R491 to 0805 size


INV_PWM 45
BKOFF# 45
DAC_BRIG 45

LCD_DDC_CLK 1
4.7K_0402_5% @

2
R274

LCD_DDC_DAT 1 @
4.7K_0402_5%

2
R275

2
C719
10U_0805_10V4Z
1
R892
100K_0402_1%
@

C511
0.1U_0402_16V4Z

2
2
R17

1
2
R16
0_0402_5%

2
R483

DMIC_CLK

PV: mount for EMI

@ 215K_0402_1%
U54

31 CAM_SHDN#

BKOFF#
1
@ 4.7K_0402_5%

+USB_CAM

SI:Change to Richtek parts

DMIC_DAT

+USB_CAM
LCD_DDC_CLK 16
LCD_DDC_DAT 16

LCD_DDC_CLK
LCD_DDC_DAT

+3VS

DMIC_DAT 40
DMIC_CLK 40
1
2
100_0805_5%
R491

INVT_PWM
BKOFF#
DAC_BRIG

+5VALW +5VS

C720
10U_0805_10V4Z

LVDS_A2- 17
LVDS_A2+ 17
LVDS_A1- 17
LVDS_A1+ 17
LVDS_A0- 17
LVDS_A0+ 17
LVDS_ACLK- 17
LVDS_ACLK+ 17

LVDS_ACLKLVDS_ACLK+

ACES_88242-4001
CONN@

PJP4
PAD-OPEN 2x2m

1
2
@ C868 680P_0402_50V7K
1
2
@ C869 680P_0402_50V7K

LVDS_ACLK+
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

C628
470P_0402_50V7K

LVDS_ACLK-

JP7
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41

C483
470P_0402_50V7K

IO1

VIN

USB20_N5

680P_0402_50V7K

D22
+5VALW

LVDS CONN

C482
470P_0402_50V7K

C481

INVPWR_B+
L44
2
1
FBMA-L11-201209-221LMA30T_0805
<BOM Structure>

C867
680P_0402_50V7K
2
1

680P_0402_50V7K

+3VS

C480

680P_0402_50V7K

B+
C479

C866
680P_0402_50V7K
2
1

+LCDVDD

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATICS,MB A4093
Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

28

of

58

1.1 PV MODIFY

SI2:change pull high from 6.8K to 2K ohm


+3VS_DELAY

+HDMI_5V_OUT

R176
@ 4.7K_0402_5%

HPD

U39
SN74AHCT1G125GW_SOT353-5

16

R210
2K_0402_5%

R236
2K_0402_5%

16 HDMIDAT_VGA

2 C850
0.1U_0402_16V4Z

R628
100K_0402_5%

+3VS
R209
@ 4.7K_0402_5%

HDMI_SDATA

P
OE#

+3VS

2.2K_0402_5%

1
R615

2
5
1

C851
0.1U_0402_16V4Z

HDMI_HPD
1

+HDMI_5V_OUT

Q139B
2N7002DW-7-F_SOT363-6

+3VS

16 HDMICLK_VGA

HDMI_SCLK

6
Q139A
2N7002DW-7-F_SOT363-6

C:Chg. PN to SB770020010.

MP:Update D10 to meet HDMI.


SI:Add R6161~R624 for EMI requset
D10
HDMI_CLK-

R616

HDMI_R_CK-

+5VS

0_0402_5%

+HDMI_5V_OUT

RB491D_SOT23
L85
1
4
@

1
4

HDMI_TX0-

HDMI_CLK+
HDMI_CLK-

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

HDMI_TX0+
HDMI_TX0-

C804 1
C827 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

HDMI_TX1+
HDMI_TX1-

16 HDMI_TX2+_VGA
16 HDMI_TX2-_VGA

C852 1
C853 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

HDMI_TX2+
HDMI_TX2-

R618

HDMI Connector
HDMI_R_CKHDMI_R_D0+

HDMI_R_D1HDMI_R_D1+
HDMI_R_D0-

HDMI_TX1-

R620

HDMI_R_D1HDMI_R_D0+

0_0402_5%

L87
1
4
@

HDMI_R_D2+

1
4

HDMI_R_D2-

1
R307
1
R315
1
R297
1
R173
1
R304
1
R172
1
R141
1
R139

2
2
2
2
2
2
2
2

499_0402_1%

499_0402_1%
499_0402_1%
499_0402_1%

R623

HDMI_R_D1+
+5VS

HDMI_R_D2-

4
@
4

HDMI_TX2+

HDMI_R_CKHDMI_R_CK+
HDMI_R_D0HDMI_R_D0+
HDMI_R_D1HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+

12
10
9
7
6
4
3
1

CKCK+
D0D0+
D1D1+
D2D2+

WCM-2012-900T_0805
1
2
R624
0_0402_5%

GND
GND
GND
GND
GND
GND
GND
GND
DDC/CEC_GND

2
5
8
11
20
21
22
23
17

SI:Update
CONN@HDMI footprint

HDMI_R_D2+

Compal Secret Data


2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

13
14

0_0402_5%

Security Classification

CEC
Reserved

Q136
2N7002_SOT23-3

2
G

R490
100K_0402_5%

L88
1

+5V
SDA
SCL
HP_DET

499_0402_1%

1
1

18
16
15
19

499_0402_1%
499_0402_1%

JP8

HDMI_SDATA
HDMI_SCLK
HDMI_HPD

HDMI_TX2-

+HDMI_5V_OUT

499_0402_1%

SUYIN_100042MR019S153ZL

WCM-2012-900T_0805
1
2
R621
0_0402_5%

HDMI_TX1+

0.1U_0402_16V4Z

HDMI_R_D00_0402_5%

WCM-2012-900T_0805
1
2
R619
0_0402_5%

HDMI_TX0+

C468

HDMI_R_CK+

HDMI_R_CK+
4
@

16 HDMI_TX1+_VGA
16 HDMI_TX1-_VGA

L86
1

C655 1
C675 1

16 HDMI_TX0+_VGA
16 HDMI_TX0-_VGA

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

C507 1
C508 1

WCM-2012-900T_0805
1
2
R617
0_0402_5%

HDMI_CLK+

16 HDMI_CLK+_VGA
16 HDMI_CLK-_VGA

SCHEMATICS,MB A4093
Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

29

of

58

Check AMD need pull low or not


1
R300

2 NB_RST#_R
@ 8.2K_0402_5%
U15A

10
10
10
10
10
10
10
10

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

C492
C493
C494
C495
C496
C497
C498
C499

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

R305
R306
+PCIE_VDDR
L53
1
2
+1.2V_HT
BLM18PG121SN1D_0603
1
+3VALW

C506

PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N

U22
U21
U19
V19
R20
R21
R18
R17

PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N

T25
T24

PCIE_CALRP
PCIE_CALRN

P24

PCIE_PVDD

P25

PCIE_PVSS

+SB_PCIEVDD
1

C505
1U_0402_6.3V4Z

A_RST#

Part 1 of 5

NB_RST#_R

U16

LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/GNT5#/GPIO68
BMREQ#/REQ5#/GPIO65
SERIRQ

G22
E22
H24
H23
J25
J24
H25
H22
AB8
AD7
V15

PLT_RST# 11,14,15,36,37,38,44,45

@ NC7SZ08P5X_NL_SC70-5

@ R314 20M_0402_5%
@R314
1
2
C643

Y3
OUT

NC

IN

NC

26 CLK_14M_SB

32.768KHZ_12.5P_1TJS125BJ4A421P

NB_HT_CLKP
NB_HT_CLKN

P17
M18

CPU_HT_CLKP
CPU_HT_CLKN

M23
M22

SLT_GFX_CLKP
SLT_GFX_CLKN

J19
J18

GPP_CLK0P
GPP_CLK0N

L20
L19

GPP_CLK1P
GPP_CLK1N

M19
M20

GPP_CLK2P
GPP_CLK2N

N22
P22

GPP_CLK3P
GPP_CLK3N

L18

25M_48M_66M_OSC

J21

25M_X1

R241
0_0402_5% J20

SB_32KHO

NB_DISP_CLKP
NB_DISP_CLKN

M24
M25

25M_X2

PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLK5

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28

+3VS

2
R319

A3

X1

SB_32KHO

B3

X2

H_PROCHOT#
1
10K_0402_5%
CPU_LDT_REQ#
H_PROCHOT#
H_PWRGD

F23
F24
F22
G25
G24

ALLOW_LDTSTP
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#

RTCCLK
INTRUDER_ALERT#
VBAT

PAD T15

PAD T16
PAD T17

CLK_PCI_EC
CLK_PCI_SIO

PCI_PIRQH#

R967

1 0_0402_5%

C501 1
2
@ 100_0402_5%
C503 1
2
@ 100_0402_5%

1
R303
1
R369

R308
1
R309
1
R310
1
LPC_AD0 44,45
LPC_AD1 44,45
LPC_AD2 44,45
LPC_AD3 44,45
LPC_FRAME# 44,45

CLK_PCI_EC
CLK_PCI_SIO

2 22_0402_5%
2 22_0402_5%
2@ 22_0402_5%

SIRQ

CLK_PCI_EC 34,45
CLK_PCI_SIO 34,44
CLK_PCI_SIO2 44

44,45

RTC_CLK 34

STRAP PIN
+3VL

+SB_VBAT

+SB_VBAT

218S7EALA11FG_BGA528_SB700
SBR1@

1
C509

+RTCVCC_R

W=20mils

C510
2
1U_0402_6.3V4Z

+RTCVCC

R317
120_0402_5%
1
2

+RTCBATT
D42
2

1
DAN202U_SC70

R876
3
1
2
W=20mils
1K_0402_5%

JBATT1
W=20mils

J1
@ JUMP_43X39

1
2
3
4

Compal Secret Data


2007/08/02

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.


SCHEMATICS,MB A4093

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

0.1U_0402_16V4Z

1
2
GND
GND
ACES_85205-02001
CONN@

Issued Date

2@ 100P_0402_25V8K

LPC_DRQ1# 44

R316
120_0402_5%
1
2

Security Classification

2@ 100P_0402_25V8K

ACCEL_INT 39

08/29 new add

C3
C2
B2

34
34
34
34
34
34

RTC

6,11 CPU_LDT_REQ#
6 H_PROCHOT#
6,56 H_PWRGD
6,11 LDT_STOP#
6
LDT_RST#

LPC

SB_32KHI

CPU

Close to SB

34
34
34
34

PCI_SERR# 45

18P_0402_50V8J

RTC XTAL

C652
1

PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN

K23
K22

R389
20M_0603_5%
2

SB_32KHI

2
1

18P_0402_50V8J

N25
N24

PCI INTERFACE

26 CLK_SBSRC_BCLK
26 CLK_SBSRC_BCLK#

1
33_0402_5%

CLOCK GENERATOR

2
R312

N1

AD3
AC4
AE2
AE3

PCIRST#

INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36

Close to SB
PLT_RST#

P4
P3
P1
P2
T4
T3

U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3
Y2
AA2
AB4
AA1
AB3
AB2
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
W4
V7
AC3
AD4
AB7
AE6
AB6
AD2
AE4
AD5
AC6
AE5
AD6
V5

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5/GPIO41

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
REQ3#/GPIO70
REQ4#/GPIO71
GNT0#
GNT1#
GNT2#
GNT3#/GPIO72
GNT4#/GPIO73
CLKRUN#
LOCK#

@ 0.1U_0402_16V4Z
2

C504
10U_0805_10V4Z

V23
V22
V24
V25
U25
U24
T23
T22

1 562_0402_1%
1 2.05K_0402_1%

2
2

SB700

SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

PCI CLKS

10
10
10
10
10
10
10
10

N2

PCI EXPRESS INTERFACE

NB_RST#_R

Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

30

of

58

U15B
1

SATA_RX0N
SATA_RX0P

C514
C515

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

1
1

AE10
AD10

SATA_TX1P
SATA_TX1N

AD11
AE11

SATA_RX1N
SATA_RX1P

AB12
AC12

SATA_TX2P
SATA_TX2N

AE12
AD12

SATA_RX2N
SATA_RX2P

AD13
AE13

SATA_TX3P
SATA_TX3N

AB14
AC14

SATA_RX3N
SATA_RX3P

T24 PAD
T25 PAD

AE14
AD14

SATA_TX4P
SATA_TX4N

T26 PAD
T27 PAD

AD15
AE15

SATA_RX4N
SATA_RX4P

T18 PAD
T19 PAD

AB16
AC16

SATA_TX5P
SATA_TX5N

SATA_STX_DRX_P1
SATA_STX_DRX_N1

35 SATA_RXN1_C
35 SATA_RXP1_C
C520
C521

43 SATA_TXP5
43 SATA_TXN5

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

1
1

SATA_STX_DRX_P5
SATA_STX_DRX_N5

43 SATA_RXN5_C
43 SATA_RXP5_C
C518
C519

35 SATA_TXP4
35 SATA_TXN4

SATA_STX_DRX_P4
SATA_STX_DRX_N4

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

1
1

35 SATA_RXN4_C
35 SATA_RXP4_C

T20 PAD
T23 PAD
2
R342

+3VS R343 1
46 SATA_LED#

+1.2V_HT

AE16
AD16
V12

SATA_CAL

Y12

SATA_X1

SATA_X2

AA12

SATA_X2

10K_0402_5%

W11

SATA_ACT#/GPIO67

+PLLVDD_SATA
2

PLLVDD_SATA

W12

XTLVDD_SATA

C523
1U_0402_6.3V4Z

HW MONITOR

C522
1U_0402_6.3V4Z

AA11

+3VS
L55
2
1
BLM18PG121SN1D_0603
C524
1U_0402_6.3V4Z
3

+XTLVDD_SATA
2

SATA PWR

L54
2
1
BLM18PG121SN1D_0603

C625
@ 0.1U_0402_16V4Z

IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23
IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30

AD24
AD23
AE22
AC22
AD21
AE20
AB20
AD19
AE19
AC20
AD20
AE21
AB22
AD22
AE23
AC23
2

SATA_RX5N
SATA_RX5P

SATA_CAL
1
1K_0402_1%
SATA_X1

IDE_IORDY
IDE_IRQ
IDE_A0
IDE_A1
IDE_A2
IDE_DACK#
IDE_DRQ
IDE_IOR#
IDE_IOW#
IDE_CS1#
IDE_CS3#

AA24
AA25
Y22
AB23
Y23
AB24
AD25
AC25
AC24
Y25
Y24

Part 2 of 5

ATA 66/100/133

SATA_TX0P
SATA_TX0N

AB10
AC10

35 SATA_RXN0_C
35 SATA_RXP0_C
35 SATA_TXP1
35 SATA_TXN1

SB700

AD9
AE9

SPI ROM

35 SATA_TXP0
35 SATA_TXN0

SATA_STX_DRX_P0
SATA_STX_DRX_N0

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

1
1

SERIAL ATA

C512
C513

SPI_DI/GPIO12
SPI_DO/GPIO11
SPI_CLK/GPIO47
SPI_HOLD#/GPIO31
SPI_CS1#/GPIO32

G6
D2
D1
F4
F3

LAN_RST#/GPIO13
ROM_RST#/GPIO14

U15
J1

FANOUT0/GPIO3
FANOUT1/GPIO48
FANOUT2/GPIO49

M8
M5
M7

CR_WAKE# 38

FANIN0/GPIO50
FANIN1/GPIO51
FANIN2/GPIO52

P5
P8
R8

LAN_ISOLATE# 36
GSENSOR_LED# 46
SB_INT_FLASH_SEL 44

TEMP_COMM
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63
TEMPIN3/TALERT#/GPIO64

C6
B6
A6
A5
B5

XMIT_OFF# 37
BT_COMBO_EN# 37

VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60

A4
B4
C4
D4
D5
D6
A7
B7

EC_THERM# 45

2
BT_OFF
43
CAM_SHDN# 28

1 C517

AVDD

F6

AVSS

G7

+SB_AVDD
1
1

2
C525
0.1U_0402_16V4Z

218S7EALA11FG_BGA528_SB700
SBR1@

10M_0402_5%
2

10P_0402_50V8J 2

AC_IN

45,49

+3VALW

PV:Add D41 and R562

R341
2

Y4
25MHZ_20P

2
150K_0402_5%

+3VALW

SATA_X1

1 C516

1
D41

1
R562

<BOM Structure>

PV:Reserve for EMI

10P_0402_50V8J 2

<BOM Structure>
CH751H-40PT_SOD323-2

L56
2
1
BLM18PG121SN1D_0603
C526
2.2U_0603_6.3V4Z

SATA_X2

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.


SCHEMATICS,MB A4093

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

31

of

58

+3VALW

R561
10K_0402_5%

PCIE_WAKE#

36,37 LAN_PCIE_WAKE#

U15D

36,37 MINI_PCIE_WAKE#

1
R320
1
R321
1
R322

+3VALW

2
@ 2.2K_0402_5%
2
@ 2.2K_0402_5%
2
@ 2.2K_0402_5%

45
45
45
45

SB_TEST2
SB_TEST1

GATEA20
KB_RST#
EC_SCI#
EC_SMI#

SB_TEST0
PCIE_WAKE#
H_THERMTRIP#

6,45 H_THERMTRIP#
11 NB_PWRGD
2
R327

1 EC_RSMRST#
100K_0402_5%

PV:delete R381 & R386

SI2: change from 2.2K to 100K ohm


EC_RSMRST#

45 EC_RSMRST#

40
SB_SPKR
8,9,26,39 SMB_CK_CLK0
8,9,26,39 SMB_CK_DAT0
37 SMB_CK_CLK1
37 SMB_CK_DAT1

+3VS

R328

2 2.2K_0402_5%

SMB_CK_CLK0

R329

2 2.2K_0402_5%

SMB_CK_DAT0

1
R400

+3VS

+3VALW

SMB_CK_CLK0
SMB_CK_DAT0
SMB_CK_CLK1
SMB_CK_DAT1

2
@ 4.7K_0402_5%

D3

AE18
AD18
AA19
W17
V17
W20
W21
AA18
W18
K1
K2
AA20
Y18
C1
Y19
G5

USB_RCOMP

G8

USB_FSD13P
USB_FSD13N

E6
E7

USB_FSD12P
USB_FSD12N

F7
E8

USB10_P12
USB10_N12

USB_HSD11P
USB_HSD11N

H11
J10

USB20_P11
USB20_N11

USB_HSD10P
USB_HSD10N

E11
F11

USB20_P10
USB20_N10

USB_HSD9P
USB_HSD9N

A11
B11

USB_HSD8P
USB_HSD8N

C10
D10

USB20_P8
USB20_N8

USB_HSD7P
USB_HSD7N

G11
H12

USB20_P7
USB20_N7

USB_HSD6P
USB_HSD6N

E12
E14

USB20_P6
USB20_N6

USB_HSD5P
USB_HSD5N

C12
D12

USB20_P5
USB20_N5

USB_HSD4P
USB_HSD4N

B12
A12

USB20_P4
USB20_N4

USB_HSD3P
USB_HSD3N

G12
G14

USB20_P3
USB20_N3

USB_HSD2P
USB_HSD2N

H14
H15

USB20_P2
USB20_N2

USB_HSD1P
USB_HSD1N

A13
B13

USB20_P1
USB20_N1

USB_HSD0P
USB_HSD0N

B14
A14

USB20_P0
USB20_N0

IMC_GPIO8
IMC_GPIO9
IMC_PWM0/IMC_GPIO10
SCL2/IMC_GPIO11
SDA2/IMC_GPIO12
SCL3_LV/IMC_GPIO13
SDA3_LV/IMC_GPIO14
IMC_PWM1/IMC_GPIO15
IMC_PWM2/IMC_GPO16
IMC_PWM3/IMC_GPO17

A18
B18
F21
D21
F19
E20
E21
E19
D19
E18

IMC_GPIO18
IMC_GPIO19
IMC_GPIO20
IMC_GPIO21
IMC_GPIO22
IMC_GPIO23
IMC_GPIO24
IMC_GPIO25

G20
G21
D25
D24
C25
C24
B25
C23

IMC_GPIO26
IMC_GPIO27
IMC_GPIO28
IMC_GPIO29
IMC_GPIO30
IMC_GPIO31
IMC_GPIO32
IMC_GPIO33
IMC_GPIO34
IMC_GPIO35
IMC_GPIO36
IMC_GPIO37
IMC_GPIO38
IMC_GPIO39
IMC_GPIO40
IMC_GPIO41

B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18

USB MISC

SUS_STAT#
SB_TEST2
SB_TEST1
SB_TEST0

C8

USB 1.1

SUS_STAT#

2
4.7K_0402_5%

SB700 has internal PD

RSMRST#

SATA_IS0#/GPIO10
CLK_REQ3#/SATA_IS1#/GPIO6
SMARTVOLT1/SATA_IS2#/GPIO4
CLK_REQ0#/SATA_IS3#/GPIO0
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39
CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
SPKR/GPIO2
SCL0/GPOC0#
SDA0/GPOC1#
SCL1/GPOC2#
SDA1/GPOC3#
DDC1_SCL/GPIO9
DDC1_SDA/GPIO8
LLB#/GPIO66
SMARTVOLT2/SHUTDOWN#/GPIO5
DDR3_RST#/GEVENT7#

2 2.2K_0402_5%

SMB_CK_CLK1

2 2.2K_0402_5%

SMB_CK_DAT1

HDA_BITCLK_CODEC
HDA_BITCLK_MDC
HDA_SDOUT_MDC
HDA_SDOUT_CODEC
HDA_SDIN0
HDA_SDIN1

46 HDA_SYNC_MDC
40 HDA_SYNC_CODEC
40 HDA_RST#_CODEC
46 HDA_RST#_MDC

STRAP PIN 34,45

R333
R334
R335
R336

33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%

R337
R338

33_0402_5%
33_0402_5%

R339
R340

33_0402_5%
33_0402_5%

1
1
1
1

1
1
1
1

2
2
2
2

HDA_BITCLK
HDA_SDOUT
HDA_SDIN0
HDA_SDIN1

2
2

HDA_SYNC

2
2

HDARST#

B9
B8
A8
A9
E5
F8
E4

USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GPM5#
USB_OC4#/IR_RX0/GPM4#
USB_OC3#/IR_RX1/GPM3#
USB_OC2#/GPM2#
USB_OC1#/GPM1#
USB_OC0#/GPM0#

M1
M2
J7
J8
L8
M3
L6
M4
L5

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO42
AZ_SDIN1/GPIO43
AZ_SDIN2/GPIO44
AZ_SDIN3/GPIO46
AZ_SYNC
AZ_RST#
AZ_DOCK_RST#/GPM8#

PAD T41

HDARST#

H19
H20
H21
F25

IMC_GPIO0
IMC_GPIO1
SPI_CS2#/IMC_GPIO2
IDE_RST#/F_RST#/IMC_GPO3

D22
E24
E25
D23

IMC_GPIO4
IMC_GPIO5
IMC_GPIO6
IMC_GPIO7

INTEGRATED uC

40
46
46
40
40
46

45 EC_LID_OUT#
37 EXP_CPPE#
38 CR_CPPE#
36 LAN_DSM#

INTEGRATED uC

R332

HD AUDIO

R331

USB OC

MV: reserve pull high for GPIO5

2@ 100P_0402_25V8K
1

USBCLK/14M_25M_48M_OSC

USB 2.0

1
R388

+3VS

45
SLP_S3#
45
SLP_S5#
45 PWRBTN_OUT#
6,45,56 SB_PWRGD
11 SUS_STAT#

C617 1
2
@ 100_0402_5%

1
R311

Part 4 of 5

SB700
PCI_PME#/GEVENT4#
RI#/EXTEVNT0#
SLP_S2/GPM9#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
TEST2
TEST1
TEST0
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/EXTEVNT1#
S3_STATE/GEVENT5#
SYS_RESET#/GPM7#
WAKE#/GEVENT8#
BLINK/GPM6#
SMBALERT#/THRMTRIP#/GEVENT2#
NB_PWRGD

GPIO

demo circuit LID use RI#

E1
E2
H7
F5
G1
H2
H1
K3
H5
H4
H3
Y15
W15
K4
K24
F1
J2
H6
F2
J6
W14

ACPI / WAKE UP EVENTS

CLK_48M_USB 26
USB_RCOMP 1
11.8K_0402_1%

2
R323

USB10_P12 43
USB10_N12 43

Touch Screen

USB20_P11 37
USB20_N11 37

USB-11 New Card

USB20_P10 37
USB20_N10 37

USB-10 MiniCard(TV tuner)


USB-9 Card Reader(delete)

USB20_P8 37
USB20_N8 37

USB-8 WLAN

USB20_P7 43
USB20_N7 43

USB-7 Fingerprint

USB20_P6 43
USB20_N6 43

USB-6 Bluetooth

USB20_P5 28
USB20_N5 28

USB-5 USB Camera

USB20_P4 43
USB20_N4 43

USB-4 Left side

USB20_P3 47
USB20_N3 47

USB-3 Dock

USB20_P2 43
USB20_N2 43

USB-2 Left Side

USB20_P1 43
USB20_N1 43

USB-1 Right side

USB20_P0 43
USB20_N0 43

USB-0 Right side

GPIO16 34
GPIO17 34

STRAP PIN
STRAP PIN
3

218S7EALA11FG_BGA528_SB700
SBR1@

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.


SCHEMATICS,MB A4093

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

32

of

58

U15C

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

22U_0805_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12

Y20
AA21
AA22
AE25

VDD33_18_1
VDD33_18_2
VDD33_18_3
VDD33_18_4

Part 3 of 5

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

1
R592
1
R593

L15 +1.2V_HT_R
M12
M14
N13
P12
P14
R11
R15
T16

@ 22U_0805_6.3V6M
2 @ 1U_0402_6.3V4Z
2 @ 1U_0402_6.3V4Z
2 @ 1U_0402_6.3V4Z

+PCIE_VDDR
L61
2
0_0805_5%

+1.2V_HT

C552
C553
C555
C554
C558
C557
C560

PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7

AA14
AB18
AA15
AA17
AC18
AD17
AE17

AVDD_SATA_1
AVDD_SATA_4
AVDD_SATA_2
AVDD_SATA_3
AVDD_SATA_5
AVDD_SATA_6
AVDD_SATA_7

4.7U_0805_10V6K
2@ 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
+1.2V_SATA
1
0_0805_5%
1
22U_0805_6.3V6M
2 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

SATA I/O

2
C566
C567 1
C568 1
C571 1
C572 1

L60
1
0_0603_5%

C546
C545
C548
C551
C550

1
1
2
2
1

+1.2V_HT

@ 1U_0402_6.3V4Z
@ 1U_0402_6.3V4Z
@ 0.1U_0402_16V4Z
@ 0.1U_0402_16V4Z
@ 10U_0805_10V4Z

2
2
1
1
2

T10
U10
U11
U12
V11
V14
W9
Y9
Y11
Y14
Y17
AA9
AB9
AB11
AB13
AB15
AB17
AC8
AD8
AE8

AVSS_SATA_1
AVSS_SATA_2
AVSS_SATA_3
AVSS_SATA_4
AVSS_SATA_5
AVSS_SATA_6
AVSS_SATA_7
AVSS_SATA_8
AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
AVSS_SATA_12
AVSS_SATA_13
AVSS_SATA_14
AVSS_SATA_15
AVSS_SATA_16
AVSS_SATA_17
AVSS_SATA_18
AVSS_SATA_19
AVSS_SATA_20

A15
B15
C14
D8
D9
D11
D13
D14
D15
E15
F12
F14
G9
H9
H17
J9
J11
J12
J14
J15
K10
K12
K14
K15

AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24

MV:internal CLKGEN no use,cap unmount

+3VALW

L63
2

+1.2V_HT

POWER
P18
P19
P20
P21
R22
R24
R25

1
1
1
1
1
1

+1.2V_CKVDD

L21
L22
L24
L25

2
2
2
2
2
2

SB700

3.3V_S5 I/O

1
1
1

CLKGEN I/O

CKVDD_1.2V_1
CKVDD_1.2V_2
CKVDD_1.2V_3
CKVDD_1.2V_4

CORE S5

A-LINK I/O

C543
C544
C547
C549

IDE/FLSH I/O

No IDE device unmount CAP


+3VS

10U_0805_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

U15E

2
+1.2VALW
@ 0_0805_5%
2
+1.2V_HT
0_0805_5%
2
C529
C532
1
C534
1
C538
1
C537
1
C527
1
C540
1

S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_3.3V_7

A17
A24
B17
J4
J5
L1
L2

+S5_3V

S5_1.2V_1
S5_1.2V_2

G2
G4

+S5_1.2V

1
2
R564
0_0805_5%
1
2
22U_0805_6.3V6M
C556
1U_0402_6.3V4Z 2
C559
1
1U_0402_6.3V4Z 2
C561
1
1U_0402_6.3V4Z 2
C562
1
0.1U_0402_16V4Z 2
C563
1
0.1U_0402_16V4Z 2
C564
1
0.1U_0402_16V4Z 2
C565
1

+1.2VALW
+1.2_USB

USB_PHY_1.2V_1
USB_PHY_1.2V_2

+1.2VALW
L64

A10
B10

L65

0_0603_5%

1U_0402_6.3V4Z
1U_0402_6.3V4Z

0_0603_5%

1
10U_0805_10V4Z
1U_0402_6.3V4Z 2
1U_0402_6.3V4Z 2

2
2

1
1

C569
C570

C573
C574
C575

1
1

C576
C577
C580
C581
C583
C582
C584
3

1
1
1
1
1
1
1

L66
1
0_0805_5%
2
2
2
2
2
2
2

A16
B16
C16
D16
D17
E17
F15
F17
F18
G15
G17
G18

10U_0805_10V4Z
10U_0805_10V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDTX_4
AVDDTX_5
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDRX_4
AVDDRX_5

PLL

+3VALW

USB I/O

+AVDD_USB
V5_VREF

AE7

+V5_VREF

AVDDCK_3.3V

J16

+AVDDCK_3.3V

AVDDCK_1.2V
AVDDC

1K_0402_5% 2

K17

C578
+AVDDCK_1.2V 0.1U_0402_16V4Z

E9

+AVDDC

C579
1U_0603_10V4Z
1

L67
1
0_0603_5%

2.2U_0603_6.3V4Z
0.1U_0402_16V4Z

218S7EALA11FG_BGA528_SB700

D14

1 R346

+5VS

+3VS

H18
J17
J22
K25
M16
M17
M21
P16

CH751H-40PT_SOD323-2

F9

+3VALW

C585

C586

PCIE_CK_VSS_1
PCIE_CK_VSS_2
PCIE_CK_VSS_3
PCIE_CK_VSS_4
PCIE_CK_VSS_5
PCIE_CK_VSS_6
PCIE_CK_VSS_7
PCIE_CK_VSS_8
AVSSC

GROUND

CORE S0

C528
C531
C530
C533
C536
C535
C539
C541
C542

PCI/GPIO I/O

+3VS

SB700

L9
M9
T15
U9
U16
U17
V8
W7
Y6
AA4
AB5
AB21

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50

PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
PCIE_CK_VSS_14
PCIE_CK_VSS_15
PCIE_CK_VSS_16
PCIE_CK_VSS_17
PCIE_CK_VSS_18
PCIE_CK_VSS_19
PCIE_CK_VSS_20
PCIE_CK_VSS_21

Part 5 of 5

AVSSCK

A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24

P23
R16
R19
T17
U18
U20
V18
V20
V21
W19
W22
W24
W25
L17

218S7EALA11FG_BGA528_SB700
SBR1@

SBR1@

+AVDDCK_1.2V

L68
1
0_0603_5%

2.2U_0603_6.3V4Z
0.1U_0402_16V4Z

+AVDDCK_3.3V

+1.2V_HT

C587

C588

L69
1
0_0603_5%

2.2U_0603_6.3V4Z
0.1U_0402_16V4Z

+3VS

1 C589

1 C590

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATICS,MB A4093
Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

33

of

58

REQUIRED STRAPS

NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK

PCI_CLK2

PCI_CLK3

PCI_CLK4

PCI_CLK5

LPC_CLK0

LPC_CLK1

RTC_CLK AZ_RST_CD#

BOOTFAIL
TIMER
ENABLED

USE
DEBUG
STRAPS

RESERVED

RESERVED

ENABLE PCI
MEM BOOT

CLKGEN
ENABLED

INTERNAL
RTC

EC
ENABLED

BOOTFAIL
TIMER
DISABLED

IGNORE
DEBUG
STRAPS

DISABLE PCI CLKGEN


MEM BOOT
DISABLED

DEFAULT

DEFAULT

DEFAULT

R354
10K_0402_5%
2
1

+3VALW

R353
10K_0402_5%
2
1

+3VALW

R352
10K_0402_5%
2
1

+3VALW

R351
10K_0402_5%
2
1

+3VALW

L,L = FWH ROM

R350
10K_0402_5%
2
1

+3VS

L,H = LPC ROM (Default)

DEFAULT

R349
10K_0402_5%
2
1

+3VS

H,H = Reserved

EC
DISABLED

R348
10K_0402_5%
2
1

+3VS

GP16

Internal pull up

H,L = SPI ROM

EXT. RTC
(PD on X1,
apply
32KHz to
RTC_CLK)

R347
10K_0402_5%
2
1

+3VS

DEFAULT

GP17

DEFAULT

PULL
LOW

+3VALW

+3VALW

R356
2.2K_0402_5%
2
1

PULL
HIGH

R355
2.2K_0402_5%
2
1

30
PCI_CLK2
30
PCI_CLK3
30
PCI_CLK4
30
PCI_CLK5
30,45 CLK_PCI_EC
30,44 CLK_PCI_SIO
30
RTC_CLK
32,45 HDARST#
32
GPIO17
32
GPIO16

R366
2.2K_0402_5%
2
1

R365
2.2K_0402_5%
2
1

R364
10K_0402_5%
2
1

R363
2.2K_0402_5%
2
1

R362
10K_0402_5%
2
1

R360
10K_0402_5%
2
1

R361
10K_0402_5%
2
1

R359
10K_0402_5%
2
1

R358
10K_0402_5%
2
1

R357
10K_0402_5%
2
1

SI2: mount 2.2K ohm

DEBUG STRAPS

PULL
LOW

PCI_AD24

PCI_AD23

USE IDE
PLL

USE DEFAULT
PCIE STRAPS

RESERVED

DEFAULT

DEFAULT

DEFAULT

DEFAULT

DEFAULT

USE
SHORT
RESET

BYPASS
PCI PLL

BYPASS
ACPI
BCLK

BYPASS IDE
PLL

USE EEPROM
PCIE STRAPS

R378
2.2K_0402_5%
2
1

R377
2.2K_0402_5%
2
1

PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
R373
2.2K_0402_5%
2
1

30
30
30
30
30
30

PCI_AD25

USE ACPI
BCLK

R376
2.2K_0402_5%
2
1

PCI_AD26

USE PCI
PLL

R375
2.2K_0402_5%
2
1

PCI_AD28
PULL
HIGH

PCI_AD27

USE
LONG
RESET

R374
2.2K_0402_5%
2
1

SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.


SCHEMATICS,MB A4093

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

34

of

58

HDD Connector
JP9

1
C594

1
C591

2
0.1U_0402_16V4Z

GND
A+
AGND
BB+
GND

C595
0.1U_0402_16V4Z

C593
10U_0805_10V4Z

+5VS

2
2
0.1U_0402_16V4Z

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

Pleace near HD CONN (JP23)

1
2
3
4
5
6
7

SATA_TXP0
SATA_TXN0
0.01U_0402_16V7K
SATA_RXN0
2
SATA_RXP0
2
0.01U_0402_16V7K

SATA_TXP0 31
SATA_TXN0 31

1 C592 SATA_RXN0_C
1 C596 SATA_RXP0_C

SATA_RXN0_C 31
SATA_RXP0_C 31

Near CONN side.


8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS

+5VS

SUYIN_127072FR022G210ZR_RV
CONN@

2nd HDD Connector-option


2

JP10

1
C602

1
C603

2
0.1U_0402_16V4Z

GND
A+
AGND
BB+
GND

C604
0.1U_0402_16V4Z

C601
10U_0805_10V4Z

+5VS

2
2
0.1U_0402_16V4Z

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

Pleace near HD CONN (JP23)

1
2
3
4
5
6
7

SATA_TXP1
SATA_TXN1
0.01U_0402_16V7K
SATA_RXN1
2
SATA_RXP1
2
0.01U_0402_16V7K

SATA_TXP1 31
SATA_TXN1 31

1 C605 SATA_RXN1_C
1 C606 SATA_RXP1_C

SATA_RXN1_C 31
SATA_RXP1_C 31

Near CONN side.


8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS

+5VS

SUYIN_127072FR022G210ZR_RV
CONN@
3

CD-ROM Connector
JP11

+5VS

Placea caps. near ODD CONN.

1
C615

10U_0805_10V4Z

1U_0603_10V4Z

1
C614

C613

0.1U_0402_16V4Z

C616
10U_0805_10V4Z

15
14

GND
GND

GND
A+
AGND
BB+
GND

1
2
3
4
5
6
7

DP
V5
V5
MD
GND
GND

8
9
10
11
12
13

SATA_TXP4
SATA_TXN4
0.01U_0402_16V7K
SATA_RXN4
2
SATA_RXP4
2
0.01U_0402_16V7K

SATA_TXP4 31
SATA_TXN4 31

1 C612 SATA_RXN4_C
1 C611 SATA_RXP4_C

SATA_RXN4_C 31
SATA_RXP4_C 31

Near CONN side.


+5VS

SUYIN_127382FR013G509ZR
CONN@

SI: Update ODD footprint to fix pin reverse issue

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATICS,MB A4093
Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

35

of

58

Place Close to Chip


U18
C485

10 PCIE_PTX_C_IRX_P3

C488

10 PCIE_PTX_C_IRX_N3

2
2

0.1U_0402_16V7K
PCIE_PTX_IRX_P3
1
PCIE_PTX_IRX_N3
1
0.1U_0402_16V7K

10 PCIE_ITX_C_PRX_P3

HSON

23

HSIP
HSIN

26 CLK_PCIE_LAN

26

REFCLK_P

26 CLK_PCIE_LAN#

27

REFCLK_N

20

PERSTB

+CTRL_18

+3V_LAN
R408 1

2 2.49K_0402_1%

32,37 LAN_PCIE_WAKE#
ISOLATE#

SROUT12

FB12

62

ENSR

64

RSET

19

LANWAKEB

36

ISOLATEB

LAN_X1

60

CKTAL1

LAN_X2

61

CKTAL2

R384
@ 1K_0402_1%

65

R398
2

31 LAN_ISOLATE#

25

ISOLATE#

31

3
4
6
7
9
10
12
13
21
32
38
43
49
52

EVDD12
EVDD12

22
28

VDD33
VDD33
VDD33
VDD33

16
37
46
53

VDDSR

63

AVDD33
AVDD33

2
59

AVDD12
AVDD12
AVDD12
AVDD12

8
11
14
58

IGPIO
OGPIO

50
51

EGND

15
17
18
34
35
39
40
41
42

1
LAN_LINK#
LAN_ACTIVITY#

+LAN_VDD12

LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1LAN_MDI2+
LAN_MDI2LAN_MDI3+
LAN_MDI3-

NC
NC
NC
NC
NC
NC
NC
NC
NC

4.7UH_1008HC-472EJFS-A_5%_1008
L71
1
2

+CTRL_18

C620
0.1U_0402_16V4Z

C621
0.1U_0402_16V4Z

C622
0.1U_0402_16V4Z

C623
0.1U_0402_16V4Z

+LAN_EVDD12
1

L72
0_0603_5%

C627
1

+LAN_VDD12

Close to Pin1

C632
0.1U_0402_16V4Z

C633
0.1U_0402_16V4Z
+LAN_VDD12

+LAN_EVDD12

C636
0.1U_0402_16V4Z

C637
0.1U_0402_16V4Z

C638
0.1U_0402_16V4Z

C639
0.1U_0402_16V4Z

C640
0.1U_0402_16V4Z

C641
0.1U_0402_16V4Z

+3V_LAN

L75
0_0603_5%

+3V_LAN

C635
2
+AVDD33

0.1U_0402_16V4Z
1

C634

1K_0402_1%
R401
15K_0402_5%

EXPOSE_PAD

EGND

+3V_LAN

C626
22U_0805_6.3V6M

DVDD12
DVDD12
DVDD12
DVDD12
DVDD12
DVDD12

+3VS

MDIP0
MDIN0
MDIP1
MDIN1
MDIP2
MDIN2
MDIP3
MDIN3

2
3.6K_0402_5%

0.1U_0402_16V4Z

+LAN_VDD12

LED3
LED2
LED1
LED0

1
R382

C
1
1
1
8
r
o
f
A
dm
a
0
e
0
B3

CLKREQB

54
55
56
57

LAN_DI

e
k
o
h
c
H
u
7
.
4

33

PLT_RST#

45
47
48
44

EEDO
EEDI/AUX
EESK
EECS

26 CLKREQ_LAN

11,14,15,30,37,38,44,45

+3V_LAN

Close to Pin16,37,46,53

HSOP

30

24

10 PCIE_ITX_C_PRX_N3

29

C644
0.1U_0402_16V4Z

C645
0.1U_0402_16V4Z

C646
0.1U_0402_16V4Z

C647
0.1U_0402_16V4Z

C648
0.1U_0402_16V4Z

10U_0805_10V4Z

+LAN_VDD12

+3V_LAN
L74
+AVDD33
C650

DSM#
2
0_0402_5%

1
R399

0.1U_0402_16V4Z

LAN_DSM# 32

0_0603_5%
C651

0.1U_0402_16V4Z

RTL8111C-GR_QFN64_9X9

Close to Pin2 & pin59


Y1
LAN_X1 2

1LAN_X2
25MHZ_20P

C182
27P_0402_50V8J

C181
27P_0402_50V8J
PJP6
1

+3VALW

2
PAD-OPEN 4x4m

40 mils
1

+3V_LAN

C707
1

1
45

1
R715

LANPWR

R713
@ 100K_0402_5%

2
10K_0402_5%

Q61
SI2301BDS-T1-E3_SOT23-3

0.1U_0402_16V4Z

LAN Conn.
JP12
13

Yellow LED+

1 300_0402_5%

14

Yellow LED-

RJ45_MIDI3-

RJ45_MIDI3+

PR4+

RJ45_MIDI1-

PR2-

+3V_LAN
LAN_ACTIVITY#
U19

7
8
9

LAN_MDI1LAN_MDI1+

10
11
12

24
23
22

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

21
20
19

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

18
17
16

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

15
14
13

C607 0.01U_0603_100V4Z
2
1

R393
1

75_0402_1%
2

C610 0.01U_0603_100V4Z
2
1

R394
1

75_0402_1%
2

C619 0.01U_0603_100V4Z
2
1

R396
1

RJ45_MIDI3RJ45_MIDI3+
RJ45_MIDI2RJ45_MIDI2+

RJ45_MIDI3- 47
RJ45_MIDI3+ 47

C659
0.01U_0402_16V7K
4

PV:Add ESD diode for EMI request

RJ45_MIDI2- 47
RJ45_MIDI2+ 47

C656
@68P_0402_50V8K

75_0402_1%
2

RJ45_MIDI0RJ45_MIDI0+

RJ45_MIDI1- 47
RJ45_MIDI1+ 47

D39
PSOT24C_SOT23-3
@

RJ45_MIDI0- 47
RJ45_MIDI0+ 47

PR3-

PR3+

RJ45_MIDI1+

PR2+

RJ45_MIDI0-

PR1-

RJ45_MIDI0+

PR1+

C657
@68P_0402_50V8K +3V_LAN
1 R395
2
1 300_0402_5%

11

LAN_LINK#

1
C663
0.01U_0402_16V7K

C658
1000P_1808_3KV7K

C664
0.01U_0402_16V7K

Compal Secret Data

Security Classification

Place these components


colsed to LAN chip

Issued Date

2007/08/02

Deciphered Date

2008/08/02

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

12

NS892402
C660
0.01U_0402_16V7K

C661

DETECT PIN1

RJ45_MIDI2LAN_LINK#

RJ45_MIDI1RJ45_MIDI1+

16

SHLD1
PR4-

RJ45_MIDI2+

LAN_ACTIVITY#

LAN_MDI0LAN_MDI0+

MCT1
MX1+
MX1-

75_0402_1%
RJ45_GND
2

4
5
6

LAN_MDI2LAN_MDI2+

TCT1
TD1+
TD1-

R392
1

1
2
3

LAN_MDI3LAN_MDI3+

C600 0.01U_0603_100V4Z
2
1

R391

DETCET PIN2

10

SHLD1

15

Green LED+
Green LEDFOX_JM36113-P1122-7F
CONN@
1
C662

0.1U_0402_16V4Z

LANGND
4

4.7U_0805_10V4Z

Compal Electronics, Inc.


SCHEMATICS,MB A4093
Document Number

Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

36

of

58

Mini Card---TV tuner


SI2: chagne power plan from +3VALW to +3VS_TV
+1.5VS_TV
+3VS_TV

+3VS_TV
0.01U_0402_16V7K

4.7U_0805_10V4Z

C665

2
4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C666

C667

C668

C669

C670

0.1U_0402_16V4Z
1

New Card
+1.5VS

+3VS
C679
2
1 0.1U_0402_16V4Z
2
C680

+3VALW
11,14,15,30,36,38,44,45

1 0.1U_0402_16V4Z
PLT_RST#

40,45,48,49,52,55 SUSP#
+3VALW

1.5Vin
1.5Vin

2
4

3.3Vin
3.3Vin

45,48,51 SYSON

32

12
14

17

PLT_RST#

2
R412

EXP_CPPE#

1@ 100K_0402_5%
EXP_CPPE#

Power Switch internal pull high

26 CLKREQ_MCARD1#

U21

C681
2
1 0.1U_0402_16V4Z

AUX_IN

1.5Vout
1.5Vout

11
13

+1.5VS_PEC

3.3Vout
3.3Vout

3
5

+3VS_PEC

SYSRST#

PERST#

STBY#

NC

18

CPPE#

26 CLK_PCIE_MCARD1#
26 CLK_PCIE_MCARD1

10 PCIE_PTX_C_IRX_N5
10 PCIE_PTX_C_IRX_P5

+3V_PEC

19

OC#

SHDN#

15

AUX_OUT

20

10

CONN@
JP14

SI: Exchange TV & WLAN


minicard location

10 PCIE_ITX_C_PRX_N5
10 PCIE_ITX_C_PRX_P5

PERST#

8
16

+3VS_TV

GND

CPUSB#
THERMAL_PAD
RCLKEN

21

R5538D001-TR-F_QFN20_4X4~D

USE TI TPS2231MRGPR

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

53

GND1GND2

54

+3VS_TV
+1.5VS_TV

SI2: chagne power plan from +3VALW to +3VS_TV


PLT_RST#
+3VS_TV
+1.5VS_TV

SMB_CK_CLK1
SMB_CK_DAT1

USB20_N10 32
USB20_P10 32

+1.5VS_TV
+3VS_TV

MOLEX 67910-0002 52P

+1.5VS

R406 1

2 0_1206_5%

+1.5VS_TV

+3VS

R407 1

2 0_1206_5%

+3VS_TV

Mini-Express Card---WLAN
+3VS_WLAN
0.01U_0402_16V7K

Near to Express Card slot.

32 SMB_CK_CLK1
32 SMB_CK_DAT1
+1.5VS_PEC
+1.5VS_PEC
32,36 MINI_PCIE_WAKE#
+3V_PEC

EXP_CPPE#

MINI_PCIE_WAKE#
PERST#

+3VS_PEC
26 CLKREQ_NCARD#
26 CLK_PCIE_NCARD#
26 CLK_PCIE_NCARD
10 PCIE_PTX_C_IRX_N0
10 PCIE_PTX_C_IRX_P0
10 PCIE_ITX_C_PRX_N0
10 PCIE_ITX_C_PRX_P0

EXP_CPPE#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND
GND1
GND2

SHIELD
SHIELD

C677

31 BT_COMBO_EN#

2
0.1U_0402_16V4Z

2 CH_CLK
0_0402_5%

1
R547

4.7U_0805_10V4Z
1
1

C783

R556
1

0_0402_5%
2

CH_DATA
CH_CLK
CH_CLK
26 CLKREQ_MCARD2#
26 CLK_PCIE_MCARD2#
26 CLK_PCIE_MCARD2

10 PCIE_PTX_C_IRX_N2
10 PCIE_PTX_C_IRX_P2

4.7U_0805_10V4Z
1
C684

10 PCIE_ITX_C_PRX_N2
10 PCIE_ITX_C_PRX_P2

1
C685

+1.5VS_WLAN

MINI_PCIE_WAKE#
43
43

+3V_PEC

SANTA_131851-A_LT

+3VS_WLAN

2
0.1U_0402_16V4Z

CONN@
4

+3VS_WLAN
+3VS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND1GND2

54

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

MOLEX 67910-0002 52P

L78

2 0_1206_5%

L79

2 0_1206_5%

+1.5VS

PLT_RST#
+3VAUX

2007/08/02

2008/08/02

Deciphered Date

XMIT_OFF# 31
R634 1
R635 1

WL_LED# 46

SI: Exchange TV & WLAN


minicard location

Title

Compal Electronics, Inc.


SCHEMATICS,MB A4093

Date:

+3VALW
+3VS

USB20_N8 32
USB20_P8 32

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

2 @ 0_0603_5%
0_0603_5%
2

SMB_CK_CLK1
SMB_CK_DAT1

Compal Secret Data

Security Classification

0.1U_0402_16V4Z
2

CONN@
JP26
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53

Issued Date

0.1U_0402_16V4Z

0.1U_0402_16V4Z

29
30

C781 C782

C682
2

R553
4.7K_0402_5%

+1.5VS_PEC

C683

2
0.1U_0402_16V4Z

1
C678

C787

+3VALW

4.7U_0805_10V4Z

USB20_N11
USB20_P11

+1.5VS_WLAN
0.01U_0402_16V7K

C784

32
32

C786

4.7U_0805_10V4Z

JP16

C785

+3VS_PEC

4.7U_0805_10V4Z

Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

37

of

58

SI:Per ME request change


JP21 to new one

Card Reader Connector


JP21
3

+VCC_4IN1
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7

+VCC_4IN1

SDCMD_MSBS_XDWE# 34
XDWP#_SDWP#
33
XD_ALE
35
XD_CD#
40
XD_RB#
39
XD_RE#
38
XDCE#
37
XD_CLE
36

R45
2 XDWP#_SDWP#
XD_RB#
2

XDCE#

C901
R411
100P_0402_25V8K @ 100_0402_5% @

+3VS

41
42
XD_RE#

SD-WP-SW

XDWP#_SDWP#

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-INS
MS-BS

26
17
15
19
24
22
13

MSCLK
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XDCD1#_MSCD#
SDCMD_MSBS_XDWE#

7IN1 GND
7IN1 GND

SDCLK

MSCLK

7IN1 GND
7IN1 GND

1
C892

C688

1
2 2
G
S

26 CLK_PCIE_MCARD0#
26 CLK_PCIE_MCARD0

CPPE#

10 PCIE_ITX_C_PRX_N1
10 PCIE_ITX_C_PRX_P1

2N7002_SOT23-3

31

CR_WAKE#

C693 1
C697 1

10 PCIE_PTX_C_IRX_N1
10 PCIE_PTX_C_IRX_P1
XDCD0#_SDCD#

0_0402_5%
1
2
R397

PCIE_PTX_IRX_N1
PCIE_PTX_IRX_P1

0.1U_0402_16V7K
0.1U_0402_16V7K

2
2

2
8.2K_0402_5%

XIN
XOUT

+3VS
1
2
C695 0.1U_0402_16V4Z

SI:Use build in Regulator


Chip mount R383,C689,C694

+5VS

C687

R370
470_0402_5%
2 2

C694
0.1U_0402_16V4Z

D5
HT-F196BP5_WHITE

C689
10U_0805_10V4Z

11,14,15,30,36,37,44,45

APCLKN
APCLKP

9
8

APRXN
APRXP

11
12

APTXN
APTXP

PLT_RST#

APVDD
APV18
DV33
DV33
DV33
DV18
DV18

19
20
44
18
37

MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MDIO6
MDIO7
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14

48
47
46
45
43
42
41
40
29
28
27
26
25
23
22

XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
SDCMD_MSBS_XDWE#
SDCLK_MSCLK_XDCE#
XDWP#_SDWP#
XD_CLE
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7
XD_RE#
XD_RB#
XD_ALE

TPA1P
TPBIAS_1
TREXT

34
35
36

TPA+
TPBIAS
TREXT

APREXT

38
39

TXIN
TXOUT

30

TAV33

1
2

XRSTN
XTEST

JMB380

CPPE#

13
14

SEEDAT
SEECLK

XDCD1#_MSCD#
XDCD0#_SDCD#

15
16

CR1_CD1N
CR1_CD0N

0_0603_5%

@ 0_0603_5%

C893
2

SI:Use build in Regulator


Chip unmount R387

2
0.1U_0402_16V4Z

+3VS

1
D

4.7K_0402_5% R111
1
2 XDCD1#_MSCD#

R933
0_0603_5%

17

+VCC_OUT
CR_LED#

@ Q53
CR_LED#
2
G
2N7002_SOT23-3
R113
4.7K_0402_5%
@

21

APGND

TCPS
TPB1N
TPB1P
TPA1N

24
31
32
33

GND

49

CR1_PCTLN
CR1_LEDN

C692

2
0.1U_0402_16V4Z

2
0.1U_0402_16V4Z

+1.8VS_OUT
1

C686
2

C690
0.1U_0402_16V4Z

0.1U_0402_16V4Z

SDCLK_MSCLK_XDCE#

2
22_0402_5% 2
22_0402_5% 2
22_0402_5%

D40
1
R124

2
12K_0402_1%

TPBTPB+
TPA-

SI2: Use B version chip

C899

R140

R133
56_0402_5%
2

2
3
4

@ 0.1U_0402_16V4Z

2
2

1
5

22P_0402_50V8J

1
2
3
4

R200
56_0402_5%

TPBIAS

TPBTPB+ GND
TPA- GND
TPA+

5
6

@ SUYIN_020115FR004S550ZL_4P-T
R290
56_0402_5%

R134

2
XOUT

1
C177
0.33U_0603_10V7K

2
4

1M_0402_5%

GND

@ G5250C2T1U_SOT23-5

C896
2

@ 1U_0603_10V4Z

@
150K_0402_5%
R123

Compal Secret Data

Security Classification
2007/08/02

Issued Date

reserved power circuit

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.


SCHEMATICS,MB A4093

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

C696
270P_0402_50V7K

OUT
OUT

C895

IN
EN

TPBTPB+
TPATPA+

XIN

X2
24.576MHz_16P_3XG-24576-43E1
C898

U22

XD_CD#

JP19
4.99K_0402_1%

+3VS

R199
56_0402_5%

C897

40mil

SI:Change 1394 connector


1

22P_0402_50V8J

+VCC_4IN1

XDCD0#_SDCD#

JMB380-QGAZ0A_QFN48_7X7

+VCC_OUT

XDCD1#_MSCD#

Close to Chip

220P_0402_50V7K 2

SI:Use new chip ,change to


High active control
SI:Use build in Regulator
Chip unmount U22 and relation parts

SDCLK
MSCLK
XDCE#

1
1 R457
1 R456
R455

DAN202U_SC70

4.7K_0402_5% R121
1
2XDCD0#_SDCD#

0707 modify

C691

5
10

+VCC_4IN1
R383
1

1000P_0402_50V7K
1
1

+3VS
1

3
4

1
R114

SI:Per Jmicro request change


R114 from 10K to 8.2K

+VCC_OUT

Power Circuit
U23

2 1

+1.8VS

0.1U_0402_16V4Z
1

2
2
10U_0805_10V4Z

CR_CPPE#

R410
C900
@ 100_0402_5% @ 100P_0402_25V8K

10K_0402_5%

32

R387

CONN@

R126

+1.8VS_OUT

SI2:Support D3E function

Q54
1

R413
C902
@ 100_0402_5% @ 100P_0402_25V8K

TAITW_R015-B10-LM

+3VS

XD_ALE

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

+VCC_4IN1

SDCLK
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7
SDCMD_MSBS_XDWE#
XDCD0#_SDCD#

200K_0402_5%

11
31

SI:Per Jmicro request change


R405 & R122 from 200K to 10K

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7
SD-CMD
SD-CD-SW

20
14
12
30
29
27
23
18
16
25
1

10K_0402_5%

XD_CLE

1
R405
1
@ R122
1
R127
1
R86

21
28

10K_0402_5%

7 IN 1 CONN

10K_0402_5%

XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

2
R106

SD-VCC
MS-VCC

XD-VCC

10K_0402_5%
1
10K_0402_5%
1

32
10
9
8
7
6
5
4

Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

38

of

58

ACCELEROMETER

U66
+3VS

C1031

Vdd_IO

GND

SDA / SDI / SDO

13

SDO

12

Reserved

GND

Reserved
GND

11
10

GND

INT 2

Vdd

INT 1

SMB_CK_DAT0 8,9,26,32

Pin12(internal pull high ) pull up I2C address :0011101b


pull low I2C address:0011100b

ACCEL_INT 30

CS

10U_0805_6.3V6M

C1030

0.1U_0402_16V4Z

+3VS

SCL / SPC

14

SMB_CK_CLK0 8,9,26,32

+3VS

2
R964

LIS302DLTR_LGA14_3x5

1
10K_0402_5%

I2C address:0111000Xb
+3VS
U68

SCK

INT

SDI

SDO

reserved

GND

GND

11

GND

12

10
1

reserved

1
C830

2
@ 0.1U_0402_16V4Z
+3VS

ACCEL_INT

C829

VDD

10U_0805_6.3V6M

SMB_CK_DAT0
B

CSB

C828

SMB_CK_CLK0

VDDIO
5

0.1U_0402_16V4Z

+3VS

@ BMA150_LGA12

SI: Reserve Bosch solution

Compal Secret Data

Security Classification
Issued Date

2006/08/04

Deciphered Date

2006/10/06

Title

Compal Electronics, Inc.


SCHEMATICS,MB A4093

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
C

401621

Wednesday, April 15, 2009

Sheet
1

39

of

58

CODEC POWER

0212_Change to +5VALW.
+5VALW

W=40Mil
C728

+VDDA_CODEC

U32

2
0.1U_0402_16V4Z

IN

GND

37,45,48,49,52,55 SUSP#

SHDN

OUT

BYP

G9191-475T1U_SOT23-5 1

C729

C731
1U_0603_10V4Z

C730
0.1U_0402_16V4Z

C904
0.1U_0402_16V4Z

C733
0.1U_0402_16V4Z

+VDDA_CODEC

2.2U_0805_16V4Z

C734
1U_0603_10V4Z

+3VS

+3VDD_CODEC
R885
1
2
BLM18BD601SN1D_0603
1

C732

(4.75V)
300mA
1

0.1U_0402_16V4Z

U27
DVDD_CORE*

DVDD_CORE

25

AVDD1*

38

AVDD2**

32
HDA_BITCLK_CODEC

32 HDA_BITCLK_CODEC

32 HDA_SDOUT_CODEC
R522 1

32 HDA_SDIN0

PV: add bead for EMI


28

DMIC_CLK

45

EC_BEEP

32

SB_SPKR

R537
R524

R523

2
L58
1
2
47K_0402_5%
1
2
47K_0402_5%

1
1
2
FBMA-L10-160808-301LMT_0603 R230
22_0402_5%
2
1
C913 1U_0603_10V4Z
MONO_INR
1
2
C955 0.1U_0402_16V4Z

31
43

MONO_OUT

GPIO 6

44

SPDIF OUT1 / GPIO 7

45

SPDIF OUT0

48

SI2: change to SPDIF to pin 45

VREFOUT-B

28

+VREFOUT_B 41

VREFOUT-C

29

BITCLK

SDI_CODEC

32 HDA_RST#_CODEC

SYNC

47

R584 1
R916 1

SENSEB#

C979

HDA_BITCLK_CODEC
10U_0805_10V4Z
C744 1
+VC_REFA
2

SENSE_A

13

DMIC_CLK

33

CAP2

PORTA_R

41

HP_OUTR

12

PCBEEP

PORTA_L

39

HP_OUTL

5.1K_0402_1% 2
20K_0402_1% 2
39.2K_0402_1% 2
@ 10K_0402_1% 2
0.1U_0402_16V4Z 2
HP_OUTR 41

PORTB_R

22

MIC_EXT_R

PORTB_L

21

MIC_EXT_L

C907 1

34

SENSE_B / NC

37

NC

PORTC_R

24

MIC_IN_R

18

NC

PORTC_L

23

MIC_IN_L

19

NC
PORTD_R

36

LINE_OUT_R

20

NC
PORTD_L

35

LINE_OUT_L

HP Jack & Dock

MIC_EXTR 41
MIC_EXTL 41

27

VREFFILT

PORTE_R

15

DOCK_MICR

26

AVSS1*

PORTE_L

14

DOCK_MICL

42

AVSS2**

DVSS**

MIC_IN_R 41

Internal MIC

MIC_IN_L 41
LINE_OUT_R 41,42

Internal SPKR.

LINE_OUT_L 41,42
C972
1
C973
1

1U_0603_10V6K
2

PORTF_R

17

PORTF_L

16

1
R943
1
R944

1U_0603_10V6K

2
R910

2
10K_0402_5%
2
10K_0402_5%

DOCK_MIC_R 47

DOCK MIC

DOCK_MIC_L 47

R911
3

1.21K_0402_1%

1.21K_0402_1%

C745
@ 33P_0402_50V8K

Jack MIC

1U_0603_10V4Z

+VDDA_CODEC
EXTMIC_DET# 41
JACK_DET# 41,47
INTMIC_DET# 41

HP_OUTL 41
1U_0603_10V4Z
C908 1
2

NC / OTP

R548
1
R569
1
R571
1
R570
1
1 C951

R525
@ 47_0402_5%

SPDIF_OUT 47

46

0.1U_0402_16V4Z

SPDIF_OUT

SENSEA#

40

2 5.1K_0402_1%
2 39.2K_0402_1%

SUB_ENABLE 42

RESET#

2 0.1U_0402_16V4Z
+VDDA_CODEC
SENSE_B#

30

GPIO 5

SDO

11

DVDD_IO

8
10

DMIC_DAT 28

VOL_DN/DMIC_1/GPIO 2

VREFOUT-E / GPIO 4

32 HDA_SYNC_CODEC

2 10K_0402_5%

C956

2 33_0402_5%

EAPD_CODEC 45

GPIO 3

+3VDD_CODEC

47

VOL_UP/DMIC_0/GPIO 1

EAPD/ SPDIF OUT 0 or 1 / GPIO 0

+VDDA_CODEC

+3VDD_CODEC

92HD71B7X5NLGXA1X8_QFN48_7X7

1/10*Vin
need close to Codec

SI2: Use new version Codec

C746
1
2
@ 1000P_0402_25V8J

SENSE A

SENSE B

Port

Resistor

Port

Resistor

39.2K

39.2K

20K

20K

10K

10K

C747
1
2
@ 1000P_0402_25V8J
C748
1
2
@ 1000P_0402_25V8J
C749
1
2
@ 1000P_0402_25V8J
R195 1

HP_DET#

MIC_DET

0(LOW)

0(LOW)

0(LOW)

2 0_1206_5%

NC

5.11K

R198
1
2
@ 0_0805_5%

NC
GNDA

LINEOUT

NC
0(LOW)
NC

GNDA

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Disable

OFF

ON

OFF

Disable

ON

OFF

ON

Enable

ON

OFF

OFF

Enable

Compal Electronics, Inc.


SCHEMATICS,MB A4093

Date:

EQ

ON

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

MIC

ON

41,42,47

5.11K
GND

PORT-A
<Earphone OUT>

OFF

Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

40

of

58

PV:change cap form 100uF

7
SPKR+

40

RIN+

ROUT+

17

RIN-

ROUT-

SPKR-

R703 2
1
7.5K_0402_1%
R704 2
1
7.5K_0402_1%

12

LIN+

LOUT+

SPKL+

13

LIN-

LOUT-

SPKL-

15

RBYPASS

11

LBYPASS

Keep 10 mil width

SI2:change from 0.047u to 0.1u

LVDD

C765
2

C767

NC

20

NC

18

GND

NC

10

GND

NC

1U_0603_10V4Z
1U_0603_10V4Z

THERMAL_PAD

SI2:change from 10u to 1u for


PA PA sound issue

HP_OUT_R
HP_OUT_L

2 HP_OUT_L
150U_D_6.3VM

EXTMIC_DET#
HP_DET#

40 EXTMIC_DET#

HP OUT For M/B

45,47

CIR_IN

CIR_IN
+5VL

40 +VREFOUT_B

1
C818

C766

1
C941

HP_OUTL

R907
4.7K_0402_5%

21

TPA6020A2RGWR_QFN20_5x5

40

MIC_EXTR

40

MIC_EXTL

1
2
3
4
5
6
7
8
9
10
11
12
13
14

1
2
3
4
5
6
7
8
9
10
11
12
13
14

ACES_87213-1400G

R909 0_0402_5%
1
1

0.1U_0402_16V7K

LS/D

16

0.1U_0402_16V7K
40,42 LINE_OUT_L

1
C776
1
C817

9
R701 2
1
7.5K_0402_1%
R702 2
1
7.5K_0402_1%

MIC_EXTR
MIC_EXTL

HP_OUT_R
2
150U_D_6.3VM

0.1U_0402_16V7K

1
C940

HP_OUTR

0.1U_0402_16V7K
40,42 LINE_OUT_R

1
C770
1
C775

RVDD

JP17
40

2
0_1206_5%

10U_0805_10V4Z

RS/D

19

10U_0805_10V4Z

42,45 EC_MUTE#

R594
1

14

U28
EC_MUTE#

to 150uF

+5VS

+5VAMP

SI2:change from 12.7K to 7.5K

2
CONN@

C742
1U_0603_10V4Z
R908
4.7K_0402_5%

MIC_EXTR
MIC_EXTL

+3VALW

JACK_DET# 40,47

R46
10K_0402_5%

B+

R871

5
Q20B

330K_0402_5%
2

2N7002DW-7-F_SOT363-6
+3VALW
2

PV:change cap form 100uF

R936 0_0402_5%
2
1

C854

to 150uF

SI2: Add cap & 44.2 ohm for dock

R47
10K_0402_5%

0.01U_0402_25V7K
Q21
2
2N7002_SOT23-3 G

Q20A

HP_OUTR

Q22A
2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

Q23A
@ 2N7002DW-7-F_SOT363-6
R947 0_0402_5%
2
1

SI: change 2n7002 to dual package

6DOCK_R

JP20

@ 2N7002_SOT23-3

SPKL+
SPKLSPKR+
SPKR-

GND1
GND2
ACES_88231-04001
CONN@

INTMIC_DET#
D
@ 2N7002_SOT23-3

DOCK_L

Q28
2
G

R957
@ 100K_0402_5%

DOCK_LOUT_L 47

150U_D_6.3VM

HP OUT For Docking

to 150uF

SPEAKER
JP15
1
2
3
4

5
6
1

1
2
3
4
GND1
GND2
ACES_88231-04001
CONN@

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

44.2_0603_1%
2

40

Q27
2
G

5
6

SP02000D000 S W-CONN ACES 85204-04001 4P P1.25

1
2
3
4

C763
220P_0402_50V7K

1
2
3
4

C762
220P_0402_50V7K

@ 1U_0603_10V6K
MICIN_L
1
2
MICIN_R
1
2
C971
@ 1U_0603_10V6K
2
1
+3VS
R956
@
10K_0402_5%
45 ANA_MIC_DET
D

PV:change cap form 100uF

C970

MIC_IN_L
MIC_IN_R

40
40

Q23B
@ 2N7002DW-7-F_SOT363-6

SI: change 2n7002 to dual package

C761
220P_0402_50V7K

R904
@ 4.7K_0402_5%

R555
@ 10K_0402_5%

C760
220P_0402_50V7K

1
2

C743 @ 1U_0603_10V4Z
R905
@ 4.7K_0402_5%

R607
1

R906 @ 0_0402_5%
1
1

+VDDA_CODEC

Q22B
2N7002DW-7-F_SOT363-6

HP_OUTL

+3VS

44.2_0603_1%
2
DOCK_LOUT_R 47

150U_D_6.3VM

C946

Analog MIC

R602
1

C945
HP_DET#

SCHEMATICS,MB A4093
Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

41

of

58

@
R917

SI2: Change C980,C990 from 0.056u to 0.027u


1

0_0603_5%

C980
1
2
+VDDA_CODEC 0.027u_0402_16V7K

+VREF

SI2: Change C982 from 0.039u to 5600p

C981
1
2

SI2: Change C984 from 0.039u to 0.027u


R918
1
2

+VREF

+VREF

TLV2464_TSSOP14

13

U41D
12

OUT

1U_0603_10V4Z

BASS_OUT

14

TLV2464_TSSOP14

SI2: Change C987 from 0.47u to 0.056u


C992
100P_0402_50V8J
C993
1
2

R927
1
2
30.1K_0402_1%

U41C

10

OUT

0.027u_0402_16V7K

+VREF

+VDDA_CODEC 0.027u_0402_16V7K

+VREF

0.056uF_0603_16V

C988
1

R926
1

11

C991

4
OUT

C985
R924
1
2
60.4K_0402_1%
C990
1
2

C987
1
2

U41A
3

R925
1
2
20K_0402_1%

11

40,41 LINE_OUT_L

C989
1
2
1U_0603_10V4Z

100P_0402_50V8J

40,41 LINE_OUT_R

R923
1
2
20K_0402_1%

+VDDA_CODEC

TLV2464_TSSOP14

R922
10K_0402_1%
C986
1
2
1U_0603_10V4Z

10K_0402_1%

10K_0402_1%

P
OUT

11

100P_0402_50V8J

0.027u_0402_16V7K

+VDDA_CODEC

10K_0402_1%

C984
1
2

R919
1

R920
1
2
30.1K_0402_1%

U41B

11

5600P_0402_25V7K
R921
1
2

C983
100P_0402_50V8J

5600P_0402_25V7K
C982
1
2

10K_0402_1%
TLV2464_TSSOP14

R928
10K_0402_1%
2

R929
1
2
60.4K_0402_1%

+VDDA_CODEC

SI2: Change C984 from 0.039u to 0.027u

+VREF

R930
1

4.7U_0805_10V4Z

0.1U_0402_16V7K

10K_0603_5%

R932
10K_0603_5%

1
C995
2

1
C996
2
C1021
4.7U_0805_25V6-K
1
2
D82

B+

SI: Change D82 & D83 to LLDS package

D83

1 2

RLS4148_LLDS2

1
2

RLS4148_LLDS2

2
C1023

+VDDA_CODEC

1U_0805_25V4Z

R934
1K_0402_5%

C1024
1

1U_0805_25V4Z

@
R935
0_0402_5%
+VCC_WOOF

R942

MV:change to 25V
1
C1014
0.22U_0603_25V7K

1
2
51_0402_5%
1
2
51_0402_5%

GAIN1

SHUTDOWN

VCLAMP

COSC
ROSC

21
20

PVCC
PVCC

16
9

OUTP
OUTP

14
15

OUTN
OUTN

10
11

C1010 1
R939 1

2 220P_0402_50V7K
2 120K_0402_5%

1
C1009

C1017

4.7U_0805_25V6-K

C1008

2 0_1206_5%

C1016

Need check

BSN

17

BSP

18
19

AGND
AGND

MV: Change L57 & L59 to 0ohm


L57
SUBWOOF+

PGND
PGND
PGND

JP13
SUBWOOF_L+

2
0_0603_5%
1
2
0_0603_5%
L59

SUBWOOF-

BAT54AW_SOT323-3~D

1
C1015
0.22U_0603_25V7K

2 1U_0603_10V4Z
2 2.2U_0603_10V6K

4.7U_0805_25V6-K

GAIN0

C1011
1U_0805_25V4Z
R941

1
1

1U_0805_25V4Z

C1003
C1004

23
22

VREF
BYPASS

6
12
13

SUBWOOF_L-

C1012
@

D44

SI: Change D44 to dual package

C1013
@

1000P_0402_50V7K

2 10K_0402_5%
2@ 0_0402_5%
2 0_0402_5%

INP

R931 1

1000P_0402_50V7K

R940 1
R633 1
R632 1

41,45 EC_MUTE#
40 SUB_ENABLE

INN

+VCC_WOOF

R937 1
2
0_0402_5%
@ R938 1
2
0_0402_5%

24

1U_0805_25V4Z

2
0.47U_0603_16V6K
2
0.47U_0603_16V6K

VCC

BASS_OUT 1
C1002
1
C1005

U60

1
2

1
2

3
4

GND
GND

ACES_88231-02001
CONN@

SUB wooffer
MV: Change C1012 & C1013 to unmount

HPA00304PWR_TSSOP24

MV:change to 25V

SI: Change C1012 & C1013 to 1000P to


reduce power consumption

2006/10/26

Issued Date

Compal Electronics, Inc

Compal Secret Data

Security Classification

2006/07/26

Deciphered Date

Title

SCHEMATICS,MB A4093

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

42

of

58

Left side

USB CONNECTOR 0

+5VALW

Left side
+USB_VCCA

ESATA/USB combination Connector

GND
OUT
IN
OUT
IN
OUT
EN#
OC#
THERMAL_PAD

TPS2061IDGN_MSOP8~N

W=100mils
1
+
2

32

1000P_0402_50V7K
C791

+USB_VCCA

JP27

L46
8
7
6
5
9

0.1U_0402_16V4Z
C790

4.7U_0805_10V4Z

1
2
3
4

C789
150U_D_6.3VM

+USB_VCCA
U40

C788

32

USB20_N4

USB20_P4

4
1

USB20_N4_R
USB20_P4_R

WCM-2012-900T_0805
2
D8
+5VALW

USB_EN#

USB20_N4_R

VIN

IO1

IO2 GND

USB20_P4_R

@ PRTR5V0U2X_SOT143-4

1
2
3
4

VCC
DD+
GND

5
6
7
8

GND
GND
GND
GND

WCM-2012-900T_0805
USB20_N2

32

USB20_P2

4
L51

31
31

SUYIN_020173MR004S50TZL_4P-T

1
2
3
4

USB20_N2_R
USB20_P2_R

C792 2
C793 2

B_VCC
B_DB_D+
B_GND

5
6
7
8
9
10
11

SATA_TXP5
SATA_TXN5

SATA_TXP5
SATA_TXN5

31 SATA_RXN5_C
31 SATA_RXP5_C

CONN@

JP28

32

1 0.01U_0402_16V7K SATA_RXN5
1 0.01U_0402_16V7K SATA_RXP5

GND
A+
AGND
BB+
GND

SI: change new footprint

USB

ESATA
12
13
14
15

SHIELD
SHIELD
SHIELD
SHIELD

TYCO_1759576-1
CONN@

SI: change new footprint


D11
+5VALW
SATA_TXN5

VIN

IO1

IO2 GND

SATA_TXP5

D9
4

+5VALW

@ PRTR5V0U2X_SOT143-4

USB20_N2_R3

IO1

IO2 GND

VIN

USB20_P2_R

@ PRTR5V0U2X_SOT143-4
D12

Touch screen

+5VALW
SATA_RXP5

JP18

USB Board Conn


2

1
2
3
4
5
GND1
GND2

JP47
1
2
3
4
5
6
7
8
9
10

+5VALW

45
32
32

USB_EN#
USB20_N0
USB20_P0

32
32

USB20_N1
USB20_P1

11
12

1
2
3
4
5
6
7
8
9
10

1
2
3
4
5
6
7

VIN

IO1

IO2 GND

SATA_RXN5

SI: new add for ESD

@ PRTR5V0U2X_SOT143-4

+5VS
USB10_N12 32
USB10_P12 32

ACES_88266-05001
CONN@

GND1
GND2
ACES_87213-1000G
CONN@

BT Connector

CONN@
ACES_87213-0800G
10

Finger printer
+3VS_FB

IO1

IO2 GND

USB20_P7

PAD-OPEN 2x2m
PJP10

IO1

IO2 GND

USB20_P6

+3VAUX_BT

0.1U_0402_16V4Z

JP39
1
2
3
4
5
6
GND
GND

2
C798
1U_0603_10V4Z

3
1

1
2
3
4
5
6
7
8

C802

R519

SI2301BDS_SOT23
1

100K_0402_5%

0.1U_0402_16V4Z

C799

C800

C801

VIN

VIN

USB20_N7

USB20_N6

D21

D16
+5VALW

+3VS

MV: add PJP10

32
32
46
37
37

0612 no install

Q24

USB20_N7
USB20_P7

USB20_N7
USB20_P7

USB20_P6
USB20_N6
BT_LED
CH_DATA
CH_CLK

1K_0402_5%
1K_0402_5%

2
2

@ PRTR5V0U2X_SOT143-4

2
0_0603_5%

C832

2
32
32

+5VALW

1
R581

@ R517 1
@R517
@R518
@
R518 1

0.1U_0402_16V4Z

USB_EN#

+3VAUX_BT
USB20_P6
USB20_N6

1
@ SI2301BDS_SOT23

8
7
6
5
4
3
2
1

SI2: change form


+3VALW to +3VS

+3VS

2
@ 0_0603_5%

+3VALW

1
R622
Q31

GND 8
7
6
5
4
3
2
GND 1
JP32

0.01U_0402_16V7K

ACES_85201-06051
CONN@

4.7U_0805_10V4Z

R520

@ PRTR5V0U2X_SOT143-4

31

BT_OFF

10K_0402_5%
4

PV: Change PN to SC300000K00 for ESD request


SI: change to 10K ohm to make
sure MOS can turn on
Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATICS,MB A4093
Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

43

of

58

+3VL

SI2: Change from +3VL to +3VALW and unmount this EEPROM


+3VALW

C484
0.1U_0402_16V4Z

U29

R521
@ 100K_0402_5%

U31
8
7
6
5

6,45,46,54 SMB_EC_CK1
6,45,46,54 SMB_EC_DA1

VCC
WP
SCL
SDA

A0
A1
A2
GND

1
2
3
4

45

SPI_CS#

45

SPI_CLK

SPI_CS#

1
R221
1
R227
2
R229

45 EC_SO_SPI_SI

INT_SPI_CS#
2
0_0402_5%
SPI_CLK_R
2
33_0402_5%
1 EC_SO_SPI_SI_R
0_0402_5%

VCC

HOLD

VSS

SI2: Change from +3VALW to +3VL


+3VL
C624
2

EC_SI_SPI_SO_R

2
R223

1
0_0402_5%

@ 0.1U_0402_16V4Z

EC_SI_SPI_SO 45

SST25LF080A_SO8-200mil

@ AT24C16AN-10SI-2.7_SO8

R526
@ 100K_0402_5%

SPI_CLK_R

SI2: chagne 0 ohm to 33ohm for EMI

SI2: Add 22p for EMI

INT_SPI_CS#

31 SB_INT_FLASH_SEL

@ 22_0402_5%

JP50
SPI_CS#
EC_SI_SPI_SO_R

U24

R385

C794
22P_0402_50V8J

@ 0.1U_0402_16V4Z

C803

20mils

G Vcc

+3VALW

SPI Flash (8Mb*1)

1
3
5
7

1
3
5
7

2
4
6
8

2
4
6
8

INT_FLASH_EN#
SPI_CLK_R
EC_SO_SPI_SI_R

INT_FLASH_EN#

R313 @ 100K_0402_5%
1
2

SPI_CS#

@ NC7SZ32P5X_NL_SC70-5

+3VL

@ E&T_2941-G08N-00E~D

C:Chg. PN to LTC00000200

LPC Debug Port

+3VS
JP41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

R137 1

CLK_14M_SIO 26

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ1#
PLT_RST#
2 @ 0_0402_5%

CLK_PCI_SIO2 30

SIRQ

@ ACES_85201-2005

LPC Debug Port


H31

+3VALW

30,45

SIRQ

30,45

LPC_AD3

30,45

LPC_AD1

PLT_RST#

LPC_AD3

LPC_AD2

LPC_AD1

LPC_AD0

LPC_FRAME#

10

CLK_PCI_SIO

LPC_DRQ1# 30
PLT_RST# 11,14,15,30,36,37,38,45
LPC_AD2 30,45
LPC_AD0 30,45
CLK_PCI_SIO 30,34

30,45 LPC_FRAME#

R232
22_0402_5%
@
1

@ DEBUG_PAD

2
4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

C486
22P_0402_50V8J
@

Compal Electronics, Inc.


SCHEMATICS,MB A4093

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

44

of

58

SI2: Change keyboard conn

+3VL_EC

+3VL

C809
2

+3VL_EC

R527
1
2
FBMA-L11-201209-601LMT_0805
+3VL

SI2: Change from

+5VL to +3VL

SMB_EC_DA2 R531
SMB_EC_CK2 R532

1
1

2 4.7K_0402_5%
2 4.7K_0402_5%
C810
1

+3VS

R530
2

2
@ 33_0402_5%

@ 15P_0402_50V8J

32
GATEA20
32
KB_RST#
30,44
SIRQ
30,44 LPC_FRAME#
30,44 LPC_AD3
30,44 LPC_AD2
30,44 LPC_AD1
30,44 LPC_AD0

30,34 CLK_PCI_EC
11,14,15,30,36,37,38,44
2
47K_0402_5%
32
32,34

R533 1

+3VL

R538
100K_0402_5%
2

10K to 100K

SI2: Change from


R539
100K_0402_5%

LID_SW#

0205_Add Pull down


R402 for SUSP#.

6,44,46,54
6,44,46,54
6,25
6,25

32
32
32
46
46
46

+3VL
ESB_CLK
ESB_DAT

R563
R576

1
1

2 4.7K_0402_5%
2 4.7K_0402_5%

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
ESB_CLK
ESB_DAT

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
ESB_CLK
ESB_DAT

46,47 DOCK_SLP_BTN#
36
R543
+3VL

LANPWR

46

4.7K_0402_5%

C813
15P_0402_50V8J
1
2

CRY2

1
2
3
4

LANPWR
E51_TXD

+5VL

INV_PWM
FAN_PWM

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

63
64
65
66
75
76

BATT_TEMP
BATT_OVP

AD

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

68
70
71
72

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

83
84
85
86
87
88

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

122
123

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

PS2 Interface

OSC

NC

OSC

28
4
40
49

97
98
99
109

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

119
120
126
128

27
28

DAC_BRIG 28
VCTRL 49
IREF
49
AC_SET 49

IREF

EC_MUTE# 41,42
USB_EN# 43
I2C_INT 46
MUTE_LED 47
TP_CLK 46
TP_DATA 46

TP_CLK
TP_DATA
AC_LED#

73
74
89
90
91
92
93
95
121
127

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

100
101
102
103
104
105
106
107
108

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

110
112
114
115
116
117
118

V18R

124

GPIO
SM Bus

GPI

CIR_IN

BAT_LED#
ON/OFFBTN_LED#
SYSON
VR_ON
ACIN_D

TP_LED#

41,47

2
C814

+3VS
R540
1

ACES_85201-0405N
TP_BTN#
CONN@
2
1
R554 10K_0402_5%

+5VL

FSTCHG 49
STD_ADP 49
CAPS_LED# 46
BAT_LED# 46
ON/OFFBTN_LED# 46
SYSON
37,48,51
VR_ON

2
10K_0402_5%

TP_CLK

R534
1

TP_DATA

R535
1

+5V_TP

2
10K_0402_5%
2
10K_0402_5%

56

PV: Change from

ACIN_D

1
R560
D33
2

+3VALW to +3VL

2
150K_0402_5%
1

+3VL

AC_IN

31,49

CH751H-40PT_SOD323-2
3

TP_LED# 46

SUSP#
PWRBTN_OUT#

1
2
3
4
5
6

1
2
3
4
G1
G2

for AC_LED function

EC_RSMRST# 32
EC_LID_OUT# 32
EC_ON
48,50
WL_BLUE_LED# 46
SB_PWRGD 6,32,56
BKOFF#
28

WL_BLUE_LED#
SB_PWRGD
BKOFF#

100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

+5VS_LED

2
1
R541 10K_0402_5%
EC_RSMRST#

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

JP48

EC_SI_SPI_SO 44
EC_SO_SPI_SI 44
SPI_CLK 44
SPI_CS# 44

FSTCHG

@ C213
@C213
@C609
@
C609
@C754
@
C754
@C756
@
C756
@C757
@
C757
@C758
@
C758
@C759
@
C759
@C764
@
C764
@C768
@
C768
@C769
@
C769
@C822
@
C822
@C823
@
C823
@C824
@
C824
@C825
@
C825
@C826
@
C826
@C875
@
C875
@C876
@
C876
@C877
@
C877
@C878
@
C878
@C884
@
C884
@C885
@
C885
@C886
@
C886
@C887
@
C887
@C888
@
C888
@C889
@
C889
@C890
@
C890

KB Back Light Conn

AC_LED# 54 PV:Add
DOCK_VOL_UP# 47
DOCK_VOL_DWN# 47
VGATE 56

CIR_IN

KSO17
KSO9
KSO16
KSI6
KSO14
KSO11
KSO10
KSO15
KSO6
KSO3
KSO12
KSO13
KSO2
KSO4
KSO7
KSO8
KSI3
KSO5
KSO1
KSI0
KSI4
KSI5
KSO0
KSI2
KSI1
KSI7

ACES_85201-26051

CIR_IN
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

G1
G2

KSO17
KSO16
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

2
C326

VFIX_EN 56
ENBKL 16
EAPD_CODEC 40
EC_THERM# 31
SUSP# 37,40,48,49,52,55
PWRBTN_OUT# 32
2
R231

1
0_0402_5%

1
100P_0402_50V8J

PCI_SERR# 30

remove in MP
4.7U_0805_10V4Z

SI: Mount C814 for KB926C


KB926QFC0_LQFP128_14X14

+3VL_EC

C815
15P_0402_50V8J

L80
FBM-11-160808-601-T_0603

+EC_AVCC

ACES_85205-0400

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

XCLK1
XCLK0

CRY1

1
C327

0.01U_0402_16V7K
ECAGND
1
2
BATT_TEMP 54
BATT_OVP 54
ADP_I 49
ADP_ID 54
TP_BTN# 46
ANA_MIC_DET 41

TP_BTN#

For EMI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

C812

SPI Flash ROM

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

@
R545
20M_0402_5%

INV_PWM
FAN_PWM
EC_BEEP
ACOFF

ACOFF

SPI Device Interface

NC

77
78
79
80

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

1
2
3
4

32.768KHZ_12.5PF_9H03200413

@
JP34

21
23
26
27

PWM Output

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

EC DEBUG port

E51_TXD
LANPWR

DIM_LED

Y7

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

BATT_OVP 2
100P_0402_50V8J

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

DA Output

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

6,32 H_THERMTRIP#
47
CONA#
48
VLDT_EN
46,47 ON/OFF

12
13
37
20
38

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

0.1U_0402_16V4Z

+3VALW

SYSON

R536
100K_0402_5%

EC_SCI#
HDARST#

CLK_PCI_EC
PLT_RST#
ECRST#
EC_SCI#

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

C811

PLT_RST#

GATEA20
1
KB_RST#
2
SIRQ
3
LPC_LFRAME# 4
LPC_AD3
5
LPC_AD2
7
LPC_AD1
8
LPC_AD0
10

GND
GND
GND
GND
GND

2 4.7K_0402_5%
2 4.7K_0402_5%

11
24
35
94
113

1
1

VCC
VCC
VCC
VCC
VCC
VCC

U33
SMB_EC_DA1 R528
SMB_EC_CK1 R529

CONN@
JP33

+EC_AVCC

67

2
2
1000P_0402_50V7K

SUSP#

KBD CONN

C808

AVCC

2
2
0.1U_0402_16V4Z

C807

AGND

C806

PV: change to BEAD for EMI request

69

C805

1000P_0402_50V7K

ECAGND

0.1U_0402_16V4Z
1

9
22
33
96
111
125

0.1U_0402_16V4Z
1
1

1
C816

2
0.1U_0402_16V4Z

L81
1
2
FBM-11-160808-601-T_0603

PV: change to BEAD for EMI request

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.


SCHEMATICS,MB A4093

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

45

of

58

CAPS LOCK LED

MDC 1.5 Conn.

+5VS_LED

WHITE
D30
1

45 CAPS_LED#

Change type 4/25

R552
1

2
HT-F196BP5_WHITE

JP25

1 R495
2
33_0402_5%

HDA_SYNC_MDC
HDA_SDIN1_MDC

MV: Modify R552 change to 750ohm

+3VS

BAT_LED#

1
R559

2
470_0402_5%

+3VS

6
2

Q138A
2N7002DW-7-F_SOT363-6
2

DIM LED

1
C845
0.1U_0402_16V4Z

GND

VIN

PV: change from MOS to Diode

C795
1U_0402_6.3V4Z

BP

VOUT

C185 @
1
R248

U55 @

Q51
2N7002_SOT23-3

2
G

DIM_LED

0.33U_0603_10V7K

2
0_0603_5%
@

D15

EN

45

1
2
R578 10K_0402_5%

CH751H-40PT_SOD323-2

+3VL_LDO

SI: Change to +3VL to support Qplay


bottom boot in BATT mode

@
1
R247

+3VL

T/P Board (Inculde T/P_ON/OFF)

2
0_0603_5%

SWITCH BOARD.

+3VL_LDO
+5VS_LED

PV: Change PN to SCA00000G00 for ESD request

2
D31

PSOT24C_SOT23-3

2
0_0603_5%

PV: Add for EMI


+5V_TP

@ SI2301BDS-T1-E3_SOT23-3
D

45
45
45

ESB_CLK
ESB_DAT
I2C_INT

R603 1
R604 1

R610 1
R611 1

Q85

JP36

SI: Add +5VALW_LED to support


PWR LED S3 flash function

1
2
3
4
5
6
7
8
9
10
11
12

GND
GND

13
14

MV:R705 change to 1.8Kohm


ACES_85201-1205N
CONN@

D38
PSOT24C_SOT23-3
@

@
C821
100P_0402_50V8J

TP_CLK 45
TP_DATA 45
TP_BTN# 45
TP_LED# 45

PV: change to 12pin


2

TP_CLK
TP_DATA
TP_BTN#
TP_LED#

ON/OFF
ON/OFFBTN_LED#
33P_0402_50V8K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.047U_0402_16V7K

2
2
2
2
2
2
2
2

1
1
1
1
1
1
1
1

C947 CAP_CLK
@ C192 +3VL_LDO
@ C191 +5VS_LED
@ C186 ON/OFFBTN_LED#
@ C187 I2C_INT
@ C188 R_PWR_LED
@ C189 LID_SW#
@ C190 ON/OFF

SI2: Add diode for EMI

CONN@

MV: Add cap for ENE board EMI

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.


SCHEMATICS,MB A4093

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

1
+5VS_LED
2
ON/OFFBTN_LED# 3
45 ON/OFFBTN_LED#
CAP_CLK
4
2 FBMA-11-100505-301T_0402
CAP_DAT
5
2 FBMA-11-100505-301T_0402
I2C_INT
6
R_PWR_LED
7
1
2
+5VALW_LED
R705
1.8K_0402_5% LID_SW#
8
45
LID_SW#
ON/OFF
9
45,47 ON/OFF
R605 1
0_0402_5% 10
2
6,44,45,54 SMB_EC_CK1
R606 1
0_0402_5% 11
2
6,44,45,54 SMB_EC_DA1
12

47,48,53 SYSON#

+5VS_LED

@
C820
ACES_85201-08051 100P_0402_50V8J

2 0_0402_5%
2 0_0402_5%

JP37

1
R235

+5VALW

1 @
C819
0.1U_0402_16V4Z

C502 4.7U_0805_10V4Z

MV: Add cap for ENE board EMI

D32
PSOT24C_SOT23-3
@

+5V_TP

SI2: add 4.7u for


Cypress cap board

PV: change from Q85 to R235

TP_BTN#
TP_LED#
3

TP_DATA
TP_CLK

PV: Add LDO for ENE cap board


APL5151-33BC-TRL_SOT23-5

1
2
3
4
5
6
7
8
9
10

+5VS
C836
0.1U_0402_16V4Z

+5VL

1
2
3
4
5
6
7
8
GND
GND

1
1

R587
10K_0402_5%

+5VS_LED

Q58

SI2301BDS-T1-E3_SOT23-3

+5VALW

+5VALW_LED

Q32

SI2301BDS-T1-E3_SOT23-3

SATA_LED#

2
820_0402_5%

MV: Modify R551& R559 to 470 ohm

1
R551

4
Amber
LED1

Q55
2N7002_SOT23-3

+5VS_LED

Q138B 31 GSENSOR_LED#
2N7002DW-7-F_SOT363-6

R505
100K_0402_5%

470_0402_5%

QSMF-C16E_AMBER-WHITE
White

31

+5VALW_LED
R550
1

2
HT-F196BP5_WHITE

HDD LED(Left 3)

WL_BLUE_LED# 45

WL_LED#

WHITE
45

10K_0402_5%
R577

37

470_0402_5%

D28

Connector for MDC Rev1.5


C780
@4.7U_0805_10V4Z CONN@

+3VS

2
G

Battery Charge LED(Left 2)

PJP8
PAD-OPEN 2x2m

BT_LED

R549
1

HT-F196BP5_WHITE

R631
10K_0402_5%

43

HDA_BITCLK_MDC 32
2
1
1
2
R496
C777
@ 10_0402_5%
@ 10P_0402_25V8K

+5VS

D27

ON/OFFBTN_LED#

GND
GND
GND
GND
GND
GND
1

+5VALW_LED

WHITE

POWER LED(Left 1)

+3VS

ACES_88018-124G

13
14
15
16
17
18

C779

0.1U_0402_16V4Z

C778

1000P_0402_50V7K

+3VS

2
4
6
8
10
12

GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK

32 HDA_SYNC_MDC
32 HDA_SDIN1
32 HDA_RST#_MDC

1
3
5
7
9
11

HDA_SDOUT_MDC

32 HDA_SDOUT_MDC

750_0402_5%

Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

46

of

58

Atlas/ Saturn Dock


+DOCKVIN

JP38
43
44

1
R586
1
R585

+5VS
+3VALW

<BOM Structure>
2
1K_0402_5%
2
1K_0402_5%

DAN202U_SC70
2
R588
10K_0402_5%

32
36
36
36
36
36
36
36
36

46,48,53 SYSON#

DOCK_PWR_ON

Q145A
2N7002DW-7-F_SOT363-6

27
GREEN_L
27
RED_L
27 D_DDCDATA
27
BLUE_L
27 D_HSYNC
27 D_DDCCLK
32 USB20_N3
27 D_VSYNC

D43
2

DOCK_PWR_ON Spec
0V = Notebook S4/S5, Dock off
2.5V = Notebook S3, Dock on
4V = Notebook S0, Dock on

D_DDCDATA
D_HSYNC
D_DDCCLK
USB20_N3
D_VSYNC
USB20_P3
RJ45_MIDI3+
RJ45_MIDI3RJ45_MIDI2+
RJ45_MIDI2RJ45_MIDI1+
RJ45_MIDI1RJ45_MIDI0+
RJ45_MIDI0+V_BATTERY

USB20_P3
RJ45_MIDI3+
RJ45_MIDI3RJ45_MIDI2+
RJ45_MIDI2RJ45_MIDI1+
RJ45_MIDI1RJ45_MIDI0+
RJ45_MIDI0PJP5
B+

1
@

+3VS

43
44

40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

41
42

41
42

SHIELD
SHIELD

45
46

DOCK_VOL_UP#
2
R589
DOCK_VOL_DWN# 2
R590

CIR_IN
DOCK_PWR_ON
MUTELED
DOCK_SLP_BTN#
R_VOL_UP#
R_VOL_DWN#
SPDIFO_L
AUDIO_OGND
DOCK_LOUT_R
DOCK_LOUT_L
DOCK_MIC_R_C
DOCK_MIC_L_C
AUDIO_IGND
DOCK_PRESENT

CIR_IN

1
10K_0402_5%
1
10K_0402_5%

41,45

R591

R567 1
R568 1

MUTE_LED 45
DOCK_SLP_BTN# 45,46
JACK_DET# 40,41
DOCK_VOL_UP# 45
DOCK_VOL_DWN# 45

1K_0402_5%

2 200_0402_5%
2 200_0402_5%

DOCK_VOL_UP#
DOCK_VOL_DWN#

DOCK_LOUT_R 41
DOCK_LOUT_L 41

2
PAD-OPEN 2x2m

FOX_QL1122L-H212AR-7F
CONN@

need change to reverse type connector


+1.5VS

+3VL

R574
@ 33_0402_5%

R565
10K_0402_5%

SPDIFO_L

5
DOCK_LOUT_R
DOCK_LOUT_L
1

0720 Add dock_present_gnd

C943

C942

MIC_Dock

Need 600 Ohm 500 mA

R575
1

2
0_0402_5%

R_VOL_UP#

1
1

1
2
0.1U_0402_16V7K
C894
R573
110_0402_5%

1
R647

2
150_0402_5%

SPDIF_OUT 40

R_VOL_DWN#

2
B
E

220P_0402_50V7K

R566
2K_0402_1%

220P_0402_50V7K

2 22_0402_5%

DOCK_PRESENT

R572

45

Q145B
2N7002DW-7-F_SOT363-6

C944
220P_0402_50V7K

CONA#

C
Q7
@ MMBT3904_NL_SOT23-3

SI2:chang R572 to 22 ohm & R566 to


2K to fix dock usb issue

1 1

1
C843
1000P_0402_50V7K

C844
1000P_0402_50V7K
3

L94
FBM-11-160808-601-T_0603
DOCK_MIC_R_C
1
2

40 DOCK_MIC_R

DOCK_MIC_L_C

1
2
L93
FBM-11-160808-601-T_0603

40 DOCK_MIC_L

1
C922

C921
220P_0402_50V7K 2

2 220P_0402_50V7K

+3VS

SENSE_B# 40

1
1

Q18
4

MMBT3904_NL_SOT23-3

R912 MMBT3904_NL_SOT23-3
C
10K_0402_5%
DOCK_MIC_L_C 1
Q16
2
2
B
E
2
R913
C978
47K_0402_5%

Q100
2N7002_SOT23-3

2
G

2
B

1
1

R915

R914
10K_0402_5%

10K_0402_5%

1U_0603_10V6K

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATICS,MB A4093
Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

47

of

58

C834

H15
H_3P0

Q17
SUSP
2
2N7002_SOT23-3
G

H16
H_3P0

H18
H_3P0

H19
H_3P0

H20
H_3P7

H14
H_3P0
@
1

H13
H_3P0

@
1

H12
H_3P0

H11
H_3P0

@
1

H10
H_3P0

H26
H_3P7

@
1

B+

H9
H_3P0

H8
H_3P0

1U_0402_6.3V4Z
SI4800BDY_SO8 RUNON
2 R152
1
750K_0402_1%
1
1
D
C840

H7
H_3P0

H6
H_3P0

H21
4P0

H22
4P0

H23
4P0

H24
4P0
@
1

RUNON

S
S
S
G

H5
H_3P0

1
4.7U_0805_10V4Z

C838

C864

4.7U_0805_10V4Z

4.7U_0805_10V4Z

SI4800BDY_SO8
1

D
D
D
D

1U_0402_6.3V4Z

C839
1
2
3
4

8
7
6
5

H4
3P0N
@

C835

Q14

1
2
3
4

0.01U_0402_25V7K

S
S
S
G

+3VS

H3
H_3P4N
@

C833

D
D
D
D

Q35
8
7
6
5

H2
H_7P0X5P0N

@
1

+3VALW

4.7U_0805_10V4Z
1

H1
H_4P5X3P0N

+3VALW TO +3VS

+5VS

+5VALW

+5VALW TO +5VS

+1.8V TO +1.8VS
H27
H_4P0

+1.2V_HT

H25
H_3P0

Q11
IRF8113PBF_SO8

Q13
SUSP
2
2N7002_SOT23-3
G

C849

1U_0402_6.3V4Z

C847
2

R808
10M_0402_5%

2 R233
1
330K_0402_5%

B+
+5VL

+5VL

D
2

C837

Q12 VLDT_EN#
2
G 2N7002_SOT23-3

B+

4.7U_0805_10V4Z

R595

R596

100K_0402_5%

SI2: Add this resistor to meet MOS voltage

SYSON#

46,47,53 SYSON#

100K_0402_5%
2

1
1

R809
10M_0402_5%

R138 2
1
750K_0402_1%

CF4
1

0.01U_0402_25V7K

1.8VS_ENABLE

4.7U_0805_10V4Z

4
C842

C862

CF3
1

1U_0402_6.3V4Z

CF2
1

1
2
3

C846

8
7
6
5

CF1
1

C841
10U_0805_10V4Z

C848

0.01U_0402_25V7K

1
1
2
3

4.7U_0805_10V4Z

8
7
6
5

Q4
IRF8113PBF_SO8
2

H33
H_4P0

@
1

+1.2VALW

+1.8VS

+1.2VALW TO +1.2V_HT
+1.8V

SUSP

SUSP

53

SI2: Add this resistor to meet MOS voltage


Q142B
2N7002DW-7-F_SOT363-6
5

Q142A
2N7002DW-7-F_SOT363-6
2
SUSP#

37,40,45,49,52,55

37,45,51 SYSON

Discharge circuit
+1.8VS

+5VS

+1.2V_HT

+1.8V

+1.2VALW
2

D
Q41
EC_ON#
2N7002_SOT23-3

2
G

Q42
2N7002_SOT23-3
@

+5VL
1

2
G

+5VL
1

1
Q37
SYSON#
2N7002_SOT23-3

VLDT_EN# 2
G

R368
470_0805_5%
@

Q48
2N7002_SOT23-3

1
D

2
G

R284
470_0805_5%

SUSP

Q46
2N7002_SOT23-3

2
G
3

SUSP

R280
470_0805_5%

R279
470_0805_5%

R239
470_0805_5%

+1.1VS

R293
470_0805_5%

R294
470_0805_5%
45

3
Q143B
2N7002DW-7-F_SOT363-6
5
EC_ON

1
Q50
2N7002_SOT23-3

2
G
S

SUSP

Q52
2N7002_SOT23-3

2
G
S

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.


SCHEMATICS,MB A4093

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

45,50

1
SUSP

Q49
2N7002_SOT23-3

2
G
3

SYSON#

D
1

Q47
2N7002_SOT23-3
S

Q143A
2N7002DW-7-F_SOT363-6
VLDT_EN 2

VLDT_EN

1
1

2
G
3

SUSP

EC_ON#
6

R292
470_0805_5%

R288
470_0805_5%

VLDT_EN#

+1.5VS

R598
100K_0402_5%
2

R597
100K_0402_5%
+0.9V

+3VS

Rev
C

401621
Sheet

Wednesday, April 15, 2009


E

48

of

58

+3VALW

+3VL

PQ3
TP0610K-T1-E3_SOT23-3

PR9
100K_0402_5%

AC_LED#46

BATT
1

499K_0402_1% 340K_0402_1%
PR4 1
PR1 1
2
2

105K_0402_1%
PR6 1
2

1
2

PC3
820P_0402_25V7

0.01U_0402_25V7K
PC6

PC5
820P_0402_25V7
2
1

PC4
1000P_0402_50V7K
2
1

1
2

PC2
2
1

@ PJSOT24C_SOT23-3

1000P_0402_50V7K

PJP1

PD1

8
3

0
-

PU1A
LM358ADT_SO8

PR5
10K_0402_5%
2
1

PL2
SMB3025500YA_2P
2
1

BATT_OVP 41

ADPIN

VIN

PL1
SMB3025500YA_2P
1
2

+DOCKVIN

1
2
PR3
10K_0402_5%

PC13
820P_0402_25V7

0.01U_0402_50V7K

5
4
3
2
1

RLZ3.6B_LL34

2
ADP_SIGNAL

5
4
3
2
1

PD4

PR2
10K_0402_5%

ACES_88334-057N

2 1

PC12
PR8
2K_0402_5%

+5VALW
0.01U_0402_16V7K
PC1

ADP_ID 41

VMB
PJP2

BATT

PL3
SMB3025500YA_2P
2

PD2
@ SM05_SOT23

PH1 under CPU botten side :


CPU thermal protection at 90 +-3 degree C

EC_SMD
EC_SMC

1
2

PC8
1000P_0402_50V7K

PC9
0.01U_0402_25V7K

1
2
3
4
5
6
7
8
GND
GND

1
2
3
4
5
6
7
8
9
10

PR7
604K_0402_1%
1
2

+5VS

@ SUYIN_200275MR008GXOLZR

CPU

PD3
@ SM24.TC_SOT23-3

PH1
10K_TH11-3H103FT_0603_1%

PQ1
@SSM3K7002FU_SC70-3

2
G

PR11
150K_0402_1%
PR12
2.4K_0402_1%

PC11
1000P_0402_50V7K

PR15
150K_0402_1%

EN0

PC10
0.22U_0603_10V7K

1
1

+3VL

PR16
6.49K_0402_1%
1
2

+5VALW

ENTRIP1 47
D

SMB_EC_CK1 6,40,41

BAT_ID 46

PU1B
LM358ADT_SO8

PR10
200K_0402_1%
1
2

SMB_EC_CK1

SMB_EC_DA1 6,40,41

2
2

SMB_EC_DA1

PR14
100_0402_5%

PR13
100_0402_5%

PR17
1K_0402_5%

PQ2
SSM3K7002FU_SC70-3

2
G
BATT_TEMP 41

6,47

Compal Secret Data

Security Classification
Issued Date

2007/05/29

Deciphered Date

2008/05/29

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATICS,MB A4093
Document Number

Rev
C

401621
Sheet

Wednesday, April 15, 2009


D

49

of

58

P4

B+

BATT
VIN

P2
PQ102
SI4835BDY-T1-E3 1P SO8
PQ103
AO4407_SO8

4
BST_CHG

HIDRV

26

DH_CHG

VREF

11

VDAC

PH

25

LX_CHG

12

VADJ

REGN

24

REGN

LODRV

23

DL_CHG

1
1
3

PC111
0.1U_0402_10V7K
1
2
4

PD102
2

PL102
10U_LF919AS-100M-P3_4.5A_20%
1
2

EXTPWR

PQ110
AO4468_SO8

22

21

20

19

18

17

3
2
1

PC119

BATT

PR112
0.015_1206_1%
1
2

PC118
0.1U_0402_10V7K

1U_0603_10V6K
PR117
100K_0402_5%
1
2

BQ24740VREF
1

IADAPT

16

DPMDET

CELLS

SRP

SRN

BAT

IADAPT

47K_0402_5%
PR119
1

D
PQ111
SSM3K7002FU_SC70-3

BATT

2
G

BAT_ID

45

PC120
0.22U_0603_10V7K
2
1

ADP_I

PC121
100P_0402_50V8J
2
1

PR118
10K_0402_5%
1
2

Charge Detector
41

15

PR116
39K_0402_5%

PGND
SRSET

ISYNSET

14
PR115
100K_0402_1%

PQ106
DTC115EUA_SC70-3

13

41

PQ108
AO4466_SO8

3
2
1

10

ACOFF

PC116
4.7U_0805_25V6-K

27

28

BTST

PVCC

AGND

PC115
4.7U_0805_25V6-K
2
1

IADSLP

RLS4148_LL34-2

PC117
1U_0603_10V6K

1
2

PC105
4.7U_0805_25V6-K

1
2

PC110
1U_0805_25V6K
1
2

PU101
BQ24740RHDR_QFN28_5X5

2
5
6
7
8

29

PC114
4.7U_0805_25V6-K

VCTRL

PC104
4.7U_0805_25V6-K

1
2
1
CHGEN

2
ACN

4
LPMD

ACDET

7
LPREF

TP

41

CHG_B+
PR108
10_1206_5%
1
2

PC113
4.7U_0805_25V6-K
2
1

PD101
RLS4148_LL34-2

PR105
10K_0402_5%

+3VL

VADJ

PR113
143K_0402_1%

PR114
@ 0_0402_5%
1
2

VIN

5
6
7
8

PQ109
SSM3K7002FU_SC70-3

PR103
47K_0402_5%
1
2

ACOFF#

2
G

CHG_B+

PC103
4.7U_0805_25V6-K

1
2

1
2

PC109
@ 0.1U_0603_25V7K

BQ24740VREF

PC112
1
2

ACOFF#

PR111
3K_0402_1%
1
2

8
7
6
5

CHGEN#

ACSET

SUSP#

1U_0603_6.3V6M
PACIN

100K_0402_5%

PR110
0_0402_5%
1
2

PACIN_1

PR140

SSM3K7002FU_SC70-3

1
2
3

PL101
HCB2012KF-121T50_0805
2

PC107
@ 0.01U_0402_16V7K

PR109
33,36,41,44,49
150K_0402_5%

PQ107

PC102
1U_0603_6.3V6M

PC108
0.1U_0603_25V7K

AC_SET

2
1
PR106
200K_0402_5%

PC106
0.1U_0603_16V7K
2
1

1
S

PQ105
DTC115EUA_SC70-3

2
G

1
ACDET

PR104
0_0402_5%
1
2 ACSET
1

4
3

DTA144EUA_SC70-3
PQ104

2
1

PR107
47K_0402_1%
1
2

PR102
0.012_2512_1%
1
2

8
7
6
5

41

PC101
47P_0402_50V8J

PR101
47K_0402_5%
1
2

1
2
3

1
2
3

8
7
6
5

ACP

PQ101
SI4835BDY-T1-E3 1P SO8

1
2

PC122
0.1U_0603_25V7K

1
2

PC124
0.1U_0603_25V7K

41

PR122
1M_0402_5%
1
2

@
3

VIN_1

IREF

PR121
200K_0402_1%
2

PR123
1M_0402_5%
1
2

PR120
2
1
133K_0402_1%

PC123
0.1U_0402_10V7K

PD104
RLS4148_LL34-2

VIN

+3VL

PR124
1K_0402_5%
1
2

VIN

VIN

PU102A
LM393DG_SO8

PACIN

PACIN

LM393DG_SO8

8
P

PU102B

PR134
10K_0402_5%

PD103
RLZ4.3B_LL34

S
FSTCHG#
1
2
G

FSTCHG

STD_ADP 41

PR136
60.4K_0402_1%
1
2

VIN_1

PQ113
SSM3K7002FU_SC70-3
3

41

1.24VREF

PR133
10K_0603_0.1%

28,41,47

PQ112
SSM3K7002FU_SC70-3

2
D

2
G

PR135
10K_0603_0.1%

1
-

PC126
0.047U_0402_16V7K

AC_IN

PR127
10K_0402_1%

CHGEN#

PR130
2.15K_0402_1%
1
2

PR132
100K_0402_5%
2
1

PC125
0.1U_0603_25V7K

+3VL

PR131
133K_0402_1%

PR129
10K_0402_1%
2
1

VIN

PR126
133K_0402_1%

PR128
10K_0402_5%
2
1

PR125
47_1206_5%

+3VL

S
PU103
4

ACDET

22P_0402_50V8J
2

100K_0402_1%
PR138

PC127
PR137
20K_0402_1%

REF

NC

NC

1.24VREF

ANODE

LMV431ACM5X_SOT23-5

Compal Secret Data

Security Classification
Issued Date

2007/05/29

Deciphered Date

2008/05/29

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

CATHODE

Compal Electronics, Inc.


SCHEMATICS,MB A4093
Document Number

Rev
C

401621
Wednesday, April 15, 2009
D

Sheet

50

of

58

20

LX_5V

12

DRVL2

DRVL1

19

LG_5V

B++

D
PQ305
SSM3K7002FU_SC70-3

2
G

2VREF_51125

D
PQ306
SSM3K7002FU_SC70-3

2
G
3

1
2

PR317
0_0402_5%

PC311
10U_0805_10V6K

ENTRIP2

5
6
7
8

4.7U_0805_25V6-K
PC313

1
2

4.7U_0805_25V6-K
PC305
2
1

1
2

5
6
7
8
2

2
1
PC312
0.1U_0603_25V7K

6,45

PR312
@ 0_0402_5%

+5VALWP
PC310
150U_D_6.3VM

1
+

2
3
2
1

EN0

14

13

VL
1

PL303
10U_LF919AS-100M-P3_4.5A_20%
1
2

+3VL

TPS51125RGER_QFN24_4X4

EN0

3
2
1

21

LL1

PR308
PC308
0_0402_5% 0.1U_0402_10V7K
BST_5V 1
PR310
2 1
2
0_0402_5%
UG_5V
1
2

UG1_5V

DRVH1

LL2

1
2
3

ENTRIP1

PC304
2200P_0402_50V7K

1
ENTRIP1

DRVH2

11

45

6,45

VFB1

10

PR311
@620K_0402_5%
@
2
1

PC309
150U_D_6.3VM

PQ303
AO4468_SO8

VREF

22

1
+

23

VBST1

PR316
100K_0402_5%

LG_3V

PGOOD

VBST2

VCLK

UG_3V

PQ302
AO4466_SO8

VREG3

18

VREG5

VIN

BST_3V

17

8
7
6
5

PL302
4.7UH_SIQB74B-4R7PF_4A_20%
2
1

16

1
2
3

UG1_3V

+3VALWP

PR307
2 1
2
0_0402_5%
PC307
0.1U_0402_10V7K
LX_3V

PR309
0_0402_5%
1
2

PR306
130K_0402_1%
2

24

OCP=4.59(min)
MOSTemperature Factor=1.3 (100C)

B++

VO1

GND

VO2

SKIPSEL

VFB2

P PAD

15

PQ301
AO4466_SO8

TONSEL

25
2

PU301

PC306
10U_0805_6.3V6M

8
7
6
5

1
2

PC303
4.7U_0805_25V6-K

1
2

PR305
105K_0402_1%
1
2

ENTRIP1

PR304
19.6K_0402_1%
1
2

ENTRIP2

PR303
20K_0402_1%
1
2

+3VLP

2
PC301
2200P_0402_50V7K

PR302
30.9K_0402_1%
1
2

PL301
HCB2012KF-121T50_0805

PR301
13.7K_0402_1%
1
2

ENTRIP2

B++

B+

PC302
0.22U_0603_10V7K

2VREF_51125

PQ304
FDS6690AS_NL_SO8

3/5V_OK 49

PR318 0_0402_5%
3

OCP=7.644(min)
MOSTemperature Factor=1.3 (100C)

+5VL

VL

PJP304

PJP302

VL
+5VALWP

PR313
100K_0402_5%
PQ307
2
G
SSM3K7002FU_SC70-3

2
2

+5VALW

(4.5A,180mils ,Via NO.= 9)

+3VALW

(3A,120mils ,Via NO.= 6)

PAD-OPEN 4x4m
PJP303

EC_ON 41,44

+3VALWP

+3VL

+3VLP
PJP301

1
PAD-OPEN 2x2m

100K_0402_5%
PR314

Compal Secret Data

Security Classification
2007/05/29

Issued Date

Deciphered Date

2008/05/29

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

1
PAD-OPEN 2x2m

PAD-OPEN 4x4m

1
2

PC314
0.047U_0603_16V7K

PACIN_1
41,44

PQ308
SSM3K7002FU_SC70-3
1
2
2
G
PR315
604K_0402_1%

Compal Electronics, Inc.


SCHEMATICS,MB A4093
Document Number

Rev
C

401621
Wednesday, April 15, 2009

Sheet
E

51

of

58

PL401

PR401
0_0402_5%
1
2

HCB1608KF-121T30_0603
1
2

B+

1
2

1
2

1
2

1
2

1
2

5
6
7
8

14

10

+5VALW

DL_1.8V

DRVL

PR408 10.5K_0402_1%
PC415
4.7U_0805_10V6K

PQ402
FDS6670AS_NL_SO8

PR410
@ 4.7_1206_5%

S
S
S

+
PC410
@ 680P_0603_50V7K

3
2
1

TPS51117RGYR_QFN14_3.5x3.5

+1.8VP

OCP=9.8913(min)
MOSTemperature Factor=1.3 (100C)
PC409
330U_4V_M

V5DRV

11

PL402
2.2UH_PCMC063T-2R2MN_8A_20%
1
2

12

2
0_0402_5%

LX_1.8V

LL
TRIP

1
PR407

3
2
1

DH_1.8V_1

5
6
7
8

13

PGOOD

PC405
680P_0402_50V7K

DRVH

VFB

PGND

VBST

TP

15

EN_PSV

V5FILT

PR411
1
2
14.3K_0603_0.1%

VOUT

DH_1.8V

+1.8VP

GND

PC411
1U_0603_10V6K

TON

PQ401
AO4466_SO8

0.1U_0402_10V7K

D
D
D
D

1+5VALW
2
2

2
1
0_0402_5%

PC404
2200P_0402_50V7K

PU401
PR405
255K_0402_1%
1
2

PR406

+1.8VP

PC412
4.7U_0805_25V6-K

PR403
316_0402_1%
2

PR404
0_0402_5%

PC403
4.7U_0805_25V6-K

BST_1.8V
1

PC406
4.7U_0805_25V6-K

PC407

+5VALW

PC408
3300P_0402_50V7-K

PC401
@ 1000P_0402_50V7K

1.8V_B+

33,41,42,44 SYSON

1
2
PC413
@ 10P_0402_50V8J

PR409
10K_0603_0.1%

PJP401
+1.8VP

+1.8V

(7A,280mils ,Via NO.= 14)

PAD-OPEN 4x4m

Compal Secret Data

Security Classification
Issued Date

2007/05/29

Deciphered Date

2008/05/29

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATICS,MB A4093
Document Number

Rev
C

401621
Sheet

Wednesday, April 15, 2009


D

52

of

58

PR501
11.5K_0402_1%
+1.2VALWP

B+++

PR502
18.7K_0402_1%

PR503
24.9K_0402_1%

PR504
11.5K_0402_1%

B+++

PL503
3.3UH_SIQB74B-3R3PF_5.9A_20%

2
0_0402_5%

1
PR508

B+
PL502
HCB2012KF-121T50_0805
2
1

UG_1.2V

10

24

EN1

23

VBST2

VBST1

22

BST_1.1V

DR VH2

DR VH1

21

UG_1.1V

LL1

20

LX_1.1V

DR VL1

19

LG_1.1V

LL2

LG_1.2V

12

DR VL2

PC507
0.1U_0402_10V7K

PR507
0_0402_5%
2
1

2
UG1_1.1V

1
PR509
0_0402_5%

1
2

1
2

PL501
2.2UH_PCMC063T-2R2MN_8A_20%
1
2

+1.1VSP

PGND1

+5VALW

PC513
0.1U_0402_10V7K

SUSP# 33,36,41,44,46

PC515
4.7U_0805_10V6K

PC512
@ 0.1U_0402_10V7K

PR513
21K_0402_1%
1
2

PR514
3.3_0402_5%
PC514
1U_0603_10V6K

PC511
220U_6.3VM_R15

OCP=9.6(min)
MOSTemperature Factor=1.3 (100C)

47 3/5V_OK

PR512
0_0402_5%
2

PQ504
AO4468_SO8
PR510
13K_0402_1%

OCP=4.487(min)
MOSTemperature Factor=1.3 (100C)

3
2
1

1
2
3

PR511
10.7K_0402_1%
1
2

PC510
4.7U_0805_6.3V6K

TPS51124RGER_QFN24_4x4

18

TRIP1

AO4468_SO8

17

V5IN
16

TRIP2

V5FILT
15

13

PQ503

14

PGND2

5
6
7
8

11

5
6
7
8

VFB1

GND

VO1

PGOOD1

LX_1.2V

PQ502
AO4466_SO8

PC516
4.7U_0805_25V6-K

BST_1.2V

PC503
0.022U_0603_25V7K

2200P_0402_50V7K
PC505

EN2

PC504
4.7U_0805_25V6-K

PGOOD2

TONSEL

1.1VS_POK 18

6
VO2

PR515
1K_0402_5%

UG1_1.2V

PC509

PC506
PR506
0.1U_0402_10V7K
0_0402_5%
2
1 2
1

8
7
6
5

4.7U_0805_6.3V6K

B+++

3
2
1

1
2
3

+1.2VALWP

+1.1VSP

1
4

VFB2

8
7
6
5
AO4466_SO8

P PAD

PU501

25

PQ501

PC508
220U_D2_4VM

2200P_0402_50V7K
PC502

1
2

PC501
4.7U_0805_25V6-K

PR505
0_0402_5%

PJP501

+1.1VSP

+1.1VS

(6A,240mils ,Via NO.=12)

PAD-OPEN 4x4m
PJP502

+1.2VALWP

+1.2VALW

(4A,160mils ,Via NO.=8)

PAD-OPEN 4x4m

Compal Secret Data

Security Classification
2007/05/29

Issued Date

Deciphered Date

2008/05/29

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATICS,MB A4093
Document Number

Rev
C

401621
Wednesday, April 15, 2009

Sheet
1

53

of

58

+1.8V
+1.8V

VOUT

NC

TP

1
PC603
1U_0603_10V6K

PC613
10U_0805_10V6K

G2992F1U_SO8

PR606
1K_0402_1%

VREF

NC

VOUT

NC

TP

+5VALW

PC612
1U_0603_10V6K

+1.5VSP

2
G

PR607
5.1K_0402_1%

2
1
PC611
0.1U_0402_10V7K

1
PR608
0_0402_5%

18,44 SUSP

PQ602
SSM3K7002FU_SC70-3
PC605
10U_0805_10V6K

+0.9VP

1
2

2
3

PC604
0.1U_0402_10V7K

PC614
10U_0805_10V6K
C

PC606
@ 0.1U_0402_10V7K

PC610
@ 0.1U_0402_10V7K

PR603
1K_0402_1%

2
G
1

PR604
@ 0_0402_5%

PQ601
SSM3K7002FU_SC70-3

18,44 SUSP

VREF1.5V

0_0402_5%

NC

G2992F1U_SO8

PR602

43,44 SYSON#

VCNTL

GND

PR601
1K_0402_1%

VIN

NC

VREF

PU603

+5VALW

PC609
10U_0805_10V6K

NC

VCNTL

GND

VIN

2
1

1
2

PC602
10U_0805_10V6K

PC601
10U_0805_10V6K

PU601

(500mA,40mils ,Via NO.= 1)

PU602
APL5508-25DC-TRL_SOT89-3

PAD-OPEN 3x3m
PJP602

+2.5VSP

+2.5VS

(500mA,40mils ,Via NO.= 1)

+1.5VS

(1A,40mils ,Via NO.= 2)

PAD-OPEN 3x3m

OUT

+2.5VSP
B

GND
1

IN

PR605
@150_1206_5%

(2A,80mils ,Via NO.= 4)

+0.9V

+0.9VP

PC607
1U_0603_6.3V6M

PJP601

PC608
4.7U_0805_6.3V6K

+3VS

PJP603

+1.5VSP

2
PAD-OPEN 3x3m

Compal Secret Data

Security Classification
Issued Date

2006/11/23

Deciphered Date

2007/11/23

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATICS,MB A4093
Document Number

Rev
C

401621
Wednesday, April 15, 2009

Sheet
1

54

of

58

PL201
4.7UH_SIQB74B-4R7PF_4A_20%
1

8
7
6
5

CPU_B+

1
2
3

1
2
3

PC202
220U_B2_2.5VM
<BOM Structure>

1
2

10U_0805_10V6K
PC201

6 VDD_NB_FB_L

PQ202
AO4466_SO8

PQ201
AO4468_SO8
8
7
6
5

6 VDD_NB_FB_H

+CPU_CORE_NB

PC204
4.7U_0805_25V6-K
D

UGATE NB 1

0_0402_5%

PR221
16.5K_0402_1%
2
1

1
1 2

PR220
4.7_1206_5%

PC218
680P_0603_50V8J

3
2
1

PQ207

1
AO4714 1N SO8

ISP 1

1
2

PC215
1000P_0402_50V7K

PC244
3300P_0402_50V7-K
2
1

0.36UH_PCMC104T-R36MN1R17_30A_20%
2
1
PL204
PR229
4.7_1206_5%

PQ208

+CPU_CORE_1

PC226
680P_0603_50V8J

+CPU_CORE_1

PR233
4.02K_0402_1%
1
2

PC229
0.1U_0603_25V7K

PC230
1000P_0402_50V7K
2
1

1
2
PC228
1000P_0402_50V7K

PC243
820P_0402_50V7K
2
1

4
3
2
1

PC224
0.22U_0603_10V7K

5
6
7
8

UGATE1_1

1 2

TP

PR226
1
2
0_0603_5%
2
1
2

49

ISP1

VW1

COMP1

ISN1
24

23

22

FB1

1
PR228
2.2_0603_5%

4.7U_0805_25V6-K

BOOT1

CPU_B+

PC236
2
1

25

4.7U_0805_25V6-K

BOOT1

PC237
2
1

VW0

2200P_0402_50V7K

UGATE1

12

4.7U_0805_25V6-K
PC222
2
1

26

PR231
16.5K_0402_1%
2
1

UGATE1
VDIFF1

ISP 0

PC221
2
1

COMP0

ISP0

PC211
68U_25V_M_R0.44

PR217
4.02K_0402_1%
1
2

PC219
0.1U_0603_25V7K

4.7U_0805_25V6-K

PHASE1

11

PC220
2
1

28
27

PQ206
AO4474 1N SO8

G
S
S
S

PGND1

PC240
68U_25V_M_R0.44

PL203

5
6
7
8
D
D
D
D
LGATE1

PHASE1

6.81K_0402_1%

PC214
2200P_0402_50V7K
2
1

PC213
4.7U_0805_25V6-K
2
1

PC212
4.7U_0805_25V6-K
2
1

PC234
4.7U_0805_25V6-K
2
1

5
6
7
8
D
D
D
D
G
S
S
S
5
6
7
8

5
6
7
8
3
2
1

PQ205
AO4714 1N SO8

+CPU_CORE_0

LGATE0

FB0

ISL6265IRZ-T_QFN48_6X6

2
<BOM Structure>

4
3
2
1

BOOT_NB
BOOT0

PHASE_NB

UGATE_NB

PGND_NB

LGATE_NB

PC235
4.7U_0805_25V6-K
2
1

1
2
UGATE NB
37

PHASE NB

LGATE NB
40

39

38

41

PC242
3300P_0402_50V7-K
2
1

PC241
820P_0402_50V7K
2
1

1
2

BOOT_NB1

0_0402_5%

2
PR209

PR207
14K_0402_1%

1
2
PR206
VSEN_NB

RTN_NB
RTN_NB

VSEN_NB

FSET_NB

FB_NB

COMP_NB

OCSET_NB

3
2
1

VDIFF0

5
6
7
8

OCSET

PR232
1

42

47

VIN

LGATE1

29

AO4474 1N SO8

PQ204
AO4714 1N SO8

3
2
1

1200P_0402_50V7K
1
2
PC227
180P_0402_50V8J

VCC

30

PC225
1
2

54.9K_0402_1%
B

31

PVCC

21

LGATE0

20

PHASE0

32

13

PR230

33

PGND0

10
2

1K_0402_1%

PHASE0

SVC

RBIAS

0.36UH_PCMC104T-R36MN1R17_30A_20%
2
1

SVD

ENABLE

UGATE0_1

1
2
0_0603_5%
PR219

UGATE0

VSEN1

PR227
1

36
35

4700P_0402_25V7K

PC210
2.2U_0603_6.3V6K

2.2_0603_5% 0.22U_0603_10V7K
PR214
PC217
1
2 1
2

34

RTN1

255_0402_1%

PQ203

BOOT0

17

PC223
1
2

PR211
1_0603_5%

BOOT_NB

B+
PL202
SMB3025500YA_2P

+5VS

UGATE0

RTN0

PR225
1

82.5K_0402_1%

CPU_B+

PWROK

VSEN0

34.8K_0402_1%~N

PC206
0.1U_0603_16V7K

PGOOD

15

VR_ON

OFS/VFIXEN

+CPU_CORE_014

CPU_SVD
CPU_SVC

41

ISP 0

PU201

2
PR242 1 @
100K_0402_5%
2
ISL6265_PWROK 3
1
2
PR234
100K_0402_5%
SVD
1
2
4
PR218
0_0402_5%
SVC
1
2
5
PR222
0_0402_5%
6
PR223
PR224
1
2
1
2
7

41
VGATE
6,27,41 H_PWRGD
6,27,41 SB_PWRGD

PR215
@ 10K_0402_5%

ISN0

PR216
10K_0402_1%
2
1

46

2
PR212
0_0402_5%
1
2
PR213
@ 0_0402_5%
1
2
48

16

+5VS

+3VS

44

PC216
0.1U_0603_25V7K

45

CPU_B+

2
1
PR210
44.2K_0402_1%

PR208
2_0402_5%
1
2

2
1
PC208
1200P_0402_50V7K

1
2

33P_0402_50V8K
PC209
2
1

PC207
0.1U_0402_10V7K

43

PR205
2_0402_5%
1
2

+5VS

PHASE NB

LGATE NB

19

Connect to EC Pin 110.

PC205
1000P_0402_50V7K

18

2
G

PC203
2200P_0402_50V7K

PR203
0_0402_5%

PR204
22K_0402_1%
1
2

PQ115
SSM3K7002FU_SC70-3

ISL6265_PWROK

VFIX_EN
6,27,41

AO4714 1N SO8
PC231
180P_0402_50V8J
2
0_0402_5%

6 CPU_VDD0_FB_L

1
PR237

2
0_0402_5%
2
0_0402_5%

6 CPU_VDD1_FB_H

PR241

2
0_0402_5%

PC238
@1000P_0402_50V7K
RTN0

1
PR236
6.81K_0402_1%

2
2

1
PR238
54.9K_0402_1%
2
1

PC232
1200P_0402_50V7K
PR240
1K_0402_1%
2
1

RTN1

PR239

6 CPU_VDD1_FB_L

ISP 1

VSEN0
1

1
PR235

6 CPU_VDD0_FB_H

PC239
@1000P_0402_50V7K
VSEN1
2

PR243
255_0402_1%
2
1

4700P_0402_25V7K
PC233

Compal Secret Data

Security Classification
2006/11/23

Issued Date

Deciphered Date

2007/11/23

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATICS,MB A4093
Document Number

Rev
C

401621
Sheet

Wednesday, April 15, 2009


1

55

of

58

PR719
0_0402_5%
2
1

PR702
0_0402_5%
1
2

PC707
2.2U_0603_10V6K

PHASE

15

LX_VGA

UG

14

DH_VGA

BOOT

13

BST_VGA 1

PC706
0.22U_0603_16V7K

2
G

PQ704
SSM3K7002FU_SC70-3

PQ705
SSM3K7002FU_SC70-3
2
1
G
PR715
0_0402_5%

2 2

@680P_0603_50V7K

1
2
+
2

1
+
2

1
+
2

PR722
+6269_VCC

1
2

FDS6676AS_SO8

3
2
1

PC709

OCP=22.8(min)
MOSTemperature Factor=1.3 (100C)

6269_PVCC

2.2_0402_5%

PJP701
+VGA_COREP

PR703
0_0402_5%

PC719
0.022U_0402_16V7K

+VGA_CORE

(18A,720mils ,Via NO.= 36)

PAD-OPEN 4x4m
PJP702

PC701
2.2U_0603_10V6K

High: VGA_CORE 0.95V


Low: VGA_CORE 1.1V

+5VALW

VGA_PWRSEL 16

PR710
PQ702 @4.7_1206_5%

10K_0402_1%

3
2
1

PR705
1
2
8.25K_0402_1%

FDS6676AS_SO8

PQ703
6269_PVCC

PR709
2
1
0_0402_5%

PR716
100K_0402_5%

PR717
1

+VGA_COREP

PC718
330U_2V_Y_D2_LESR9M

+VGA_COREP

12

11

10

+5VALW
PR713
9.09K_0402_1%

PL702
0.33UH_PCMC063T-R33MN_20A_20%
1
2

PC714
330U_2V_Y_D2_LESR9M

BST1_VGA1

PC713
330U_2V_Y_D2_LESR9M

PR708
2.2_0402_5%

DH_VGA_1

PC708
330U_2V_Y_D2_LESR9M

3
2
1

PQ701
AO4474_SO8
PR711
0_0402_5%
1
2

5
6
7
8

LG

PVCC

VO

PC705
@680P_0402_50V7K

FSET

5
6
7
8
16

1
VIN

2
VCC

PGOOD
PU701
ISL6269ACRZ-T_QFN16_4X4

ISEN

PR704
4.32K_0402_1%

17

5
6
7
8

FCCM

EN
FB

2
1
PC715
0.01U_0402_16V7K 8

GND

PGND

2
1
PR706
49.9K_0402_1%

4
1
2
PR707
2.55K_0402_1%

COMP

B+

PC710
2200P_0402_50V7K

PR712
10_0402_5%
1
2

+VGA_COREP

PC704
10U_1206_25V6M

PR721
2
1
0_0402_5%

+VGA_CORE

PC703
10U_1206_25V6M

2
1
PC716
22P_0402_50V8J
PR720
2
1
2
1
PC717
90.9K_0402_1%
6800P_0402_25V7K

PL701
HCB2012KF-121T50_0805
2
1

VGA_B+

PC702
@ 0.1U_0402_10V7K

<32,40,41,43,49> SUSP#

+6269_VCC

2
PAD-OPEN 4x4m
PJP703

2
PAD-OPEN 4x4m

Compal Secret Data

Security Classification
Issued Date

2007/05/29

Deciphered Date

2008/05/29

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATICS,MB A4093
Document Number

Rev
C

401621
Wednesday, April 15, 2009
D

Sheet

56

of

58

Item
1

Modify List

Remove Q23

PAGE

Fixed Issue and change item

M.B. Ver.

HP OUT For Docking

1.1

41

(2N7002)

ADD R936 R937

41

HP OUT For Docking

1.1

Remove U5 (M82-S)

15,16,17
18,19,20,21

change M82S TO M86M

1.1

Remove U54

15,16,17
18,19,20,21

change M82S TO M86M

1.1

Remove Q8(SI2301BDS)

15,16,17
18,19,20,21

change M82S TO M86M

1.1

Remove Q9(2N7002)

15,16,17
18,19,20,21

change M82S TO M86M

1.1

Remove R149 (240 ohm)

15,16,17
18,19,20,21

change M82S TO M86M

1.1

Remove L32,L33 (0 ohm)

15,16,17
18,19,20,21

change M82S TO M86M

1.1

Remove R42,R625,R630
(0 ohm)

15,16,17
18,19,20,21

change M82S TO M86M

1.1

10

Remove R189 (100 ohm)

15,16,17
18,19,20,21

change M82S TO M86M

1.1

11

Remove R131,R142 (1K ohm)

15,16,17
18,19,20,21

change M82S TO M86M

1.1

12

Remove R120,R130,R190,R197,R243,R244,R245,R246(10K ohm)

15,16,17
18,19,20,21

change M82S TO M86M

1.1

13

Remove R151 (10Kohm)

15,16,17
18,19,20,21

change M82S TO M86M

1.1

14

Remove R145,R146,R147,R241,R242,R403 (4.7Kohm)

15,16,17
18,19,20,21
change M82S TO M86M

1.1

15

Remove R159,R160,R165,R166(56 ohm)

15,16,17
18,19,20,21

change M82S TO M86M

1.1

16

Remove R143,R144,R148,R150 (100 ohm)

15,16,17
18,19,20,21

change M82S TO M86M

1.1

17

Remove R109 (1.27K ohm)

change M82S TO M86M

1.1

18

Remove R112 (150 ohm)

15,16,17
18,19,20,21

change M82S TO M86M

1.1

19

Remove R108 (2K ohm)

15,16,17
18,19,20,21

change M82S TO M86M

1.1

18

Remove R1136 (249 ohm)

15,16,17
18,19,20,21

change M82S TO M86M

1.1

20

Remove R119,R132 (499 ohm)

15,16,17
18,19,20,21
change M82S TO M86M

1.1

21

Remove R155,R156,R157,R158,R161,R162,R163,R164 (4.99Kohm)

15,16,17
18,19,20,21

change M82S TO M86M

1.1

22

Remove R135 (715 ohm)

15,16,17
18,19,20,21

change M82S TO M86M

1.1

23

Remove R177 (75 ohm)

15,16,17
18,19,20,21

change M82S TO M86M

1.1

24

Remove C254,C255,C256,C257,C258,C259,C260,C261,C262,C263,C264,C265,C266,C267,C268,C269,C270,C271,C272,C273,C274,C275,C276,C277,C278,C279,C280,C281,C282,C283,C284,C285 (0.1U)

15,16,17
18,19,20,21

change M82S TO M86M

1.1

25

Remove C478 (220U)

15,16,17
18,19,20,21

change M82S TO M86M

1.1

26

Remove L23,L24,L25,L26,L27,L28,L29,L30,L31,L34,L35,L36,L37,L38,L39,L40,L41,R110,R115
(BLM18PG121SN1D)
Remove C294,C295,C298,C299,C302,C303,C305,C307,C310,C315,C318,C319,C322,C330,C331,C332,C336,C337,C341,C351,C356,C359,C364,C368,C373,C380,C386,C390,C392,C395,C405,C406,C413,C414,C428,C429,C436,C437,C599
(10 U)

15,16,17
18,19,20,21

change M82S TO M86M

1.1

15,16,17
18,19,20,21

change M82S TO M86M

1.1

Remove C287,C288,C290,C292,C297,C300,C306,C308,C311,C314,C317,C320,C323,C325,C328,C329,C339,C344,C358,C382,C391,C394,C397,C398,C400,C402,C403,C408,C409,C410,C411,C416,C417,C418,C419,C421,C423,
C425,C426,C431,C432,C433,C434,C439,C440,C441,C442,C598
(0.1 U)
Remove C286,C312,C338,C340,C342,C343,C345,C346,C352,C353,C354,C355,C360,C361,C362,C363,C369,C370,C371,C372,C374,C375,C376,C377,C387,C388,C393,C396,C289,C291,C293
C296,C301,C304,C309,C313,C316,C321,C324,C333,C334,C335,C347,C348,C349,C350,C357,C365,C366,C367,C378,C379,C381,C383,C384,C385,C389,C399,C401,C407,C415,C422,C424,C430,C438,C597(1U)

15,16,17
18,19,20,21

change M82S TO M86M

1.1

15,16,17
18,19,20,21

change M82S TO M86M

1.1

Remove U12 (ADM1032ARMZ)

15,16,17
18,19,20,21
15,16,17
18,19,20,21

change M82S TO M86M

1.1

change M82S TO M86M

1.1

38

Fix CR_LED

1.1
1.1

(0 ohm)

15,16,17
18,19,20,21

27

28
29

30

31
32

Remove R330(4.7K ohm)


Remove C466
(0.1U)

33

Remove C467 (2200P)

38

Fix CR_LED

34

Remove Q53(2N7002)

38

Fix XD_ALE

35

ADD R933(0 ohm)

36

ADD R127(10Kohm)

Compal Secret Data

Security Classification
Issued Date

2007/08/02

Deciphered Date

2008/08/02

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATICS,MB A4093
Document Number

Rev
C

401621
Sheet

Wednesday, April 15, 2009


1

57

of

58

Item

Modify List

PAGE

Fixed Issue and change item

M.B. Ver.

ADD ":U6,UV7,U7,UV8,U8,UV9,U9,UV10
"(MEMARY)

P15~P25

change M82S TO M86M

ADDQ9

P15~P25

change M82S TO M86M

1.1

ADD QV3(SI2301BDS)

P15~P25

change M82S TO M86M

1.1

ADD RV47(240 ohm)

P15~P25

change M82S TO M86M

1.1

ADD R42(0 ohm)

P15~P25

change M82S TO M86M

1.1

(2N7002)

1.1

ADD RV19,RV44
(1K ohm)

P15~P25

change M82S TO M86M

1.1

ADD RV96,RV100,RV72,RV73,RV74,RV75,RV76,RV77,RV78,RV79,RV92,RV93,RV94,RV95,RV97,RV99,RV101,RV107,RV108,RV7,RV9,RV10,RV11,RV12,RV13,RV14,RV16,RV17,RV18,RV33,RV98,RV102(10K ohm)

P15~P25

change M82S TO M86M

1.1

ADD RV30,RV34(100K ohm)

P15~P25

change M82S TO M86M

1.1

ADD RV103,RV104,RV45,RV46,R403(4.7K ohm)

P15~P25

change M82S TO M86M

1.1

10

ADD RV36,RV37,RV38,RV39,RV40,RV41,RV42,RV43(100 ohm)

P15~P25

change M82S TO M86M

1.1

11

ADD RV6
(1.27Kohm)

P15~P25

change M82S TO M86M

1.1

12

ADD RV25,RV26,RV27,RV8(150 ohm)

P15~P25

change M82S TO M86M

1.1

13

ADD RV5(2K ohm)

P15~P25

change M82S TO M86M

1.1

14

ADD RV23,RV15,RV22(499 ohm)


P15~P25

change M82S TO M86M

1.1

15

ADD RV60,RV61,RV62,RV63,RV66,RV67,RV68,RV69,RV54,RV55,RV56,RV57,RV48,RV49,RV50,RV51(4.99K ohm)

P15~P25

change M82S TO M86M

1.1

16

ADD RV24(715 ohm)

P15~P25

change M82S TO M86M

1.1

ADD RV28(75 ohm)

P15~P25
change M82S TO M86M

1.1

17

18

ADD YV1(CRYSTAL 27MHZ)

P15~P25

change M82S TO M86M

1.1

19

ADD RV103,RV104,RV45,RV46,R403(4.7K ohm)

P15~P25

change M82S TO M86M

1.1

20

ADD LV1,LV2,LV3,LV4,LV5,LV6,LV7,LV8,LV9,LV10,LV11,LV12,LV13,LV14,LV15,LV16,LV17,LV18,LV19,LV21,LV22,LV23,LV24,LV25
(MURATA BLM18PG121SN1D )

P15~P25

change M82S TO M86M

1.1

21

ADDCV226,CV227,CV234,CV235,CV249,CV250,CV257,CV258,CV203,CV204,CV211,CV212,CV180,CV181,CV188,CV189,CV42,CV45,CV48,CV52,CV53,CV56,CV59,CV64,CV67,CV68,CV71,CV76,CV84,CV85,CV90,CV92,CV95,CV97,CV99,CV101,CV108,
CV117,CV119,CV131,CV132,CV136,CV140,CV145,CV149,CV157,CV165,CV166,CV169,CV173(10u)

P15~P25
change M82S TO M86M

1.1

22

ADD CV80,CV244,CV229,CV230,CV231,CV232,CV237,CV238,CV239,CV240,CV242,CV246,CV247,CV252,CV253,CV254,CV255,CV260,CV261,CV262,CV263,CV265,CV267,CV269,CV270,CV206,CV207,CV208,CV209,CV214,CV215,CV216,
CV217,CV219,CV221,CV223,CV224,CV196,CV183,CV184,CV185,CV186,CV191,CV192,CV193,CV194,CV198,CV200,CV201,CV44,CV46,CV49,CV50,CV55,CV58,CV60,CV62,CV66,CV69,CV72,CV75,CV79,CV83,
CV87,CV88,CV106,CV114,CV120,CV125,CV159,CV168,CV171,CV172,CV175,CV176,CV177,CV178,CV179,CV272(0.1u)

change M82S TO M86M

1.1

change M82S TO M86M

1.1

P15~P25

23

ADD CV77,CV78(22P)

P15~P25

change M82S TO M86M

1.1

24

ADD CV273 (2200P)

P15~P25

change M82S TO M86M

1.1

25

ADDCV233,CV241,CV256,CV264,CV210,CV218,CV187,CV195(0.01U)

P15~P25

change M82S TO M86M

1.1

26

ADD CV245,CV228,CV236,CV243,CV251,CV259,CV266,CV268,CV205,CV213,CV220,CV222,CV197,CV182,CV190,CV199,CV41,CV43,CV47,CV51,CV57,CV63,CV65,CV70,CV73,CV74,CV82,CV86,CV89,CV93,CV96,CV98,CV100,CV103,CV104,
CV105,CV107,CV109,CV111,CV113,CV118,CV121,CV135,CV139,CV144,CV162,CV163,CV164,CV54,CV61,CV94,CV102,CV110,CV112,CV115,CV116,CV123,CV124,CV126,CV127,CV129,CV130,CV133,CV134,CV137,CV138,CV141,CV142,
CV146,CV147,CV150,CV151,CV153,CV154,CV155,CV156,CV158,CV160,CV161,CV167,CV170,CV174(75 ohm)
ADD RV28(1U)

change M82S TO M86M

1.1

change M82S TO M86M

1.1

P15~P25

27

ADD CV9,CV10,CV11,CV12,CV13,CV14,CV15,CV16,CV17,CV18,CV19,CV20,CV21,CV22,CV23,CV24,CV25,CV26,CV27,CV28,CV29,CV30,CV31,CV32,CV33,CV34,CV35,CV36,CV37,CV38,CV39,CV40
( 0.1U)

P15~P25

change M82S TO M86M

1.1

28

ADD CV122,CV91,CV128(33OU)

P15~P25

change M82S TO M86M

1.1

Change RV30 100K to

P16

About GBU 27MHz

Change PR702 4.7K to 0 ohm

P55

About GBU 3V_delay time

del PC702 0.1 U

P55

About GBU 3V_delay time

change NET DQMA#4 TO U8 F3 Pin

P22

about GBU A chanel VRAM

change NET DQMA#5 TO U8 B3 Pin

P22

about GBU A chanel VRAM

Change NET QSA4 QSA#4 TO U8 F7,E8 PIN

P22

about GBU A chanel VRAM

Change NET QSA5 QSA#5TO U8 B7,A8 PIN

P22

about GBU A chanel VRAM

change NET DQMA#7 TO U8 F3 Pin

P22

about GBU A chanel VRAM

change NET DQMA#6 TO U8 B3 Pin

P22

about GBU A chanel VRAM

10

Change NET QSA7 QSA#7TO U8 F7,E8 PIN

P22

about GBU A chanel VRAM

11

Change NET QSA6 QSA#6 TO U8 B7,A8 PIN

P22

about GBU A chanel VRAM

12

Change UV12 BOM SA010320120 to SA010320110

P25

PV

100 ohm

13

Modify R237,R238,R176,R209 PULL +3VS TO +3VS_DELAY

14

ADD LV20,CV152,CV148,CV143

P27 P29
P18

ADD M86M +VDDR5 POWER

Compal Secret Data

Security Classification
Issued Date

about GBU Thermal Sensor


Change power plan

2007/08/02

Deciphered Date

2008/08/02

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATICS,MB A4093
Document Number

Rev
C

401621
Sheet

Wednesday, April 15, 2009


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