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Implementation of DQ Domain Control in

DSP and FPGA


Venkata Anand Prabhala, Mauricio Cspedes and Jian Sun
Department of Electrical, Computer and Systems Engineering
Rensselaer Polytechnic Institute, Troy, NY 12180-3590, USA
Telephone: (518) 276-8297; Fax: (518) 276-6226; E-mail: jsun@rpi.edu
AbstractCurrent control in three-phase voltage source
converters (VSC) is usually performed in the dq-coordinate
system because of its ability to eliminate steady-state tracking
errors. For grid-connected VSCs, such as PWM rectifiers and
grid-parallel inverters for integration of renewable energy and
energy storage devices, a phase-locked loop (PLL) is commonly
used to synthesize a set of harmonic-free voltages synchronized to
the grid voltages for transformation between the dq and the abc
coordinate systems. The multitude of control functions in large
systems, such as wind turbines, necessitate the use of multiple
digital control devices. In such cases, the PLL output has to be
transferred among different devices. To reduce the bandwidth
requirements and noise susceptibility of such signal transfer, this
paper presents a PLL implementation method that distributes the
PLL function into different devices. Instead of transferring
directly the synthesized grid voltage angle, the synthesized grid
frequency, which has much lower signal bandwidth, is communi-
cated. A binary reset signal is used to eliminate the difference
between initial values of the distributed integrators that convert
locally frequency into reference angle. An experimental system
consisting of a three-phase VSC, a TMS320F28335 DSP, and an
Altera DE2 board with a Cyclone II EP2C35 field programmable
gate array (FPGA) is used to demonstrate the proposed concept.
I. INTRODUCTION
VSCs such as PWM rectifiers and grid-parallel inverters for
integration of renewable energy and energy storage devices
typically rely on digital signal processing for realization of their
current control and grid synchronization functions. Other forms of
power-electronics based equipment such as STATCOMs and
active power filters commonly include such control functions
among many other power regulation functions. Three-phase
power converter current control is usually performed in a dq-
coordinate system because of its ability to eliminate steady-state
tracking errors [1]. Transformation of the converter currents in the
abc-coordinate system into a rotating reference frame requires to
make the transformation angle available to the current controller.
The angular rotating frequency may also be required in some
frequency-feedforward compensation schemes and other current
control methods that operate in the abc-coordinate reference
frame. Hence grid synchronization is a common requirement for
grid-connected power converters regardless of the implemented
current control method. Despite the ever increasing computational
capabilities of FPGAs [2] and DSPs [3], distributed processing of
the variety of power converter regulation functions among
different digital platforms becomes a desirable feature in high-
performance applications, where realization of the numerous
digital/analog communication ports may become problematic.
Among the several grid synchronization methods, many of the
advanced strategies [4-5] rely on the fundamental concept of a
synchronous reference frame PLL [6]. The output of the PLL is
typically regarded as the synchronization angle. However, this
represents a challenge if analog signal transmission of the PLL
angle is to be realized by conventional operational amplifier
circuitry. The problem in any practical implementation of the PLL
is that it requires resetting of the detected angle every 2t radians,
which makes it impossible to transmit the detected angle through
band-limited analog channels without causing distortion at the
sharp angle-reset instants.
This paper presents a distributed implementation of the grid
synchronization and current control functions of a VSC using a
DSP and a FPGA. The grid synchronization PLL is implemented
in a TMS320F28335 DSP while the dq-domain current control is
implemented in an Altera DE2 board with a Cyclone II EP2C35
FPGA. To overcome the limitation of analog circuitry in trans-
mitting the synthesized PLL reference angle, transmission of the
PLL angular frequency is proposed, which has much lower signal
bandwidth. A binary reset signal is used to eliminate the difference
between initial values of the distributed integrators that convert
locally frequency into reference angle. The rest of the paper is
organized as follows: Section II explains the requirements for
signal transmission in practical implementations of the PLL.
Section III presents the dq-domain current control implementation
by transmitting the PLL reference angle. Section IV explains the
proposed implementation by transmitting the angular frequency
and reset instants, together with the salient advantages over other
possible realizations. Experimental system performance is
presented in Section V and Section VI summarizes the findings.
II. PLL IMPLEMENTATION
Grid synchronization is responsible for generating a sinusoidal
reference free of harmonic distortion and imbalance for the current
control loop. Several grid synchronization methods have been
proposed in the literature. Open-loop methods develop a
sinusoidal references by low-pass filtering of the grid voltage but
dont work well under unbalanced grid conditions in three-phase
systems. Closed-loop grid synchronization methods based on the
synchronous-frame PLL [6] can be upgraded to differentiate
between positive- and negative-sequence components of the grid
voltage. Fig. 1 shows the block diagram of a basic synchronous-
frame PLL. More advanced PLL methods, such as the cross-
coupled PLL [4] and the de-coupled double-synchronous
978-1-4577-1216-6/12/$26.00 2012 IEEE 1439
reference frame PLL [5], use the same basic PLL as a building
block. The output of the PLL for the current controller reference
frame is the detected angle of the grids positive-sequence voltage.
For obvious reasons, the detected angle is reset every 2t
radians which makes its transmission problematic through band-
limited analog channels. Digital signal transmission does not
suffer from the band-limited problem, but the number of digital
channels required to accurately transmit the angle signal increases
significantly compared to the analog signal implementation. Serial
communication is a possible alternative but complicates FPGA
programming and increases the computational delay in the current
controller. Time delays in the current controller are the main
problem for such fast acting loop and need to be minimized.
In order to reduce the burden on the bandwidth of the analog
channel for reference-frame synchronization between the DSP and
FPGA two possible alternatives are to transmit the cosine of the
PLL angle or the frequency of the angle may suffice when the
reset instants are also made available to the FPGA controller. The
former, although plausible in single-phase systems, becomes
impractical in three-phase systems since for transformation
between abc and dq-coordinate systems not only the cosine of the
angle is required but also other terms in the Parks transformation.
Implementation of a PLL in the FPGA to detect the angle of the
cosine signal is a possibility but increases the computational
burden on the FPGA. Hence the second alternative becomes the
most viable. This is because the PLL frequency is not a high-
bandwidth signal, which may in fact be fairly constant for most
normal operating conditions. Utilization of the PLL angular
frequency in the FPGA to generate a number of trigonometric
functions and realize all terms in Parks transform is straight-
forward. Such realization would require one additional digital link
to make the reset instants in the DSP available to the FPGA.
Fig. 1. Block diagram of a basic PLL.
k
p
k
i
s
---- +
v
b
v
c
v
a
u
PLL
v
d
v
q
abc
dq 1
s
---
III. CURRENT CONTROL BY TRANSMISSION OF u
PLL
A. Control Structure, Partitioning, and PLL Implementation
In this case, the PLL is implemented in DSP and the dq-domain
current control references together with the reference angle are
transmitted to the FPGA for the current control implementation as
shown in Fig. 2.
Fig. 2. Block diagram for implementation of dq-domain control in FPGA by
transmitting u
PLL
from DSP.
k
p
k
i
s
---- +
v
b
v
c
v
a
u
PLL
v
d
v
q
abc
dq 1
s
---
m
b
m
c
m
a
u
PLL
i
q

i
d

i
qr
i
dr
E H
i
(s)
E
E
E
abc
dq
H
i
(s)
K
d
K
d
PWM
s
b
s
c
s
a
m
b
m
c
m
a
i
dr
i
qr
u
PLL
Sine & Cosine
Look-up Table
e
PLL
The modulating signals are the output of the
current controller and need to be converted back to the abc-
coordinate frame for comparison with a carrier signal in conven-
tional SPWM implementations. Hence both the forward and
inverse Parks transformations are needed to be realized in the
FPGA, for which look-up tables are a straight-forward method to
implement when the PLL reference angle is made available to the
FPGA. The forward Parks transformation is defined as follows
T u
PLL
( )
2
3
---
u
PLL
( ) cos u
PLL
2t
3
------
\ .
| |
cos u
PLL
2t
3
------ +
\ .
| |
cos
u
PLL
( ) sin u
PLL
2t
3
------
\ .
| |
sin u
PLL
2t
3
------ +
\ .
| |
sin
1
2
---
1
2
---
1
2
---
= (1)
While inverse Parks transformation is given by
T u
PLL
( )
1
u
PLL
( ) cos u
PLL
( ) sin 1
u
PLL
2t
3
------
\ .
| |
cos u
PLL
2t
3
------
\ .
| |
sin 1
u
PLL
2t
3
------ +
\ .
| |
cos u
PLL
2t
3
------ +
\ .
| |
sin 1
= (2)
B. Performance Measurement and Evaluation
Performance of the algorithm presented in this section is illus-
trated by Fig. 3. The spike in the cos(u
PLL
) calculated in FPGA
occurs due to the non-ideal transitions between 2t and 0 radians in
the transmitted PLL angle around its reset instants. The error in
calculation of the trigonometric functions propagates to the
modulating signals fed to the PWM and cause malfunctioning of
the overall controller implementation. Fig. 4 depicts the resulting
error in calculation of the modulating signals. Performance of the
three-phase power converter in Fig. 5 with the presented control
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Fig. 3. Error in the calculation of cos(u
PLL
) when u
PLL
is transmitted from
DSP to FPGA.
u
PLL
calculated in DSP
u
PLL
transmitted to FPGA
Error in cos(u
PLL
) calculation in FPGA
Fig. 4. Error in the calculation of modulation signals.
Error in calculation of modulation signals
implementation is depicted in Fig. 6.
+

v
a
v
c
v
b
s
a
s
b
s
c
i
q
i
d
u
PLL
V
dc
C
L
f
R
d
C
d
C
f
R
V
n
i
a
i
c
i
b
Fig. 5. Diagram of a three-phase VSC for standalone operation.
abc
dq
The dq domain current
controllers were implemented using PI current regulators with K
p
= 0.0059 and K
i
= 0.00036. The d-axis current reference i
dr
and q-
axis current reference i
qr
are set to 3 A and 0 A respectively. The
input voltage is V
dc
= 450 V with a 25 resistive load. From Fig.
6, it is observed that the current controller regulates the output
current at 3 A peak, but the spikes in the modulation signals result
in spikes in output phase current i
a
and phase voltage v
a
.
Fig. 6. Spikes in inverter output current and voltage waveforms.
v
a
i
a
m
a
IV. CURRENT CONTROL BY TRANSMISSION OF e
PLL
This section presents implementation of dq-domain current
control in the FPGA when the angular frequency of the PLL is
transmitted from a DSP via an analog channel. Additionally, the
initial phase information is also required to synthesize the PLL
angle. A binary signal state is transmitted using a digital channel at
the reset instants of the PLL reference angle in the DSP.
A. Integrator Reset and Sensitivity to Noise
The control algorithm was modified to transmit e
PLL
calcu-
lated in the DSP to the FPGA as depicted in Fig. 7. The synchro-
nizing signal is represented by RESET_SIGNAL in the block
diagram. Fig. 8 shows the synchronizing RESET_SIGNAL in the
DSP. The synchronizing signal is used to synchronize the u
PLL
calculated in the FPGA by resetting it when the binary state of the
resetting signal changes.
B. Performance Measurement and Comparison
Fig. 9 shows that the cos(u
PLL
) calculated in DSP is in phase
with cos(u
PLL
) calculated in FPGA, thus successfully synchro-
nized with the PLL angle reference frame without incurring in
erroneous calculation at the resetting instants of the PLL reference
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Fig. 7. Block diagram for implementation of dq domain control in FPGA by
transmitting e
PLL
and resetting signal from DSP.
k
p
k
i
s
---- +
v
b
v
c
v
a
u
PLL
v
d
v
q
abc
dq 1
s
---
m
b
m
c
m
a
u
PLL
i
q

i
d

i
qr
i
dr
E H
i
(s)
E
E
E
abc
dq
H
i
(s)
K
d
K
d
PWM
s
b
s
c
s
a
m
b
m
c
m
a
i
dr
i
qr
e
PLL
Sine & Cosine
Look-up Table
e
PLL
1
s
---
e
PLL
RESET_SIGNAL
Fig. 8.
PLL
in synchronized with synchronizing signal RESET_SIGNAL.
RESET_SIGNAL
u
PLL
frame.
The time delay associated with the FPGA computation is
quantified in Fig. 10. All power converter current control
functions are programmed in the FPGA including the PWM.
Since the power converter switching frequency for the present
application is 40 kHz, we confirm all required computations are
completed within a single 25 s interrupt interval.
Fig. 9. cos(u
PLL
) synchronized as calculated in DSP and FPGA together with
RESET_SIGNAL.
RESET_SIGNAL
cos(u
PLL
) calculated in DSP
cos(u
PLL
) calculated in FPGA
Fig. 10. Computation time delay for proposed algorithm in FPGA.
21.8 s
C. Other Alternatives and Considerations
It is possible to compute all entries in the forward and inverse
Parks transformation without specifying the angular frequency
and reset instants nor the transformation angle directly. From
straight-forward trigonometric identities, all terms in Parks
transform may be computed from linear combinations of
u
PLL
( ) cos and u
PLL
( ) sin which are also characterized by much
lower signal bandwidth than the sawtooth angle reference. Such
implementation, however, requires one additional analog signal
channel between the DSP and FPGA.
V. SYSTEM PERFORMANCE
Fig. 11 shows a picture of the experimental set-up. Dc power is
provided by a 600 V Sorensen regulated dc power supply. The
filter inductor and capacitor are L
f
= 0.7 mH and C
f
= 10 F
respectively. A damper capacitor and resistor are C
d
= 60 F and
R
d
= 5 O. The inverter switching frequency is 40 kHz and the
current controller was designed with K
p
= 0.0059 and K
i
=
0.00036 with a bandwidth of 400 Hz and a phase margin of 52
o
.
An ADC prefilter is included to avoid aliasing problems in the
discretization. The proposed current control implementation by
transmission of e
PLL
is tested in grid-parallel mode, standalone-
mode and standalone-mode with unbalanced loads.
1442
Fig. 11. Experimental set-up for implementing the dq domain control.
A. Grid-Parallel Mode
For this test, the inverter voltage is first synchronized with the
grid voltage in terms of both amplitude and phase. After the
voltages are matched the inverter is connected to the grid for grid
parallel operation avoiding potential inrush currents at the inter-
connection instant. The current references are set to i
dr
= 4.2 A and
i
qr
= 5.1 A respectively and the input voltage is set to 600 V. Fig.
12 shows the grid voltage when the converter operates in grid-
parallel mode together with the injected current. The resonance of
the inverter current may originate on system interaction problems
between the inverter impedance and the grid impedance.
Fig. 12. Inverter phase voltage and current waveforms for grid parallel mode.
v
a
i
a
B. Standalone Mode
For this test, the inverter is disconnected from the grid but
supplies power to a local resistive load with 25 O. The current
references are set to i
dr
= 5 A and i
qr
= 0 A. The input voltage was
set to 550 V and it can be observed from Fig. 13 that the current
controller regulates the output phase current i
a
at 5 A peak,
resulting in 125 V at v
a
.
The change in implementation of the control algorithm by
transmitting e
PLL
instead of u
PLL
has removed the spikes in the
current and the voltage waveforms due to the sharp PLL angle
transitions.
Fig. 13. Inverter phase voltage and current waveforms for standalone mode with
balanced loads.
v
a
i
a
m
a
The stand-alone system was also tested under unbalanced
load conditions by removing resistor load in phase c. No changes
were introduced to the current control structure and system
currents and voltages are depicted in Fig. 14 and 15 respectively.
Fig. 14. Inverter phase currents for standalone mode with unbalanced loads.
i
a
i
b
i
c
Fig. 15. Inverter phase voltages for standalone mode with unbalanced loads.
v
a
v
b
v
c
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VI. SUMMARY
A distributed implementation of grid synchronization by PLL
and dq-domain current control has been presented using DSP and
FPGA. An implementation by direct analog transmission of the
PLL synchronization angle was presented first to illustrate the
problems associated to the sharp resetting of the synchronization
angle. The synchronization algorithm between DSP and FPGA
was then modified to transmit the e
PLL
along with a binary
resetting signal. Since e
PLL
has a much lower signal bandwidth
compared to the sawtooth PLL angle reference, the performance
in the latter implementation has shown better results. Experi-
mental results are included to confirm the improvement of perfor-
mance in the latter realization.
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