The distinction between Mobile and Desktop computing segments is not new.

There are several vectors in which these segments differ, two of which are relevant to our discussion: power dissipation and battery life Power, Power Density, and Thermal. The overall dissipated power, as well as the power dissipated by the chip per unit area, are important factors. Power generates heat. In order to keep transistors within their allowed operating temperature range, the generated heat has to be dissipated from its source in a cost-effective manner. These constraints limit the processor.s peak power consumption. Peak power consumption limits apply both to desktops and mobile computers. However, the mobile computer.s smaller form-factor and lighter weight decrease the mobile processor.s power budget2. Battery Life. Batteries are designed to support a certain Watts x Hours3. The higher the average power is, the shorter the time that a battery can operate. This constraint limits the processor.s average power consumption, which is a crucial factor for mobile computers but less relevant for desktop computers. DVO Slot - The GMCH DVO port interface supports a wide variety of third party DVO compliant devices (e.g. TV encoder, TMDS transmitter or integrated TV encoder and TMDS transmitter).The GMCH has two dedicated Digital Video Out Ports (DVOB and DVOC). Intels DVO port is a 1.5-V only interface that can support transactions up to 165 MHz. Some of the DVO port command signals may require voltage translation circuit depending on the third party device. Internal Thermal Sensor This section describes the new on-die Thermal sensor capability. . Overview The Thermal sensor functions are provided below: Catastrophic Trip Point: This trip point is programmed through the BIOS during initialization. This trip point is set at the temperature at which the GMCH should be shut down immediately with minimal software support. The settings for this are lockable. High Temperature Trip Point: This trip point is nominally 14C below the Catastrophic trip point. The BIOS can be programmed to provide an interrupt when it is crossed in either direction. Upon the trip event, Hardware Throttling may be enabled when the temperature is exceeded. Package Mechanical Information The Intel 855GM GMCH comes in a Micro-FCBGA package, which is similar to the mobile processors. The package consists of a silicon die mounted face down on an organic substrate populated with solder balls on the bottom side. Capacitors may be placed in the area surrounding the die. Because the die-side capacitors are electrically conductive, and only slightly shorter than the die height, care should be taken to avoid contacting the capacitors with electrically conductive materials. Doing so may short the capacitors and possibly damage the device or render it inactive. The use of an insulating material between the capacitors and any thermal solution should be considered to prevent capacitor shorting. An exclusion, or keepout area, surrounds the die and

capacitors, and identifies the contact area for the package. Care should be taken to avoid contact with the package inside this area. Intel 82801DBM ICH4-M The component contains the primary PCI interface, LPC interface, USB 2.0, ATA-100, AC97, and other I/O functions. It communicates with the Intel 855GM GMCH over a proprietary interconnect called the Hub Interface

****************************************************************************************** ******* Intel Centrino mobile technology is based on a new mobile processor architecture (Pentium M Processors), designed specifically for higher performance, at low power to enable extended battery life, thinner and lighter notebook designs. What is Micro-Ops Fusion? Micro-Ops Fusion is a technology that uses fewer CPU resources to execute operations than traditional microprocessors by merging CPU operations together prior to execution in order to increase performance and efficiency. When the micro-operations are fused they use less processor resources in order to handle the same number of operations. Two fused micro-operations occupy a single resource and thus they make the machine behave as a wider machine. Micro-ops fusion delivers efficiency in both performance and power management. Analogy: A taxi pooling multiple riders into a single trip to save time and energy. What is Advanced Instruction Prediction? Intel Pentium M processor also uses advanced instruction prediction, a technology that allows the processor to study the past behavior of programs and intelligently anticipate what instructions will be needed next. The processor can line up instructions for execution before a program requests them. By anticipating changes in program flow rather than merely responding to them, the processor improves performance and efficiency. Predicting branches correctly is one of the areas of high leverage for both performance and power. On top of the standard Bi-Model/Global predictor Intel Pentium M processor also includes a loop detector and an indirect branch target buffer. Intel Pentium M processor employs the best in class branch prediction mechanism. Analogy: A word processing program that completes a word after you type the first few letters, improving speed and efficiency. What is dedicated stack manager? Intel Pentium M processor also has a Dedicated Stack Manager, which significantly reduces the number of micro-operations required for the "overhead" of stack management inside the processor. Traditional processors repeatedly interrupt program execution to maintain their own internal accounting. Intel Pentium M processor uses sophisticated, specialized-hardware enabling the processor to execute program instructions without interruption, using less power. Certain instructions use the architectural stack as source of operands. In those instructions there's an overhead work of managing the stack on top of the actual operation that needs to occur. Typically those overhead operations are done using the main machine flow which is a very inefficient way from both power and performance perspective. There are advanced synchronization mechanisms that make sure that the stack pointer value is visible to the software just when it's

needed. What is the power-optimized processor system bus? Finally, Intel Pentium M processor micro-architecture has a Power-Optimized 400MHz Processor System Bus, which remains powered down until it senses incoming data form the chipset, allowing to the processor to consume less power. In a typical microarchitecture, a processor has its bus turned on even when it is not in use. With Intel Pentium M processor, portions of the bus are turned on only when they are needed. Architectural and circuit innovations enabled this power-optimized processor system bus technology which lowers power through reduced voltage swing and tighter buffer management. What is intelligent power distribution? Most machines employ some level of hardware clock gating to reduce power consumption. Intel Pentium M processor implements finer granularity hardware gating mechanisms that allows turning on hardware units partially based on program demand. Analogy: A motion sensor that turns lights on when you enter a room and shuts them off when you exit. Large, Power-Aware 1MB Secondary Cache? The processor also includes a 1MB secondary cache. The large cache allows a significant reduction in memory data latency providing a big performance improvement. The power-aware cache implements several features to reduce cache power consumption. Traditional microprocessors run the cache as fast as possible, the processor cache on the Intel Pentium M processor runs slightly slower to save energy and cut down on electricity leakage enabling longer battery life. Special circuit and micro-architectural innovations were implemented in order to reduce power consumption. For example the cache unit keeps track of the last entry that was accessed such that repeating accesses to the same location will not have to lookup the array, thus eliminating a high power operation. The processors 1MB power managed L2 cache, which contains roughly two-thirds of the transistors in the processor, is built with low-leaking transistors. Low-leaking transistors are somewhat slower, thus slightly increasing the cache access latency, but the significant power saved justifies the small performance loss. What is deeper sleep alert state? Deep Sleep and Deeper Sleep Alert States are very low power states the processor can enter during periods of inactivity while still maintaining its context. The Deeper Sleep Alert State is functionally identical to the Deep Sleep Alert State but at a significantly lower voltage providing added benefits of power savings and longer battery life. The Deeper Sleep Alert State is automatically enabled on the platform through the I/O Controller Hub component and the voltage regulator, so there is no user interaction required. This feature maintains processor performance characteristics while taking advantage of the increased power savings. What is Enhanced Intel SpeedStep Technology with Multiple Voltage / Frequency Operating Points? Mobile Intel Pentium 4 Processor-M supports Enhanced Intel SpeedStep technology allowing the processor to switch between only two core performance frequencies. Intel Pentium M processors add new capabilities to Enhanced Intel SpeedStep technology with multiple voltage / frequency operating points. This means that dynamic transitions will happen

at smaller intervals between the Battery-Optimized mode (lowest voltage / frequency) and the Performance-Optimized mode (highest voltage / frequency), enabling higher performance and lower power for each workload. With dynamic switching capability mobile systems can switch between the multiple operating points based on CPU utilization, without user intervention. The result is that the user observes higher performance and extended battery-life automatically. Enhanced Intel SpeedStep technology with multiple voltage / frequency operating points enables optimum performance at the lowest power whether connected to AC or Battery Power, resulting in a better user experience with no battery life degradation.

Explain the latest mobile packaging technology. Flip-chip packaging eliminated the wire-bond approach in favor of mounting the die directly to a substrate, improving power delivery and reducing impedance. The mobile Micro-FCPGA (micro flip chip pin grid array) and Micro-FCBGA (micro flip chip ball grid array) packaging technology provides significant improvements in power delivery and pin inductance compared to their predecessors resulting in dramatically improved performance. The packages incorporate separate power and ground planes and on-package capacitance needed at higher speeds - reducing board space for the implementation. Space savings contribute to smaller designs and more mobility. What is streaming SIMD extensions 2 (SSE2)? Intel Pentium M processor micro-architecture includes the new extensions to SIMD capabilities that MMX technology and SSE technology delivered by adding 144 new instructions. These instructions include 128-bit SIMD integer arithmetic and 128-bit SIMD double-precision floating-point operations. These new instructions reduce the overall number of instructions required to execute a particular program task and as a result can contribute to an overall performance increase. They accelerate a broad range of applications, including video, speech, and image, photo processing, encryption, financial, engineering and scientific applications. Explain the 0.13 micron Process Technology Microprocessors designed on the 0.13 micron technology enable Intel to design processors with the highest levels of performance, the lowest power consumption and at lower cost for all mobile PC segments. Intel's 0.13 micron technology features the world's fastest transistors; the smallest transistor gate; the thinnest gate oxide and the smallest SRAM cell in volume production today. These features combined deliver the highest performance and lowest power consumption across all Mobile PC segments. The 0.13 micron technology means that the size of lines (or spaces on the chip) is 0.13 microns. This higher density of transistors enables more computing power (i.e. Performance) and more features (i.e. Capabilities) to be packed within the same space, or less, giving you more functionality for your PC. More transistors equates to more computing power plus added functionality. Q: It seems that Intel is changing the way it measures performance (not leading with MHz), what can you tell me about this? A: Megahertz (clock speed) is only one aspect of performance in PC platforms and remains a reliable measure of relative performance within each architecture family. For example: Intel Centrino mobile technology at 1.6GHz outperforms an Intel Centrino mobile technology at1.3GHz. Examples of factors that influence platform performance are CPU architecture and frequency, usage models,

software applications, BIOS and different types of memory. Intel believes that for mobile PCs, benchmarks that simultaneously measure battery life and performance are the best indicator of the real end-user experience. MobileMark* 2002 is a benchmark used to evaluate notebook PC user experience by measuring both performance and battery life at the same time on the same workload. MobileMark* 2002 is a tool that measures notebook PC performance on popular business-oriented applications in the Microsoft* Windows operating environment. The productivity usage model provides computations representing today's business users using popular office productivity and content creation applications. This usage model reports a performance score and a battery life score.

Q: How do Intel Centrino mobile technology-based systems deliver high performance, even at relatively lower frequencies? A1a: There are many ways to influence a system's performance, one of which is the processor's MHz. Intel Centrino mobile technology benefits from a unique micro-architecture, optimized for the mobile segment, to deliver breakthrough mobile performance with low power characteristics through efficient execution and advanced power-saving techniques. A2b: The design focuses on three main areas, efficient execution engine, enhanced data bandwidth and advanced power control. This combination delivers the outstanding mobile performance that you ordinarily might associate with higher MHz, but at much lower power consumption. MHz remains the relative measure of goodness within each architectural family. A2c: Examples of 'Efficient Execution' include, Advanced Branch Prediction, Micro-Ops Fusion & Dedicated Stack Manager, 'Enhanced Data Bandwidth" includes Larger 1MB Cache, High Performance PSB, and Advanced Pre-Fetch Logic, while example of 'Advanced Power Control' include fine grain Aggressive Clock Gating, and Enhanced Intel SpeedStepTM Technology. The idea behind micro-ops fusion is to bundle micro-ops (decoded instructions) together before sending them down the pipeline to the execution units. The idea behind micro-ops fusion is that the pipeline is not used unless a fixed number of micro-ops are ready to be sent down the pipe, thus the efficiency of the overall pipeline is improved. Obviously the downside to this approach is increased latency, but as you will see with a number of the design decisions behind Banias, the power savings enable higher overall performance at the end of the day. +Banias' dedicated stack manager is another power saving tool integrated into the Banias architecture that is designed to manage stack pointers and other stack-related data. Remember that stacks are used to store information about the current state of the CPU including data that cannot be kept in registers due to limits in the number of available registers, thus a dedicated manager can help performance considerably. As usual, whenever efficiency is improved power consumption is optimized which is the case with Banias here as well. The combination of a very advanced branch predictor, micro-ops fusion and a dedicated stack manager make Banias a very interesting architecture. Despite having a 20 - 50% longer pipeline, Banias still maintains a significantly higher IPC than the Pentium III, which is not an insignificant achievement. Remember from our discussions about the Pentium 4 that IPC (Instructions executed Per Clock) is generally reduced by moving to a longer pipeline, but is made up for by the fact that longer pipeline architectures can reach higher clock speeds. With Banias, we have an architecture that already has a longer pipeline than the Pentium III, thus enabling higher clock speeds, all while boasting a higher IPC - you're in fact getting the best of both worlds with Banias.