Direct memory access (DMA) is a feature of modern computers that allows certain hardware subsystems within the computer

to access system memory independently of the central processing unit (CPU). Without DMA, when the CPU is using programmed input/output, it is typically fully occupied for the entire duration of the read or write operation, and is thus unavailable to perform other work. With DMA, the CPU initiates the transfer, does other operations while the transfer is in progress, and receives an interrupt from the DMA controller when the operation is done. This feature is useful any time the CPU cannot keep up with the rate of data transfer, or where the CPU needs to perform useful work while waiting for a relatively slow I/O data transfer. DMA channels can transfer data to and from devices with much less CPU overhead than computers without a DMA channel. Similarly, a processing element inside a multi-core processor can transfer data to and from its local memory without occupying its processor time, allowing computation and data transfer to proceed in parallel DMA can also be used for "memory to memory" copying or moving of data within memory. Principle A DMA controller can generate addresses and initiate memory read or write cycles. It contains several registers that can be written and read by the CPU. These include a memory address register, a byte count register, and one or more control registers. The control registers specify the I/O port to use, the direction of the transfer (reading from the I/O device or writing to the I/O device), the transfer unit (byte at a time or word at a time), and the number of bytes to transfer in one burst. To carry out an input, output or memory-to-memory operation, the host processor initializes the DMA controller with a count of the number of words to transfer, and the memory address to use. The CPU then sends commands to a peripheral device to initiate transfer of data. The DMA controller then provides addresses and read/write control lines to the system memory. Each time a word of data is ready to be transferred between the peripheral device and memory, the DMA controller increments its internal address register until the full block of data is transferred. Modes of Operation Burst Mode An entire block of data is transferred in one contiguous sequence. Once the DMA controller is granted access to the system bus by the CPU, it transfers all bytes of data in the data block before releasing control of the system buses back to the CPU. This mode is useful for loading program or data files into memory, but renders the CPU inactive for relatively long periods of time. The mode is also called Block Transfer Mode. Cycle Stealing Mode In the cycle stealing mode, the DMA controller obtains access to the system bus the same way as in burst mode, using BR (Bus Request) and BG (Bus Grant) signals, which are the two signals controlling the interface between the CPU and the DMA controller. However, in cycle stealing mode, after one byte of data transfer, the control of the system bus is deasserted to the CPU via BG. It is then continually requested again via BR, transferring one byte of data per request, until the entire block of data has been transferred. By continually obtaining and releasing the control of the system bus, the DMA controller essentially interleaves instruction and data transfers. The CPU processes an instruction, then the DMA controller transfers one data value, and so on. On the one hand, the data block is not transferred as quickly in cycle stealing mode as in burst mode,

but on the other hand the CPU is not idled for as long as in burst mode. Cycle stealing mode is useful for controllers that monitor data in real time. Transparent Mode The Transparent Mode takes the most time to transfer a block of data, yet it is also the most efficient mode in terms of overall system performance. The DMA controller only transfers data when the CPU is performing operations that do not use the system buses. It is the primary advantage of the transparent mode that the CPU never stops executing its programs and the DMA transfer is free in terms of time. The disadvantage of the transparent mode is that the hardware needs to determine when the CPU is not using the system buses, which can be complex and relatively expensive In a bus mastering system, both the CPU and peripherals can be granted control of the memory bus. Where a peripheral can become bus master, it can directly write to system memory without involvement of the CPU, providing memory address and control signals as required. Some measure must be provided to put the processor into a hold condition so that bus contention does not occur.

Bus Interfaces Different types of buses: ISA (Industry Standard Architecture) PCI (Peripheral Component Interconnect) USB (Universal Serial Bus) PCMCIA Industry Standard Architecture (ISA) is a computer bus standard for IBM PC compatible computers introduced with the IBM Personal Computer to support its Intel 8088 microprocessor's 8-bit external data bus and extended to 16 bits for the IBM Personal Computer/AT's Intel 80286 processor. ISA is the oldest of all buses and today's computers still have a ISA bus interface in the form of an ISA slot (connection) on the main board Designed to connect peripheral cards to the motherboard, ISA allows for bus mastering although only the first 16 MB of main memory are available for direct access. The 8-bit bus ran at 4.77 MHz , while the 16-bit bus operated at 6 or 8 MHz 8 Bit ISA Bus Connector

In the original IBM PC, there was only one Intel 8237 DMA controller capable of providing four DMA channels (numbered 0-3). These DMA channels performed 8-bit transfers and could only address the first megabyte of RAM. With the IBM PC/AT, a second 8237 DMA controller was added. This second controller performed 16-bit transfers. Each DMA channel has a 16-bit address register and a 16-bit count register associated with it. To initiate a data transfer the device driver sets up the DMA channel's address and count registers together with the direction of the data transfer, read or write. It then instructs the DMA hardware to begin the transfer. When the transfer is complete, the device interrupts the CPU. Peripheral Component Interconnect (PCI) Bus The PCI (Peripheral Component Interconnect) is a high performance Bus for interconnecting chips, expansion boards, and memory cards. A PCI architecture has no central DMA controller, unlike ISA. Instead, any PCI component can request control of the bus ("become the bus master") and request to read from and write to system memory. More precisely, a PCI component requests bus ownership from the PCI bus controller, which will arbitrate if several devices request bus ownership simultaneously, since there can only be one bus master at one time. When the component is granted ownership, it will issue normal read and write commands on the PCI bus, which will be claimed by the bus controller and forwarded to the memory controller using a scheme which is specific to every chipset. PCI functions with either a 32-bit or 64-bit address or data bus. The address and data buses are multiplexed to reduce the size of the edge connector. PCI Bus Performance PCI is the highest performance general I/O bus currently used on PCs. This is due to several factors:

Burst Mode: The PCI bus can transfer information in a burst mode, where after an initial address is provided multiple sets of data can be transmitted in a row. This works in a way similar to how cache bursting works. Bus Mastering: PCI supports full bus mastering, which leads to improved performance. High Bandwidth Options: The PCI bus specification 2.1 calls for expandability to 64 bits and 66 MHz speed; if implemented this would quadruple bandwidth over the current design. In practice the 64bit PCI bus has yet to be implemented on the PC (it does exist in non-PC platforms such as Digital Equipment's Alpha and is also found now on servers) and the speed is currently limited to 33 MHz in most PC designs, most likely for compatibility reasons. The Speed of the PCI bus can be set synchronously or asynchronously, depending on the chipset and motherboard. In a synchronized setup (used by most PCs), the PCI bus runs at half the memory bus speed; since the memory bus is usually 50, 60 or 66 MHz, the PCI bus would run at 25, 30 or 33 MHz, respectively. In an asynchronous setup, the speed of the PCI bus can be set independently of the memory bus speed.

PCI Bus Commands The following commands can appear on the C/BE pins in cycle T1. I/O Read Cycle: Data are read from an I/O device at address AD0-AD15. I/O Write Cycle: Data are written to an I/O device. Memory Read Cycle: Data are read from memory device. Memory Write Cycle: Data are written to memory device. Configuration Read: Configuration information is read from PCI device Configuration Write: Configuration information is written to PCI device. Memory Multiple Access: Multiple data are read from memory device. Dual Addressing Cycle: Used for transferring data to a 64-bit PCI device this only contains a 32bit data path. Line Memory Access: Used to read more than two 32-bit numbers. Memory Write with Invalidation: Same as line memory access, but used with write and bypasses write-back function of the cache. INTA Sequence: Get the interrupt vector from the interrupt controller. The interrupt vector byte is returned during a read operation. Special Cycle: Used to transfer data to all PCI components, e.g. processor shutdown.

PCMCIA Short for Personal Computer Memory Card International Association, and pronounced as separate letters, PCMCIA is an organization consisting of some 500 companies that has developed a standard for small, credit card-sized devices, called PC Cards. Originally designed for adding memory to portable computers, the PCMCIA standard has been expanded several times and is now suitable for many types of devices. There are in fact three types of PCMCIA cards. All three have the same rectangular size (85.6 by 54 millimeters), but different widths Type I cards can be up to 3.3 mm thick, and are used primarily for adding additional ROM or RAM to a computer. Type II cards can be up to 5.5 mm thick. These cards are often used for modem and fax modem cards. Type III cards can be up to 10.5 mm thick, which is sufficiently large for portable disk drives. As with the cards, PCMCIA slots also come in three sizes: A Type I slot can hold one Type I card A Type II slot can hold one Type II card or one Type I card A Type III slot can hold one Type III card or any combination of two Type I or II cards.

IEEE-488
IEEE-488 refers to the Institute of Electrical and Electronics Engineers (IEEE) Standard number 488. IEEE-488 comprises a bus on a cable, providing both a parallel data transfer path on eight lines and eight dedicated control lines. During the 1980s, a new layer was added to the IEEE488 standard, IEEE-488.2. The original standard was re-designated IEEE-488.1 GENERAL INFORMATION The IEEE-488 interface, sometimes called the General Purpose Interface Bus (GPIB), is a general purpose digital interface system that can be used to transfer data between two or more devices. It is particularly well suited for interconnecting computers and instruments. Some of its key features are: Up to 15 devices may be connected to one bus Total bus length may be up to 20 m and the distance between devices may be up to 2 m Communication is digital (as opposed to analog) and messages are sent one byte (8 bits) at a time Message transactions are hardware handshaked Data rates may be up to 1 Mbyte/sec Mechanical Specifications CONNECTOR The IEEE-488 connector is a 24-pin connector. Devices on the IEEE-488 bus have female receptacles; interconnecting cables have the mating male connectors.

INTERCONNECTION CABLING The IEEE-488specification limits the total length of all cabling used to interconnect devices on a common bus to 20 m, or 2 m times the number of interconnected devices (up to 20 m). Devices may be interconnected in a star or linear topology, or in a combination of the two, as long as the distance limits are observed. Electrical Specifications BUS LINES The 24 bus lines group into four categories: Data Lines - Eight lines used to transfer information (data and commands) between devices on the bus, one byte at a time. Handshake Lines - Three lines used to handshake the transfer of information across the data lines: DAV: Data Valid NDAC: Not Data Accepted NRFD: Not Ready for Data Bus Management Lines - Five lines used for general control and coordination of bus activities: ATN: Attention I FC: Interface Clear REN: Remote Enable SRQ: Service Request EOI: End or Identify Ground Lines - Eight lines used for shielding HANDSHAKING

The IEEE-488 bus uses three handshake lines in a We're ready - Here's the data - We've got it sequence to transfer information across the data bus. Before sending any data, the Talker verifies that NDAC is asserted (low) which indicates that all Listeners have accepted the previous data byte. The Talker then places a byte onto the data lines and waits until NRFD is unasserted (high), indicating that all Addressed Listeners are ready to accept the information. When NRFD and NDAC are in the proper state, the Talker asserts DAV (active low) to indicate that the data on the bus is valid. NRFD is used by the Listeners to inform the Talker that they are ready to accept the new data. The Talker must wait for each Listener to unassert this line (high), which they do at their own rates when they are ready for more data. This assures that all devices accepting the information are ready to receive it. NDAC, also controlled by the Listeners, indicates to the Talker that each device addressed to listen has accepted the information. Each device releases NDAC (high) at its own rate, but NDAC does not go high until the slowest Listener has accepted the data byte. This type of handshaking permits multiple devices to receive data from a single data

transmitter on the bus. All active receiving devices participate in the data handshaking on a byteby-byte basis and operate the NDAC and NRFD lines in a wired-or scheme so that the slowest active device determines the rate at which the data transfers take place. IEEE-488 FUNCTIONS When information is placed on the data lines, it can represent either a data byte or a command. If the Attention bus management line (ATN) is asserted while the data is transferred, then the data lines are carrying a multiline command to be received by every bus device. If ATN is not asserted, then a data byte is being transferred, and only the Active Listeners receive that byte. ADDRESSING The IEEE-488 standard normally permits up to 15 devices to be configured within one system. Each of these devices has a unique bus address, a number from 0 to 30. THE SYSTEM CONTROLLER The System Controller, usually a computer with an IEEE- 488 board installed, always retains ultimate control of the bus. When the system is first powered up, the System Controller is the Active Controller and controls all bus transactions. The System Controller may Pass Control to a device, making it the New Active Controller, which may then Pass Control to yet another device. Even if it is not the Active Controller, the System Controller maintains exclusive control of the Interface Clear (IFC) and Remote Enable (REN) bus management lines and can take control of the bus whenever it desires. IEEE-488.2 The IEEE-488.2 standard was developed to simplify the basic process of communicating with instruments. IEEE488.2 extends the 488 standard with code, format

RS 232 to be studied from Microcontrollers- Mazidi textbook Limitations of RS-232 RS-232 has some serious shortcomings as an electrical interface. Firstly, the interface presupposes a common ground between the DTE and DCE. This is a reasonable assumption where a short cable connects a DTE and DCE in the same room, but with longer lines and connections between devices that may be on different electrical busses, this may not be true. We have seen some spectacular electrical events causes by "uncommon grounds". Secondly, a signal on a single line is impossible to screen effectively for noise. By screening the entire cable one can reduce the influence of outside noise, but internally generated noise remains a problem. As the baud rate and line length increase, the effect of capacitance between the cables introduces serious crosstalk until a point is reached where the data itself is unreadable. Using low capacitance cable can reduce crosstalk. Also, as it is the higher frequencies that are the problem, control of slew rate in the signal (i.e., making the signal more rounded, rather than square) also decreases the crosstalk. The original specifications for RS-232 had no specification for maximum slew rate. Voltage levels with respect to ground represent the RS 232 signals. There is a wire for each signal, together with the ground signal (reference for voltage levels). This interface is useful for point-to-point communication at slow speeds. For example, port COM1 in a PC can be used for a mouse, port COM2 for a modem, etc. This is an example of point-to-point communication: one port, one device. Due to the way the signals are connected, a common ground is required. This implies limited cable length - about 30 to 60 meters maximum. (Main problems are interference and resistance of the cable.) Shortly, RS 232 was designed for communication of local devices, and supports one transmitter and one receiver. RS422 and RS485 When communicating at high data rates, or over long distances in real world environments, single-ended methods are often inadequate. Differential data transmission (balanced differential signal) offers superior performance in most applications. EIA has recently released new serial interface, RS-422 and RS-485. These standards were designed for highspeed communication. The RS-485 and RS-422 standards have much in common, and are often confused for that reason. RS-485, which specifies bi-directional, half-duplex data transmission, is the only EIA/TIA standard that allows multiple receivers and drivers in "bus" configurations. RS-422, on the other hand, specifies a single, unidirectional driver with multiple receivers. RS423 Serial Port Connector Pin Layout RS-423 is a serial communications standard that provides asynchronous communication capabilities, such as hardware flow control, software flow control, and parity check. It has been widely used for decades. Unlike RS-232, RS-423 is capable of data transmissions over long distances (up to 4000 Feet). RS-423 tolerates ground voltage differences between sender and

receiver. The maximum signal voltage levels are 6 volts. Ground voltage differences can occur in electrically noisy environments where heavy electrical machinery is operating. The following document describes the functions of the pins on the RS423 25 and 37 pin Sub-D connectors used in serial communications. The pins in the images are as viewed from the pin side (not the solder or printed circuit board side). The male sockets are used on the DTE (Data Terminal Equipment ) or PC side. The female sockets are on the DCE (Data Communication Equipment ) or Modem Side. Using the ActiveXperts ActiveComport you can send and receive data and control the RS423 port. 25 Pin connector (DB-25)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

GND TDA RDA RTSA CTSA DSRA GND RLSDA RTA RLSDB XTB TTB CTSB TDB TTA RDB RTA LL RTSB DTRA RL DSRB DTRB XTA

Shield Transmitted Data A Received Data A Request To Send A Clear To Send A Data Set Ready A Signal Ground Receive Line Signal Detect A Receive Timing A Receive Line Signal Detect B External Timing B Transmit Timing B Clear To Send B Transmit Data B Transmit Timing A Received Data B Receive Timing A Local Loopback Request To Send B Data Terminal Ready B Remote Loopback Data Set Ready B Data Terminal Ready B External Timing A

25 TM RS-422

Test Mode Indicator

RS-422, like RS-232, is used to connect only two systems. It uses differential, or "double ended" data transmission, which means that data is transmitted simultaneously on two wires between two stations independent of the ground wire. Each signal requires 2 wires with a ground present in the system. The advantage of this method over RS-232 is higher speeds and longer cable lengths 4000 feet at a 100K baud rate, for example. RS-485 RS-485 is an improved RS-422 with the capability to connect up to 16 devices (transceivers) on one serial bus to form a network. Such a network can have a "daisy chain" topology where each device is connected to two other devices except for the devices on the ends. Only one device may drive data onto the bus at a time. The standard does not specify the rules for deciding who transmits and when on such a network. That's up to the system designer to define. PXI PCI eXtensions for Instrumentation (PXI) is a rugged PC-based platform that offers a highperformance, low-cost deployment solution for measurement and automation systems. PXI combines the Peripheral Component Interconnect (PCI) electrical bus with the rugged, modular Eurocard mechanical packaging of Compact PCI and adds specialized synchronization buses and key software features. PXI also adds mechanical, electrical, and software features that define complete systems for test and measurement, data acquisition, and manufacturing applications. These systems serve applications such as manufacturing test, military and aerospace, machine monitoring, automotive, and industrial test. Hardware Architecture PXI systems are composed of three basic components chassis, system controller, and peripheral modules. The chassis provides the rugged and modular packaging for the system. The chassis contains the high-performance PXI backplane, which includes the PCI bus and timing and triggering buses.

PXI Timing and Triggering Buses PXI combines industry-standard PC components, such as the PCI bus, with advanced triggering and synchronization extensions on the backplane Using these timing and triggering buses, you can develop systems for applications requiring precise synchronization.

SCXI SCXI is a high-performance signal conditioning and switching platform for measurement and automation systems. Whether you need to measure sensors or raw signals, generate voltages or currents, monitor digital lines, or route signals with switching, SCXI provides a single, integrated platform for all of your signal conditioning and switching needs. An SCXI system consists of multichannel signal conditioning modules installed in one or more rugged chassis. You can choose from a wide selection of analog input, analog output, digital I/O, and switching modules to exactly fit your application needs. Difference between SCXI and PXI PXI stands for PCI eXtensions for Instrumentation. It is like the PCI bus, but extended. This means that extra connections are available to share signals between multiple PXI peripherals. SCXI stands for Signal Conditioning eXtensions for Instrumentation. Signal Conditioning is the general term for the process of making a signal more useful by improving its precision, accuracy, or signal-to-noise ratio. Think about a sensor/transducer such as a thermocouple. In order to get quality temperature readings, you need to amplify the thermocouple signal. You should also filter out high frequencies, because while noise is high-frequency in most environments, temperature changes almost always happen very slowly. SCXI can also handle switching, and has some multiplexer's in the background so that a separate ADC can capture the conditioned signals.

So, to put these two together, a real-world signal from a transducer goes into SCXI, which might then send the conditioned signal into a DAQ board in a PXI system. Another key difference is that a PXI bus directly communicates to an operating system on a computer, while SCXI only does things to signals and passes them on to DAQ devices. VXI A VXI system consists of a chassis, VXI instruments, a slot 0 card, and a resource manager. The slot 0 card controls the VXI backplane. The resource manager configures the modules for proper operation whenever the system is powered on or reset (the slot 0 card can also be the resource manager). The chassis holds the VXI instruments, the slot 0 card, and the resource manager, and contains the VXI backplane. VXI instruments can be either message-based or register- based. A message-based instrument is generally easier to use than a register-based instrument. While a register- based instrument is generally faster than a message-based instrument. The VXI interface uses an embedded VXI controller (in slot 0) to access the VXI instruments over the VXI backplane.

IMPORTANT QUESTIONS 1. Describe the principle and different modes of operation of a DMA 2. Describe key features and the Handshaking process of IEEE 488 3. Explain RS232 along with pin diagram of 25pin connector 4. Write about SCXI and PXI along with their differences 5. Explain about PCMCIA 6. Explain the PCI Bus in detail 7. Draw and explain the pin diagram of an 8 bit ISA bus connector