CHAPTER 7 DIGITAL SWITCHING SYSTEMS A switching system is called digital when tlrc input to and output fiom the

swiiching systen can directly supporl of the digital signal. Many basic element's the digital switching system and its operation are vell sinilar 1o the sloredprogramcontrol (SPC) switching system. The function of the digital-switchingnetwork rs to comect pails of chafirels. So that rnforrnatronanivirg al the sultching centerin a particular channelon one PCM multiplex systen can be passedto some other channelon an outgoing PCM mr hplex systems.To achievethe switching two types of switching can be used. These are called dn1eswrtcling and spaceswitching. In digiial datacommunication( analogor digital signal) a lundanental requireNent is that the recei|cr should kno\r and synchfonolrs the startingtime and duration of each bit that it receives.To meet this requirementasynchronous t llansn11sslon used, are It ^ nodefn dig'tal swiiohing system (Electronic switcling systen l) empioys a number of processors. rs pufely 'Ihe i)pe of control ls clectronic ri1 operation and the switching processis by time divisjon/ digrtal transnission. usesPCM. Figure 7.I showsthe digital slvitching system. stoledprogram common contol and the net\,vork

Dleira I

Figxre 7.1. Digital s*,itching system 7.1 Spacedivision s\Yitching from emh other spalially. A crosspoints',{itchis In spacedivision switching, the paths in the circuit are separated refened to us as a spacedivision switch, becauseit moves bit stream ftom one cfcuiirbus to another.Ior large group of outlets, considemblesavingsin total crosspointscan be achievedif each inlct can accessonly a limilcd nunber ofoutlets. Such situationis called linited availabiliq'. Bt overlapping the available ontlet groups lor vadous inlet gloups, a technique called "gradlng" is established. Rectangular crosspointarray is an exampleofgrading. 11ls inefiicient to build conplete exchangesin single stages.Single stage can only be useclto interconnectone particular inlet outlet pair. Also the number of crosspointsgro\,r' the squareof the inputs for gradng. N (N-1)/2 as Iorat angulal araJ' and N (N-1) for a squarearray. Also the large nunbel of crosspoints each rnlei and outlei on paths.Therefore,ii is usu.rl1{)build cxchangcsin 2 line rnply a large anrountofcapacitive loading on the message or 3 stagesto reduce the number of crosspointsand to provide altemative paths. The shadng ol clossporntstbr potentialpathsthrough the switch is accomplrshed multiple stageswitching. by I'igrLrc7.2 shows the 3 stageswitching skuctureto accommodate128 inputs and 128 outputs $'rth 16 first and last srage.

Figule 7.2 Tlnee stages\:r.rtchrng stlucture The structufeprovidespath for N inlets and N olrtlets.The N input lines are drvrdedinto N/ n groupsofn lincs eech Lach group oln mputs is accommodated an n- input, k-output nlatrix. I'he outpul matdces are identical to $e by lnput rnatlices except they are reversed.The intermediatestagesare k in number and N,rn inputs and N,rn outputs. Thc inlcBlagc connectio1$ are oftm called junctors. Each of the k paths utilizes a scparatcccnter slageanay. An arbilrar)'inpu! can find k altemateoutput. Thus nultjsiage shuctureprovides altematepaih. Also ihlj sr'itc|jng link is connected a limited number ofcrosspoints.This enablesthc minimized capacitjveloading. to l l \ e t o . a n . r m b e r oc r o - . p o r l . N , l o _l " t d g e ,

N.=2NK+K(N/n)l

$,hereN = number ol ulets-outputs n = sirc olcach inlet-outlet group k = numbefoiseoond stage "' 2NK : nunber of cmss pojnts ir1 I anal2'd stage (Nm)r.- number olfioss points in eacharray olsecond stage k(Nin)'= nunbcr ofcross points in secondstage In space division s\.rtching crosspoirltsare used to establish a specific connection bctween 2 subcribc^. lhr crosspomts multistage spaceswitchesassignedto a particular connectionis dedicatedto thai conncclion lor ils of dufation.Thus the crosspoints can not be shared. 7.2 Time division switching Time division s$itching involves the sharing of crosspointsfor shorter peiods of timc. Timc division s*,ilchrDg Lrscstin1e division nultiplexing to achieve switchng. Two popular methods that afe used in trme division Lnulliple\ing are: time slot interchange(lsl) and'lDM bus. In ordinary time dinsion multipLexjng.the datareaches lhe ou4rut rn the same order- they sent. But TSI changesthe ordering of slots basedon the desired connections. as The demultiplexer separates the slots and passesthem to the proper outputs. The TDM uses a control Lrnit.The control unit opensand closesthe gatesaocordingto the switchingneed. Figure 7.3 shows simple analogtime division swjtching structue. The speechrs carried as PAM analog samplesof PCN4 digilalsanples. occuring at 125ps iDtervals. WheDPAM samples s\\,i1ched a lilne divisionmanner. are in t|e swiichrng is called analog trme division switching. If PCM binary sanples afe switched, then the s$'ilching is c.rllcd digital time division switching. A srngle snitching bus suppons a multiple number of connectronsby rntefleavingPAM sampleslionl recerveline jnterlacesto fianslnjt ljne interl-aces. There two cyclic control slores '1hc first conijol slorc controls gaiing olinputs onto the bus one samplcat a limc. The secondconlrol slore opcratcs in slrchronism widl the first and selects the approp ale output 1me for each input sample. lhe selection of rs in1et,'outlet controlledby various ways.

17.1l

o
I'igue 7.3. Analog time djvision switching structure The L\cliL co trol rs organized by using Modulo-N counter and k to 2' decoder as shown in Figure 7.4.

i$il*
<t-

-f-igure 7.4. Cyclic control The k and N are related by logr N =k whereN = number of iniets/outlets h = decodersize I : gives the lowest integer.It meansk may be assuned lowest integeror more than that. This kind ol switching is non-blockingbut lack of full availability as it is noi possibleto connecrinlet to any outlel. The switching capacityor nlrmberof channelsupported cyclic controlled systemis by C=l25psec/t, I25 p sec is the time taken to scan iDletand outlet and ts is the tirne in p secto set ut connection. I.Lrllavailabiliry can be achievedif any one conirol is made memory based.Ifthe mput side is cyclically switched and the outletsar:econnectedbasedon the addresses ofdre outlets storedin contiguouslocation is relletTed input as input driven. If the outlets are cyclically switched,the switch is refered as output controlled oulput controlled or driven. As the physical connectionis established betweenthe inlet and the outlet througb the comnon bus fbr the duration of one sample transfer, the switching technique is k-no$rl as time division space multjplexing. For this sysrenl C = 125F sec/ [ti +tn,+ ti + t( ] t7.21 where t,,, = time to read the control memory

tj = timeto decode address select inletandoutlet and the = time to incrementthe modulo N cormter t i = lime to transferthe sample The capacity equationsare valid only for an 8 kHz sampling and non folded network but can be used for folded is network\\'ith certamchanges ntwork.The switchingcapacity the rnemorycontrolled equalto N. Use of in in cycllccontrolin inputor ouQutswitches restricts number on ofsubscribers the system.

No restricdonson subscribernumber and full availability of ile switching systemcan be achrevedby designlnga switchrng configuration wifi conhol memory for controlling both inieis and outlets. This configuration retened to as nelnory confiolled time division spaceswitch is shown in Figure 7.5. and an outlet ad&ess,the conftol memory width is 2 logrN . As eachword ofthe control memory has inlet address 'Ihe confol memory words are readoutone after another.The modulo counteris updatedat the clock rate. For the path scllLpof i- th niet andj th outlet, the addresses entel-ed control memory and path is nlade. Then the are in are location is markedbusy. When conveffation is terminated,the addrcsses replacedby null values and localiorl is Hence

Cl-(125/t,)psec lvhere = ti+ tn + td+ t, ts

t7.31

Decoder

I Deccder

ManoryDaiaReg (MDR) sler

>
Addrcss sler Req lvl^RMemory

Figure 7.5. Memory control for both inlet and outlet Tbe switching natrix above is referred to as time multiplexed swiiching as d1e swltch ln this conliguratior is replcated once for eachtime slot. multiplexed signals usually require switching between time slots as well as betrveen The digital time divririor? physrcal lines. The switching between time slots are called time switching. The time division switch can be conuolled in 3 ways. The basic requirement of time division switching is that ihe transler oI inlomation ariving at in a time slot ol one input link to other time slot of any one of output 1ink.A completl3 ofpulses. a1T1l1ng each actjve inpui |ne is sel at known as a fiame. The ftame rate is equal to the sample mte of each line. A lime switch opemtesby writing data into and reading data out of a single rnemory. Tn the processthe ulonnalion in selectedtrme slots is interchansed shown in Fisure 7.6. as

I g-fe

-.rr.

I rrre .'nt rrterchange operatror .

Ln I SI operation,inputs are sequentrally contolled and outputs are selectirly controlled The RAM have several nemory locations,each size is the sameas ofsingie time slot,

Figure 7.7 showsthe genenl arrangement ofthe time division switching.

Flgur-e 7.7. Ilmctional diagramofthe time division switching The serialto parallel and palallel to serial convertera1eusedto wnte the data ll1tothe mcmory and readthe dataoul of the memory. For convenience,2 MDR are sho$n, but MDR is a single register.Gating mechanisn rs used to connectthe inlet/outletto MDR. The input and output lines are connecledto a high-speedbus through input and output gates.Each input gateis closedduing one ofthe four time s1ots. During the sametime s1ot, only one lnput gateis closed.This parf ol gates allows a bulst of data to be transferredlrom one inpui line to a specific output line through the bus. The control tulit opensand closesthe gatesaccordingto switchltg need. Tbe time division time switch may be controlled by sequential \\.ritelrandonr rcad or fandonl wrrte/sequentlal read. Figure 7.8 depicts both modes of operationand indicateshow the memories arc accesscd to tfanslateinfomation ftom time slot 2 to time slol 16. Both methodsuse a cyclic control. Ligure 7-8(a) implies that specific memory locations are dedicatedto respectivechannelsof the incoming TDM l1nL.
Illl

-NT

va-l

t NI-- l

Figure 7.E (a) Sequential write/randomread, (t) random*rite/sequentjal l ead

Data are storedin sequentiallocationsin memory by incrementingmodulo N counler with every tilne slot. Thus lncoming data during time slot 2 is storedin the secondlocationwithin the memory. On output, informationretrievedfiom the control storespecifieswhich address to be accessed that particular is for time slot. Thus 16-thword ofcontrol storecoDtains number 2, implying tlat the contentsofdata slore the address is transfer to the output link during outgoing slot 16. 2 red Randomwite/sequential read mode ofoperation is oppositeto that ofsequontjalwrite/raldon r.ead. Incoming dataare written into the memory locationsas specifiedby the control storebLltoutgoing data:ue retrievedsequentiallyunder control ofan outgoingtime slot counter.The dala receivedduring time slot 2 is written directly into data storeaddress16 and it is retrieveddlLringoutgoing TDM channelnumber 16. 7.3 Two dimensional digital switching Coinbination the time and spacoswitches of leads a configuration achieved to that both tine slot interchange and samplcs$'itching across mlnl$. Theseslructures alsopermit a largenumberoI simultaneous connections bc to supported a giveniechnology. fbr Largedigital switches rcquireswitching operations both a spacc in and a tinr di]nension. The incoming and outgoing PCM lighways arespatially separate. s\\'iiching The networkmusrbe able10 r'eceilePCM samples liom one time slot and retransmit them in a dlfferenttime slot. This is known as lirnc Thustheswitching switchjng. net\:r,ork pedo1m must bothspace time switching. and Thespace switching t'me switching and may be accomplished rnanyways.A two stage in cornbination switchmay be organized with time switch as first stageand spaceswilch as secondstage01 vice versa. The fesulting conligurations calledtime space (TS.)or spacetime (ST) switches are respecti\,ely. Threestagetime and spece conbinations ofTST and STSconfigurations morepopularand flexible.Very largcdivisionswitches are includc manycombjnations time and space ol switches. T).'trical configuratrons TSST,TSSSST TSTSTSTS. are and These swrtches suppofi 40000linesor moreeconomically. Thegeneral blockdiagram shownin Figure7.9 is Thc marntaskof the switching pafi is to jnterconnect incomingtrme slot and an outgoing an time siot.The unit responsiblc this lunctron thegroupswitchlbr is In Figure7.9,ihe subscrjber makesa 1ocal to B. The controlunrthasassigned 3 to thecall on its rvayinlo call slot thegfoupswitch,andtime slot I on its way out ofthe groupswitch(to B). This is maintained dulingcntirecalt.

t' \ -.-/l l I x
Figure 7.9 Cencralblock diagramofcombined switching 52a.e rt'i|.fr (Figure 7.10, usesa spacearay to provide switchrng.Generally thc spaceswitch consjstsof a matrix M x N swilching points where M rs number ofinlets and N is numbel ofoutlets. A connectionbet\\,een inlet and an an outlct is made by simple logic gates(AND gates).As logic gatesarc unidirectional,t$o pathsthrough swiichlng nutfix n,ust be established to accommodate a two-way conversation. The logic gate array can serl'e fbr concentration, expansionor distr:ibution dependingon M is larger, smaller or equal to N. Fi$re 7.10 sho$'sonly l \,'ojcedirection.Flowever,the corresponding componentsare avajlablefor the oppositedirection too. A nrnnberof M, ofX slot muftiplexers,provide the inputs and the outletsare connected N. X slot demultiplexers. to The gate selectmemory has X locations.The word containinginlomation about which crosspoint is to be enablcd is decodedby the translator-During each intemal time s1ot,one qoss lroint is activated.In the shili to the nexi inlerval lime slot- thc contol memory is incrementedby one step, and a new dosspoinl pattun is fbrned in the

Figure 7.10. Spaceswitch Time s.,Nitch !'igure 7.11 shows the block diagram of time switch. Each incomng time slot is storedin sequmcein a speechmemory(SM). The control m,jmot' (CM) detenninesin wlich order the time slots arc to be read fiom SM-

TITM-IT

Fig 7.1i. Time switch. (Figure 7.12). The spaceanays have N inlcls and N oullets. ,pdce (TS) Srritchirg consistolonly two stages l\.rtb T slots is introduced.Each TSI is provided \\'ith time slot mcmorics lor eachinlet line, a time slot interchanger (not showr). Simjlarly a gate selectmemory needsto be povided for the spacearray (not shown). The uansmission of signals is calaied out from senderto receiver tltough multiplexer input and demultiplexef ouFut. A hybrid anangementis neededto isolatethe transmittedsignal fiom ile receivedsignal.Tlrc basic lunclron ofthe time switch is to delay infomation in arriving time slots until the desired outpnt time slot occurs. Let the communication take place between subscriberA and B. A is assignedtime slot 2 and line 7 and B rs assjgned time slot 16 and line 11. Then the signalmoved fion time slot 2 to time slot 16 by the time slot exchangef and is transfered from line 7 to line 11 in the space array. Similarly, the si$al originated by B is moved fiom slot 16 to slot 2 through line 11 to 8. 'Iine

Figure 7.12. Time Space(TS) switching The cyclic control and gate selectmemory containsinformation neededto specify the spacestageconiguratron lbr eachrndividual time slot ofa ilame. The time stagehasto prcvide decaysranging ftom one time slot to a full lianre. that speclfiesinterstagelink numbel to output link. Dulng each outgoing time s1ot,control inlomation is accessed Dunng other time slots,the spaceswitch is completelyreconfiguredto supportother conneltionsLet each time slot interchangerhave T slots. Il the spacearray is a N x N, then thl3 simultaneousconnectjons possibleis NT. IIT=128 and N=16, 204E connections This slructureis not free olblocking. The can be supported. confol store is a parallel end around shift register.lfspace array is at the inlet side and time switch is at the output (ST) switching.ST and 1S arangenents a1eeqLrally effective. side,the smrchrreis referredto as space-time 'fhe blockingprobabiliry ofTS switching is calculatedas follows:

Theprobability a subscriber is active= p/ T that A

[7.4]

link is b sy measurod Erlangs. in wherep = fiactionof time that a parlicular I .ndmber nme"lorsin a lidme. oand cost savings can alsobe achieved. The n]ultiplestages overcome limitations the individuals{.itches the of used in digital arc TST,STS, TSST, TSSSSTand TSTSTSTSTSTSTS the switchingsysten configuraiions switching systemFigure7.13 showsile STSswrtching In STS stNitching, time stageis sandwiched the between two space arrays. PCM highways. retworl< M incomjng outgoing ibr and

,1

'1d

_itI

Frgure7.13 STS switching structule. The pnncrpal opention ofTST switching is shown in Figure 7.14. E

ecuJ
l r g ue -.11 f h e p | | n c i poe T S T . u ' r c \ i n g . lI

which explains transfer signals the of lrom inlet to outlel is shownin Figure7.15. The functional block diagram The infornation arriving at the incoming link of TDM channel is delayed in the inlet times stage until an path through the spacestageis available.Then the information is transferredthroughthe spacestageto appropriate time slol occurs. Any space Herethe inforrnation helduntil thedesired is outgoing theappropdate outlettime stage. in a The spacestageoperates a t1medivided fashion, stagetrme slot can be used to establish connection. pathsbetween prescibedinput and output a of independently the extemalTDM links. Therearemanyaltemative unlike a two stagenetwork which hasonly one lixed path.

TDM

TONl

116

2l

121 21

J+- r t Figue 7.15 TST switching stmcture.