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Code No: D109115508 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD M.Tech I Semester Regular Examinations March 2010 DIGITAL SYSTEM DESIGN (Common to Embedded Systems, DS&CE, DE&CS, VLSI System Design / VLSI / VLSI Design, Embedded System & VLSI Design, VLSI & Embedded Systems, Electronics & Communication Engineering, Systems & Signal Processing) Time: 3hours Max.Marks:60 Answer any five questions All questions carry equal marks --1. 2. 3. a) Derive state machine chart for binary multiplier? Discuss about designing with programmable logic devices? For the circuit shown below generate test pattern for locating a , an S-a-0 at point P1 using D-algorithm.

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For the circuit shown below generate the test pattern to detect an S-a-1 fault at P2 using path sensitization.

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Define the terms failure and fault? Discuss the different fault models? Discuss about any one method of fault diagnosis in sequential circuits using an example? Cont.2

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Code No: D109115508 6.

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Minimize the following function by II SC algorithm. f = 001210 + 001121 + 001001 + 001011 + 011122 + 011221 + 101000 + 101010. How many cubes have been processed to get the final result? Explain how incompletely specified machines are simplified? Write about the following: a) Races b) Hazards. ******

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