Introduction

Polish-American physicist and inventor Julius E. Lilienfeld filed a patent in 1926, "Method and Apparatus for Controlling Electric Currents," in which he proposed a three-electrode structure using copper-sulfide semiconductor material. Today this device would be called a field-effect transistor. While working at Cambridge University in 1934, German electrical engineer and inventor Oskar Heil filed a patent on controlling current flow in a semiconductor via capacitive coupling at an electrode essentially a field-effect transistor. Although both patents were granted, no records exist to prove that Heil or Lilienfeld actually constructed functioning devices. The field-effect transistor (FET) is a transistor that uses an electric field to control the shape and hence the conductivity of a channel of one type of charge carrier in a semiconductor material. FETs are sometimes called unipolar transistors to contrast their single-carrier-type operation with the dual-carrier-type operation of bipolar (junction) transistors (BJT). The concept of the FET predates the BJT, though it was not physically implemented until after BJTs due to the limitations of semiconductor materials and the relative ease of manufacturing BJTs compared to FETs at the time.

History
Main article: History of the transistor The field-effect transistor was first patented by Julius Edgar Lilienfeld in 1925 and by Oskar Heil in 1934, but practical semi-conducting devices (the JFET, junction gate field-effect transistor) were only developed much later after the transistor effect was observed and explained by the team of William Shockley at Bell Labs in 1947. The MOSFET (metaloxidesemiconductor field-effect transistor), which largely superseded the JFET and had a [1] more profound effect on electronic development, was first proposed by Dawon Kahng in 1960.

Basic information
FETs are majority-charge-carrier devices. The device consists of an active channel through which majority charge carriers, electrons or holes, flow from the source to the drain. Source and drain terminal conductors are connected to the semiconductor through ohmic contacts. The conductivity of the channel is a function of potential applied to the gate, referred to the source. The FET's three terminals are:
[2]

Source (S), through which the majority carriers enter the channel. Conventional current entering the channel at S is designated by IS. Drain (D), through which the majority carriers leave the channel. Conventional current entering the channel at D is designated by ID. Drain to Source voltage is VDS. Gate (G), the terminal that modulates the channel conductivity. By applying voltage to G, one can control I D.

More about terminals

Cross section of an n-type MOSFET

All FETs have gate, drain, and source terminals that correspond roughly to the base, collector, and emitter of BJTs. Most FETs also have a fourth terminal called the body, base, bulk, or substrate. This fourth terminal serves to bias the transistor into operation; it is rare to make non-trivial use of the body terminal in circuit designs, but its presence is important when setting up the physical layout of an integrated circuit. The size of the gate, length L in the diagram, is the distance between source and drain. The width is the extension of the transistor, in the diagram perpendicular to the cross section. Typically the width is much larger than the length of the gate. A gate length of 1 m limits the upper frequency to about 5 GHz, 0.2 m to about 30 GHz. The names of the terminals refer to their functions. The gate terminal may be thought of as controlling the opening and closing of a physical gate. This gate permits electrons to flow through or blocks their passage by creating or eliminating a channel between the source and drain. Electrons flow from the source terminal towards the drain terminal if influenced by an applied voltage. The body simply refers to the bulk of the semiconductor in which the gate, source and drain lie. Usually the body terminal is connected to the highest or lowest voltage within the circuit, depending on type. The body terminal and the source terminal are sometimes connected together since the source is also sometimes connected to the highest or lowest voltage within the circuit, however there are several uses of FETs which do not have such a configuration, such as transmission gates and cascode circuits.

FET operation
See also: Field effect (semiconductor)

IV characteristics and output plot of a JFET n-channel transistor.

The FET controls the flow of electrons (or electron holes) from the source to drain by affecting the size and shape of a "conductive channel" created and influenced by voltage (or lack of voltage) applied across the gate and source terminals (For ease of discussion, this assumes body and source are connected). This conductive channel is the "stream" through which electrons flow from source to drain. In an n-channel depletion-mode device, a negative gate-to-source voltage causes a depletion region to expand in width and encroach on the channel from the sides, narrowing the channel. If the depletion region expands to

completely close the channel, the resistance of the channel from source to drain becomes large, and the FET is effectively turned off like a switch. Likewise a positive gate-to-source voltage increases the channel size and allows electrons to flow easily. Conversely, in an n-channel enhancement-mode device, a positive gate-to-source voltage is necessary to create a conductive channel, since one does not exist naturally within the transistor. The positive voltage attracts free-floating electrons within the body towards the gate, forming a conductive channel. But first, enough electrons must be attracted near the gate to counter the dopant ions added to the body of the FET; this forms a region free of mobile carriers called a depletion region, and the phenomenon is referred to as the threshold voltage of the FET. Further gate-to-source voltage increase will attract even more electrons towards the gate which are able to create a conductive channel from source to drain; this process is called inversion. For either enhancement- or depletion-mode devices, at drain-to-source voltages much less than gate-to-source voltages, changing the gate voltage will alter the channel resistance, and drain current will be proportional to drain voltage (referenced to source voltage). In this mode the FET operates like a variable resistor and the FET is said to [3][4] be operating in a linear mode or ohmic mode. If drain-to-source voltage is increased, this creates a significant asymmetrical change in the shape of the channel due to a gradient of voltage potential from source to drain. The shape of the inversion region becomes "pinched-off" near the drain end of the channel. If drain-to-source voltage is increased further, the pinch-off point of the channel begins [5] to move away from the drain towards the source. The FET is said to be in saturation mode; some authors refer to it [6][7] as active mode, for a better analogy with bipolar transistor operating regions. The saturation mode, or the region between ohmic and saturation, is used when amplification is needed. The in-between region is sometimes considered to be part of the ohmic or linear region, even where drain current is not approximately linear with drain voltage. Even though the conductive channel formed by gate-to-source voltage no longer connects source to drain during saturation mode, carriers are not blocked from flowing. Considering again an n-channel device, a depletion region exists in the p-type body, surrounding the conductive channel and drain and source regions. The electrons which comprise the channel are free to move out of the channel through the depletion region if attracted to the drain by drain-to-source voltage. The depletion region is free of carriers and has a resistance similar to silicon. Any increase of the drain-to-source voltage will increase the distance from drain to the pinch-off point, increasing resistance due to the depletion region proportionally to the applied drain-to-source voltage. This proportional change causes the drain-to-source current to remain relatively fixed independent of changes to the drain-to-source voltage and quite unlike the linear mode operation. Thus in saturation mode, the FET behaves as aconstant-current source rather than as a resistor and can be used most effectively as a voltage amplifier. In this case, the gate-tosource voltage determines the level of constant current through the channel.

Surface conductance and band bending The change in surface conductance occurs because the applied field alters the energy levels available to electrons to considerable depths from the surface, and that in turn changes the occupancy of the energy levels in the surface region. A typical treatment of such effects is based upon a band bending diagram showing the positions in energy of the band edges as a function of depth into the material. An example band-bending diagram is shown in the figure. For convenience, energy is expressed in eV so energy is expressed in volts, avoiding the need for a factor q for the elementary charge. In the figure, a two-layer structure is shown, consisting of an insulator as left-hand layer and a semiconductor as righthand layer. An example of such a structure is the MOS capacitor, a two terminal structure made up of a metal gate contact, a semiconductor body (such as silicon) with a body contact, and an intervening insulating layer (such as silicon dioxide, hence the designation O). The left panels show the lowest energy level of the conduction band and the highest energy level of the valence band. These levels are

"bent" by the application of a positive voltage V. By convention, the energy of electrons is shown, so a positive voltage penetrating the surface lowers the conduction edge. A dashed line depicts the occupancy situation: below this Fermi level the states are occupied and above it they are empty, assuming zero temperature.[clarification needed] At operating temperatures, however, some electrons populate the conduction band, and some vacancies (holes) populate the valence band. Bulk region The example in the figure shows the Fermi occupancy level in the bulk material beyond the range of the applied field as lying close to the valence band edge. This position for the occupancy level is arranged by introducing impurities into the semiconductor. In this case the impurities are so-called acceptors which soak up electrons from the valence band becoming negatively charged, immobile ions embedded in the semiconductor material. The removed electrons are drawn from the valence band levels, leaving vacancies or holes in the valence band. Charge neutrality prevails in the field-free region because a negative acceptor ion creates a positive deficiency in the host material: a hole is the absence of an electron, it behaves like a positive charge. Where no field is present, neutrality is achieved because the negative acceptor ions exactly balance the positive holes. Surface region Next the band bending is described. A positive charge is placed on the left face of the insulator (for example using a metal "gate" electrode). In the insulator there are no charges so the electric field is constant, leading to a linear change of voltage in this material. As a result, the insulator conduction and valence bands are therefore straight lines in the figure, separated by the large insulator energy gap. In the semiconductor at the smaller voltage shown in the top panel, the positive charge placed on the left face of the insulator lowers the energy of the valence band edge. Consequently, these states are fully occupied out to a so-called depletion depth where the bulk occupancy reestablishes itself because the field cannot penetrate further. Because the valence band levels near the surface are fully occupied due to the lowering of these levels, only the immobile negative acceptor-ion charges are present near the surface, which becomes an electrically insulating region without holes (the depletion layer). Thus, field penetration is arrested when the exposed negative acceptor ion charge balances the positive charge placed on the insulator surface: the depletion layer adjusts its depth enough to make the net negative acceptor ion charge balance the positive charge on the gate. Inversion The conduction band edge also is lowered, increasing electron occupancy of these states, but at low voltages this increase is not significant. At larger applied voltages, however, as in the bottom panel, the conduction band edge is lowered sufficiently to cause significant population of these levels in a narrow surface layer, called an inversion layer because the electrons are opposite in polarity to the holes originally populating the semiconductor. This onset of electron charge in the inversion layer becomes very significant at an applied threshold voltage, and once the applied voltage exceeds this value charge neutrality is achieved almost entirely by addition of electrons to the inversion layer rather than by an increase in acceptor ion charge by expansion of the depletion layer. Further field penetration into the semiconductor is arrested at this point, as the electron density increases exponentially with bandbending beyond the threshold voltage, effectively pinning the depletion layer depth at its value at threshold voltage.