Вы находитесь на странице: 1из 3

2007 IEEE INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS

2007 IEEE INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS

A Low-Voltage Sub-1V CMOS Bandgap with Modied Differential Pair


Anurup Mitra (anurup@bits-pilani.ac.in), Junaid Yousuf (junaid@bits-pilani.ac.in)

Abstract This work proposes a new CMOS bandgap which can operate down to 0.95V power supply. The reference voltage generated can be any value upto the power supply. The variation of this voltage with temperature can be made very small over a temperature range of 150 C degrees right down from 0 C upto 150 C. The circuit has been simulated using a UMC 0.18 process. The issue of the input common mode voltage has been circumvented by using a simplied differential pair. Index Terms low voltage bandgap, temperature independence.

I. I NTRODUCTION HERE are two features of the proposed bandgap which sets it apart from conventional designs. First, it uses resistive weighting of PTAT and CTAT parameters, and this allows the setting of the reference voltage to any value. Second, it uses a simplied differential pair one without the tail current source for easier biasing at low power supplies. The absence of the tail current source implies that the inputs to the feedback amplier can directly be tapped from the branches of the core bandgap circuit via nMOS transitors.

Fig. 1.

Overall circuit

A. Circuit Overview The circuit in Fig. 1 is used for this work. A PTAT voltage is generated across R and a CTAT voltage across the transistor Q3. The resistors R1 and R2 act to resisitively divide the PTAT and CTAT voltages and create a voltage reference at Vref which can be any value between zero and the supply voltage. Employing KCL at the Vref node, we get R1 VT ln(n) R2 R + |VBE | (1) R1 + R2 R R1 + R2 where VT = kT /q and is representative of the thermal voltage. It is thus seen that, the PTAT voltage, namely VT ln(n).(R/R ), and the CTAT voltage |VBE | are weighted and added. The resistors R, R , R1, R2 can be used to control the value of the reference voltage. 1) Temperature Independence: To evaluate the conditions for complete theoretical temperature independence of this circuit, the derivative of the expression on the right hand side of (1) is taken with respect to temperature and zero TC is sought at a temperature of 75 C. Vref = Vref R1 R ln(n) VT R2 |VBE | = + =0 T R1 + R2 R T R1 + R2 T (2) |V |(3+m)VT Eg /q where VT = k/q and |VBE | = BE . T T T
This work was carried out using the 0.18 UMC design kit provided by MOSIS

2) Design of Reference Circuit: This work provides a greater degree of freedom over [5] in the form of the resistor R . R can be used to set the current in the bandgap core and R can be used to control the weight of the PTAT term (in (1)) without affecting the CTAT term. While (1) can be used to generate any given reference voltage, (2) can be be employed simultaneously to achieve temperature independence for the same. For the manual ne tuning of the circuit, again (1) can be used to get an intuitive feel of the dependence of the reference voltage on the various circuit elements used in the circuit. It is to be noted that the absolute values of the resistances R1 and R2 are to be made sufciently large so that the PTAT and CTAT voltages do not cause an unduly strong interaction between themselves. Values of the mentioned resistances which are too low might alter the very character of the CTAT and PTAT voltages, thus rendering this scheme useless.

B. Modied Differential Pair As mentioned earlier a modied differential pair Fig. 2 is used as the feedback amplier in this circuit. This dispenses with the tail current source traditionally used in a differential amplier. Doing this would reduce the biasing requirements and would also solve the problem of achieving an optimum input common mode voltage for the input transistor pair of the diffamp. The transistor sizing of this new amplier has been modied to suit the requirements of the input voltage at the gates of both the input transistors. This input voltage would be around the |VBE | of the parasitic BJTs.

2007 IEEE INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS

Fig. 2.

Simplied Differential Pair TABLE I VARIATION AT CORNERS

Corner tt ss-typ ff-typ snfp-typ fnsp-typ ss-min ss-max ff-min ff-max

Vo,ref Variation (%) 0.00 -0.16 +0.16 -0.06 +0.06 -0.48 +0.48 -0.16 +0.80

Effective T Cf (ppm/ C) 7.91 8.09 9.87 8.35 7.75 10.32 18.62 14.87 10.91

T0 (ppm/ C) 75 88 55 76 70 64 124 29 110

Fig. 4. Variation in the reference voltage as the power supply voltage is swept. Results are provided at three different temperatures for the worst corner i.e. ss-max TABLE II P ERFORMANCE S UMMARY Parameter Power Supply Voltage Technology Power Consumption @ 27 C Reference Voltage @ 27 C Voltage Variation (0 C T 150 C) Dependence on Supply Voltage (PSRR) Value 1.8V 0.18m CMOS 60 W 620 mV 7.91 ppm/ C 28 V/V (-97 dB)

This design is not altogether without peril. The absence of the tail current could make the common mode response of the circuit unpredictable, as it can the individual currents owing in the two branches of the diffamp. This necessitates careful design and simulation checks to ensure that the performance of the circuit remains within acceptable limits. II. S IMULATION R ESULTS FOR BANDGAP The bandgap circuit was designed to a give a nominal voltage of 620 mV with a zero TC at 75 C. Fig. 3 shows variations in the output voltage of the bandgap circuit across corners. The results are provided in Table I. Vo,ref refers to the temperature at 27 C. Effective T Cf is V 1 dened by Tmax Vmin . Vo,ref and T0 is the temperature at max Tmin which the temperature coefcient is zero. As can be seen from Table I, the maximum Vo,ref variation (+0.80%) is in the ff-max case, which corresponds to fast

nMOS and pMOS and maximum value of resistors, while the maximum effective TC is in the ss-max case (18.62 ppm/ C). Fig. 4 shows the results of a supply voltage sweep on the reference voltage for three different temperatures namely 0, 75 and 150 degrees Centigrade for the worst corner, ss-max. As can be seen, this circuit can be used down to 0.95V for 0 C and down to 0.85V for higher temperatures.. III. C ONCLUSION A CMOS bandgap has been designed and simulated on a 0.18m logic process. The bandgap can be used a reference in low power applications as it can generate a temperature independent voltage for any value between ground and supply by using resistive weighting of PTAT and CTAT voltages directly. Also a simplied differential pair facilitates operation of the bandgap at low supply voltages across a temperature range of 150 degrees Centigrade. R EFERENCES
[1] B.Razavi, Design of Analog CMOS Integrated Circuits. Tata McgrawHill, 2001. [2] Piero Malcovati, Franco Maloberti, Carlo Fiocchi and Marcello Purzi,Curvature compensated BICMOS bandgap with 1-V supply voltage, IEEE J. Solid-State Circuits, Vol. 36, No. 7, July 2001. [3] Ka Nang Leung, Philip K. T. Mok,A sub-1-V 15-ppm/ C CMOS bandgap voltage reference without requiring low threshold voltage device, IEEE J. Solid-State Circuits, Vol. 37, No. 4, April 2002. [4] H. Banba, H. Shinga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi and K. Sakui,A CMOS bandgap reference circuit with sub-1-V operation, IEEE J. Solid-State Circuits, Vol. 34, pp. 670-674, May 1999. [5] H. Neuteboom, B. M. J. Kup and M. Jansens,A DSP-based hearing instrument IC, IEEE J. Solid-State Circuits, Vol. 32, pp. 1790-1806, Nov 1997. [6] P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits., 4th ed. Wiley, 2001.

Fig. 3. Variation in the bandgap voltage across process corners. The legends are to be interpreted by the following example. e.g. ss-max implies : slow nMOS, slow pMOS, maximum variation of resistances.

Вам также может понравиться