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Code No: W0102/R05

Set No. 1

I I B.Tech I Semester Supplementary Examinations, April/May 2011 BUILDING MATERIALS AND CONSTRUCTION (Civil Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) What are the tools for blasting and explain them along with neat sketches. (b) What does dressing of a stone mean? Describe how dressing is carried out for Rubble and Ashlar masonry. [8+8] 2. (a) Describe the process of burning bricks in intermittent kilns. (b) Give the detailed and neat sketch of the Ho mans kiln. [8+8] 3. (a) i. State the advantages and disadvantages of high-alumina cement. ii. What are the precautions to be taken for the storage of cement? (b) Distinguish between quick lime and slaked lime. [4+4+8] 4. (a) Di erentiate between natural seasoning and artificial seasoning. (b) Enumerate various market forms of steel and explain any two. [8+2+3+3] 5. (a) Describe the points to be considered while designing the footings on black cotton soils. (b) Describe the stepped footing with a neat sketch. [8+8] 6. (a) Explain the following tools used in masonry [6] i. Line and pins. ii. Masons square. iii. Brick hammer . (b) Define the terms i. Bed Joint. ii. Lap. iii. Bull nose. iv. Quion. v. Facing, backing and hearting. [10]

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Code No: W0102/R05

Set No. 1

7. (a) Di erentiate between Mosaic and Terrazzo oors? For what type of works you recommend the above oorings? (b) For large spans shell roofs are provided. Discuss the factual situation of the above statement. [8+8] 8. Describe the method of removing oil paint from woodwork and repainting it. [16]

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Code No: W0102/R05

Set No. 2

I I B.Tech I Semester Supplementary Examinations, April/May 2011 BUILDING MATERIALS AND CONSTRUCTION (Civil Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) What are the precautions to be taken in the process of blasting. (b) Write a brief note on preservation of stones. [8+8] 2. (a) What are the advantages, disadvantages and uses of sand-lime bricks. (b) Explain the compressive strength and water absorption tests for bricks. [6+10] 3. Write short notes on: (a) Expanding cement. (b) Continuous are kiln. (c) Standard briquette in testing cement. [5+6+5] 4. (a) Explain the qualities of a good timber. (b) Explain defects due to seasoning. [8+8] 5. Design an isolated stepped footing for a brick pillar, 30cm 30cm, carrying a super imposed load of 250kN at its top. The height of the column above ground level is 3.5m. The brick masonry weighs 19.5kN/m 3 while lime concrete to be used in the base weighs 21 kN/ m 3 . The soil has angle of repose of 300 , unit weight of 17 kN/m 3 and safe bearing capacity of 160 kN/m 2 . The foundation concrete has a modulus of rupture equal to 150 kN/m 3 . [16] 6. (a) State the requirements to be satisfied by bond at a connection. (b) What are the points should be considered while providing a junction. (c) What are the features of English bond? [4+4+8] 7. (a) What are curved roofs? (b) Describe the Method of construction of on R.C.C. at roof. [4+12]

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Code No: W0102/R05

Set No. 2

8. Mention the types of failures commonly met with in paint work and state their causes. [16]

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Code No: W0102/R05

Set No. 3

I I B.Tech I Semester Supplementary Examinations, April/May 2011 BUILDING MATERIALS AND CONSTRUCTION (Civil Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) What are the materials required for the process of blasting. (b) Explain comparison of using blasting powder and dynamite in stone Quarrying. [8+8] 2. Describe the two field tests which may be carried out to determine the suitability of soil for the purpose of brick manufacture. [16] 3. (a) What is the importance of consistency test on cement? Describe the test with a neat diagram. (b) Explain what is meant by quality control of concrete. [2+6+8] 4. (a) Draw a neat cross-section of an exogenous tree and show various components of it and explain. (b) Distinguish between mild steel and hard steel. [10+6] 5. (a) What do you understand by raft foundation? When do you prefer this type of foundation? (b) Explain with the help of sketches common types of raft foundation. [6+10] 6. (a) State the advantages of cavity walls. (b) Explain with the help of sketches, the details of cavity walls at the Foundation level and the Parapet level. [6+10] 7. (a) Define a at roof and mention its advantages & disadvantages over pitched roofs. (b) Explain king post truss along with a neat sketch. [10+6] 8. (a) What are the requirements of good plaster? (b) Discuss the mortars which are used for painting and plastering. [6+10] 1 of 2

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Code No: W0102/R05

Set No. 3

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Code No: W0102/R05

Set No. 4

I I B.Tech I Semester Supplementary Examinations, April/May 2011 BUILDING MATERIALS AND CONSTRUCTION (Civil Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. What are the various tests for stones and explain them in detail. [16] 2. (a) Explain the following: i. Clamp and kiln. ii. Bullnose brick and cownose brick. (b) Explain brie y water absorption test and warpage tests for tiles. [8+8] 3. Di erentiate between (a) White cement and ordinary cement. (b) Acid resistant cement and hydrofobic cement. (c) Quick setting cement and Rapid hardening cement. (d) Ordinary portand cement and pozzolana cement. [4x4=16] 4. (a) Write a critical note on storage of timber. (b) Explain the properties of galvanized iron. [8+8] 5. (a) Derive an expression for the depth of concrete block required for a strip footing of a wall. (b) Explain how do you design the stepped pad footing for a masonry square column. [8+8] 6. Explain the various sorts of coursed rubble masonry with sketches. [16] 7. Define roof covering? What are the various types of roof coverings commonly adopted in India? Explain them in detail. [16] 8. How would you proceed to paint (a) a new wood paneled door. (b) a new steel roof truss of a workshop. [8+8]

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Code No: X0203/R05

Set No. 1

I I B.Tech I Semester Supplementary Examinations, April/May 2011 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering, Bio-Medical Engineering, Electronics & Control Engineering, Electronics & Computer Engineering and Instrumentation & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. Convert the following to Decimal and then to Hexadecimal. (a) 1234 8 (b) 1267 8 (c) 11001111 2 (d) 110111012 (e) 78610 (f) 555 10 [3+3+3+3+2+2] [8]

2. (a) Draw the logic diagram using only two input NAND gates to implement the following expression. (AB + AB)(CD? + CD) (b) Obtain the complement of the following Boolean expressions. i. BCD + (B + C + D) + BCDE ii. AB + (AC) + (AB + C) (c) Obtain the dual of the following Boolean expressions. i. ABC + ABC + ABC + ABC ii. AB + (AC) + ABC 3. Minimize the following function using tabular minimization and verify the same with K-map minimization F (A, B, C, D) = m(0, 1, 2, 5, 7,8, 9, 10, 13, 15). [8+8] 4. (a) Implement the full adder function by using two 4:1 multiplexers.

[4]

[4]

(b) What is a decoder? How do you convert a decoder to a Demultiplexer.[10+6] 5. Write a brief note on: (a) Architecture of PLDs (b) Capabitation and the limitations of threshold gates. [8+8] 6. (a) Compare synchronous & Asynchronous circuits (b) Design a Mod-6 synchronous counter using J-K ip ops. [6+10] 1 of 2

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Code No: X0203/R05

Set No. 1

7. (a) Find the minimal table equivalent to the state table given below: (b) And obtain equivalent classes using implication - table. [8+8]
v+1 Present state Next state q Output Z qv X=00 01 10 11 00 01 10 11 162110000 263110000 369410010 456781010 559711010 666110000 7 5 10 7 1 1 0 1 0 862180000 999110000 10 6 11 1 1 0 0 0 0 11 6 9 4 1 0 0 1 0

8. (a) Draw the ASM chart for the following state transistion, start from the initial state T1 , then if xy=00 go to T 2 , if xy=01 go to T 3 , if xy=10 go to T 1 , other wise go to T3 . (b) Show the exit paths in an ASM block for all binary combinations of control variables x, y and z, starting from an initial state. [8+8]

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Code No: X0203/R05

Set No. 2

I I B.Tech I Semester Supplementary Examinations, April/May 2011 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering, Bio-Medical Engineering, Electronics & Control Engineering, Electronics & Computer Engineering and Instrumentation & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) Express the Decimal Digits 0 - 9 in BCD, 2421, 84-2-1 and Excess-3. (b) Convert the Hexadecimal number 1010 to Decimal and then to Binary. [12+4] 2. (a) Simplify the following expressions and implement them with NAND gate circuits. [8] i. AB + ABD + ABD + ACD + ABC ii. BD + BCD + ABCD (b) Obtain the Dual of the following Boolean expressions. i. AB + A(B + C) + B(B + D) ii. A + B + ABC (c) Obtain the complement of the following Boolean expressions. i. AB + ABC + ABCD + ABCDE ii. ABEF + ABEF + ABEF [4] [4]

3. Minimize the following function using tabular minimization and verify the same with K-map minimization F = m(0,1, 6, 7, 8, 9, 13, 14, 15) [8+8] 4. (a) Implement the full adder function by using two 4:1 multiplexers. (b) What is a decoder? How do you convert a decoder to a Demultiplexer.[10+6] 5. Write a brief note on: (a) Architecture of PLDs (b) Capabitation and the limitations of threshold gates. [8+8] 6. (a) Explain the operation of 5 - stage twisted ring counter with circuit diagram State transition diagram & state table (b) Find a ring code for a module - 5 shift counter using D- ip ops. Explain with the waveforms. [8+8] 7. A clocked sequential circuit is provided with a single input x and single output Z. Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the sequence it produce an output Z = 1 and overlapping is also allowed. 1 of 2

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Code No: X0203/R05 (a) Obtain State - Diagram. (b) Also obtain state - Table.

Set No. 2

(c) Find equivalence classes using partition method & design the circuit using D - ip- ops. [4+4+8] 8. (a) Draw the ASM chart for the following state transistion, start from the initial state T1 , then if xy=00 go to T 2 , if xy=01 go to T 3 , if xy=10 go to T 1 , other wise go to T3 . (b) Show the exit paths in an ASM block for all binary combinations of control variables x, y and z, starting from an initial state. [8+8]

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Code No: X0203/R05

Set No. 3

I I B.Tech I Semester Supplementary Examinations, April/May 2011 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering, Bio-Medical Engineering, Electronics & Control Engineering, Electronics & Computer Engineering and Instrumentation & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. Convert the following to Decimal and then to Hexadecimal. (a) 765 8 (b) 1002 8 (c) 11001001 2 (d) 111100002 (e) 25710 (f) 239 10 2. (a) Simplify the following Boolean expressions. [8] i. AC+ABC+AC to three literals ii. (xy+z)+z+xy+wz to three literals iii. AB(D+CD)+B(A+ACD) to one literal iv. (A+C)(A+C)(A+B+CD) to four literals (b) Obtain the complement of the following Boolean expressions. [8] i. BCD+(B+C+D)+BCDE ii. AB+(AC)+(AB+C) iii. ABC+ABC+ABC+ABC iv. AB+(AC)+ABC 3. (a) What is a cell of a K-map? What is meant by pair, a quad, and an octet of a map and how many variables are eliminated? [8] (b) Reduce the following function using K- map and implement it using NAND logic. F= m(0, 2, 3, 4, 5, 6, ) [8] 4. (a) A combinational circuit is defined by the following three functions F y 1 = x + xyz F2 =x + y F 3 =xy + x Design the circuit with a decoder and external y gates. (b) List the applications of Multiplexer and Demultiplexer. [12+4] 5. Write a brief note on: [3+3+3+3+2+2]

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Code No: X0203/R05 (a) Architecture of PLDs

Set No. 3

(b) Capabitation and the limitations of threshold gates. [8+8] 6. (a) Compare synchronous & Asynchronous circuits (b) Design a Mod-6 synchronous counter using J-K ip ops. [6+10] 7. A Clocked sequential circuit with two inputs x and y and a single output Z is described by the following J - K ip- ops input equations and output equation of Z = Q1 x J1 = Q 2 x + Q2 y J 2 K 1 = Q2 x K y = Q 1 + xy 2 Z = Q 1 y + Q2 x y x (a) Obtain state - table. (b) Draw the logic circuit diagram using T - ip- ops. (c) Draw the state diagram. (d) Derive state - equations. [4+4+4+4]

8. (a) Draw the ASM chart for the following state transistion, start from the initial state T1 , then if xy=00 go to T 2 , if xy=01 go to T 3 , if xy=10 go to T 1 , other wise go to T3 . (b) Show the exit paths in an ASM block for all binary combinations of control variables x, y and z, starting from an initial state. [8+8]

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Code No: X0203/R05

Set No. 4

I I B.Tech I Semester Supplementary Examinations, April/May 2011 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering, Bio-Medical Engineering, Electronics & Control Engineering, Electronics & Computer Engineering and Instrumentation & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. Convert the following to Decimal and then to Binary. (a) 1876 16 (b) AB22 (c) 12128 (d) 1556 8 (e) 97710 (f) 664 10 [3+3+3+3+2+2]
16

2. (a) Express the following functions in sum of minterms and product of maxterms. [8] i. F(A,B,C,D)=BD+D+BD ii. F(x,y,z)=(xy+z)(xz+y) (b) Obtain the complement of the following Boolean expressions. [8] i. (AB+AC)(BC+BC)(ABC) ii. ABC+ABC+ABC iii. (ABC)(A+B+C) iv. A+BC(A+B+C) 3. (a) Design an SOP logic circuit, which will output a 1(logic High) whenever the input binary equivalent of decimal 0,1,5,7,8,10,13,15,16,17,23,24and31. (b) Draw the Karnaugh map to represent the following Boolean function. F= ( D + A). B 4. (a) What is a Hazard in a Digital system? (b) What are the various types of Hazards that may be encountered in a combinational logic? Explain in detail how Hazards are eliminated? [4+12] 5. Write a brief note on: (a) Architecture of PLDs (b) Capabitation and the limitations of threshold gates. [8+8] 1 of 2 [12+4]

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Code No: X0203/R05 6. (a) Compare synchronous & Asynchronous circuits

Set No. 4

(b) Design a Mod-6 synchronous counter using J-K ip ops. [6+10] 7. A clocked sequential circuit is provided with a single input x and single output Z. Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the sequence it produce an output Z = 1 and overlapping is also allowed. (a) Obtain State - Diagram. (b) Also obtain state - Table. (c) Find equivalence classes using partition method & design the circuit using D - ip- ops. [4+4+8] 8. (a) Draw the ASM chart for the following state transistion, start from the initial state T1 , then if xy=00 go to T 2 , if xy=01 go to T 3 , if xy=10 go to T 1 , other wise go to T3 . (b) Show the exit paths in an ASM block for all binary combinations of control variables x, y and z, starting from an initial state. [8+8]

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Code No: X0303/R05

Set No. 1

I I B.Tech I Semester Supplementary Examinations, April/May 2011 MECHANICS OF SOLIDS ( Common to Mechanical Engineering, Mechatronics, Metallurgy & Material Technology, Production Engineering, Aeronautical Engineering and Automobile Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. An unknown weight falls 4 cm on to a collar rigidly attached to the lower end of a vertical bar 4m long and 8 cm2 in section. If the maximum instantaneous extension is found to be 0.42 cm, find the corresponding stress and the value of the unknown weight. E = 200 kN/mm 2 . [16] 2. Sketch the shear force and bending moment diagrams showing the salient values for the loaded beam shown in the figure2 below. [16]

Figure 2 3. (a) State the assumptions involved in the theory of simple bending. [6] (b) Derive the Bending equation from fist principle. [10] 4. (a) From first principles show that the maximum shear stress in a beam of circular section is 4/3 times the average shear stress. [8] (b) A beam is of T- section, anges 135mm 12mm and web 120mm 15mm. It is subjected to a sheer force of 29kN. Draw shear stress distribution across the depth marking values at salient points. What percentage of the shearing force at any section is carried by the web? [8] 5. A cantilever truss is loaded as shown in Figure 5 Find the forces in members AB, BE and EF. [16]

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Code No: X0303/R05

Set No. 1

Figure 5 6. (a) What is moment area method? Explain the two Mohrs theorems, as applicable to the slope and de ection of a beam. [6] (b) A cantilever of uniform cross-section of length l carries two point loads, W at the free end and 2W at a distance a from the free end. Find the maximum de ection due to this loading. [10] 7. Calculate the increase in volume enclosed by a boiler shell 2.5 m long and 1 m in diameter, when it is subjected to an internal pressure of 1.5 N/mm 2 . The wall 2 thickness is such that the maximum tensile stress is 22 N/mm , under this pressure. Given E = 200 kN/mm 2 and Poissons ratio = 0.25. [16] 8. Compare the values of max. and minimum hoop stresses for a cast steel cylindrical shell of 600 mm external dia. And 400 mm internal dia. Subjected to a pressure of 30N/mm 2 applied (a) Internally and (b) Externally. [8+8]

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Code No: X0303/R05

Set No. 2

I I B.Tech I Semester Supplementary Examinations, April/May 2011 MECHANICS OF SOLIDS ( Common to Mechanical Engineering, Mechatronics, Metallurgy & Material Technology, Production Engineering, Aeronautical Engineering and Automobile Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. Prove that Poissons ratio for the material of a body is 0.5, if its volume does not change when stressed. Prove also that Poissons ratio is zero when there is no lateral deformation when a member is axially stressed. [16] 2. (a) Device the relations among loading, shear force and bending moment in a beam. [9]

(b) A cantilever beam AB span 6m is subjected to a uniformly varying load of 8 kN/m intensity at the fixed end A and zero at the free end B. draw SFD and BMD. [7] 3. (a) State the assumptions involved in the theory of simple bending. [6] (b) A rectangular beam 180mm wide and 300mm deep is simply supported over a span of 5m and carries a load of 4kN/m. It also carries three equal point loads WkN each equispaced over the beam. If the permissible bending stress is 6.7 MPa, find the maximum allowable value of W. [10] 4. (a) A beam of square section is used as beam with one diagonal horizontal. Obtain the magnitude and location of maximum shear stress in the beam. Draw the variation of shear stress across the section. [8] (b) A beam is of T-section, ange 145mm 15mm, web 18mm 120mm. If it is subjected to a shear force of 30kN, find the maximum intensity of shear stress and sketch the distribution of shear stress across the section. [8] 5. Find the forces in all members of a four-bay simply supported truss which is shown in Figure 5. [16]

Figure 5 1 of 2

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Code No: X0303/R05

Set No. 2

6. A steel girder of uniform section, 13 meters long, is simply supported at its ends. It carries concentrated loads of 135 kN at two points 3 meters and 4.5 meters from the two ends respectively. Calculate the de ection of the girder at the two points under the two loads; And the maximum de ection. Take I = 1610 -4 m4 and E = 210 106 kN/m 2 . [16] 7. A spherical shell of 90 mm internal dia. has to withstand an internal pressure of 35N/mm 2 . Find the thickness of shell required, the max. permissible tensile stress is 80N/mm 2 . [16] 8. Compare the values of max. and minimum hoop stresses for a cast steel cylindrical shell of 600 mm external dia. And 400 mm internal dia. Subjected to a pressure of 30N/mm 2 applied (a) Internally and (b) Externally. [8+8]

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Code No: X0303/R05

Set No. 3

I I B.Tech I Semester Supplementary Examinations, April/May 2011 MECHANICS OF SOLIDS ( Common to Mechanical Engineering, Mechatronics, Metallurgy & Material Technology, Production Engineering, Aeronautical Engineering and Automobile Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. An unknown weight falls 4 cm on to a collar rigidly attached to the lower end of a vertical bar 4m long and 8 cm2 in section. If the maximum instantaneous extension is found to be 0.42 cm, find the corresponding stress and the value of the unknown weight. E = 200 kN/mm 2 . [16] 2. (a) Define statically determinate and statically indeterminate beams. Give examples. [6] (b) A cantilever beam of length 2m carries a uniformly distributed load of 2 kN/m over the whole length and a point load of 3 kN at the free end. Draw the SF [10] and BM diagrams. 3. (a) A water main 110mm internal diameter is made of mild steel plate 12mm thick and is running full. If it is freely supported at the ends find the maximum permissible span if the bending stress is not to exceed 5MPa. Unit weight if steel is 81 kN/m 3 and unit weight of water = 9.8 kN/m 3 . [10] (b) State the assumptions involved in the theory of simple bending. [6] 4. (a) Derive an expression for the shear stress at any point in a circular section of a beam, which is subjected to a shear force F. Sketch the variation of shear stress. [8] (b) A timber beam 150mm wide and 260mm deep supports u.d.l. of intensity w kN/m length over a span of 2.5m. If the safe stresses are 27MPa in bending and 2MPa in shear, calculate the safe intensity of the load which can be supported by the beam. [8] 5. Find the forces in all members of a four-bay simply supported truss which is shown in Figure 5. [16]

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Code No: X0303/R05

Set No. 3

Figure 5 6. (a) What is moment area method? Explain the two Mohrs theorems, as applicable to the slope and de ection of a beam. [6] (b) A cantilever of uniform cross-section of length l carries two point loads, W at the free end and 2W at a distance a from the free end. Find the maximum de ection due to this loading. [10] 7. (a) Define pressure vessel and discuss the most important considerations while designing pressure vessel. [6] (b) A boiler shell is made of 15 mm thick plate having a limiting tensile stress of 125 N/mm 2 . If the longitudinal and circumferential e ciencies are 70% and 60% respectively, determine the maximum diameter of the shell. The allowable maximum pressure is 2.2 N/mm 2 . [10] 8. (a) Find the ratio of thickness to internal dia. Of a tube subjected to internal pressure when the pressure is 3/8 of the max permissible hoop stress. (b) Find the increase in internal dia of such a tube 100 mm in internal dia. Subjected to an internal pressure of 90N/mm 2 . Neglect longitudinal strain and take E = 200GN/m 2 and 1 = 0.3. [8+8]
m

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Code No: X0303/R05

Set No. 4

I I B.Tech I Semester Supplementary Examinations, April/May 2011 MECHANICS OF SOLIDS ( Common to Mechanical Engineering, Mechatronics, Metallurgy & Material Technology, Production Engineering, Aeronautical Engineering and Automobile Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. A round steel bar 25 mm diameter and 360 mm long is placed concentrically within a brass tube which has an outside diameter of 35 mm and an inside diameter of 27.5 mm. The length of the tube exceeds, that of the bar by 0.15 mm. Rigid plates are placed on the ends of the tube, through which an axial compressive force of 80 KN is applied on the compound bar. Determine the compressive stresses in the bar and tube. E for steel = 2.110 5 N/mm 2 . E for brass = 10 5 N/mm 2 . [16] 2. A beam 6m in length carries a uniformly distributed load of 1.5kN/m run and a point load of 2kN at the left free end. The left support is at 1.5m. Locate the right support such that there is no shearing force at the center of the beam. Draw also the SF and BM diagrams and determine the position and magnitude of maximum bending moment. [16] 3. (a) State the assumptions involved in the theory of simple bending. [6] (b) Derive the Bending equation from fist principle. [10] 4. (a) Prove that for a rectangular section the maximum shear stress is 1.5 times the average stress. Sketch the variation of shear stress. [8] (b) A timber beam 120 mm wide and 185 mm deep supports a u.d.l. of intensity w kN/m length over a span of 2.7 m. If the safe stresses are 29 MPa is bending and 3 MPa in shear, Calculate the safe intensity of the load which can be supported by the beam. [8] 5. Analyse the truss shown in Figure 5 by method of tension coe cients. [16]

Figure 5 1 of 2

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Code No: X0303/R05

Set No. 4

6. (a) What is moment area method? Explain the two Mohrs theorems, as applicable to the slope and de ection of a beam. [6] (b) A cantilever of uniform cross-section of length l carries two point loads, W at the free end and 2W at a distance a from the free end. Find the maximum de ection due to this loading. [10] 7. (a) Enumerate the di erences between longitudinal stress and circumferential stress in a cylindrical shell subjected to an internal pressure. [6] (b) A thin cylindrical pressure vessel of inside diameter 350 mm is subjected to an internal pressure of 500 kPa. Determine the thickness of the cylindrical wall assuming joint factor to be 0.85 and corrosion allowance 1 mm. The allowable stress for the cylindrical material is 160 N/mm 2 . [10] 8. Compare the values of max. and minimum hoop stresses for a cast steel cylindrical shell of 600 mm external dia. And 400 mm internal dia. Subjected to a pressure of 30N/mm 2 applied (a) Internally and (b) Externally. [8+8]

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Code No: X0404/R05

Set No. 1

I I B.Tech I Semester Supplementary Examinations, April/May 2011 ELECTRONIC CIRCUIT ANALYSIS ( Common to Electronics & Communication Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) For a CE configuration, what is the maximum value of R S for which R o di ers by no more than 10 percent of its value for R S = 0. The h-parameter values are hf e = 50, h ie = 1.1K , h re = 2.5 10 -4 , hoe = 25A/V. (b) For a CE configuration, what is the maximum value of R L for which R i di ers by no more than 10 percent of its value at R L = 0. The h-parameter values are hf e = 50, h ie =1.1K , h re = 2.510 -4 , hoe = 25A/V. (c) For the CB configuration, what is the maximum value of R for which R i L does not exceed 60 ohms .The h-parameter values aref b - 0.98, hib =21.6 , h= hrb = 2.9 10-4 , hob = 0.49A/V. (5+6+5) 2. (a) Draw the circuit diagram of Darlington emitter follower and derive expressions for current gain and input impedance. List the important characteristics of it. (b) If six identical amplifiers are cascaded each having f the overall f H . Assume non interacting stages.
H

=100 KHz, determine

(c) Write a short note on Gain-Bandwidth product of amplifiers. [8+4+4] 3. (a) Show that in Hybrid - p model, the di usion capacitance is proportional to the emitter bias current. (b) What is the frequency range to consider Giacolletto model of a transistor at high frequencies? What is the significance of f T in discussing the frequency range of a transistor at high frequencies? [8+8] 4. (a) Draw push-pull amplifier Class-B amplifier circuit. What are the advantages and disadvantages of Push-pull amplifier [8] (b) Draw and discuss the operation of Class - C power amplifier. [8] 5. A single tuned class-A transformer coupled RF amplifier has the following parameters: gm =5mA/V, coe cient of coupling =0.01, Primary inductance=70 H & Secondary inductance =50 H, Primary resistance=10 ,secondary resistance=8 .The primary is tuned with a 100pF capacitor and the secondary is loaded by a 10K . Assume rO of the transistor to be very large. (a) Draw the circuit diagram (b) Determine the resonant frequency (c) The e ective Q of the tank circuit 1 of 2

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Code No: X0404/R05 (d) The 3-dB bandwidth (e) The voltage gain at resonance. (A res ). [16]

Set No. 1

6. (a) Explain the reasons for potential instability in tuned amplifiers? (b) Explain with circuit diagram and frequency response as to how the problem of potential instability is overcome in a double tuned amplifier? [6+10] 7. (a) The voltage regulator in Figure 7amaintains an output voltage of 25 V. i. What value of Rsc should be used to limit the maximum current to 0.5A? ii. With the value of Rsc found in (i) what will be the output voltage when RL= 100 ohms? When RL =10 ohms?

Figure 7a (b) Draw and explain the regulator which will provide the foldback limiting .[8+8] 8. (a) What is catcher diode and explain the necessity of catches diode in Switch Regulator with the help of circuit diagram. (b) List the operating ratings and electrical characteristics of IC 723. [8+8]

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Code No: X0404/R05

Set No. 2

I I B.Tech I Semester Supplementary Examinations, April/May 2011 ELECTRONIC CIRCUIT ANALYSIS ( Common to Electronics & Communication Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) Draw the circuit diagram and low frequency equivalent circuit of common source amplifier and derive an expression for its voltage gain. (b) For the emitter follower circuit with R = 0.5K and R = 5K, calculate S L A I , Ri , AV , AV S , and R 0 . Assume , h f e = 50, h ie =1K, h oe = 25 A/V.[8+8] 2. (a) Draw the circuit of two stage R-C coupled JFET amplifier and explain its working.
* and (b) Obtain the theoretical expressions for overall lower 3dB frequency f L higher 3-dB frequency f * , when n-stages of identical amplifiers are cascaded. h Assume non interacting stages [8+8]

3. (a) What is typical value of each resistance in the Hybrid - p model ? What is the significance of each of these components? (b) Given the following transistor measurements made at I and at room temperature: hfe = 100, hie = 600 , Cc = 3pF, A ie = 10 at 10 MHz. Find f T , f .
C

= 5mA, V C E =10V

[8+8]

4. (a) In transformer coupled Class - A power amplifier, show that the conversion e ciency is 50%. [8 ] (b) Discuss in detail the cross-over distortion. How do you avoid the cross over distortion in power amplifier circuit? Discuss in detail. [8] 5. For the circuit shown in figure 5: (a) Draw the small signal equivalent circuit. (b) Derive Voltage gain (A
V

). ).

(c) Derive the expression for resonant frequency. (d) Voltage gain at resonant frequency (A
res

(e) Quality factor of the resonant circuit. [16]

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Code No: X0404/R05

Set No. 2

Figure 5 6. Explain in detail the e ect of cascading tuned amplifiers and hence derive the expression for bandwidth of n-stage amplifier. Also draw the frequency response and explain what happens as the number of stages increases? [16] 7. (a) With the help of a neat circuit diagram, explain the operation of BJT shunt voltage regulator. (b) What is a voltage reference? Why is it needed? (c) What is the function of a series pass transistor? [8+4+4] 8. (a) What is catcher diode and explain the necessity of catches diode in Switch Regulator with the help of circuit diagram. (b) List the operating ratings and electrical characteristics of IC 723. [8+8]

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Code No: X0404/R05

Set No. 3

I I B.Tech I Semester Supplementary Examinations, April/May 2011 ELECTRONIC CIRCUIT ANALYSIS ( Common to Electronics & Communication Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) With the help of necessary equations, discuss the variation of A Ro withR S andRL in Common Emitter configuration (b) Design a single stage Emitter follower having R Assume hfe = 50, hie = 1K, h oe = 25A/V. (8+8) 2. (a) Derive the expression for the high 3-dB frequency f acting stages in terms of f H for one stage.
i

, AV , Ri , and
o

= 400K

and R

= 20 .

* h

of n-identical non inter-

(b) If four identical amplifiers are cascaded each having f H =100 KHz, determine the overall upper 3dB frequency f * . Assume non interacting stages. h (c) Write a short note on Bootstrapped Darlington circuit. [5+5+6] 3. (a) Derive the transfer function of a single stage CE transistor amplifier response. (b) Discuss Millers Theorem? Apply this theorem to find approximate equivalent circuit for a transistor amplifier stage in CE configuration with a resistive load and hence prove that the voltage with resistive load is -g m RL . [8+8] 4. (a) In transformer coupled Class - A power amplifier, show that the conversion e ciency is 50%. [8 ] (b) Discuss in detail the cross-over distortion. How do you avoid the cross over distortion in power amplifier circuit? Discuss in detail. [8] 5. For the circuit shown in figure 5: (a) Draw the small signal equivalent circuit. (b) Derive Voltage gain (A
V

). ).

(c) Derive the expression for resonant frequency. (d) Voltage gain at resonant frequency (A
res

(e) Quality factor of the resonant circuit. [16]

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Code No: X0404/R05

Set No. 3

Figure 5 6. Explain what you mean by Synchronous tuning of tuned amplifiers? Draw the frequency response of a synchronously tuned amplifier showing the response of individual stages and overall responses? [16] 7. (a) Explain how voltage regulators maintain constant output voltage with the help of any one type of a circuit? (b) out of three two Power Supplies A and B with the following specifications A: No-load voltage is 20V and full load voltage is 19V B: No-load voltage is 30V and full load voltage is 29V Which is better power supply and why? [8+8] 8. (a) Explain how Switching Regulator overcomes the disadvantage of Series and Shunt type of regulators? (b) Explain why pulse width modulator is used in Switching regulators and also explain the operation of it. [8+8]

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Code No: X0404/R05

Set No. 4

I I B.Tech I Semester Supplementary Examinations, April/May 2011 ELECTRONIC CIRCUIT ANALYSIS ( Common to Electronics & Communication Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) With the help of necessary equations, discuss the variation of A Ro with R S andRL in Common Base configuration

, AV , Ri , and

(b) What is swamping resistor? what are its e ects when used in CS amplifier circuit ? (10+6) 2. (a) Draw the circuit diagram of single stage R-C coupled amplifier. Discuss the e ect of an emitter bypass capacitor on low-frequency response. (b) In an R-C coupled amplifier, A V M =50, f L =50Hz and f H =100KHz. Find the values of frequencies at which the gain reduces to 40 on either side of mid band region. [8+8] 3. Derive all components in the Hybrid - p model in terms of h parameters in CE configuration. [16] 4. (a) What are the advantages and disadvantages of push pull configuration? Show that in Class-B push pull amplifier the maximum conversion e ciency is 78.5% [8] (b) A transistor in a transformer coupled (Class - A) power amplifier has to deliver a maximum of 5 Watts to a load of 4 load. The quiescent point is adjusted for symmetrical swing, and the collector supply voltage is VCC =20 Volts. Assume Vmin =0 volts. i. What is the transformer turns ratio? ii. What is the peak collector current? [8] 5. (a) Draw and explain the circuit diagram of a single tuned Capacitance coupled amplifier. Also explain its operation? (b) Draw and explain the significance of Gain versus Frequency curve of tuned amplifiers when they are used in radio amplifiers? (c) Draw the Ideal and actual frequency response curves of a single tuned amplifier? [8+4+4] 6. (a) Explain in detail about the Instability caused in tuned amplifiers at high frequencies? (b) What is the importance of Stagger tuning? Explain brie y about Stagger tuned amplifiers? [8+8]

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Code No: X0404/R05

Set No. 4

7. (a) Explain why voltage regulators are called as closed loop control systems? (b) A power Supply having output resistance of 2 ohms supplies a full-load current of 100mA to a 50 ohms load. Find the percent voltage regulation and no-load output voltage of the supply? (c) Draw and explain the load voltage and load current characteristic for a current limited regulator. [4+6+6] 8. (a) What is catcher diode and explain the necessity of catches diode in Switch Regulator with the help of circuit diagram. (b) List the operating ratings and electrical characteristics of IC 723. [8+8]

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Code No: X0504/R05

Set No. 1

I I B.Tech I Semester Supplementary Examinations, April/May 2011 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. Convert the following to Decimal and then to Octal. (a) 1234 16 (b) 12EF
16

(c) 10110011 2 (d) 100011112 (e) 35210 (f) 999 10 2. (a) Simplify the following Boolean expressions. i. AC + ABC + AC to three literals ii. (xy + z) + z + xy + wz to three literals iii. AB(D + CD) + B(A +ACD) to one literal iv. (A + C)(A + C)(A + B + CD) to four literals. (b) Obtain the complement of the following Boolean expressions. [8+8] i. BCD + (B + C + D) + BCDE ii. AB + (AC) + (AB + C) iii. ABC+ ABC + ABC + ABC iv. AB + (AC) + ABC. 3. (a) Implement the following function with Excusive - OR and AND gates: F = ABC D + ABC D + AB C D + ABC D (b) If F 1 = wxy+yz+w yz+xyz And F 2 = (w + x + y + z)(x + y + z)) (w + y + z) Obtain minterms list of F 1 + F 2 using K-map obtain minimal POS function of F 1 + F 2 . [8+8] 4. (a) Implement the following Boolean - function using suitable decoder with active high outputs and with additional OR gates. Y1 = S0, 1, 3, 6, 7 Y2 = 0, 2, 4, 7 Y3 = 1, 3, 6, 7 (b) Implement full-adder circuit using decoder and OR- gates. [8+8] [3+3+3+3+2+2]

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Code No: X0504/R05

Set No. 1

5. A sequential circuit with 3 D- ip- ops A, B and C has only one input X and one output X with following relationship DA = B C X, D B = A, D C = B (a) Draw the logic diagram of the circuit. (b) Obtain logic diagram, state table and state diagram. [16] 6. (a) Explain synchronous and ripple counters. Compare their merits and demerits. (b) Design a modulo -12 up synchronous counter using T- ip ops and draw the circuit diagram. [8+8] 7. (a) Show the memory cycle timing waveforms for the write and read operations. Assume a CPU clock of 50 MHz and a memory cycle time of 50 ns. (b) The following memory units are specified by the number of words times the number of bits per word. How many address lines and input-output data lines are needed in each case? [8+8] i. 4K * 16, ii. 2G * 8 , iii. 16M * 32, iv. 256K * 64. 8. Reduce the number of states in the state table listed below. Use an implication table. [16] Present state Next state Output x=0 x=1 x=0 x=1 afb00 bdc00 cfe00 dga00 edc00 ffb11 ggh01 hga10

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Code No: X0504/R05

Set No. 2

I I B.Tech I Semester Supplementary Examinations, April/May 2011 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) Explain di erent methods used to represent negative numbers in binary system. [6] (b) Perform the subtraction with the following unsigned binary numbers by taking the 2s complement of the subtrahend. [52] i. 11010 - 10010 ii. 11011-1101 iii. 100-110000 iv. 1010100-1010100 v. 11-1011. 2. (a) Write short notes about the various digital logic families. (b) Obtain the complement of the following Boolean expressions. i. AB + A(B + C) + B(B + D) ii. A + B + ABC. (c) Obtain the dual of the following Boolean expressions. [8+4+4] i. AB + ABC + ABCD + ABCDE ii. ABEF + ABEF + ABEF. 3. (a) If F 1 (A, B, C, D) = (1,3, 4, 5, 9, 10, 11) + d6, 8 And F2 (A, B, C, D) = (0, 2, 4, 7, 8, 15) + d9, 12 Obtain minimal SOP expression for F 1 F 2 using K- map and draw the circuit using NAND gates. (b) Draw the multiple -level NAND circuit for the following Boolean - expression: AB + C D E + BC (A + B) [8+8] 4. (a) Implement 64 1 multiplexer with four 16 1 and one 4 1 multiplexer. (Use only block diagram). (b) A combinational logic circuit is defined by the following Boolean functions. F1 = ABC + AC F2 = ABC + AB F3 = ABC + AB Design the circuit with a decoder and external gates. [8+8] 5. Convert the following:

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Code No: X0504/R05 (a) J-K ip- op to T- ip- op (b) R-S ip- op to J-K- ip- op (c) J-K ip- op to D- ip- op (d) R-S ip- op to D- ip- op. [4+4+4+4]

Set No. 2

6. (a) Explain synchronous and ripple counters. Compare their merits and demerits. (b) Design a modulo -12 up synchronous counter using T- ip ops and draw the circuit diagram. [8+8] 7. (a) Explain the block diagram of a memory unit. Explain the read and write operation a RAM can perform. (b) i. How many 32K * 8 RAM chips are needed to provide a memory capacity of 256K bytes. ii. How many lines of the address must be used to access 256K bytes? How many of these lines are connected to the address inputs of all chips? iii. How many lines must be decoded for the chip select inputs? Specify the size of the decoder. [8+8] 8. (a) Describe the analysis procedure of asynchronous sequential logic using transition table. (b) An asynchronous sequential circuit is described by the excitation and output functions. [6+10] Y = x 1 x2 + (x 1 + x 2 )y z=y i. Draw the logic diagram of the circuit. ii. Derive the transition table and output map. iii. Obtain a two-state ow table. iv. Describe in words the behavior of the circuit.

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Code No: X0504/R05

Set No. 3

I I B.Tech I Semester Supplementary Examinations, April/May 2011 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. Convert the following to Decimal and then to Binary. (a) 1234 16 (b) ABCD (c) 11228 (d) 1726 8 (e) 99710 (f) 654 10 i. (xy + z) ( y + xz) ii. BD + AD + BD. (b) Obtain the complement of the following Boolean expressions. [8+8] i. ABC + ABD + AB ii. ABC + ABC + ABCD iii. ABCD + ABCD? + ABCD iv. AB + ABC. 3. (a) Implement the following Boolean expression with Excusive-NOR and NOR gates: F = ABC D + ABC D + AB C D + ABC D (b) If F 1 = wxy+y z+wyz+xyz And F 2 = (w + x + y + z) (x + y + z) (w + y + z) Obtain minterms list of F 1 F 2 using K-map obtain minimal SOP function of F1 F 2 . [8+8] 4. (a) Implement the following expression using a 3 to 8 line Demultiplexer and F1 = AB + AC + BC AN D gates. F 2 = S0, 1,2, 3, 5, 7 F3 = 1, 2, 4, 6, 7 (b) Derive the expression for 4-bit look-a-head carry generator and draw the circuit for C3 . [8+8] 5. (a) Explain the following terms related to filp- ops. i. race round conditions 1 of 2 [3+3+3+3+2+2] 2. (a) Express the following functions in sum of minterms and product of maxterms.
16

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Code No: X0504/R05 ii. propagation delay iii. clock.

Set No. 3

(b) Explain the operation of R-S ip- op with negative edge triggering with neat sketch. And explain its truth table. [8+8] 6. (a) Design a 4-bit ring counter using T- ip ops and draw the circuit diagram and timing diagrams. (b) Draw the block diagram and explain the operation of serial transfer between two shift registers and draw its timing diagram. [8+8] 7. (a) Explain the block diagram of a memory unit. Explain the read and write operation a RAM can perform. (b) i. How many 32K * 8 RAM chips are needed to provide a memory capacity of 256K bytes. ii. How many lines of the address must be used to access 256K bytes? How many of these lines are connected to the address inputs of all chips? iii. How many lines must be decoded for the chip select inputs? Specify the size of the decoder. [8+8] 8. (a) Explain critical and non critical races with the help of examples. (b) An asynchronous sequential circuit has two internal states and one output. The excitation and output functions describing the functions are: [6+10] Y1 = x 1 x2 + x 1 y2 + x 2 y1 Y2 = x 2 + x 1 y1 y2 +x 1 y1 Z = x 2 + y1 i. Draw the logic diagram of the circuit. ii. Derive the transition table and output map. iii. Obtain a ow table for the circuit.

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Code No: X0504/R05

Set No. 4

I I B.Tech I Semester Supplementary Examinations, April/May 2011 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) Explain, How error occurred in a data transmission can be detected using parity bit.

[6]

(b) Perform the subtraction with the following unsigned binary numbers by taking the 2s complement of the subtrahend. [52] i. 111011 - 111000 ii. 1110-110110 iii. 10010-1101 iv. 110-10100 v. 11011-10000. 2. (a) Simplify the following Boolean functions. i. xyz + xyz + xyz + xyz ii. xyz + xyz + xyz + xyz iii. xz + xy + xyz + yz iv. xyz + xyz + xyz + xyz + xyz. (b) Obtain the complement of the following Boolean expressions. [8+8] i. AC + ABC + AC ii. (xy + z) + z + xy + wz iii. AB(D + CD) + B(A +ACD) iv. (A + C)(A + C)(A + B + CD). 3. (a) Show that: A (b) Show that: A B C (A + B) = AB B=ABC

(c) Obtain minimal POS expression for the complement of the given expression: F (A, B,C ) = S0,3,4,6 And draw the circuit using NOR-gates. [4+4+8] 4. (a) Design a code converter to convert BCD code to 9s complement code using suitable Decoder and OR - gates. (b) Design a 4- bits 2s complement circuit to generate 2s complement for the given 4 - bit binary number. Use Decoder and OR - gates. [8+8] 5. (a) Explain the operation of D- ip- op with negative edge triggering using NAND gates. 1 of 2

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Code No: X0504/R05

Set No. 4

(b) Obtain the state diagram for the synchronous sequential circuit with two inputs (X, Y) and one output Z. The input represents alphabet letters as 00 -A, 01-B, 10-C and 11-D. The output is one if the most recent two inputs are in alphabetic order, i.e., AB, BC, CD. [6+10] 6. (a) Design a 4-bit ring counter using T- ip ops and draw the circuit diagram and timing diagrams. (b) Draw the block diagram and explain the operation of serial transfer between two shift registers and draw its timing diagram. [8+8] 7. (a) Show the memory cycle timing waveforms for the write and read operations. Assume a CPU clock of 50 MHz and a memory cycle time of 50 ns. (b) The following memory units are specified by the number of words times the number of bits per word. How many address lines and input-output data lines are needed in each case? [8+8] i. 4K * 16, ii. 2G * 8 , iii. 16M * 32, iv. 256K * 64. 8. (a) Describe the operation of the SR Latch using NAND gate with the help of truth table, transition table and the circuit. (b) An asynchronous sequential circuit has two internal states and one output. The excitation and output functions describing the functions are: Y1 = x 1 x2 + x 1 y2 + x 2 y1 Y2 = x 2 + x 1 y1 y2 +x 1 y1 z= x 2 + y 1 Implement the circuit defined above with NAND SR latches. [8+8]

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Code No: W0802/R05

Set No. 1

I I B.Tech I Semester Supplementary Examinations, April/May 2011 ORGANIC CHEMISTRY (Chemical Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) Using inductive e ect, explain why chloro acetic acid stronger then acetic acid. (b) Explain why aniline is less basic in comparison with methyl amine. [8+8] 2. (a) Write the various steps involved in the conversion of pyrrole to pyrrole-2carboxaldehyde in the presence of chloroform and KOH. (b) Describe the mechanism of alkylation of benzene in the presence of AlCl 3 . [8+8] 3. Discuss the following reactions with detailed mechanism As shown in figures 3 & 3 [16]

Figure 3

Figure 3 4. (a) What is a free-radical? (b) How do you get bromine free radicals? (c) Describe the free-radical mediated addition of HBr to alkenes. [4+8+4] 5. (a) Which of the following compounds exhibit optical isomerism? i. Nitromethane ii. Methyl chloride iii. Glycer aldehyde iv. Ethylene glycol

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Code No: W0802/R05

Set No. 1

(b) Describe a method to determine the optical activity of an organic compound. [2+2+2+2+8] 6. (a) What are high polymers? How are they classified - explain with examples. (b) With the help of a block diagram, discuss the manufacture of polyethylene terephthalate. [8+8] 7. (a) Explain how pyrrole, furan and thiophene can behave as aromatic compounds? (b) What happens when pyridine is i. treated with NaNH 2 in Liq. ammonia. ii. Trated with H 2 in the presence of Pd/C. [10+3+3] 8. Outline the synthesis of the following: (a) Malachite Green (b) para-rosaniline (c) Magenta red. [6+5+5]

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Code No: W0802/R05

Set No. 2

I I B.Tech I Semester Supplementary Examinations, April/May 2011 ORGANIC CHEMISTRY (Chemical Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) Discuss the applications of the inductive e ect towards reactivity of organic molecules with examples. (b) Write the hyperconjugated structures for i) Pent-2-ene ii) 2-methyl-1-butene [8+4+4] 2. (a) What happens when phenol is treated with CCl Write the mechanism involved in it?
4

in the presence of KOH?

(b) Explain, how benzanilide can be prepared from benzophenone using Beckmann rearrangement reaction? Discuss the mechanism of rearrangement. [8+8] 3. (a) Discuss the reaction mechanism and applications of Aldol condensation. (b) What happens when benzaldehyde is re uxed with acetic anhydride in the presence of potassium acetate? [8+8] 4. (a) What is a free-radical? (b) How do you get bromine free radicals? (c) Describe the free-radical mediated addition of HBr to alkenes. [4+8+4] 5. (a) Write the structural formulae of the stereo isomers of 3-bromo-3-chlorobutane. Which of them are enantiomers and diastereomers? (b) Which one of the following compounds is not optically active? i. Isobytyl alcohol ii. Lactic acid iii. Cyclohexanol iv. Maleic acid. [8+2+2+2+2] 6. (a) Explain the di erence between addition and condensation polymerizations. (b) Discuss the preparation, properties and uses of bakelite. [10+6] 7. (a) Explain the aromatic character of the five membered heterocyclic compounds. (b) Write a note on Skraups syntheis. [8+8] 8. Suggest the synthesis of each of the following: (a) From benzaldehyde and dimethyl aniline As shown in figure 8a

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Figure 8a (b) From aniline, ortho and para tolidines As shown in figure 8b

Figure 8b (c) From Michlers ketone and dimethyl aniline As shown in figure 8c

Figure 8c

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Set No. 3

I I B.Tech I Semester Supplementary Examinations, April/May 2011 ORGANIC CHEMISTRY (Chemical Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) Explain the acidic properties of dicarboxylic acids using inductive e ect. (b) Explain the following applications of inductive e ect. i. basic character of amines. ii. reactivity of alkyl benzenes. [8+4+4] 2. Write the sequence of steps involved in the following conversions.As show in figures 2&2 [16]

Figure 2

Figure 2 3. Describe the mechanism for the following reactions.As shown in figures 3 & 3 [16]

Figure 3

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Figure 3 4. (a) Why do you use peroxides in the anti-Markoniko addition of HBr to alkenes? (b) Explain the stability order of simple alkyl free-radicals by structural theory. [8+8] 5. (a) Write the structural formulae of the stereo isomers of 3-bromo-3-chlorobutane. Which of them are enantiomers and diastereomers? (b) Which one of the following compounds is not optically active? i. Isobytyl alcohol ii. Lactic acid iii. Cyclohexanol iv. Maleic acid. [8+2+2+2+2] 6. (a) What are high polymers? How are they classified - explain with examples. (b) With the help of a block diagram, discuss the manufacture of polyethylene terephthalate. [8+8] 7. (a) What are heterocyclic compounds? How are they classified? (b) What happens when? i. Furan is treated with SO 3 in pyridine. ii. Pyridine is treated with sodamide. iii. Quinoline is treated with alkaline. KmnO

[4+4+4+4] 8. Give an example and synthesis for each of the following: (a) Mordant dyes. (b) Azo dyes. (c) Vat dyes. (d) Triphenyl amine dyes. [4+4+4+4]

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Set No. 4

I I B.Tech I Semester Supplementary Examinations, April/May 2011 ORGANIC CHEMISTRY (Chemical Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) Mention the role of resonance on increasing or decreasing the strength of acids and bases. (b) Explain how inductive e ect in uences the basic strength of amines. [8+8] 2. (a) Discuss the mechanism of reaction involving benzene and acyl chlorides in the presence ofAlCl3 . (b) Explain, how phenol can be converted into Salicyaldehyde and write the mechanism involved in it? [8+8] 3. Discuss the following reactions with detailed mechanism As shown in figures 3 & 3 [16]

Figure 3

Figure 3 4. (a) Give the reaction and mechanism for the diborane addition to styrene followed by treatment with H 2 O2 . (b) Explain the addition of HBr to styrene in the absence of any peroxides. [8+8] 5. (a) Which types of compounds exhibit geometrical isomerism? Give examples. (b) Draw the structures of maleic acid and fumaric acid and assign configuration on the basis of E-Z notation. [8+8] 6. (a) Describe the preparation properties and uses of nylon (6, 6). (b) Describe the preparation, properties and uses of PVC. [8+8] 1 of 2

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Set No. 4

7. (a) Compare the reactivity of pyrrole and furan towards electrophilic substitution reaction. (b) Pyridine is less than ammonia explain. [8+8] 8. What are azo dyes? Write down the methods of preparation of any two of the azo dyes? How is the structure of azo dyes determined? [4+6+6]

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