Combi Logic

C H A P T E R
Analyzing and Synthesizing Combinational Logic Circuits

This chapter begins with standard graphic symbols and two-valued switching circuits. This includes both relay-type and IC-type circuits. Next we show how to analyze and design logic circuits, including techniques for designing with NAND gate and also with NOR gates. Shannons Expansion Theorem provides a technique for compressing truth tables and K-maps. With compressed K-maps, larger functions can be reduced using smaller K-maps. Understanding this reduction technique adds depth to your study of digital design. We present function and logic hazards and resulting glitches along with a chain link method that can be used to remove logic hazards that contribute to glitches. Trivial, simple, and complex functions round out your study.We discuss Decoders and Multiplexers along with the design techniques for using them. Programmable logic device architectures then illustrate how industry utilizes simple circuit architectures to rapidly design circuits.To give you a different slant on digital design, we contrast circuits drawn using the positive logic convention (PLC) system with circuits drawn in the direct polarity indication (DPI) system. Both systems are supported in IEEE Std 991-1986, the IEEE Standard for Logic Circuit Diagrams. The chapter ends with a case study that shows different ways to design a BCD to 7-segment Display Decoder. 3.1 STANDARD GRAPHIC SYMBOLS AND TWO-VALUED SWITCHING CIRCUITS
CHAPTER OUTLINE
3.1 Standard Graphic Symbols and Two-Valued Switching Circuits 3.2 Designing Logic Circuits 3.3 Compressing Truth Tables and K-Maps 3.4 Glitches and Their Causes 3.5 Types of Functions and Delays 3.6 Programmable Logic Devices (PLDs) 3.7 Positive Logic Convention and Direct Polarity Indication 3.8 Case Study Number 1 (BCD to 7-segment Display System) 3.9 Worked Exercises
Given a Boolean function, we have learned how to convert that function into a truth table. The truth table is just another description of a Boolean function. A logic circuit diagram is yet another description of a Boolean function. A set of standard graphic symbols have been agreed upon internationally by an organization called the International Electrotechnical Commission (IEC) and published in their publication 617-12. These graphic symbols are also published in the United States by the Institute of Electrical and Electronic Engineers (IEEE) in the publication IEEE Std 91a-1991/IEEE Std 91-1984 (Graphic Symbols for Logic Functions). New computer aided design (CAD) tools provide libraries of graphic symbols for drawing logic circuit diagrams. In this text we will use primarily the IEEEs shape distinctive graphic symbols for the basic logic functions. Outside the United States, most countries have elected to use the IECs non-shape distinctive graphic symbols for the basic logic functions. Although standards are now available, not all manufacturers have chosen to use them. (See the Bibliography.)
3.1.1 SWITCHING CIRCUITS FOR THE OR, AND, AND COMPLEMENT OPERATIONS
In Fig. 3.1.1 we show a summary of the Boolean functions for the OR, AND, and complement (invert or NOT) operations and corresponding hardware switching
122
CHAPTER 3
ANALYZING AND SYNTHESIZING COMBINATIONAL LOGIC CIRCUITS
circuits. These functions and their different representations are very important and should be committed to memory.
Function Truth Table IEEE (Shape Distinctive Graphic Symbol) IEC (Non-Shape Distinctive Graphic Symbol) Pass Logic Switching Circuit 0 = not pressed 1 = pressed OR F=A+B A 0 0 1 1 B 0 1 0 1 F 0 1 1 1 A B F A B 1 F A B F 0 = no continuity 1 = continuity
n.o.
Regenerative Logic Switching Circuit Vcc = H = 1 B

n.o.
A
n.o.
n.o.
F B
n.c.
0=L=V L 1=H=V H
A
n.c.
(a)
GND = L = 0 Vcc = H = 1
AND F = AB A 0 0 1 1 B 0 1 0 1 F 0 0 0 1 A B F A B & F A
n.o.
A B
n.o. n.o.
B
n.o.
A
n.c.
B
n.c.
(b)
GND = L = 0 Vcc = H = 1
Complement (Invert, NOT) F=A A F 0 1 1 0 A F A 1 F A F

n.c.
A
n.c.
A
n.o.
(c)
GND = L = 0
Figure 3.1.1 Summary of the Boolean functions for (a) the OR operation, (b) the AND operation, and (c) the complement operation.
You can implement each logic operation in Fig. 3.1.1 as a pass logic switching circuit or as a regenerative logic switching circuit using momentary pushbutton switches. In industrial circuits, either relays or field effect transistors (FETs) are substituted for the momentary pushbutton switches in Fig. 3.1.1. Examples of relay symbols and FET symbols are shown in Fig. 3.1.2(a) and (b). Other types of regenerative logic switching circuits are also commonly used. These circuits use bipolar junction transistors (BJTs) whose symbols are shown in Fig. 3.1.2(c). Relays, FETs, and BJTs simply emulate the operation of momentary pushbutton switches. Since they are easily understood, we are using pushbutton switches to illustrate switching circuit operations. Later, when you get to your course in electronics, you will begin to understand transistors and see how they can be used to imitate the operation of simple momentary pushbutton switches. Refer to Appendix A to observe different types of circuits for logic functions.
SECTION 3.1
Drain Spring n.c. contacts =
n.c.
STANDARD GRAPHIC SYMBOLS AND TWO-VALUED SWITCHING CIRCUITS
123
Emitter =
n.c.
Gate
Base
=
n.c.
N V Coil + S Current (when current flows the relay opens) Relay with n.c. contacts n.c. pushbutton switch
Source PMOS FET n.c. pushbutton switch
Collector PNP BJT n.c. pushbutton switch
Drain Spring n.o. contacts =

n.o.
Collector =
n.o.
Gate
Base
=
n.o.
N V Coil + S Current (when current flows the relay closes) Relay with n.o. contacts (a) n.o. pushbutton switch
Source NMOS FET n.o. pushbutton switch
Emitter NPN BJT n.o. pushbutton switch
(b)
(c)
Figure 3.1.2 Relay, FET, and BJT symbols and the equivalent pushbutton switch: (a) relay symbols, (b) PMOS and NMOS FET symbols, and (c) PNP and NPN BJT symbols.
A normally open (n.o.) type of pushbutton switch is what you encounter when you type on the keyboard of a computer or use when you phone in a pizza using a pushbutton phone. The normally open type must be pressed to make a connection (provide continuity) across the switch. Another type of momentary pushbutton switch is the normally closed (n.c.) type, which must be pressed to break a connection (provide no continuity) across the switch. Both types are used in the switching circuits shown in Fig. 3.1.1. Figure 3.1.1(a) shows that two n.o. type switches must be placed in parallel for the pass logic switching circuit to generate the 2-input OR function. To implement an OR operation, switches must be connected in parallel. If switch A or switch B or both are pressed (0=not pressed and 1=pressed), then the function F is 1, since continuity exists across the two switches in parallel. Otherwise F is 0, since no continuity exists across the two switches. To obtain a regenerative logic switching circuit for the OR function, simply rotate the pass logic switching circuit clockwise 90 degrees and connect one end to the supply voltage, Vcc , and the other end to F. To obtain the bottom half of the circuit, change the switches to the opposite type and place them in series, since the top half of the circuit is in parallel. One end of the series circuit is connected to F and the other end is connected to ground, GND, i.e., the other terminal of the power supply. The circuit is now a 2-input OR regenerative logic switching circuit that provides the function F with 0 = L = VL and 1 = H = VH . Dashed lines in the regenerative logic switching circuit represent two different switches that are ganged, i.e., mechanically interconnected, with a single pushbutton labeled A. Pressing switch As pushbutton closes the n.o.-type switch in the top half of the circuit and opens the n.c.-type switch in the bottom half.
124
CHAPTER 3
Anytime switches are labeled with the same signal name (such as B) this means that they are ganged and operate as a unit with one pushbutton. A pass logic switching circuit provides continuity or the lack of continuity (no continuity), while a regenerative logic switching provides a high or low. Regenerative logic switching circuits are predominantely used today. To implement a 2-input AND function via a pass logic switching circuit requires two n.o. switches connected in series as shown in Fig. 3.1.1(b). To implement an AND operation, switches must be connected in series. If both switch A and switch B are pressed (0=not pressed and 1=pressed) then the function F is 1, since continuity exists across the two switches in series. Otherwise F is 0, since no continuity exists across the two switches.To obtain the regenerative logic switching circuit for the AND function, simply rotate the pass logic switching circuit and connect one end to the supply voltage, Vcc, and the other end to F. To obtain the bottom half of the circuit, change the switches to the opposite type and place them in parallel, since the top half of the circuit is in series. One end of the parallel circuit is connected to F and the other end to ground, GND, i.e., the other terminal of the power supply. The circuit is now a 2-input AND regenerative logic switching circuit that provides the function F with 0 = L = VL and 1 = H = VH . The pass logic switching circuit for the complement function is just a single n.c. type switch. If switch A is pressed, then function F is 0 (or no continuity), else F is 1 (continuity). The Inverter regenerative logic switching circuit provides the function F either a high voltage (or a 1 in positive logic) or a low voltage (or a 0 in positive logic) as illustrated in Fig. 3.1.1(c).
3.1.2 CONTRASTING PASS LOGIC SWITCHING CIRCUITS WITH R E G E N E R AT I V E L O G I C S W I T C H I N G C I R C U I T S
We use regenerative logic switching circuits to implement digital circuits because their signal loss is less than that of pass logic switching circuits when they are cascaded. A cascaded circuit is a multiple-stage circuit that consists of a series of components or networks, such that the output of each one serves as the input of the next one in the series. Multistage circuits designed with regenerative logic switching circuits thus provide better performance and signal quality than pass logic switching circuits. Circuits that use PMOS FETs, NMOS FETs, or BJTs generally have the following characteristics: (1) they switch very fast, (2) they have extremely low cost, (3) they operate very reliably, (4) they require a very small area, and (5) they consume very little power. MOS transistors are generally used in newer designs. BJTs are somewhat more power hungry and tend to be used in supercomputers because of their speeds. At this point in your career you need only be aware of the names of these fast switching devices. We will discuss switching circuits only from the standpoint of pass logic and regenerative logic pushbutton switching circuits. Pass logic circuits pass a signal through the circuit from one location to another (shown by the line with the double arrows in Fig. 3.1.1) and thus provide either continuity through the circuit, F=1=continuity, or no continuity, F=0=no continuity. Regenerative logic circuits provide an output F that is either a high voltage VH or a low voltage V . L E X A M P L E An example of both types of circuits connected to a light-emitting diode (LED) is shown in Fig. 3.1.3. To simplify switching circuits we generally use logic symbols as illustrated in Fig. 3.1.3(c).
SECTION 3.1
125
X
n.o.
Y X Vcc Power Supply + _ GND

n.o.
n.o. n.o.
Vcc R LED Power Supply + _ X

n.c.
F = XY Y
n.c.
X Y R
F = XY AND symbol R LED GND
F = XY
LED
GND (a) (b) (c)
Figure 3.1.3 (a) Pass logic switching circuit, (b) regenerative logic switching circuit, (c) symbolic representation using a graphic symbol.
In each circuit in Fig. 3.1.3, the LED will light when the function F=1 and will not light when the function F=0. The squiggly line labeled R in each circuit is a called a resistor and is necessary in most cases to protect the LED. The function F in each circuit is the AND function, F=X Y. As a note of interest, a single resistor can be used in either the top half or the bottom half of each of the regenerative logic switching circuits in Fig. 3.1.1 and not change the circuits functionality.
3.1.3 I N T E G R AT E D C I R C U I T D E V I C E S
Many manufacturers provide physical hardware devices called integrated circuits (ICs) that are capable of carrying out two-valued Boolean functions. These devices can contain as few as tens to as many as millions of transistors on a small silicon semiconductor crystal called a die or chip. Since the circuitry contains mainly transistors, diodes, and resistors which are all interconnected inside the chip, power consumption can be quite low and reliability quite high.The die is constructed and then welded to a frame as illustrated in Fig. 3.1.4. Its input and output leads are connected by thin gold wires to the packages leads or pins. The unit is encapsulated using glass, ceramic, or plastic. Finally the unit is hermetically sealed. Hermetic sealing guards against die contamination in many different environments.
Cutaway View Metal Lead Frame Die or Chip 1 2 3 4 Package's Leads or Pins 5 6 7 8 Thin Gold Wire Metal Die Frame upon which Die Is Mounted
Figure 3.1.4 Cutaway view of an IC package showing the die or chip, the die frame, the gold wire, the lead frame, the packages leads or pins, and the pin numbers or pinouts.
126
CHAPTER 3
E X A M P L E Five different types of integrated circuit packages are shown in Fig. 3.1.5.
Figure 3.1.5 Packages for integrated circuits: (a) dual-in-line package, (b) flat package, (c) surface-mounting package, (d) plastic leaded chip carrier package, (e) pin grid array package.
(a)
(b)
(c)
1 (d)
1 (e)
The package shown in Fig. 3.1.5(a) is the common dual-in-line package (DIP). In Figs. 3.1.5(b) and (c) are the flat package (flat pack) and the surface-mount (small outline) package. These packages are generally used in applications in which real estate on a printed circuit board (PCB)) is critical and/or a lower cost must be achieved for high-volume application. The packages shown in Figs. 3.1.5(d) and (e) are the plastic leaded chip carrier (PLCC) package and the pin grid array (PGA) package, which are used for very large IC designs, especially when the count of pins, i.e., the package inputs and outputs, for the designs becomes very large. Note the location of pin 1 for each package type. The integrated circuit (IC) packages shown in Fig. 3.1.5 are only a few among many different types of packages available. Data books have a list of IC packages available for their devices so engineers can choose the ones they prefer to use.
3.1.4 SWITCHING CIRCUITS FOR THE NOR, NAND, BUFFER, XOR, AND X N O R O P E R AT I O N S
In Fig. 3.1.6 we show a summary of the Boolean functions for the NOR, NAND, and Buffer operations and a hardware pass logic and regenerative logic switching circuit for each operation using momentary pushbutton switches.These functions and their different representations are very important and should be committed to memory. To draw the pass logic switching circuits for the NOR and NAND functions, we must first write the functions in a literal form (each expression contains literals connected only by AND and OR operators). We can easily do this by using DeMorgans Theorem. The literal form for the NOR function is F = A B. Using this form, we can draw the 2-input pass logic switching circuit for the 2-input NOR function as shown in Fig. 3.1.6(a).The circuit consists of two n.c. type switches connected in series. We obtain the regenerative logic switching circuit for the NOR function by the same process we described earlier. For either of the 2-input NOR switching circuits (the pass logic or regenerative logic switching circuit), if both switch A and switch B are not pressed (0=not pressed and 1=pressed), then F
SECTION 3.1 Function Truth Table IEEE (Shape Distinctive Graphic Symbol)
STANDARD GRAPHIC SYMBOLS AND TWO-VALUED SWITCHING CIRCUITS IEC (Non-Shape Distinctive Graphic Symbol) Pass Logic Switching Circuit 0 = not pressed 1 = pressed Regenerative Logic Switching Circuit Vcc = H = 1 A
127
NOR F=A+B = AB
A 0 0 1 1
B 0 1 0 1
F 1 0 0 0
A B
A B
A F
n.c.
n.c. n.c.
B
n.c.
F 0 = no continuity 1 = continuity
0 = L = VL 1= H = VH
A
n.o.
B
n.o.
(a)
GND = L = 0
Vcc = H = 1 NAND F = AB =A+B A 0 0 1 1 B 0 1 0 1 F 1 1 1 0 A A B F A B & F B

n.c.
B
n.c.
A
n.c.
n.c.
F F B
n.o.
A (b)
n.o.
GND = L = 0 Vcc = H = 1
Buffer F=A
A F 0 0 1 1
A F
A
n.o. n.o.
A
n.c.
(c)
GND = L = 0
Figure 3.1.6 Summary of the Boolean functions for (a) the NOR operation, (b) the NAND operation, and (c) the Buffer operation.
is 1, else F is 0. For the pass logic circuit F is either 0=no continuity or 1=continuity. For the regenerative logic circuit F is either 0 = L = VL or 1 = H = VH . The literal form for the NAND function is F = A + B. From this form we can draw the circuit for the pass logic switching circuit for the 2-input NAND function as shown in Fig. 3.1.6 (b). The circuit consists of two n.c. type switches connected in parallel. The regenerative logic switching circuit for the NAND function is obtained by the same process described earlier. For either of the 2input AND switching circuits, if switch A or switch B or both are not pressed (0=not pressed and 1=pressed) then F is 1, else F is 0. For the pass logic circuit F is either 0=no continuity or 1=continuity. For the regenerative logic circuit F is either 0 = L = VL or 1 = H = VH . The pass logic switching circuit for the Buffer function is a single n.o. type switch as shown in Fig. 3.1.6 (c). The corresponding regenerative logic switching circuit is shown in the same figure. If switch A is not pressed, then the function F=0, else
128
CHAPTER 3
the function F=1. As a note of interest, a single resistor can be used in either the top half or the bottom half of each of the regenerative logic switching circuits in Fig. 3.1.6 and not change the circuits functionality. Manufacturers refer to the actual hardware circuit that performs the Buffer function as simply a Buffer. In Fig. 3.1.7 we show a summary of the Boolean functions for the XOR, and XNOR operations and a hardware pass logic and regenerative logic switching circuit for each operation using momentary pushbutton switches. Like the other functions, these functions and their different representations are very important and should be committed to memory.
Function Truth Table IEEE (Shape Distinctive Graphic Symbol) IEC (Non-Shape Distinctive Graphic Symbol) Pass Logic Switching Circuit 0 = not pressed 1 = pressed XOR F=AB = AB + AB A 0 0 1 1 B 0 1 0 1 F 0 1 1 0 A A B F A B =1 F A
n.c.
Regenerative Logic Switching Circuit Vcc = H = 1 A

n.o.
B B
n.o.
A
n.c.
n.o.
n.c.
B
n.c.
B
n.o.
0 = no continuity 1 = continuity R (a)
0 = L = VL 1= H = VH
GND = L = 0
Vcc = H = 1 XNOR F=AB = AB + AB A 0 0 1 1 B 0 1 0 1 F 1 0 0 1 A A B F A B =1 F A

n.c.
B B
n.c.
A
n.o.
A
n.c.
n.o.
n.o.
B
n.o.
B
n.c.
F R (b) GND = L = 0
Figure 3.1.7 Summary of the Boolean functions for (a) the XOR operation, and (b) XNOR operation.
Notice in each case that the modulo 2 operator or XOR operator ({) is used in both function definitions. The literal form for the XOR function is F = A B + A B while that for the XNOR function is F = A B + A B. Using these literal forms of the functions we can draw the pass logic and regenerative logic switching circuits as shown in Fig. 3.1.7. Manufacturers refer to the actual hardware circuits that perform the XOR and XNOR functions as XOR and XNOR gates. For the XOR switching circuits, the function F is 1 if only one of the two switches is pressed, else the function is 0. For the XNOR switching circuits, the function F is 1 if both switches are pressed or neither switch is pressed, else the function is 0. In each case a resistor (R) is used in the bottom part of the regenerative logic switching circuit to simplify the circuit. Figure 3.1.8(a) shows a relative size summary for ICs. Integrated circuits have been classified by name (SSI, MSI, LSI and VLSI circuits) according to the number of equivalent circuits they contain such as gates, Inverters, or Buffers.This clas-
SECTION 3.1
129
sification is becoming blurred as technology provides smaller and smaller gate sizes. Integrated circuits are also classified by device process technology or family.This classification is also constantly changing as different device technologies appear. Figure 3.1.8(b) shows a device technology summary for ICs.
IC size classification Small-Scale Integration (SSI) Medium-Scale Integration (MSI) Large-Scale Integration (LSI) Very Large-Scale Integration (VLSI) (a) IC device technology or family classification Standard Transistor-Transistor Logic Low-Power Schottky TTL Schottky TTL Advanced Low-Power Schottky TTL Advanced Schottky TTL Fairchild Advanced Schottky TTL Advanced Complementary Metal-Oxide Semiconductor Advanced CMOS TTL (TTL compatible) High-Speed CMOS High-Speed CMOS TTL (TTL compatible) Bipolar CMOS Technology Emitter-Coupled Logic Integrated-Injection Logic (b) AC ACT HC HCT BCT ECL I2L Abbreviation STD TTL LS TTL S TTL ALS TTL AS TTL F or FAST TTL Number of gates Less than 12 12 to 99 100 to 999 1000 or more
Figure 3.1.8 IC classification: (a) size summary, (b) device technology summary.
3.1.5
A L L P O S S I B L E S I N G L E - A N D T W O - VA R I A B L E F U N C T I O N S
A general relationship for the number of functions that exist for n input variables is expressed as Number of functions = (2)2
n
n
where n is the number of input variable
(3.1.1)
There are 2 rows for n input variables in a truth table, and the function value in each row can be a 1 or a 0. For one input variable (n=1), the number of funcn 1 tions=(2)2 = (2)2 =(2)2=4. In Fig. 3.1.9 we show all possible functions for a
One input variable X 0 1 F0 0 0 F1 0 1 F2 1 0 F3 1 1 Vcc GND
Figure 3.1.9 All possible functions for a single input variable and graphic symbols with compact description names.
BUF
INV
130
CHAPTER 3
single input variable along with a graphic symbol or a connection to ground (GND) or Vcc , and a compact description name for each function. n 2 For two input variables (n=2), the number of functions=(2)2 = (2)2 =(2)4=16. In Fig. 3.1.10 we show all possible functions for a single or for two input variables along with a graphic symbol or a connection to ground (GND) or V . cc
Two input variables X 0 0 1 1 Y 0 1 0 1 F0 0 0 0 0 F1 0 0 0 1 F2 0 0 1 0 F3 0 0 1 1 F4 0 1 0 0 F5 0 1 0 1 F6 0 1 1 0 F7 0 1 1 1 F8 1 0 0 0 F9 1 0 0 1 F10 F11 F12 F13 F14 F15 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Vcc GND AND2 AND2B1 BUF AND2B1 BUF XOR2 OR2 NOR2 XNOR2 NAND2 NAND2B1 INV NAND2B1 INV
Figure 3.1.10 All possible functions for a single variable or for two input variables and graphic symbols with compact description names.
Functions F2, F4, F11, and F13 with single bubbled inputs are not available as off-the-shelf IC devices; however, some manufacturers do provide these symbols in their library parts list for schematic capture programs. Functions are sometimes classified by the following compact description names as shown in Fig. 3.1.10. The compact description names AND2, OR2, NAND2, and NOR2 are used to signify 2-input gates while AND3, OR3, NAND3, and NOR3 are used to signify 3-input gates, etc. Adding B1 after the gate name/number of inputs, such as AND2B1, signifies one-bubbled or inverted input, adding B2 signifies two bubbled inputs, etc. A NAND2B2 is a 2-input NAND gate with two bubbled inputs, which is the same as an OR2. The number of functions that can be written for 3 input variables is 256. The number of functions that can be written for 4 input variables is 65,536, while for just 5 input variables the number of functions that can be written is 4,294,967,296. All of the functions are not necessarily unique, as you can tell from the symbols and compact description names of some of the functions in Fig. 3.1.10.
SECTION 3.1
131
E X E R C I S E S
T O
T E S T
Y O U R
K N O W L E D G E
(For solutions see Section 3.9, Worked Exercises) 1. 2. Draw and label the IEC standard graphic symbols for a 3-input NAND function, 2-input OR function, Inverter function, and XNOR function. For each of the following functions, write the truth table, provide the function name, and draw the IEEE graphic symbol with correctly labeled inputs and output. (a) F1 = A + B (b) F2 = A B (c) F3 = B 3. Draw and name the function for each type of graphic symbol that provides complementation and show under what condition complementation (inversion) takes place. Hint: Look closely at the truth table for each of the functions. Name two different types of momentary pushbutton switches and show a symbol to represent each type. What logic operation results when switches are connected in series? What logic operation results when switches are connected in parallel? Which types of transistors (MOS or BJT) are generally used in newer designs? Which type of transistor (MOS or BJT) generally requires more power to operate? Which size of integrated circuit contains a larger number of equivalent circuits: an SSI, MSI, LSI, or VLSI circuit? How many equivalent circuits does the largest size contain? Write the truth table and the function name of each of the following pass logic switching circuits.
A A
n.c.
4. 5. 6. 7. 8.
B B
n.c.
A A
n.c.
B B
n.o.
F1 0 = no continuity 1 = continuity (a)
F2
F3
(b)
(c)
9.
Write the truth table and the function name of each of the following regenerative logic switching circuits.
Vcc = H = 1 A
n.o.
Vcc = H = 1 A
n.o.
Vcc = H = 1 A
n.c.
A
n.c.
B
n.o.
B F1
n.c.
B B
n.o. n.c.
A
n.c.
B
n.c.
F2 0 = L = VL 1 = H = VH R A
n.o.
0=L=V F3 1 = H = VL H B
n.o.
GND = L = 0 (a) (b)
GND = L = 0 (c)
GND = L = 0
(continues on next page)
132
CHAPTER 3
10. Draw the gate symbol for each of the following compact description names. Next draw the DeMorgan equivalent symbol for each gate symbol and list its equivalent compact description name. (a) NAND3B2 (b) AND2B2 (c) NOR4 (d) OR4B3 11. Determine the maximum number of functions that can be obtained from just 3 variables. Are they all unique? What is the number for 4 variables? Are they all unique?
3.2
DESIGNING LOGIC CIRCUITS
When a functional description such as an equation or a truth table is obtained from a logic circuit, the process is called analysis. When a logic circuit is obtained from a functional description such as an equation or a truth table, the process is called design or synthesis.
3.2.1 A N A LY Z I N G A N D D E S I G N I N G R E L AY L O G I C C I R C U I T S
Before we introduce the analysis/design process using IC logic circuits, lets first analyze a pass logic switching circuit that uses relays. Switching circuits of this type are used in heavy power equipment. In Fig. 3.2.1 we show common symbols for normally closed relay contacts and normally open relay contacts.
Figure 3.2.1 Common symbols for normally closed and normally open relay contacts.
n.c. n.o.
n.c. pushbutton switch
common symbol for n.c. relay contacts
n.o. pushbutton switch
common symbol for n.o. relay contacts
E X A M P L E A pass logic switching circuit that uses relays connected to a drive a motor is shown in Fig. 3.2.2.
+ A B D A B C C M DC Motor A B F D F F (a) (b) (c) D + A B M DC Motor
Figure 3.2.2 Relay pass logic switching circuits: (a) original relay circuit, (b) minimized symbolic logic circuit, (c) minimized relay circuit.
SECTION 3.2
133
Pass logic switching circuits used in power applications are generally referred to as ladder logic circuits. This term is used because it refers to the physical layout of the circuit (it looks like a ladder that may be climbed). In the switching circuit in Fig. 3.2.2(a), when F is 1, the motor M is turned on. Otherwise the motor is turned off, i.e., M=F, where M=1 means the motor is turned on and M=0 means the motor is turned off. One must remember that switches or relays connected in series are ANDed together, while switches or relays connected in parallel are ORed together. Analyzing, we obtain the following Boolean equation for the circuits: F = A B C+D+A B C. Applying Boolean algebra or using a K-map, we can reduce the function to the following minimum form: F=A B + D. Using the minimum form of the function, we can design the circuit in symbolic form as shown in Fig. 3.2.2(b). The relay logic circuit drawn for the minimum form of the function is shown in Fig. 3.2.2(c). In general, logic circuits that use ICs may not be hefty enough to drive high-powered motors or electric light bulbs; however, logic circuits that use relays can be used for these applications. To design a logic circuit using relays as illustrated in the last example, first obtain a minimum Boolean equation for the function in literal form. Next substitute for each input the appropriate relay type or mechanical switch type (either normally open or normally closed) and connect each relay or switch either in series or in parallel depending on the literal form of the function. Connect the resulting relay circuit in series with an output device such as a motor, a pilot or indicator light, a control relay (the coil of a relay), or a solenoid (the coil of a magnetic actuator similar to a relay). The voltage for a ladder logic circuit is applied across the vertical lines labeled+and-.
3.2.2 A N A LY Z I N G I C L O G I C C I R C U I T S
Now lets analyze the symbolic logic circuits shown in Fig. 3.2.3.
U1 U2 A B F1 U4 C B U3 U3 U2 U1 U4 F2
X Y X Z
Figure 3.2.3 Circuits to be analyzed to obtain their Boolean functions.
(a)
(b)
We need to obtain the Boolean function and/or truth table for each circuit to analyze it. These circuits could represent relay pass logic circuits or they could represent regenerative logic circuits constructed from ICs. In this section we will assume that the circuits are IC logic circuits.
E X A M P L E In Fig. 3.2.3(a) the function F1 is written by first obtaining the outputs of U2 (Unit 2, an OR gate with output X + Y) and U3 (Unit 3, another OR gate with output X+Z) and then obtaining the output of U4 (Unit 4, an AND
134
CHAPTER 3
gate with output F1 = AX + YB (X + Z)). Function F1 is shown in POS form, so if X + Y=0 (X=1 when Y=0) or X+Z=0 (X=0 when Z=0) then F1=0, else F1=1. The truth table for F1 is shown below.
XY Z 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 F1 0 1 0 1 0 0 1 1
E X A M P L E In Fig. 3.2.3(b) the function F2 is written by first obtaining the outputs of U1 (Unit 1, an AND gate with output A B) and U3 (Unit 3, another AND gate with output C B) and then obtaining the output of U4 (Unit 4, an OR gate with output F2 = AA B + C BB ). Function F2 is shown in SOP form, so if A B=1(A=1 when B=1) or C B=1(C=0 when B=1) then F2=1, else F2=0. The truth table for F2 is shown below.
AB C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 F2 0 0 1 0 0 0 1 1
As you can see from these examples, the analysis of small IC (or relay) logic circuits is fairly simple. All one needs to do is to write the output function of the circuit in terms of the input variables.The truth table for the output function can also be obtained. In practice, each IC package in a circuit or on a printed circuit board (PCB) is assigned a unit number (U number). Each IC package can contain more than one gate or more than one Inverter.When using TTL small-scale integration (SSI), the circuit in Fig. 3.2.3(a) would only be assigned three U numbers, since the Inverter would be available in one IC package, two OR gates would be available in one IC package, and the AND gates would be available in another IC package. The Inverter could be labeled U1a, the two OR gates could be labeled U2a and U2b, while the AND gate could be labeled U3a. When using a programmable logic device (PLD), the IC package would be labeled U1, since all the gates are contained in the same package. U numbers are called reference designators. The analysis of IC logic circuits for all gate types is carried out in the same manner as illustrated in the previous examples. Simply write the function of each circuit in terms of the inputs.
SECTION 3.2
135
3.2.3
DESIGNING IC LOGIC CIRCUITS
We present circuit design or synthesis working from Boolean functions. After a Boolean function has been minimized and written in a literal form, we can substitute the required graphic symbols for the operators to obtain a symbolic logic diagram. The easiest way to manually design an IC logic circuit is to initially use only the graphic symbols for OR gates, AND gates, and Inverters. Later we will show how to generate design implementations using NAND gates and NOR gates. The computer aided design (CAD) approach to IC logic circuit design involves writing functional descriptions for circuits in terms of a hardware description language (HDL) such as VHDL or Verilog HDL. An alternate CAD approach uses an industrial software package, such as StateCAD by Visual Software Solutions Inc., to generate these functional descriptions for you. We will use the manual method to introduce you to digital design. If you have access to VHDL, Verilog HDL, or StateCAD you should strive to learn these CAD packages, since they are true productivity tools and used in industry on a daily basis. A productivity tool is a tool that helps shorten the design cycle (the time it takes to design a product and get it into the market). As shown earlier, we can reduce a Boolean function to a minimum form via a K-map. The resulting minimum SOP or POS form is in literal form, i.e., each expression of an SOP or a POS form contains literals that are connected only by AND and OR operators. The process for designing an IC logic circuit with gates can be broken down into four simple steps: (a) draw the gate layout, (b) show all signals, (c) interconnect the gates including Inverters, and (d) clean up or simplify. E X A M P L E To illustrate the design process for an IC logic circuit, consider the following minimum SOP form for function F1: F1=A B C+B C+A B. For F1 the gate layout requires three AND gates and one OR gate as shown in Fig. 3.2.4 using a horizontal input scheme.
A B C 3-input AND gate
Figure 3.2.4 IC logic circuit design for a minimum SOP form of a function using a horizontal input scheme.
B C 2-input AND gate A
F1 3-input OR gate
2-input AND gate
We will assume for now that all the signal names for the circuit inputs and the circuit output must be non-complemented signal names. The next step is to interconnect the gates to produce the required function, providing Inverters where necessary. The final step is one of cleanup or simplification if necessary. In this step we didnt have to use a fourth Inverter, since we can use B anywhere once we have generated it. This is also true for the signals A and C if we need them to obtain the output for a particular function.
136
CHAPTER 3
Each IC for a particular logic family has a fan-out. The fan-out is the maximum number of inputs to which the IC output can be connected without electrically loading down the output. As long as the fan-out is not exceeded, the IC will function properly. The fan-out for the LS TTL family is 20 (or 20 inputs). The original or standard TTL family has a fan-out of 10 (or 10 inputs) only. Be careful to label each signal line with only one name. Another name you should know is fan-in. Fan-in is the name used to describe the number of inputs to a gate. A signal line is a line drawn to an input line of a gate symbol or an Inverter symbol, or a line drawn from an output line of a gate symbol or an Inverter symbol. A net is the name used to describe signal lines that are connected together to carry the same signal. In Fig. 3.2.4, signal lines with the same signal names are considered to be connected, i.e., they belong to the same net. If you were to wire up the circuit in Fig. 3.2.4 in the laboratory, you would need to connect all signal lines together that have the same name.
E X A M P L E In Fig. 3.2.5 we show two alternate solutions for function F1: F1=A B C+ B C+A B. Both solutions use a connection scheme for the input signal lines called a vertical input scheme. Circuits drawn using a vertical input scheme are usually more organized. With this scheme one can draw large circuit designs in SOP or POS form quite rapidly. The vertical input scheme eliminates the need for a cleanup or simplification step.
AABBCC A A B C
B C
3-input AND gate
3-input AND gate
F1 2-input AND gate 3-input OR gate IC package count = 4 2-input AND gate (a)
or 3-input AND gate
F1 3-input OR gate IC package count = 3 (due to fan-in reduction) 3-input AND gate (b)
Figure 3.2.5 IC logic circuit designs for a minimum SOP form of a function using a vertical input scheme: (a) without fan-in reduction, (b) with fan-in reduction.
Notice in Fig. 3.2.5(a) that the IC package count is 4, but in Fig. 3.2.5(b) the IC package count is only 3. After obtaining a circuit design for a minimum function it is sometimes possible to build a smaller implementation of the circuit by using fewer ICs. This may sometime be accomplished by using the spare (or unused) gates in an IC package as illustrated in Fig. 3.2.5(b). An IC package containing a 3-input AND gate actually has three such AND gates in one package. This allows us to use the two extra 3-input AND gates as 2-input AND gates by
SECTION 3.2
137
tying each extra input to one of the used inputs as shown in Fig. 3.2.5(b). This technique may be referred to as fan-in reduction. By using fan-in reduction one less IC package is required for the design, namely the package containing 2-input AND gates. OR gates with more than two inputs for some off-the-shelf logic families (such as TTL) are not available in ICs. This may pose a problem with the circuit designs in Fig. 3.2.4 and Fig. 3.2.5. Connecting (cascading) 2-input OR gates in series to obtain a 3-input OR gate easily solves this problem as in Fig. 3.2.6(a).
=
(a) (b)
Figure 3.2.6 Cascading IC gates: (a) 3-input OR gate, (b) 4-input OR gate.
Connecting 2-input OR gates in series provides us with a 4-input OR gate as shown in Fig. 3.2.6(b). This solution also has a problem. The resulting cascaded circuit provides an output that responds more slowly to input changes as the number of cascaded stages is increased. We will consider this phenomenon farther a little later on.
E X A M P L E
Consider the function F2 written in a minimum POS form as F2= AX + YB AX + YB AX + ZB. A circuit design for this function is shown in Fig. 3.2.7 using a vertical input scheme.
XXYYZZ X
Figure 3.2.7 IC logic circuit design for a minimum POS form of a function using a vertical input scheme.
Y 2-input OR gate Z F2 2-input OR gate 3-input AND gate
2-input OR gate
The main difference between the design of an SOP form of circuit and a POS form of circuit is the placement of the AND gates and the OR gates. For an SOP form of circuit, the ANDs in the circuit feed into an OR, and for a POS form of circuit, the ORs feed into an AND.
138
CHAPTER 3
The circuit design for the SOP form in our examples was for the 1s of the function F1, while the circuit design for the POS form in the last example was for the 0s of the function F2.
E X A M P L E Suppose you were asked to design a logic circuit, an event detector, that could detect when exactly two 1s out of three occurred when monitoring three signal lines A, B, and C. Let F3 represent the detection output (a logic 1 represents detection while a logic 0 represents no detection). Obtaining a function for the circuit: F3(A, B, C) must consist of the three product terms A B C, A B C, and A B C that each detect exactly two 1s via the three inputs. These product terms must be ORed together and equated to the detection output signal line F3, our detection output indicator. Our function to detect exactly two 1s out of three thus becomes: F3(A, B, C)=A B C+A B C+A B C. Notice that this is a minimum function since it cannot be reduced. Obtaining a circuit diagram or schematic for the function: A circuit design for the function F3 is shown in Fig. 3.2.8.
Figure 3.2.8 Circuit design for a two-1s-out-of-three event detector.
A B C A B C A B C 3-input AND gate 3-input AND gate F3 3-input OR gate 3-input AND gate
You should now understand the concept of an event detector.The circuit design for a two-1s-out-of-two event detector is a 2-input AND gate, and the Boolean function is F4(A, B)=A B. The circuit design for a one-or-more-1s-out-of-two event detector is a 2-input OR gate from the Boolean function F5(A, B)=A B A B+A B=A+B, i.e., the truth table for an OR operation.
3.2.4 G E N E R AT I N G D E TA I L E D S C H E M AT I C D I A G R A M S
All the circuits that we have drawn up to now are functional logic diagrams, that is, they are functionally correct but lack the details necessary to show the actual IC connections (or wiring) required to build the circuit in the lab. The circuit shown in Fig. 3.2.9(a) is an example of a detailed schematic diagram using off-the-shelf Advanced Low Power Schottky (ALS) TTL IC devices.
SECTION 3.2
Input pins 4 2-input OR gates/ IC package 3 1 U2b 6 Output pins 4 2-input AND gates/ IC package (a) 2 U3a 3 F8 U1 U2 U3 74ALS04 74ALS08 74ALS32
139
A 1 B C B 3
U1a
2 1 2 4 4 5
U2a
Reference designator
Part number Pin number Vcc* GND 14 14 14 7 7 7
Figure 3.2.9 Detailed schematic diagrams (a) implemented with TTL IC devices, (b) implemented with a CMOS IC device.
U1b 6 Inverters/ IC package
* +5 V
4 2-input XOR gates/ IC package A 1 B 2 U1a 3 F8 U1 (b) 74HC86 Reference designator Part number Pin number Vcc* GND 14 7 * +5 V
In Fig. 3.2.9(b) we show a detailed schematic diagram for the function using a high-speed CMOS (HC) IC device. This IC has four XOR circuits in the same package, of which we are only using one. The following steps are necessary when drawing a detailed schematic diagram: (1) identify the part number for each IC in the circuit; (2) show the pin numbers (also referred to as pinouts) for all ICs in the circuit; and (3) show the power connections (Vcc and GND) for all ICs in the circuit. Consult manufacturers data books or data sheets for the information needed for detailed schematic diagrams. See Appendix B for selected devices with pinout diagrams for 74 series ICs. Before wiring up a circuit in the lab you should generate a detailed schematic diagram and then use it to wire up the circuit. Many companies require detailed schematic diagrams so that an accurate record can be kept for each design. In addition they require a written record to explain how the circuit works.
3.2.5 D E S I G N I N G C I R C U I T S U S I N G D E M O R G A N E Q U I VA L E N T S Y M B O L S A N D E Q U I VA L E N T S I G N A L L I N E S
In designs using gate-level IC devices, NANDs and NORs are preferable to ANDs and ORs. There are three main reasons that this is true. NAND gates are generally faster than AND gates, and NOR gates are generally faster than OR gates in the same SSI logic family. The second reason may seem strange at first. NAND gates can be used to design a circuit for any function, since, as we shall discover, a NAND gate can be used as an Inverter, an AND gate, or an OR gate. The same is true for NOR gates. This makes NAND and NOR gates functionally complete gates, since either of them can be used to design a circuit for any function. Neither AND gates nor OR gates are functionally complete, since you cannot design a circuit for any function with only AND gates or only OR gates without using Inverters. The third reason is simply that NAND gates and NOR gates are available with a larger variety of fan-ins (gate inputs) to choose from than AND gates and OR gates.
140
CHAPTER 3
Equivalent Graphic Symbols for NAND, NOR, AND, and OR Gates
DeMorgans Theorem allows us to represent expressions and graphic symbols in two different forms, an AND form and an OR form. These two forms allow us to more rapidly draw circuit designs from functions.
E X A M P L E Lets begin with the NAND function F = A B. A circuit design for this function is shown in Fig. 3.2.10(a). It consists of an AND symbol and an Inverter symbol. Merging the Inverter symbol with the AND symbol (the triangle is removed and the circle or bubble is attached to the output of the AND symbol) results in an AND symbol with a bubbled output as shown in the same figure. We call this symbol the AND form of a NAND gate. Observe that this AND form has an internal Inverter on its output. Manufacturers normally draw the AND form of the NAND gate in their data books. The circle or bubble is called a negation indicator and represents the complement operation.
Figure 3.2.10 (a) Development of the AND form of a NAND gate, (b) development of the OR form of a NAND gate.
Function Circuit design with AND or OR gate and Inverters A B F = AB AND gate Graphic Symbol Naming Convention
NAND
F External Inverter
A B
F Internal Inverter
AND form of a NAND gate
(a)
A NAND F=A+B B External Inverter OR gate F A B Internal Inverter (b) F OR form of a NAND gate
By DeMorgans Theorem we can also write the NAND function as F = A + B. The circuit design for this function is shown in Fig. 3.2.10(b) and consists of two Inverter symbols and an OR symbol. Merging the two Inverter symbols with the OR symbol (the triangles are removed and the circles or bubbles are attached to the inputs of the OR symbol) results in the OR symbol with bubbled inputs as shown in the same figure. We call this alternate NAND symbol the OR form of a NAND gate. Observe that this OR form has two internal Inverters, one on each input. The AND form and OR form of a NAND gate are DeMorgan equivalent symbols. Graphically we obtain DeMorgan equivalent symbols by the following change symbol rule: (1) change an AND symbol to an OR symbol (or vice versa); (2) where bubbles exist remove them, and (3) where no bubbles exist add them.
SECTION 3.2
141
E X A M P L E Show the DeMorgan equivalent symbols for the following gate types: NAND gate, NOR gate, AND gate, and OR gate. A summary of gate types and their DeMorgan equivalent symbols is shown in Fig. 3.2.11. When converting from one form to the other, you may use DeMorgans Theorem or simply apply the change symbol rule.
Gate Type NAND gate
AND symbol with a bubbled output
AND form
OR form
=
OR symbol with bubbled inputs
Figure 3.2.11 Summary of gate types and their DeMorgan equivalent symbols.
NOR gate
AND symbol with bubbled inputs
=
OR symbol with a bubbled output
AND gate
AND symbol
=
All bubbled OR symbol
OR gate
All bubbled AND symbol
=
OR symbol
Fan-in reduction can be used for NAND gates and NOR gates to convert these gate types to simple Inverters. This is an application of the Idempotency Theorem since F = A B C p =A A A p =A and F=A + B + C p =A + A + A p =A. Simply tie all the inputs together and these gate types may be used as Inverters. In some cases this may be done to reduce the IC package count when there are spare (or unused) NAND gates or spare NOR gates in an IC package. Equivalent Signal Lines The technique of using equivalent signal lines allows us to draw a circuit in many different ways without changing the functionality of the circuit, i.e., the Boolean equation of the circuit.The components or parts that are used to build the circuit are changed instead.A summary of equivalent signal lines is provided in Fig. 3.2.12, where each dotted line represents an input or an output of a gate.
External Inverter Inputs Internal Inverter
=
Bubble pushed in
=
Double complementation
Figure 3.2.12 Equivalent signal lines at inputs, outputs, and internal or between components.
Outputs
=
Bubble pushed in
=
Internal
=
=
142
CHAPTER 3
The same signal applied to the left-hand side of each of the equivalent signal lines in Fig. 3.2.12 results in an equivalent signal on the right-hand side. Substituting equivalent signal lines in a circuit design does not change the functionality of the circuit. Learning two different symbolic forms (equivalent AND and OR forms) for each gate and equivalent signal lines allows you to more easily obtain circuit designs for functions. Designing circuits in this fashion is a graphical design technique as opposed to a pure mathematical design technique which requires arranging Boolean functions in a form required for the desired gate types. The Double Complementation Theorem and DeMorgans Theorem are used to arrange the Boolean functions. For the graphical design technique, designs are first obtained in SOP form or POS form using AND gates, OR gates, and Inverters. Designs are then modified using equivalent signal lines to obtain the required gate types.
Designing Circuits with NAND Gates and with NOR Gates
E X A M P L E To show the technique, we will design a circuit using only NAND gates and Inverters to implement the minimum Boolean function F1=A B C+B C+A C. First, obtain the design for the circuit in SOP form as the function is stated. This is shown in Fig. 3.2.13(a) and is also commonly referred to as AND/OR gate form for the obvious reason that the circuit is drawn with AND gates feeding an OR gate.
A B C 3-input AND gate B C 2-input AND gate A C 2-input AND gate (a)
A B C
(Three AND forms of NAND gates)
3-input NAND gate B C
(One OR form of a NAND gate) F1
F1 3-input OR gate
2-input NAND gate 3-input NAND gate A C 2-input NAND gate (b)
Figure 3.2.13 Technique for designing a circuit using NAND gates and Inverters: (a) obtain design for circuit in AND/OR gate form, (b) change the circuit to NAND/NAND gate form via equivalent signal lines.
The AND/OR gate form of the circuit is then modified to a NAND/NAND gate form via equivalent signal lines.
SECTION 3.2
143
E X A M P L E Modifying the AND/OR gate form for the circuit for F1 in Fig. 3.2.14(a) allows us to obtain a circuit in NOR/NOR gate form as shown in Fig. 3.2.14(b). To do this we must know the DeMorgan equivalent forms for the NOR gate and then use equivalent signal lines to obtain the correct forms.
A B C 3-input AND gate B C 2-input AND gate A C 2-input AND gate (a) B C 2-input NOR gate A C 2-input NOR gate (b) 3-input NOR gate (Three AND forms of NOR gates) A B C 3-input NOR gate (One OR form of a NOR gate) F1
F1 3-input OR gate
Figure 3.2.14 Technique for designing a circuit using NOR gates and Inverters: (a) draw the circuit in AND/OR gate form, (b) change the circuit to NOR/NOR gate form via equivalent signal lines.
Circuits are easier to analyze and design if the gate forms for the circuits are chosen such that indicator matching (bubble matching) occurs on the signal lines between the gate forms. A signal line with matching indicators has the same indicator at each end of the signal line. In Fig. 3.2.15 we show equivalent circuits with matching
A B
Signal lines with matching indicators
A B F1
C D Preferred form of AND/OR circuits
Signal lines with mismatching indicators
F1
C D
Figure 3.2.15 Circuits drawn with matching and mismatching indicators on signal lines between gate forms: (a) preferred form for AND/OR circuits, (b) preferred form for NAND/NAND circuits, (c) preferred form for NOR/NOR circuits.
(a) W X
Signal lines with matching indicators Bubble matching
Bubble mismatching
F2
X
F2
Y Z Preferred form of NAND/NAND circuits (b) T U

Signal lines with matching indicators Non-bubble matching
Y Z
T U
F3
V W Preferred form of NOR/NOR circuits
(c)
F3
V W
144
CHAPTER 3
signal line indicators and with mismatching indicators (bubble mismatching). Circuits drawn with matching signal line indicators are preferred. E X E R C I S E S T O T E S T Y O U R K N O W L E D G E
(For solutions see Section 3.9, Worked Exercises) 12. Analyze each of the following pass logic switching circuits to obtain their output functions and their truth table.
Z X Z
n.o. n.c.
n.c.
X
n.o.
Y F2
F1
13. Design a pass logic switching circuit for the function F1 = Z Y + X Y using pushbutton switches and for the function F2=X Y Z + X Y Z+X Z using relays. 14. Show the design for an AND-gate ladder logic circuit driving a control relay. Show the circuit first in symbolic form and then using relays. 15. Show the design for a NAND-gate ladder logic circuit driving a green pilot lamp. Show the circuit first in symbolic form and then using relays. 16. Analyze each of the following symbolic logic circuits to obtain its Boolean function and its truth table.
A B C B F1 A B C B F2
17. Analyze each of the following circuits to obtain its Boolean function and its truth table.
A B W X
A C
F1
Y X
F2
18. Write the change symbol rule in words. The change symbol rule results from the application of what theorem? 19. Obtain the symbols for the following functions using the change symbol rule: (a) an OR gate with one bubbled input and a bubbled output and (b) an AND gate with one bubbled input and a bubbled output. Identify the form of the converted symbol, i.e., an AND form or an OR form and a name.
SECTION 3.3
COMPRESSING TRUTH TABLES AND K-MAPS
145
20. Name the resulting gate types for the following circuits: (a) a circuit with two external Inverters, each driving a separate input of a 2-input NOR gate and (b) a circuit with a 3-input AND gate driving an external Inverter. To determine the gate types, substitute equivalent signal lines for lines that contain external Inverters. 21. Obtain a minimum SOP form for the 1s of function F(X, Y, Z)= g (0, 1, 3) + g md(5, 6, 7) using a K-map. If you were to implement a circuit for function F with IC packages, which gate form would be preferred, NAND/NAND or NOR/NOR? Show the design for both forms. Be sure to use fan-in reduction, if you can, to reduce the IC package count. 22. Obtain a minimum SOP form for the 0s of function F expressed as F(W, X, Y, Z)= g (0, 1, 2, 3, 4, 5, 6, 15)+ g md(7) using a K-map. If you were to implement a circuit for function F with IC packages, which gate form would be preferred, NAND/NAND or NOR/NOR? Show the design for both forms. Be sure to use fan-in reduction, if you can, to reduce the IC package count. 23. Design a two-1s-out-of-four event detector for inputs A, B, C, D and output F with NAND gates. Use a vertical input scheme and fan-in reduction if required for off-the-shelf IC packages. 24. Implement the function F=X Y+X Z in NAND/NAND gate form. Also implement the function F in NOR/NOR gate form.
3.3
Compressed truth tables save space, and compressed K-maps allow functions to be reduced with smaller maps. In this section we first present compressed truth tables and then use the compressed truth tables to draw compressed K-maps. An algorithm is presented to read reduced functions from the reduced K-maps. Compressed truth tables and K-maps may also be used when designing circuits with Multiplexers, as we shall see a little later in this chapter.
3.3.1 T E C H N I Q U E F O R C O M P R E S S I N G T R U T H TA B L E S A N D K - M A P S
To understand the compression of truth tables let us first show how to form a truth table via Shannons Expansion Theorem for one variable: F(A)=A F(0) A F(1), where the function F is expanded about A. F(A) = A F(0) + A F(1) 1 F(A) 1 A F(0) + A F(1) F(A) A F(0) A F(1) 1 A F(A) 0 F(0) 1 F(1)
Reversing the procedure provides the technique for compressing a truth table. The following truth table is for the Complement function, i.e., F(0)=1 and F(1)=0, and shows the compression of a truth table about A. A F(A) 0 1 1 1 0 F(A) A1 A0 c 1 F(A) A1 + A0 c
Row compression requires ORing
F(A) 1 A
Column compression requires ANDing
146
CHAPTER 3
We can compress the truth table by one column by ANDing and then compress the truth table to one row by ORing. In other words, column compression requires ANDing while row compression requires ORing. To speed up the process it is more efficient to write the result on one line as A 1+A 0, which reduces to A. Once you understand the compression concept, you can easily compress any truth table using Shannons Expansion Theorem.
E X A M P L E For the function, F2(A, B)= g (2), obtain the truth table and then compress the truth table about B. The truth table and its compression about input variable B follow:
A 0 0 1 1 B 0 1 0 1 F2 0 F2(0, B)=0 0 1 F2(1, B)=B 0 1 1 B F2 A F2 0 0
Observe how easily the truth table is compressed about input variable B, i.e., the least significant bit. You can actually compress any size truth table by one variable simply by inspection. We partitioned off variable B so that a comparison can easily be made with the function column and the B column. Input variable A remains as one of the columns in the compressed table while input variable B is compressed into the function column F2. Compare the function values of F2 with the values of the B column when A is constant at 0 and also when A is constant at 1. When A is constant at 0, F2 is not a function of B and is always 0. The same result is obtained from Shannons Expansion Theorem by expanding F2 about variable B when A is constant at 0: F2(0, B)=B F2(0, 0)+B F2(0, 1)=B 0+B 0=0. It is helpful to draw a line in the truth table separating the two values of A as shown. When A is constant at 1, F2 is a function of B and is B. From Shannons Expansions Theorem when expanding about B when A is constant at 1 we obtain the same result: F2(1, B)=B F2(1, 0) B F2(1, 1)=B 1+B 0 = B. Any size truth table can easily be compressed by expanding about the least significant bit in the table. Compressed truth tables are space savers. The number of lines in a compressed truth table is decreased 50% (or decreased by a factor of 2) for each compressed variable, i.e., the compressed table is 1/2cv*original size, where cv=number of compressed variables. Compressed truth tables may be used to plot compressed K-maps that also are space savers. Some software reduction packages allow compressed truth tables to be used as an entry method for a function. Compressed truth tables can also be used to implement functions with Multiplexers (MUXs).
SECTION 3.3
147
E X A M P L E Compress the following truth table about C, the least significant bit.
A B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 C 0 1 0 1 0 1 0 1 F3 F3 0 0 0 AB 0 C 1 1 1 1 1 C 0 1 0 0 0 1 1 0 1 1 F3 0 C 1 C
Compare the values for F3 to the values of C when A B=00, then when A B=01, A B=10, and finally when A B=11. Partitioning off variable C, the least significant bit, helps in the comparison process. The results of these comparisons are shown in the second column of F3 and represent, F3(0, 0, C)=0, F3(0, 1, C)=C, F3(1, 0, C)=1 and F3(1, 1, C)=C, respectively. The same results are obtained by applying Shannons Expansion Theorem with respect to variable C (the least significant bit) using row and column compression. A K-map can also be compressed by inspection using the same technique as illustrated for truth table compression. Figure 3.3.1 shows the technique for compressing variable C for function F3 to obtain a compressed K-map.
Figure 3.3.1 Compressing variable C for function F3 to obtain a compressed K-map.
00 0 01 C 11 C 10 1
AB F3 =
C 0 00 01 11 10 0 0 1 1 1 0 1 0 1
Compare
AB F3 =
Compare
Uncompressed K-map
Compressed K-map
In Fig. 3.3.1, variable C was chosen as the reference variable, i.e., the K-map was compressed about variable C. One advantage of compressing a K-map rather than a truth table is the ease with which any variable can be selected as the reference variable.
148
CHAPTER 3
E X A M P L E Use variable A as the reference variable and obtain a compressed K-map for function F3. The compressed K-map is shown in Fig. 3.3.2.
Figure 3.3.2 Compressing variable A for function F3 to obtain a compressed K-map.
Compare
AB F3 =
C 0 00 01 11 10 0 0 1 1 1 0 1 0 1 Compare
B F3 =
C 0 0 A 1 A
1 A
Uncompressed K-map
Compressed K-map
As an example of multivariable K-map compression, consider the 4-variable truth table shown in Fig. 3.3.3.
W X Y Z 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
F 1 1 0 0 1 0 0 1 1 0 0 0 1 0 0 1 Compare WX F= 00 01 11 10 YZ 00 01 11 10 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 WX F= 00 Y 0 1 1 0 Z Z 0 Compare WX F= 00 Y 01 YZ +YZ 11 YZ +YZ 10 YZ
01 Z 11 Z 10 Z
Figure 3.3.3 Multivariable K-map compression using reference variables Y and Z.
Plotting the usual truth table, i.e., the uncompressed or 0-1 truth table, in a usual K-map (uncompressed K-map) allows us to use K-map compression to compress the map first to a 3-variable compressed K-map and then to a 2-variable compressed K-map as illustrated in the figure. Notice that when the values for the function are just 0s and 1s, i.e., no dont cares, the comparisons are simple and result in one of four possibilities (0, 1, Z, or Z) for the reference variable Z in the 3-variable compressed K-map. Shannons Expansion Theorem must be used to compute the result when comparisons are made with reference variable Y for values of the function that contain variables in the 3-variable compressed K-map.The 2-variable compressed K-map can be obtained directly from the usual K-map using two reference variables. Treating each row of the 4-variable K-map as a subK-map and obtaining a minimum function for the 1s of the submap easily does this.
SECTION 3.3
149
3.3.2
PLOTTING, FILLING, AND REDUCING COMPRESSED K-MAPS
Compressed K-maps were first introduced by T. E. Osborne in his Patent No. 3566160 filed in June 1966. Osborne referred to variables plotted in the cells of a compressed K-map as map-entered variables. Compressed K-maps were used by the Hewlett Packard Company to reduce the functions implemented in the first hand-held calculator and many other successful HP products.Today computer programs perform function reduction, but the concept of compressed K-maps is a tool to help us perform function reduction by hand. The compressed truth table for function F2(A, B)= g (2) about B is repeated as follows:
A 0 1 F2 0 B
From this compressed truth table we can plot a 1-variable compressed K-map shown in Fig. 3.3.4.
A F2 = 0 0
0
1 B
1
Figure 3.3.4 Compressed K-map plotted for function F2(A, B)= g (2).
Now consider the more complex function F3 plotted in the compressed 2variable K-map in Fig. 3.3.5.
WX F3 = 00 Y 0 01 11 1 1 3
Figure 3.3.5 Compressed 2-variable K-map.
10 Z 2 - = don't care
Input variables Y and Z that appear in the cells of the compressed map are the mapentered variables.A functional relationship for the function F3 in Fig.3.3.5 may be written as follows:F3(W, X, Y, Z)= g A0 Y, 1, 2 ZB+ g md(3), where m=m(W, X). The term m=m(W, X) indicates that the minterms in the summation list are formed using only the variables W and X. This means for function F3(W, X, Y, Z) that 0 Y=m0 Y=W X Y, 1=m1=W X, 2 Z=m2 Z=W X Z, and md(3) m3 =W X . Expanding the compressed 2-variable K-map to a 4-variable K-map allows us to write the function F3 as F3(W, X, Y, Z)= g (2, 3, 4, 5, 6, 7, 8, 10)+ g md(12, 13, 14, 15), where m=m(W, X, Y, Z) as shown in Fig. 3.3.6.
WX F3 = 00 Y 0 01 11 1 1 3
WX F3 =
YZ 00 01 11 10 00 01 11 10 0 1
0 4
Figure 3.3.6 Expanding the compressed 2-variable K-map.

2 6
0 1
1 5
1 1
3 7
1 1
- 12 - 13 - 15 - 14 1
8
10 Z 2
011 110
150
CHAPTER 3
Compressed K-maps can be used to reduce functions. The steps to follow in reading the 1s of a function plotted in a compressed K-map are listed in the following two-step reduction procedure.
Step 1:
Choose cube sizes that result in minimum expressions for the function by covering each map-entered variable separately, treating other map-entered variables as 0s and all 1s as dont cares. Choose cube sizes that result in minimum expressions for the function by covering the 1s in the map that are not complementary covered in step 1, treating all map-entered variables as 0s and all complementary-covered 1s as dont cares.
Step 2:
DEFINITION 3.3.1 A complementary-covered 1 in a compressed K-map is a 1 that is covered with a map-entered variable and covered again by the complement of the same map-entered variable. An example of a complementary-covered 1 on a compressed K-map is illustrated in Fig. 3.3.7(a).
Figure 3.3.7 (a) Complementary covered 1 on a compressed K-map, (b) Same function on a uncompressed K-map showing that the complementary-covered 1 is a redundant prime implicant.
XY FC1 = 00 (Complementarycovered 1) 0 p3 = XY (Redundant prime implicant) p2 = XZ 01 Z 11 1 p1 = YZ XY FC1 = 00 01 11 10 Z 0 0 0 1 1 1 0 1 1 0
10 Z Compressed K-map (a)
Uncompressed K-map (b)
Function FC1 has a complementary-covered 1 at minterm location 3 on the compressed K-map.This is a complementary-covered 1, since it is covered once by the cube that covers Z and again by the cube that covers Z. A complementarycovered 1 on a compressed K-map results in a redundant prime implicant if it is used as a 1 in step 2 of the reduction procedure (notice in the reduction procedure that all complementary-covered 1s must be used as dont cares in step 2). Expanding the compressed K-map in Fig. 3.3.7(a), we obtain the uncompressed K-map in Fig. 3.3.7(b). To expand a map, reverse the procedure for compressing a map. In Fig. 3.3.7(b) we can easily observe that the complementary-covered 1 should not be covered if we are trying to obtain a minimum function.
E X A M P L E Plot the following 6-variable function in a 4-variable compressed K-map, then obtain a minimum expression for the function by reading the compressed K-map: F4(A, B, C, D, Y, Z, )= g A0 Y, 1 Y, 4, 5, 6 Z, 7, 12 Y, 14, 15 ZB = + g md(13), where m=m(A, B, C, D) The function is shown plotted in Fig. 3.3.8.
SECTION 3.3 Step 1: AB CD F4 = 01 p3 Y 1 0 (a) 0 1 Z 0 0 Z 1 0 00 Y Y 0 (b)
151
AB F4 =
CD 00 01 11 10 00 Y 01 1
p2
Step 2: AB CD F4 = 00 p1 01 11 10 00 01 11 10 0 0 0 0 0 (c) 0 1 0 0 0 0 1 0 p4 p5 0 Z 0
00 01 11 10 0 Z 0
11 Y 10 0
11 Y 10 0
Figure 3.3.8 (a) Compressed K-map to be read: (b) step 1 of procedure, (c) step 2 of procedure.
First read the product terms for the compressed K-maps in the normal manner and AND them with the respective map-entered variable. The product term for p1 is the normal product term B C ANDed with the mapentered variable Z, or p1=B C Z. The product term for p2 is the normal product term A C ANDed with the map-entered Y, or p2 = A C Y. The product term for p3 is the normal product term B C ANDed with the map-entered variable Y, or p3 = B C Y. In step 2, list only 1s that are not complementary covered while all other 1s (the complementary covered 1s in cells 4 and 5) are listed as dont cares. If complementary covered 1s are not listed as dont cares in step 2, then they will be covered and result in redundant product terms. Read product terms for the ones in the normal manner. Product term p4 = A B C D while product term p5 = A B D. A reduced function for F4 is F4=p1+p2+p3+p4+p5, which results in F4=B C Z+A C Y+B C Y+A B C D+A B D as a minimum SOP expression for the function F4. We have demonstrated how to read reduced expressions for compressed K-maps by using two separate maps, one map for each step listed in the procedure. Using only one map to cover the product terms saves time and effort, but until the concept is well understood, it may be wise to apply each step with a separate map as we demonstrated in Fig. 3.3.8(b) and (c). E X E R C I S E S T O T E S T Y O U R K N O W L E D G E
(For solutions see Section 3.9, Worked Exercises) 25. Write the function F(A, B, C, D)= g (0, 5, 7, 12, 15) in a 4-variable truth table, then compress the truth table about input variable D. 26. Write the function F(A, B, C)= g (2, 3, 5, 6) in a 1-variable compressed K-map using B and C as the compressed variables. Use K-map compression to obtain the 1-variable compressed K-map. Verify your solution using truth table compression. 27. Plot the following 6-variable function in a 3-variable compressed K-map: F(A, B, C, D, E, G)= g A0,1 D, 4, 6, 7 AE GBB, m=m(A, B, C). Also write the function F in terms of its input variables.
28. Obtain a minimum expression for the function F(A, B, C, D, E, G)= g A0,1 (D G), 4, 6, 7 AE + GBB + g md(5), m=m(A, B, C). Show the plotted compressed K-map, and label the p-terms for a minimum expression on the map.
152
CHAPTER 3
29. Obtain a minimum SOP expression for the 0s of the function F3 shown in the following compressed K-map by complementing the function and solving for its 1s. Show the plotted compressed K-map, and label the p-terms for a minimum expression. Solving for the 1s of the function F3 in the complemented map is the same as solving for the 0s of the function F3.
W F3(X, Y, Z) = 0 1 X 0
Y Z
0 2
1 0 1 3
30. Obtain a minimum SOP expression for the 1s of the function FMOD in the following compressed truth table. Show a compressed K-map for FMOD with p-terms labeled for a minimum expressions on the map. Also solve for a minimum SOP expression for the 0s of the function FMOD.
A B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 C 0 1 0 1 0 1 0 1 F 0 0 1 1 0 1 0 1 FMOD 0 0 X YZ 0 1 0 1
3.4
GLITCHES AND THEIR CAUSES
A glitch is a momentary error condition on the output of a circuit due to unequal signal delay paths in a circuit. A glitch is identified as an additional pulse or pulses on the output.After the input signals to a circuit have settled or reached a steady state value of 1 or 0, the output signals are normally not available, i.e., not valid, until all the output signals have settled. Between the time that the input signals have settled and the output signals are being established, a glitch can occur if a hazard exists. There are two major types of hazards, function hazards and logic hazards. A glitch due to a function hazard can occur when two or more input signals to a circuit change in value at the same time. A function hazard is related to the function that is being implemented and cannot be removed by adding additional circuitry to the logic function. A glitch due to a logic hazard can occur only when one input signal to a circuit changes its value.A logic hazard can be removed by adding additional circuitry.A function hazard can be either static or dynamic.A logic hazard can also be either static or dynamic.
3.4.1 S TAT I C F U N C T I O N H A Z A R D S A N D S TAT I C L O G I C H A Z A R D S
A hazard is only an indication that a glitch may occur. As an example of a static function hazard, consider the function plotted in the K-map in Fig. 3.4.1(a).
SECTION 3.4
A F1 = 0 1 BC 00 01 11 10 0 1
0 4
153
A F1 = 0 0 13 02 17 16
BC 00 01 11 10 0 1 0 1
0 4
A F1 = 0 0 13 02 17 16
BC 0 1 0 1 0 0
p1 = BC 13 02 17 16 p2 = AC
00 01 11 10
0 4 1 5
1 5
1 5
Static function hazard (two or more input signals change) (a)
Static logic hazard (a single input signal changes) (b)
Static logic hazard (logic hazard cover term p3 = AB) (c)
p3 = AB
Figure 3.4.1 (a) K-map showing a static function hazard, (b) K-map showing a static logic hazard, (c) K-map showing a logic hazardcover term p3.
The arrows start and terminate on a 1, indicating a static 1 function hazard. The minimum SOP form of this function for its 1s is F1=A C + B C as obtained from the K-map. After implementing this function in NAND/NAND form (see Fig. 3.4.2), the circuit can be analyzed with a logic simulator in a software package such as B2 Logic or Logic Works.
A C
Figure 3.4.2 NAND/NAND form of circuit being analyzed via a simulator.
F1
You can use a circuit simulation to verify the following discussion. If the inputs to the circuit are changed from ABC=100 (cell 4 which has an output F1=1) to ABC=011 (cell 3 which has an output of F1=1) or vice versa, a static 1 hazard or logic 0 glitch may occur on the output F1 as shown in the timing diagram in Fig. 3.4.3(a).This is a function hazard, since three input signals (A, B, and C) are changed at the same time.
Static 1 hazard Logic 0 glitch 0 t (a) F1 0 Static 0 hazard (b) t
1 F1
1 Logic 1 glitch
Figure 3.4.3 Timing diagrams (a) Static 1 hazard and corresponding logic 0 glitch, (b) Static 0 hazard and corresponding logic 1 glitch.
If the inputs to the circuit are changed from ABC=000 (cell 0 which has an output F1=0) to ABC=101 (cell 5 which has an output of F1=0) or vice versa, a static 0 hazard exists and a logic 1 glitch may occur on the output F1, as shown in the timing diagram in Fig. 3.4.3(b). This hazard is also a function hazard, i.e., two input signals (A and C) are changed at the same time.
Logic Hazard-Free Functions A static 1 hazard may occur in the circuit shown in Fig. 3.4.2 if the inputs to the circuit are changed from ABC=111 (cell 7 which has an output F1=1) to ABC=110 (cell 6 which has an output of F1=1) or vice versa, as shown in the K-map in Fig. 3.4.1(b). This is a logic hazard, since only one input signal (C) is changed. The logic hazard may be removed if a logic hazard cover term p3=A B is provided in the function for the circuit design, see Fig. 3.4.1(c). The logic hazard cover term is the consensus term and it will hold the
154
CHAPTER 3
output F1 at 1 when the single input signal C changes from 0 to 1 or from 1 to 0. This is shown in Fig. 3.4.4.
Figure 3.4.4 Logic hazard-free function implemented with NAND gates.
A C
F1
A B
Gate that provides the logic hazard cover term that holds F1 at 1 when C changes
Remember that the logic hazard cover term is a redundant product term and serves only to remove the logic hazard and its corresponding glitch. A function written with all logic hazard cover terms included is called a logic hazardfree function. To obtain all of the logic hazard cover terms for a function, obtain a minimum function using a K-map and then chain link all of the product terms together.We call this the chain link rule. Each chain link term is a logic hazard cover term. The product terms for the 1s of the minimum function F1 are chain linked by product term p3 the logic hazard cover term as shown in Fig. 3.4.1(c). OR all logic hazard cover terms to the minimum SOP form to obtain a logic hazard-free function. E X A M P L E Write a logic hazard-free function for the 0s of function F1 in Fig. 3.4.1. Show the circuit implementation using NOR gates. To do these we first obtain a minimum SOP form for the 0s instead of for the 1s of the function for F1 as F1 = A C + B C. This function does not have the logic hazard cover term A B, which chain links the product terms for the 0s of the minimum function. Moving between the cells on the K-map covered by product term A B may cause a static 0 logic hazard as shown in Fig. 3.4.3(b) unless this product term is used in the function for F1 and also included in the circuit design for F1 as shown in Fig. 3.4.5.
Figure 3.4.5 Logic hazard-free function implemented with NOR gates.
A
B C
F1
A B
Gate that provides the logic hazard cover term that holds F1 at 0 when C changes
It is interesting to note that all static and all dynamic hazards will be removed by using the chain link rule when covering either the 1s or the 0s of a function.
SECTION 3.4
155
A circuit can be hazardous but cause a glitch only under certain circumstances. The circumstances might be just the correct amount of delay in the circuit.Since Boolean functions are implemented with components that have propagation delays, these delays are responsible for glitches. If all inverters, gates, and interconnect wires in a circuit had 0 propagation delay time, hazards and their corresponding glitches would not exist. If we remove a logic hazard, a glitch due to that hazard cannot occur. In most designs we can ignore glitches if we can wait until the output(s) settle prior to using them, i.e., wait until the output(s) become valid. In certain types of designs (asynchronous sequential circuit designs), however, we must to remove logic hazards or the circuits will malfunction.
3.4.2 DYNAMIC HAZARDS
A dynamic hazard can occur when an output changes from either 1 to 0 or from 0 to 1.A dynamic 1 to 0 hazard and a dynamic 0 to 1 hazard are illustrated in the timing diagrams in Fig. 3.4.6(a) and (b).
1 F2 0 t (a) Dynamic 1 to 0 hazard Logic 1 glitch F2 0 Dynamic 0 to 1 hazard (b) t 1 Logic 0 glitch
Figure 3.4.6 Timing diagrams: (a) dynamic 1 to 0 hazard and corresponding logic 1 glitch, (b) dynamic 0 to 1 hazard and corresponding logic 0 glitch.
Dynamic hazards are generally produced by multilevel logic circuits (cascaded logic circuits that contain more than two gate levels of logic). To substantiate this claim we tested the multilevel logic circuit for the function F2=A { (B { C) with the logic simulator in the software package B2 Logic.The K-map for the function F2 is shown in Fig. 3.4.7.
A F2 = 0 1 BC 00 01 11 10 0 1
0 4
Figure 3.4.7 K-map for function F2 showing two dynamic 0 to 1 hazards.
1 0
1 5
03 12 17 06
Dynamic 0 to 1 hazards
Expanding the function F2 into SOP form and implementing it as a 2-level gate circuit, we found that a dynamic hazard didnt produce a glitch (maximum propagation delays were used for all components). However, when we connected two XOR gates (maximum propagation delays were used for both XOR gates), a dynamic 0 to 1 hazard caused a logic 0 glitch as shown in Fig. 3.4.6(b) in two cases. The first case was when the inputs were changed from ABC=101 (cell 5 which has an output F2=0) to ABC=010 (cell 2 which has an output of F2=1). The second case was when the inputs were changed from ABC=110 (cell 6 which has an output F2=0) to ABC=001 (cell 1 which has an output of F2=1). In these two cases the delays in the circuit were distributed just right to allow the logic 0 glitch from dynamic function hazards. No other glitches occurred due to dynamic hazards. If the delays in the circuit were distributed differently, we would have also observed logic 1 glitches due to dynamic 1 to 0 hazards. Setting the XOR gates delays to 0 when using the simulator removes all static and dynamic hazards. In general, static hazards and the dynamic hazards exist in real circuits since the delays, which are due to circuit components and the wires connecting them, cannot be removed. It is interesting to play around with a simulator,
156
CHAPTER 3
since you can get a good feel for how a real circuit may respond under the conditions tested. Measuring real responses in a circuit requires rather expensive measuring equipment and much more time and patience. E X E R C I S E S T O T E S T Y O U R K N O W L E D G E
(For solutions see Section 3.9, Worked Exercises) 31. Name two types of hazards in logic circuits. How do they differ, and what can result from a hazard in a circuit? 32. What is the chain link rule, and what is it used for? State the chain link rule. 33. Show a timing diagram for a glitch that can result from a static 0 logic hazard. Name the glitch. Show a timing diagram for a glitch that can result from a static 1 function hazard. Name the glitch. Show a timing diagram for a glitch that can result from a dynamic 0 to 1 hazard. Name the glitch and tell how it is generally produced. 34. Design a logic hazard-free circuit to implement the function F(A, B, C, D)= g (0, 2, 4, 5, 6, 7, 8, 10, 11, 15) for its 1s. 35. Determine if there is a possibility that a glitch may occur if the inputs are changed from ABC=001 to ABC=110 in the circuit implemented for the function F = A{AB CB when the circuit is implemented with an XOR gate and an NAND gate. Is there a possibility that a glitch may occur if the inputs are changed from ABC=000 to ABC=001, from ABC=001 to ABC=010, and from ABC=110 to ABC=101? Provide your reasoning for each of the four cases.
3.5
TYPES OF FUNCTIONS AND DELAYS
Functions may be classified as trivial, simple, or complex.Trivial functions are those that contain no variables or only one variable. Simple functions are those that contain one or more OR operators or AND operators but not both. Complex functions are those that contain at least one OR operator and one AND operator after removing expressions with overbars by applying DeMorgans Theorem. Each of these function types is demonstrated below with examples of their circuit implementations. Circuit delays are caused by signals passing through the components that make up the circuit.Worst-case delay is caused by a signal passing through the slowest delay path in the circuit.
3.5.1 T R I V I A L F U N C T I O N S A N D D E L AY S
Trivial functions are equal to a fixed binary value such as 0 or 1 (the identity elements) or to a single noncomplemented or complemented variable. The circuit for a function like F1=0 represents a direct connection to Ground (GND) while the circuit for a function like F2=1 represents a direct connection to Vcc as illustrated in Fig. 3.5.1(a) and (b). The circuit for a function like F3=A is implemented with a Buffer, while the circuit for a function like F4 = A is implemented with an Inverter, as illustrated in Fig. 3.5.1(c) and (d).
Figure 3.5.1 Circuit implementations for trivial functions and their output delays.
F1 GND F1 = 0 (a) (b) Vcc F2 F2 = 1 A F3 A F4
F3 = A Output delay = 1tp (c)
F4 = A Output delay = 1tp (d)
SECTION 3.5
157
Notice that each of the trivial functions F1=0, F2=1, F3=A, and F4 = A contains one variable or fewer on the right-hand side of the equal sign. Circuits for trivial functions use Ground, Vcc , a Buffer, or an Inverter. When a signal must pass through a circuit, that circuit delays the signal. The delay caused by a component in a circuit is called propagation delay time and represented by the symbol tp . Each circuit has an output delay dependent on the number of components that an input signal must pass through to get to the output. The delays add up. For example, three similar Buffers connected in cascade or in series (where one output feeds into the next, etc.) cause a propagation delay of three times the propagation delay of one of the Buffer components or 3tp . Sometimes Buffers are used to slow down or delay a signal through a circuit.
3.5.2 S I M P L E F U N C T I O N S A N D D E L AY S
Simple functions contain only a single product or a single sum term.The single product or single sum term may be complemented. Examples of simple functions are: F5 = A + B F6 = X + Y + Z F7 = A B F8 = X Y Z Notice that each of these simple functions contains a single product term or a single sum term, i.e., F8 = X Y Z = X + Y + Z, where F8 is equal to a single product term complemented or a single sum term not complemented. E X A M P L E Show different circuit implementations or designs for the simple functions F5 through F8. The circuit designs are shown in Fig. 3.5.2.
A B F5 A F5
or
F5 = A + B
X X Y Z F6
F5 = A + B
X F6
or
Y Z
or
F6
F6 = X + Y + Z
F6 = X + Y + Z
F6 = X + Y + Z
A B
F7
or
F7
or
F7
F7 = AB
X X Y Z F8
F7 = AB
X F8
F7 = AB
or
Y Z
or
F8
F8 = XYZ 1-level gate circuits Output delay = 1tP
F8 = XYZ 1-level gate circuits Output delay = 2tP 2-level gate circuits Output delay = 3tP
F8 = XYZ
Figure 3.5.2 Circuit implementations for simple functions and their output delays.
158
CHAPTER 3
Each of the circuits shown in Fig. 3.5.2 is either a 1-level gate circuit or a 2-level gate circuit. A 1-level gate circuit is a circuit with only one gate. A 2-level gate circuit is a circuit with two cascaded gates. The number of gate levels of a circuit is usually a good measure of the output delay of the circuit. Every circuit has an output delay dependent on the slowest delay path through all the components in the circuit including gates, buffers, and inverters.The circuits on the left in Fig. 3.5.2 are faster than the circuits in the middle or on the right, since the signals have to travel through only one circuit component, assuming that the worst-case propagation delay time tp through each component in Fig. 3.5.2 is the same. tp=AtPLH+tPHL B/2 where tPLH is the average worst-case propagation delay time for a components output going low to high and tPHL is the average worst-case propagation delay time for a components output going high to low. In general, faster circuits have shorter delay paths. If all components have the same delay (this is not always true and must be checked by referring to manufacturers data books), then the fewer the number of cascaded components from the input to the output of the circuit, the faster the circuit. The circuits on the left in Fig. 3.5.2 have an output delay of tp or 1tp , the circuits in the middle have an output delay of 2tp , and the circuits on the right have an output delay of 3tp . In Fig. 3.5.2, output delay means the delay caused by the worst-case delay path, i.e., the slowest delay path, through the circuit. Notice in Fig. 3.5.2 that all simple functions can be implemented with 1-level gate circuits like the ones shown on the left in the figure.
Decoders
A very useful circuit that utilizes simple functions is called a Decoder. A circuit that converts a binary code applied to n input lines to one of 2n different output lines is called an n-to-2n Decoder.A Decoder with n input lines can convert 2n different codes applied to its input lines. Each code applied to its input is converted to a corresponding single bit on the output. In other words, a Decoder deciphers or decodes a binary code applied to its input lines by asserting a single output line that corresponds to the value that is deciphered or decoded. An example of a 2-to-4 Decoder circuit (or 2-to-4 Decoder) is shown in Fig. 3.5.3(a).
B1 B0
Figure 3.5.3 Decoder: (a) gatelevel circuit diagram, (b) logic symbol.
F0 = B1B0
F1 = B1B0 Decoder 0 F2 = B1B0 B0 B1 F3 = B1B0 0 B 1 F 2 3 F2 F3 1 F0 F1
(a)
(b)
SECTION 3.5
159
Notice that this Decoder is also a minterm generator. The logic symbol for the Decoder in Fig. 3.5.3(b) has active high inputs (no bubbles present) and active high signal names B0 B1, i.e., signal names with no overbars. Each signal name for the input is chosen to match the active high input (no bubble present) and hence each signal name has no overbar. The outputs on the logic symbol have active low outputs (bubbles are present) and active low signal names F0 F1 F2 F3, i.e., signal names with overbars. Each signal name for the output is chosen to match the active low output (bubble present) and hence each signal name has an overbar. Choosing signal names in this manner is called signal matching. When the binary input B1 B0 to the circuit is 00, for example, output F is decoded as 0 and the active low output named F0 is enabled and thus goes to 0. When the binary input B1 B0 to the circuit is 01, output F is decoded as 1 and the active low output named F1 is enabled and goes to 0.When the binary input B1 B0 to the circuit is 10, output F is decoded as 2 and the active low output named F2 is enabled and goes to 0, etc. This leads to the following truth table for a 2-to-4 Decoder with active high inputs and active low outputs.
B1 0 0 1 1 B0 0 1 0 1 F0 0 1 1 1 F1 1 0 1 1 F2 1 1 0 1 F3 1 1 1 0
Larger decoders (3-to-8, 4-to-16, 5-to-32, etc.) have similar truth tables and operate in a similar manner. Decoder circuits are available in software libraries of parts and as off-the-shelf devices. Decoders are often used in microprocessor or microcontroller systems as address decoders to select a specific device in the system such as RAM (random access memory) or EPROM (electrically erasable programmable read only memory) when an address is supplied to its input. Offthe-shelf Decoders are usually equipped with one or more enable inputs, some active high and some active low. A Decoder with an enable input is also called a Demultiplexer.
Designing Circuits with Decoders
You can design a circuit for any 2-variable function with a 2-to-4 Decoder (such as a 74LS139A) and a 3-input NAND gate (such as a 74LS10). You can use fan-in reduction to reduce the number of gate inputs required for the minterms for the 1s of the function. The design technique utilizes the fact that a 2-to-4 Decoder generates all possible minterms for two variables. A Decoder is a minterm generator. ORing the required minterms for the 1s of the function is the job of the NAND gate.
E X A M P L E Design a circuit with a 2-to-4 Decoder and a 3-input NAND gate that performs the XNOR function or F=X{Y. For input variables X and Y, the XNOR function may be written in compact minterm form for its 1s as F(X, Y)= g m(0, 3) = g (0, 3). The circuit design for the XNOR function is shown in Fig. 3.5.4. Since an off-the-shelf Decoder generally contains at least one enable input, we show the design using a 2-to-4 Demultiplexer
160
CHAPTER 3
(DMUX). The enable input must always be enabled, i.e., tied to its active level, which is low or ground in this case, for the circuit to work properly. See Appendix B for the pinout diagram of the 74 series 139 device.
Figure 3.5.4 Circuit design for the XNOR function using a Decoder and a NAND gate.
DMUX EN 0 GND Y X 0 B 1 3 F 2 1
F=XY
In a similar manner, you can design a circuit for any 3-variable function with a 3-to-8 Decoder (such as a 74LS138) and an 8-input NAND gate (such as a 74LS30; a 7-input NAND gate is sufficient but not available as an off-the-shelf component.) For any 4-variable function you need a 4-to-16 Decoder (such as a 74L154) and a 15-input NAND gate (this can be designed from smaller gates). A 15-input NAND gate requires an 8-input AND gate feeding an 8-input NAND gate. In each of these cases we are assuming that the circuit is being generated using the minterms for the 1s of the function. When implementing a function with a Decoder, it is best to use the fewest number of 1s or 0s to make up the function so that the fan-in of the gate is as small as possible. If there are fewer 1s in the function, use the compact minterm form for the 1s of the function to obtain the design; however, if there are fewer 0s in the function, use the compact minterm form for the 0s of the function. In the last example we could have used the following compact minterm form for the 0s of the function: F(X, Y)= g m(1, 2)= g (1, 2). Instead of using a NAND gate to obtain the output signal F, we must use an AND gate (all bubbled input OR form with a bubbled output) to OR the required minterms for the 0s of the function to obtain the output signal F. Additional gates can also be added to provide for additional outputs, thus allowing more than a single function to be implemented with a Decoder.
3.5.3 C O M P L E X F U N C T I O N S A N D D E L AY S
Complex functions contain at least one OR operator and one AND operator after removing expressions with overbars by applying DeMorgans Theorem. Examples of complex functions are: F9 = B C + A F10 = Y Z + X F11 = A B C + A B D + B C D E X A M P L E Show different circuit implementations for the complex functions F9 through F11. The circuit designs are shown in Fig. 3.5.5.
SECTION 3.5
A B C F9 A F9 = BC + A 2-level gate circuit Output delay = 2tp (a) F9 = BC + A 2-level gate circuit Output delay = 2tp A B D B C D

A B C
161
B C A F9
B or C
A F11 or B D B C D
F11
F11 = ABC + ABD + BCD 2-level gate circuit Output delay = 2tp Gate fan-in = 3
F11 = ABC + ABD + BCD 2-level gate circuit Output delay = 3tp Gate fan-in = 3 or
Y Z X F10
F10 = YZ + X 2-level gate circuit Output delay = 2tp or Y Z X F10
C D C D F11 = ABC + ABD + BCD = B(A(C + D) + CD) Multi level (4-level) gate circuit Output delay = 4tp Gate fan-in = 2 (c) B A F11
F10 = YZ + X 2-level gate circuit Output delay = 3tp (b)
Figure 3.5.5 Circuit implementations for complex functions and their output delays.
Two-level gate circuits implement the complex functions illustrated in Fig. 3.5.5(a) through (c). Circuits with more than two cascaded gates are called multilevel gate circuits like the 4-level gate circuit in Fig. 3.5.5(c). Factored functions result in multilevel gate circuits. Factoring a function also allows the function to be implemented with gates that have a smaller fan-in; however, the output delays of multilevel gate circuits are generally slower than those of 2-level gate circuits.
Multiplexers (Data Selectors)
A very useful circuit that utilizes a complex function is called a Multiplexer or MUX. A MUX is a circuit that is used to direct one of 2n inputs to a single output. Since n select lines are used to select each of the 2n input signals and direct it to the output, a MUX is also called a Data Selector. An example of a 2-to-1 MUX is shown in Fig. 3.5.6(a).
MUX D0 F D1 S0 F = D0S0 + D1S0 D0 D1
0 D 1 S 0 OUT
F or D0 D1
0 1 D OUT S 0
D0 D1
0 1
S0 S0 (a) (b) S0 (c)
Figure 3.5.6 Multiplexer (data selector): (a) gate level circuit diagram, (b) logic symbol, and (c) switch representation.
162
CHAPTER 3
The logic symbol for the MUX in Fig. 3.5.6(b) has active high inputs (no bubbles present) and active high signal names D0 D1 and S0, i.e., signal names with no overbars.The output on the logic symbol is also active high (no bubble present) and has an active high signal name F, i.e., a signal name with no overbar.All signals were chosen for signal matching. When the select input S0 is 0, output F connects to input D0 (as illustrated in the mechanical switch representation for the MUX shown in Fig. 3.5.6(c)).When the select input S0 is 1, output F connects to input D1.
E X A M P L E Show the truth table for the 2-to-1 MUX in Fig. 3.5.6.
S0 D1 D0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 F 0 1 0 1 0 0 1 1
Notice in the truth table that output F follows (is the same as) input D0 when S0 is 0, but output F follows (is the same as) D1 when S0 is 1. Based on this statement and the truth table for the 2-to-1 MUX, we may write a compact or compressed form of the truth table for the 2-to-1 MUX as follows:
S0 0 1 F D0 D1
Larger MUXs or Data Selectors (4-to-1, 8-to-1, 16-to-1, etc.) have a similar truth table and operate in a similar manner with more inputs. Off-the-shelf MUXs usually have an active low enable input (also called the strobe input). The active low enable input must be pulled low for the circuit to perform its normal operation. When the enable input is pulled high, the output is inactive. The truth table for a 2-to-1 MUX with an active-low enable input is shown as follows:
EN S0 0 0 1 0 1
F D0 D1 0
=.X.=dont care
SECTION 3.5
163
Two different logic symbols are shown in Fig. 3.5.7 for a 2-to-1 MUX with an active low enable input. See Appendix B for the pinout diagram of the 74 series 157 device.
EN MUX EN D0 D1
EN 0 D 1 S 0 OUT
or
D0 D1
0 1
EN D OUT S 0
Figure 3.5.7 Logic symbols for a 2to-1 MUX with an active low enable input.
F
S0 S0
MUXs are used to implement designs for logic functions and to provide dataflow paths between circuits. We discuss the implementation of logic functions with MUXs in the following section. In Chapter 4 we discuss using MUXs to provide data-flow paths between circuits.
Designing Circuits with MUXs With a large enough MUX (Multiplexer or Data Selector) you can design a circuit for any function. First write the truth table (or K-map) for the function with no inputs partitioned off, i.e., not compressed. To obtain a Type-0 MUX design, set the data inputs to the MUX to the output values in the truth table or K-map for the function and connect the select lines to the appropriate input variables.
E X A M P L E Obtain a Type-0 MUX design for the function F1(X, Y, Z)= g (1, 2, 5, 7). We first obtain the truth table as shown in Fig. 3.5.8(a). Do not compress the truth table. The data inputs (0 through 7) of the MUX are connected to Vcc for a 1 or to Ground for a 0 for each function value in the table. The design is shown in Fig. 3.5.8(b) using an 8-to-1 MUX with an active low enable input EN.
Vcc X Y Z 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 (a) F1 0 1 1 0 0 1 0 1 Power surge protection resistor
0 1 1 0 0 1 0 1 GND
Type-0 MUX design

MUX EN 0 1 2 3 4 5 6 7
Vcc Type-0 MUX design

0 1 1 0 0 1 0 1 GND 0 1 EN 2 3 OUT 4 5 S 0 6 1 72
Figure 3.5.8 (a) Truth table for function F1, and (b) Type-0 MUX design for function F1.
OUT
F1
or
F1
S 1 0
XYZ (b)
XYZ
164
CHAPTER 3
You can obtain a design for any 3-variable function with an 8-to-1 MUX as a Type-0 MUX design. You can obtain the design for any 2-variable function using a 4-to-1 MUX as a Type-0 MUX design. In general, you need a 2n-to-1 MUX for any n-variable function as a Type-0 MUX design. Notice that we do not consider function minimization when designing with MUXs.A MUX design may be overkill, i.e., excessive, if used for the design of a trivial or simple function. To obtain a Type-1 MUX design, partition off one input in the truth table (the least significant bit is the easiest to partition off) and compress the truth table using the input that is partitioned off. This is the same as a compressed K-map with one variable being entered into the map. Set the data inputs to the MUX to the function values in the compressed truth table (or K-map). The select lines for the MUX are the remaining inputs (those not partitioned off) in the truth table (or the perimeter variable in a compressed K-map). E X A M P L E Obtain a Type-1 MUX design for the function F2(A, B, C)= g (2, 3, 4, 7)+ g md(6). We first obtain the truth table as shown in Fig. 3.5.9(a) and then partition off one variable as illustrated. A compressed K-map can also be used as shown in Fig. 3.5.9(b). The data inputs (0 through 3) of the MUX are connected to the variable that is partitioned off (or the variable that is map-entered), or the complement of the variable partitioned off, or V for a 1, or Ground for a 0 for each function value in the compressed cc truth table or compressed K-map. The select lines are connected to the appropriate remaining input variables. The design is shown in Fig. 3.5.9(c) using a 4-to-1 MUX with an active low enable input EN.
Figure 3.5.9 (a) Truth table for function F2 with variable C partitioned off, (b) compressed K-map with variable C compressed, (c) Type1 MUX design for function F2.
C Vcc Type-1 MUX design 00 01 11 C C or 1 0 1 1
0 1 C 1 EN 0 1 2 3 1 GND S OUT
A B C F2 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 (a) 0 0 1 1 1 0 1
F2 0 1
AB F2 =
F2
10 C
AB (b) (c)
One word of caution when designing from a K-map: the decimal data inputs to the MUX must match the perimeter binary numbers on the K-map. Type-2 and higher-type MUX designs are also possible. For a Type-2 MUX design partition off two inputs in a truth table (the two least significant input variables are the easiest to partition off) and compress the truth table using the inputs partitioned off.You can use a K-map rather than a truth table.When using a K-map, it is easy to compress any of the input variables.As before, data inputs to the MUX are set to the function values in the compressed truth table (or compressed K-map).
SECTION 3.5
165
The select lines for the MUX are connected to the appropriate remaining inputs (those not partitioned off) in the truth table (or the perimeter variables in the compressed K-map). Code Converters, Display Decoders, Arithmetic Circuits, and other circuits with more than one output are classified as multiple-output circuits. A Code Converter is a circuit that converts one binary code to a different binary code. A Display Decoder is a circuit that converts a BCD number to the code necessary to drive a display such as a 7-segment display.An Arithmetic Circuit is a circuit that performs arithmetic such as addition, subtraction, multiplication, or division. Each output of a multiple-output circuit requires a separate Boolean function or equation. We present an example of a Display Decoder at the end of this chapter and examples of Arithmetic Circuits in the next chapter.
Designing Gate-Level Circuits with Multiple Outputs
E X A M P L E Consider the design of a multiple-output gate-level circuit (a circuit designed with gates as opposed to a circuit designed with a decoder or with a MUX) that performs the following functions: F1 = X Y + Z, F2 = X Y + Z + Y Z, lc=3 lc=5, combined lc=8
These minimum functions are obtained by reading the K-maps in Fig. 3.5.10(a) in the normal way, i.e., each K-map is read independently. A gate-level circuit implementation for each function is shown in Fig. 3.5.10(b) using an AND/OR gate form.
Z X F1 = 0 1 Y Z p1 00 01 11 10 1 1 1 0 0 0 1 1 p2 X F2 = 0 1 YZ 0 0 1 0 p3 0 0 1 1 Z F2 Y p4 X Y F1
00 01 11 10
F1 = p1 + p2 = XY + Z (a)
F2 = p3 + p4 = XYZ + YZ
(b)
Figure 3.5.10 (a) Independent function minimization, (b) circuit design for functions minimized independently.
You can obtain an alternate solution for multiple-output circuits by using the concept of multiple function minimization. Multiple function minimization means to obtain a combined set of reduced output expressions that uses shared product terms. You need to generate a shared product term only once; afterward it is used as needed by other expressions in the combined set of functions. Cover a product term that represents the same cube on two or more maps to generate a shared product term. You might need to make several attempts to obtain a combined set of equations with a minimum number of literals.The goal is to obtain a combined set of minimum SOP expressions with a complexity in terms of
166
CHAPTER 3
total literal count less than the total literal count of an independent set of minimum SOP expressions. The concept of multiple function minimization is easy to understand but usually difficult to execute by hand when a large number of maps are involved. Software programs do exist that will perform multiple function minimization.
E X A M P L E Show a design for functions F1 and F2 that uses product term sharing. In Fig. 3.5.11(a) we show the same maps for functions F1 and F2 with a slightly different covering of the 1s on the maps.
Z X F1 = 0 1 YZ 00 01 11 10 1 1 1 0 0 0 1 1 p1 p2 X F2 = 0 1 YZ 00 01 11 10 0 0 1 0 0 0 1 1 p3 X Y Z F2 Y F1
F1 = p1 + p2 = XYZ + Z
F2 = p1 + p3 = XYZ + YZ
(a)
(b)
Figure 3.5.11 (a) Multiple function minimization, (b) circuit design for functions using product term sharing.
For the 1s of the functions F1 and F2 in Fig. 3.5.11(a) we obtain the set of equations shown below each K-map. The product terms X Y Z and Z are necessary to cover the 1s of the function F1. This is not a minimum covering for F1. The product terms X Y Z and Y Z are essential to cover the 1s of the function F2. Since X Y Z is used for both F1 and F2 it is a shared product term. We show shared product terms underlined after the first time they appear in an expression. Underlined terms are considered 0 cost terms since they do not contribute to the literal count. The total literal count for these functions is now only 6 due to the shared product term. Observe that the output of the 3-input AND gate is generated only once for F1 and then shared with F2 in Fig. 3.5.11(b). Sometimes it is easier to identify shared product terms after you obtain an independent set of reduced equations. This approach to multiple function minimization can also result in a circuit that contains fewer components. This is illustrated by the following set of independently obtained reduced equations, where all shared product terms are underlined. FA = A C + A B + A C FB = A C + A C FC = A C + A B + A B Notice that the product terms in FAA A C, A B, and A CB are also contained in FB and FC. Compare the combined literal count of 8 using product sharing to a literal count of 16 when product sharing is not used. Recall that a smaller literal count means fewer components are needed for a design.
SECTION 3.5
167
E X A M P L E Show a design for functions FA, FB, and FC that uses product term sharing.
A C FA FA = AC + AB + AC A C
Figure 3.5.12 Circuit design for functions using product term sharing.
FB FB = AC + AC
A B
FC FC = AC + AB + AB
E X E R C I S E S
T O
T E S T
Y O U R
K N O W L E D G E
(For solutions see Section 3.9, Worked Exercises) 36. Draw a circuit for a function FDELAY=A with an output delay of 4tp , where tp represents the propagation delay of each single Buffer or Inverter making up the circuit. 37. Draw a circuit for the function FD1 = A B implemented with an AND gate and Inverters. Also draw a circuit for the function FD2 = X + Y implemented with an OR gate and Inverters. Determine the output delay for each circuit, assuming each circuit element has a delay of tp . 38. Draw and label a gate-level circuit for a 3-to-8 Decoder with active high inputs and active low outputs. Draw a logic symbol for the circuit and then show its truth table.Assuming each Inverter and gate in your 3-to-8 Decoder circuit has a propagation delay of 1tp , determine the output delay of your circuit. Use signal matching for the signal names. 39. Design a circuit with an off-the-shelf Decoder that has an active low enable input, i.e., a DMUX, and an AND gate or a NAND gate that performs the function F(X, Y, Z)= g (0, 1, 5, 6, 7). Obtain the design so that the fan-in of the gate is as small as possible. 40. Draw a circuit for the function FCOMP = A B C + A D implemented first as a 2-level gate circuit and also as a multilevel gate circuit. Determine the output delay for each circuit assuming each circuit element has a delay of tp . Which circuit implementation is faster, the 2-level gate circuit or the multilevel gate circuit? Which circuit implementation requires gates with smaller fan-ins? 41. Draw and label a circuit for a 4-to-1 MUX (Data Selector). Draw a logic symbol for the circuit and then show its truth table. Assuming each Inverter or gate in your 4-to-1 MUX circuit has a propagation delay of 1tp , determine the output delay of your circuit. Use signal matching for the signal names. 42. Obtain a Type-0 MUX design for the function F(X, Y, Z)= g (0, 1, 5, 6, 7) using an off-the-shelf 8-to1 MUX with an active low strobe input. 43. Obtain a Type-1 MUX design for the function F(X, Y, Z)= g (0, 1, 5, 6, 7) using an off-the-shelf 4-to1 MUX with an active low enable input.
168
CHAPTER 3
44. Obtain a Type-2 MUX design for the function F(X, Y, Z)= g (0, 1, 5, 6, 7) using an off-the-shelf 2-to1 MUX with an active low strobe input. 45. Obtain the minimum SOP forms for the following functions independently: F1(A, B, C)= g (0, 1, 3, 7), and F2(A, B, C)= g (0, 1, 7). Underline all shared product terms for the independent set of reduced equations, i.e., use the product sharing approach to multiple function minimization. Provide the combined literal count for the independent minimized functions and the combined literal count after product sharing for the independent minimized functions. Show a circuit implementation for the independent set of minimized functions and also a circuit implementation for the product-sharing set of minimized functions, i.e., the set resulting from multiple function minimization.
3.6
PROGRAMMABLE LOGIC DEVICES (PLDS)
Industry only wired up so many circuits in laboratory situations before it developed a smarter way. It is not known for sure who invented the PROM (Programmable Read Only Memory). The PROM was introduced back in the early 1960s. The PLA (Programmable Logic Array) was invented at Signetics in 1975. PLA is a registered trademark of Signetics. The PAL (Programmable Array Logic) was invented in 1976 by John Birkner at MMI (Monolithic Memories Inc.). Another name for a PAL is a GAL (Generic Array Logic). Both acronyms PAL and GAL are registered trademarks of Lattice Semiconductor Corporation. The PROM, PLA, and PAL or GAL are PLDs (Programmable Logic Devices). Each of these architectures utilizes the AND/OR gate form discussed earlier. Each can implement multiple functions. The PROM and PLA both allow product term sharing; however, the PAL or GAL does not. You can implement any simple or complex function with these architectures provided the architectures have enough circuitry. Figure 3.6.1 illustrates a sort of template or generalized format for PLDs.
Figure 3.6.1 Template or generalized AND/OR gate form architecture for PLDs.
Device Inputs AND array connections OR array connections Device Outputs
Inverter /Buffer Array
AND Array
By circuitry we mean the required number of inputs to each of the AND gates and the required number of inputs to each OR gate in a functionally equivalent AND/OR gate form of the architecture. Small functions may fit the architecture of each PLD while larger functions with more inputs or more product terms may not fit. One solution is simply to increase the size of the PLD, i.e., increase the number of AND gates and corresponding inputs to those gates and/or increase the number of inputs to each OR gate. Industry has taken this approach and manufactured larger and larger PLDs.
OR Array
SECTION 3.6
169
The connections to the AND array (AND array connections) and to the OR array (OR array connections) determine the type of PLD. The connections and their types are summarized as follows.
Device type PROM AND array connections Fixed at the factory OR array connections Programmable with fuses by the customer PLA Programmable with fuses by the customer PAL or GAL Programmable with fuses by the customer Programmable with fuses by the customer Fixed at the factory
A brief programmable symbology summary for the different types of PLDs is shown in Fig. 3.6.2.
No fuse Intact fuse Intact fuse Blown fuse Blown fuse
Figure 3.6.2 Programmable symbology summary for the different types of PLDs.
Fixed connection at factory
Programmable connection
Simplified representation
Connection broken (after programming)
Simplified representation
Multiple input AND gate Input terms A A B B
Product terms p1 p 2 p 3 p 4 A.A.B.B = 0
Pull-up resistors not shown
Multiple input Pull-down resistors OR gate not shown
p1 + p2 + p3 + p4 ... An placed inside an OR gate also represents all fuses intact 0 (Due to pull-down resistors
All fuses intact
An placed inside an AND gate also represents all fuses intact
All fuses intact
Input terms A A B B 1 (Due to pull-up resistors All fuses blown
Product terms p1 p 2 p 3 p 4
All fuses blown
Note that an * is used as a programmable connection (an intact fuse). Actual fuses may be used or they may be emulated by a transistor circuit that is reprogrammable. If a transistor circuit is emulating a fuse connection, the circuit may be volatile (such as the RAM storage in your PC; when the power is turned off, the connection is effectively broken) or the circuit may be nonvolatile. If the circuit is nonvolatile, the connection is not broken when power is turned off. Nonvolatile circuits may be of the ultraviolet erasable type or of the electrically erasable (EE) type. Erasing a PLD reestablishes all fuse connections. Once a reprogrammable device is programmed, it needs to be erased prior to programming it again. The ultraviolet erasable type requires a window in the top of the package to expose the circuit to ultraviolet light when it needs to be erased. The EE type is a newer technology, and it may be erased more quickly by simply applying pulses to the correct
170
CHAPTER 3
device pins. The latest technology type can be erased and reprogrammed even after the device has been mounted on a PC board. A device called a Universal Programming Unit erases and programs programmable devices. Several different companies manufacture these units. To use one, you must first generate a map of the fuses that need to be blown. The fuses that are not blown are the connections you want to keep, and the connections that are blown are the ones you dont want to keep. A map of the fuses is called a fuse map and is generated automatically by specialized industrial software packages. MACHXL (formerly called PLDesigner),ABEL, and CUPL are three of the many programs that are available to generate fuse maps. A standard has been devised by the Joint Electronic Devices Engineering Council called the JEDEC standard fuse map file for PLDs.All companies use this standard. It may be used to program the PLD on the Universal Programming Unit. Once the device is programmed with the proper connections for the required Boolean functions, the PLD is just a special-purpose circuit. For emulated fuse devices the circuit is semipermanent and the emulated fuse connections can last for several years. If actual fuses are used, the fuses are permanent and cannot be reprogrammed.
3.6.1 PROMS
Lets look a little closer to see how the AND/OR gate circuits are connected for the different PLDs. A PROM circuit is shown in Fig. 3.6.3 with just two inputs and four outputs. Much larger PROM circuits are available with many more inputs and up to eight outputs. For the simple PROM circuit shown in Fig. 3.6.3, each additional input that is added causes the AND array to double in size; i.e., for 2 inputs there are 4 AND gates, for 3 inputs there are 8 AND gates. Observe that the
Inputs (two in this case) A B OR array connections programmable m0 2-to-4 Decoder circuit Inputs (two in this case) A B OR array connections programmable m0
m1
m1
m2
m2
m3
m3
AND array connections fixed
F1
F2
F3
F4
AND array connections fixed
F1
F2
F3
F4
Outputs (four in this case) (a)
Outputs (four in this case) (b)
Figure 3.6.3 PROM circuit: (a) circuit representation using gates, (b) simplified circuit representation using gates.
SECTION 3.6
171
AND array is a minterm generator circuit (or Decoder circuit). For each combination of inputs only one AND gate output can go high at one time, hence the name Decoder. For example, for A B=00 the top AND gate is pulled to a 1 or high and all other AND gates are pulled to a 0 or low. For A B=01 the second AND gate down is pulled to a 1 or high and all other AND gates are pulled to a 0 or low, etc. A circuit that performs in this manner is called a Decoder since it selectively decodes at its outputs each binary combination applied to its inputs. A nonprogrammable read only memory (ROM) is mask programmed one time at the factory and may not be altered. Metal connections are used for the mask, and these are permanent connections. Mask programmed ROMs are much more economical and are used after designs are finalized. PROMs are used primarily in the development stage of a project when designs are not fixed and may be changed.
3.6.2 PLAS
Since a PROM or ROM doubles in size in its AND array when additional inputs are added, it seems natural to look back in history and see why Signetics engineers invented the PLA. When the decoder is replaced by another programmable array, the AND array, the PLA can have more inputs without increasing the size of its circuit. The PLA circuit is quite versatile. Product terms generated at the outputs of the AND array can be shared by all the ORs in the OR array. The PLA is, however, somewhat slower. Its propagation delay time is longer due to its two programmable arrays. It is also harder to manufacture and therefore more costly than the PROM.The two fuse maps that have to be generated make it harder to use than the PROM. The PLA circuit is shown in Fig. 3.6.4.
Inputs (three in this case) A B C OR array connections programmable p1 Inputs (three in this case) A B C OR array connections programmable p1
p2
p2
p3
p3
p4
p4
p5 AND array connections programmable F1 F2 F3 F1 F2 F3 Outputs (three in this case) (a) Outputs (three in this case) (b)
p5
AND array connections programmable
Figure 3.6.4 PLA circuit: (a) circuit representation using gates, (b) simplified circuit representation using gates.
172
CHAPTER 3
3.6.3
PALS OR GALS
The PAL or GAL circuit is easiest to use because it only has one fuse map to generate. It is also faster than the PLA because of the single programmable array. Like the PLA, increasing the number of inputs for the PAL does not cause the AND array to double in size for each additional input as it does for the PROM. PALs have become the programmable device workhorse of the industry for smaller designs because of their lower cost, higher speed, and ease of use. Larger designs fit more easily into another class of programmable logic devices called Field Programmable Gate Arrays (FPGAs). For more information on PLDs see Appendix C, Selected Programmable Devices. The PAL circuit is shown in Fig. 3.6.5.
Inputs (three in this case) A B C OR array connections fixed p1 F1 p2 Outputs (two in this case) F2 p4 p4 p2 Outputs (two in this case) F2 Inputs (three in this case) A B C OR array connections fixed p1 F1
p3
p3
AND array connections programmable (a)
AND array connections programmable (b)
Figure 3.6.5 PAL circuit: (a) circuit representation using gates, (b) simplified circuit representation using gates.
In the PAL circuit in Fig. 3.6.5 there can be no product-term sharing, since each AND gate output cannot be used by more than one OR gate input. This is the only drawback of the PAL compared to the PLA, which allows productterm sharing. Commercially available PALs also have other features not shown in Fig. 3.6.5. One feature provides for function sharing or additional inputs as shown in Fig. 3.6.6. The Inverters on the output side of the circuit in Fig. 3.6.6 with the additional inputs labeled OE1, OE2, etc. (where OE stands for Output Enable) are single Inverters with a 3-state output (we will discuss this type of output in Chapter 4). The Inverters in Fig. 3.6.6 can provide an output or function sharing only when their respective output enable input OE1, OE2, etc. is active. When an OE input is inactive, then the pin at the output of the Inverter becomes an input pin. A device pin that has this capability is referred to as an I/O, since it can be used as an input or as an output.
SECTION 3.6 A B C
173
Inverter with a 3-state output
p1
OE1 F1 P1 (I/O)
p2 Note: (If OEi = 1 then Fi is an output, if OEi = 0 then Pi is an input for i = 1, 2, ...) F2 P2 (I/O)
p3
OE2
p4
Connections back into the AND array that allow for function sharing or for additional inputs
Figure 3.6.6 A PAL circuit which provides either function sharing or additional inputs.
Function sharing allows a designer to perform equation splitting, i.e., splitting an equation or function into subparts that are then used to form the function. Another name for equation splitting is functional decomposition. This technique is often used to implement larger functions with smaller PALs, PLAs, and FPGAs. An equation that is split or functionally decomposed into smaller parts and then implemented generally requires fewer interconnections, i.e., less real estate on the chip, but the circuit will usually run slower than a 2-level gate circuit. For example, assume the PAL in Fig. 3.6.6 has only the three inputs A, B, and C and the two outputs shown in the figure.The equation F1 = A B + A C + B C cannot be directly fit into this PAL because it has three product terms. By splitting the equation into the following parts: F1 = A B + F2, where F2 = A C + B C, the function F1 can now be implemented with this PAL, provided OE1=1 and OE2=1. Notice that function F2 is shared with F1, i.e., F2 is a subpart of F1. Function sharing is also used in the design of feedback circuits (circuits with memory). We will introduce feedback circuits in Chapter 5. One might ask,Why use PLDs to design circuits when you can always build circuits in gate form? It is desirable to use programmable devices for the following reasons: (a) to shorten design timePLD designs provide rapid prototyping since fuses serve as connections or no connections based on the fuse map, making all wiring of the gates unnecessary; (b) to allow rapid design changeschanging the fuse map or fuse connections changes the PLD design; (c) to decrease PC board real estatePLD designs in a single package are less costly and bulky than multiple packages for gate-level designs; (d) to improve reliabilityPLD designs require fewer packages and thus fewer interconnections.
PAL or GAL classification nomenclature PALxxyzz:
Examples of two different PALs are PAL16L8 and PAL22V10, where xx represents the maximum number of AND array inputs, y represents the type of outputs as indicated below, and zz represents the maximum number of dedicated outputs. H is active high, L is active low, P is programmable, C is
Combinational outputs:
complementary.
174
CHAPTER 3
Registered outputs:
R is registered, RP is registered with programmable polarity, where registered means it contains memory devices.
Combinational or registered macrocells: V is versatile, that is, programmable output macrocells that can be configured to be either combinational or registered.
The PAL shown in Fig. 3.6.5 is too small for manufacture but would be called PAL3H2, where 3 represents 3 inputs, H indicates active high outputs, and 2 represents 2 outputs. A PAL with active high outputs (outputs without Inverters) can be used only to implement equations written for the 1s of the functions. The PAL16L8 has 16 possible inputs, 8 possible outputs, and active low outputs (outputs with Inverters) that can only be used to implement equations written for the 0s of the function. The PAL22V10 has 22 possible inputs, 10 possible outputs, and versatile outputs that can be used to implement equations written either for the 1s or the 0s of the functions. In addition, versatile outputs can be configured as registered outputs (outputs with flip-flops) that provide memory capability. We will discuss registered outputs later. See Appendix C, Selected Programmable Devices, for logic diagrams of the PAL16L8, PAL16R4, PALLV16V8, and PALCE22V10. The JEDEC fuse map file has become the specific format used for the fuse map. A universal programmer reads the fuse map file to determine which fuses to blow and which fuses to leave intact when programming a PLD. A 1 in the JEDEC fuse map file represents a fuse to be blown while a 0 represents a fuse to be left intact (not blown). This is opposite to the data bit when programming a PROM. Today, the PALs or GALs we have discussed in this section are referred to in industry as simple programmable logic devices (SPLDs). When several PALs or GALs are included on the same chip, industry calls these devices complex programmable logic devices (CPLDs). Refer to Appendix C for more information on CPLDs.
3.6.4 DESIGNING WITH PROMS
The first two items in the previous list are the most important for students. They provide rapid prototyping and allow rapid design change. E X A M P L E Show how to implement an Inverter (to invert A or complement A, i.e., A), an OR gate (A OR B), a NAND gate AA AND BB, and an XOR gate (A XOR B) with a PROM. These functions in truth table form are shown as follows for F1 (Inverter), F2 (OR gate), F3 (NAND gate), and F4 (XOR gate).
A B 0 0 1 1 0 1 0 1 F1 1 1 0 0 F2 0 1 1 1 F3 1 1 1 0 F4 0 1 1 0
Since a PROM has a Decoder front end that generates all the minterms for each of the functions, think of the inputs to a PROM as an address and its outputs as data stored at each address. A 1 in each column of a function in the table represents a fuse connection that has not been blown (an intact fuse). A
SECTION 3.6
175
0 in each column of a function in the table represents a fuse connection that has been blown (a blown fuse). Given the circuit for a PROM without the fuses, we can rapidly draw the intact fuses as shown in Fig. 3.6.7. This is what we mean by rapid prototyping. In the lab the universal programmer does just the opposite; it actually blows the fuses where the connections need to be removed, since each new device comes with all fuses intact.
Fixed connections (address) A B Programmed connections (data) 1 1 0 0 0 1 1 1 1 1 1 0 0 1 1 0
Figure 3.6.7 PROM implementation for an Inverter, an OR gate, a NAND gate, and an XOR gate.
m0 m1 m2 m3
AB = 00 AB = 01 AB = 10 AB = 11
F1
F2
F3
F4
The fuse map consists of the addresses 00B, 01B, 10B, 11B, where the B stands for binary. Addresses can also be represented in decimal, octal, or hexadecimal. The corresponding data listed in binary is 1010B, 1111B, 0111B, and 0100B, respectively. In hexadecimal the address and data could be listed as follows:
Address (hexadecimal) 0 1 2 3 Data (hexadecimal) A F 7 4
To change the fuse map we simply need to change the data for the PROM. If we decided later to complement input B rather than input A for function F1, then the address and data sequence would be changed to address (data) as follows: 0(A), 1(7), 2(F), 3(4). This is a small change (software change) to the fuse map that initiates a hardware change (reprogramming of fuses) inside the device. Since the hardware change is made internally by reprogramming fuses, the engineer who is using the PROM does not have to make hardware changes externally (wiring changes to the circuit) unless the number of inputs and/or outputs is also changed.
3.6.5 DESIGNING WITH PLAS
A PLA requires two fuse maps to implement functions. One is for the AND array connections and one is for the OR array connections. Because there is a fuse map for the OR array, product terms can be shared.
176
CHAPTER 3
E X A M P L E Show how to implement an Inverter (to invert A or complement A, i.e., A), an OR gate (A OR B), a NAND gate AA AND BB and an XOR gate (A XOR B) with a PLA. An implementation with the PLA is shown in Figure 3.6.8.
Figure 3.6.8 PLA implementation for an Inverter, an OR gate, a NAND gate, and an XOR gate.
A B Programmed connections p1 = A p2 = A.B p3 = A p4 = A.B Programmed connections F1 F2 F3 F4
PLA implementations are usually made by software that uses multiple function minimization techniques such that product-term sharing occurs. Fuses must be blown in two different fuse map areas for PLAs. The K-maps shown in Fig. 3.6.9 are used to determine the product terms for the AND array connections. Product-term sharing is used in some of the OR array connections.
AB F1 = 1 1 p1 F2 = 0 0 AB 0 1 p2 p3 F3 = 1 1 AB 1 1 p1 0 1 p4 F4 = AB 0 1 p2 0 1 p4
00 01 11 10
00 01 11 10
00 01 11 10
00 01 11 10
F1 = p1 = A
F2 = p2 + p3 = AB + A =A+B
F3 = p1 + p4 = A + AB =A+B = AB
F4 = p2 + p4 = AB + AB =A B
Figure 3.6.9 Multiple function minimization for PLA implementation.

3.6.6 DESIGNING WITH PALS OR GALS
The circuit for a PAL or GAL has a programmable AND array and a fixed OR array. As a result of the single fuse map, product terms are easier to generate. To use minimum resources on the chip, functions are generally minimized prior to creating the fuse map. E X A M P L E Show how to implement an Inverter (to invert A or complement A, i.e., A), an OR gate (A OR B), a NAND gate AA AND BB and an XOR gate (A XOR B) with a PAL. The minimum function can be easily written as F1 = A, F2=A+B, F3=A + B, and F4 = A B+A B. The fuse map is blown as shown in Fig. 3.6.10. The *s in the AND array connection show fuses that remain intact.
SECTION 3.6 A B
177
Fixed connections A F1 0 A F2 B A F3 B AB F4 AB Programmed connections
Figure 3.6.10 PAL implementation for an Inverter, an OR gate, a NAND gate, and an XOR gate.
Notice that each output for the PAL shown in Fig. 3.6.10 can provide only two product terms, neither of which can be shared with the other outputs. Also notice that the PAL can fit equations only for the 1s of the functions. A different PAL with inverted outputs must be used to fit equations for the 0s of the functions. E X E R C I S E S T O T E S T Y O U R K N O W L E D G E
(For solutions see Section 3.9, Worked Exercises) 46. Which gate form of architecture does a PROM have? Can equations written in POS form directly fit into this architecture? 47. What PLD has programmable AND array connections and also programmable OR array connections? Discuss the advantages and disadvantages of having two programmable array connections. 48. Which PLD architecture is called an SPLD and, when used with multiple devices in the same package, is called a CPLD? 49. Describe the form of the equations that can be fitted into a PAL or GAL that has active high outputs (no Inverters on the outputs) such as a 16H8 or the PAL in Fig. 3.6.10. 50. Use the same PROM architecture shown in Fig. 3.6.3(b) to design a circuit for the following functions after increasing the number of inputs by one and reducing the number of outputs by one. Show the correct intact fuse connections with * s, i.e., provide the fuse map connections, for (a) an XOR function using inputs X and Z, (b) a majority of 0s function using inputs X, Y, and Z, and (c) an AND function using inputs X, Y, and Z. Also specify the address (data) sequence for the design using octal. 51. Design a circuit for the following functions using a PAL3L3.This PAL is too small to be commercially available. Let the PALs OR gates each be fed by four AND gates so that the PAL can handle up to four product terms for each output. Remember that the L refers to a PAL that has active low outputs. Only equations for the 0s of functions can be implemented with this PAL. Show the correct intact fuse connections with * s, i.e., provide the fuse map connections, for (a) an XNOR function using inputs Y and Z, (b) an odd number of 1s function using inputs X, Y, and Z, and (c) an OR function using inputs X, Y, and Z. If a JEDEC file is created for the fuse map, what logic value is used to represent an intact fuse in that file?
178
CHAPTER 3
3.7
POSITIVE LOGIC CONVENTION AND DIRECT POLARITY INDICATION
Up until now we have only used logic symbols and signal names that correspond to the Positive Logic Convention (PLC) system. In some cases in other books and data sheets a different logic symbolic notation and signal naming notation is sometimes used. This system is referred to as the Direct Polarity Indication (DPI) system, sometimes called mixed logic notation since signal names are assigned a suffix of either (H) or (L) to indicate the logic convention chosen for the signal name. These signal names are called polarized signals. A suffix of (H) indicates a positive logic signal while a suffix of (L) indicates a negative logic signal. There are no negative logic signals in the positive logic convention, only positive logic signals. Knowledge of both the positive logic convention system and the direct polarity indication system will provide you with a better understanding when reading technical literature or conversing with other engineers.
3.7.1 SIGNAL NAMES REVISITED
The signals used in the positive logic convention system and in the direct polarity indication system are summarized below.
Signal names in the positive logic convention system A or A(H) B or B(H) Equivalent polarized signal names in the Direct Polarity indication system A(H) or A(L) B(H) or B(L) Type of signal Active when high or active high Active when low or active low
Double complementation can be used to obtain equivalent signal names for polarized signals as follows: A(H) = A(H)
21
= A (H ) = A(L)
1 2
21
B(H) = B(H) = B (H ) = B(L) Notice in the positive logic convention system that a signal name without an overbar is an active high signal while one with an overbar is an active low signal. In the direct polarity indication system a signal name without an overbar but with a suffix of (H) is an active high signal while one without an overbar but with a suffix of (L) is an active low signal. The suffix (H) or (L) is the polarity part of the signal. In addition to the signal names, there is a slight difference in graphics notation for each system. The positive logic convention system uses a bubble or negation indicator to indicate complementation. The direct polarity indication system uses a wedge or polarity indicator to indicate an active low input or output. If a wedge or polarity indicator is not present at an input or output, that input or output is active high. Preferred signal names in the direct polarity indication system are written without overbars. Polarized signal names can be written with overbars but these are not preferred. In contrast, an active high positive logic signal is written without an overbar, such as A, with or without a suffix (H), while an active low positive logic signal is written with an overbar, such as B, with or without a suffix (H). The suffix is always (H) for positive logic signals and therefore may be dropped. Signal names without a suffix have an implied high suffix since (H) is the default suffix.
SECTION 3.7
179
3.7.2
C O N V E RT I N G C I R C U I T S A N D S I G N A L M AT C H I N G
You can convert circuits drawn in the direct polarity indication system to the positive logic convention system by simply changing all wedges to bubbles. Likewise, you can convert circuits drawn in the positive logic convention system to the direct polarity indication system by simply changing all bubbles to wedges. Strictly speaking, the signal names in the circuit should also be substituted to match the system being used to be in compliance with IEEE standards. (See Bibliography.) Figure 3.7.1 shows a simple circuit drawn first in the positive logic convention (PLC) system and then in the direct polarity indication (DPI) system. Both circuits are equivalent and both are drawn using indicator matching on all signal lines. Such matching is not always possible but helps in analyzing and designing circuits when it is used.
A B Indicator matching C D PLC F C(L) D(H) DPI A(H) B(L) Indicator matching F(H)
(a)
(b)
Figure 3.7.1 Equivalent circuits using indicator matching on all signal lines: (a) the PLC system, (b) the DPI system.
When specifying a design it is wise to list the input and output signals. We refer to this list as the signal list. If a signal list is not provided in the positive logic convention system, this implies that all the signals are active high signals, i.e., uncomplemented signals. Some data books refer to active high signals as signals in true form while complemented signals are referred to as signals in complemented form. Analyzing the circuit in Fig. 3.7.1 provides us with the following function and corresponding signal list: F=A B+C D; SL: F, A, B, C, D. Analyzing the circuit in Fig. 3.7.1(b), we can write its function and signal list as F(H)=(A B+C D)(H); SL: F(H), A(H), B(L), C(L), D(H). Since both circuits are the same, the function and the signal list for each circuit are equivalent. One needs to learn how to analyze circuits in both the PLC system and the DPI system to determine their functions and their signal lists. Engineers who prefer to work with voltage levels usually choose the DPI system, while those who prefer to work with ones and zeroes choose the PLC system. This author prefers to work with ones and zeroes and therefore has chosen to use the PLC system throughout the text. Analyzing a circuit is a little harder in the DPI system than in the PLC system. The analysis of either type of circuit is easier if the circuit is first drawn with matching indicators on all signal lines if possible. To analyze a circuit in the DPI system, we use a concept called signal matching. If a signals suffix does not match the indicator where the signal is being applied, simply use the equivalent signal name to obtain a match of the suffix with the indicator on the signal line.Then use the variable part of the signal in the normal fashion. If W(L) is used for signal matching, we must use W as the variable part; however, if W(H) is used for signal matching, we must use W as the variable part. Remember that W(L) = W(H), i.e., these are equivalent signal names, where W(L) is a negative logic signal and W(H) is the equivalent positive logic signal.
180
CHAPTER 3
E X A M P L E The key to analyzing a circuit in the DPI system is to mentally think of (or write down) the required polarized signals to obtain signal matching on each signal line in the circuit. This is shown in the detailed analysis in Fig. 3.7.2.
Figure 3.7.2 Detailed analysis of a circuit in the DPI system.
or W(H) W(L) X(H) or X(L) For signal matching Y(H) Z(L) or Z(H) 3 Attach H for signal matching 4 1 X(H) 2 or F3(L) F3(H) (WX + YZ)(L) Attach L for signal matching WX(L) For signal matching Attach L for signal matching For signal matching
DPI YZ(L) Attach L for signal matching
As you can observe, the double complementation theorem is used to write a polarized signal in its equivalent form wherever there is a signal mismatch. As usual, the function is written at the output of each gate (or Inverter) only in terms of the variable parts of the polarized signals, i.e., the suffix parts of the polarized signals are not carried along to the outputs of the gate (or Inverter). At each gate output or Inverter output, the suffix part of the signal is added back to the function to achieve signal matching at the respective output. Based on our analysis in Fig. 3.7.2 we can write the function for the circuit as F3(L) = AW X + Y ZB(L). The signal list for the circuit should be written using preferred polarized signals as SL: W(L), X(H), Y(L), Z(H), F3(H). It would be improper to write the function as F3(H) = AW X + Y ZB(L), since both sides of the equation should be written using the same logic convention so that the variable parts are equal. Rather than working in the DPI system, you may elect to convert to the PLC system to analyze circuits. You can then write the function and signal list obtained from the PLC system in terms of polarized signals. You can handle the design of circuits in the DPI system in a similar manner. You would design the circuit in the PLC system and then substitute bubbles for wedges and change the positive logic signal names to polarized signal names. E X A M P L E Analyze the circuit shown in Fig. 3.7.3 to obtain the function and its signal list in the DPI system. Does signal matching occur at all inputs and the output in the circuit in Fig. 3.7.3? Obtain the function and its signal list in the PLC system. Also show the same circuit in the DPI system and the PLC system with indicator matching on all interior signal lines.
Figure 3.7.3 Circuit diagram in the DPI system.
A(L) B(L) C(L) F(L) DPI
SECTION 3.7
181
The function may be obtained from the DPI circuit directly as F(H) = AAA + BB CB(H). The signal list is simply the list of the input and output signals in the circuit in preferred form. This is SL: A(L), B(L), C(L), F(L). Signal matching does not occur anywhere for the circuit in Fig. 3.7.3. An equivalent circuit diagram in the PLC system is shown in Fig. 3.7.4(a). Figure 3.7.4(b) and (c) also show an equivalent circuit diagram in the DPI system and in the PLC system with indicator matching on all interior signal lines.
A B C F PLC (a) A(L) B(L) C(L) F(L) DPI A B C F PLC
(b)
(c)
Figure 3.7.4 (a) Equivalent circuit diagram in the PLC system, (b) equivalent circuit diagram in the DPI system with indicator matching on all interior signal lines, and (c) equivalent circuit diagram in the PLC system with indicator matching on all interior signal lines.
The function obtained from the PLC circuit in Fig. 3.7.4(a) or (c) is F = AA + BB C and the signal list is SL: A, B, C, F. Notice that the function and the signal list for our DPI circuit and equivalent PLC circuit are in fact equivalent, since each can be obtained from the other. Circuits drawn in a modular or block diagram form can be described by either the PLC system with positive logic signals or the DPI system with polarized signals. Data books sometimes use positive logic signals for the DPI system to save space. Before this is done, all the signals must first be written as equivalent positive logic signals in polarized form so that the suffix (H) can be dropped. Three data-book examples of circuits drawn in modular or block diagram form are shown in Fig. 3.7.5. The first of these circuits is a bus buffer (or buffer/driver) with a 3-state output as illustrated in Fig. 3.7.5(a).
74LS49
BCD to 7-seg Display Decoder
74LS138
DMUX
74LS125A G A F PLC BI A B C D
G20 1 2 4 8
a20 b20 c20 d20 e20 f20 g20
a b c d e f g DPI
A B C G1 G2A G2B
1 2 4
0 1 2 3
& EN
4 5 6 7
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
Figure 3.7.5 Circuits with specified signal names (signal matching is preferred but not always used).
DPI (c)
(a)
(b)
The signal line with the bubble is the 3-state output control line. This line must be pulled to a 0 (as indicated by the bubble at the input) to enable the buffer for normal operation (F=A). The active low signal G was chosen for this signal line so that there would be signal matching. When signal G goes to 1 the buffer is
182
CHAPTER 3
disabled and the output disconnects (F=Z), where Z represents a disconnect state or high-impedance state. We will discuss this operation in more detail in the next chapter.The signal line by A is an active high input, since it has no attached bubble, and the signal line by F is an active high output, since it has no attached bubble. Signals A and F were chosen as active high signals for signal matching. When signal matching is used, it helps to explain the operation of a circuit via the signals used in the circuit. For example, signal name G is an active low signal. When G is asserted (pulled to its active state) we know that the input that it is tied to will be pulled low and thus enable the bus buffer. In other words, the signal name implies what action must be taken to enable or disable the bus buffer. Signal matching is not a requirement but is a distinct advantage from the signal description standpoint. In Fig. 3.7.5(b) we show a BCD to 7-segment Display Decoder with a blanking input and open-collector outputs. The blanking input will be discussed in the case study at the end of this chapter, and open-collector outputs will be presented in the next chapter. In this circuit the DPI system is used with positive logic signals. All the signals for the block diagram symbol in Fig. 3.7.5(b) are active high and have the form SIGNAL_NAME except for the blanking signal BI, which is an active low signal. Notice that signal matching is used at all inputs and outputs, i.e., the active level of each signal name for each logic line matches the active level of the corresponding indicator for that line. If polarized signals were used on the logic symbol, all active high signals would be listed in the form SIGNAL_NAME(H) and the blanking signal would be listed as BI(L), i.e., the preferred form for an active low polarized signal. In Fig. 3.7.5(c) we show a block diagram for a Demultiplexer (DMUX). Recall that a Demultiplexer is a Decoder with an enable input. For the Demultiplexer circuit, all the input and output signals are active high except G2A and G2B. In order to enable the output of the Demultiplexer circuit, all the enable signals G1, G2A, and G2B must be asserted at the same time. Since G1 is an active high signal it must be pulled high to be asserted while G2A and G2B must be pulled low to be asserted, i.e., G1=H, G2A = L, and G2B = L at the same time. Notice that signal matching is used at all the inputs; however, the manufacturer chose not to use signal matching at the outputs. To provide signal matching at the outputs in Fig. 3.7.5(c), all of the output signals should be named Y0 through Y7. When we choose signal names that satisfy signal matching, we gain greater flexibility in explaining the operation of circuits.
E X E R C I S E S
T O
T E S T
Y O U R
K N O W L E D G E
(For solutions see Section 3.9, Worked Exercises) 52. What is the active level of a positive logic signal that contains an overbar? Provide several examples of such signals. If a polarized signal does not contain an overbar, what is its active level? Give several examples of active high and active low signals. What is the preferred way to write polarized signals? 53. Convert each of the following circuits into a circuit in the opposite system, i.e., from the PLC system to the DPI system or from the DPI system to the PLC system. Use polarized signals for the DPI system and positive logic signals for the PLC system. Use only preferred polarized signal names in the DPI system. Analyze each converted circuit to obtain its function and corresponding signal list.
SECTION 3.8
CASE STUDY NUMBER 1 (BCD TO 7-SEGMENT DISPLAY SYSTEM)
183
A B F2 C D (a) PLC
W(L) X(H) F3(H) Y(H) Z(L) (b) DPI
54. Specify the polarized signal names that could be used for the inputs and outputs for the circuits shown in Fig. 3.7.5 if all of the circuits were drawn using the DPI system. Use only preferred polarized signal names that satisfy signal matching.
C A S E 3.8
S T U D Y CASE STUDY NUMBER 1 (BCD TO 7SEGMENT DISPLAY SYSTEM)
Case studies are introduced to promote critical thinking by providing multiple ways for solving the same problems. A common-cathode (or common-anode) 7-segment display device requires seven separate inputs as shown in Fig. 3.8.1.
Common-cathode display Common-cathode 7-segment display a b c d e f g dp dp Anode a Ground connection for common-cathode (Vcc connection for common-anode) Cathode b c e d c Common-anode display Vcc a f b Anode LEDs (light emitting diodes) Cathode g GND a b c
Figure 3.8.1 Common-cathode (or common-anode) 7-segment display device with decimal point.
LED protection resistors
To use this display device, the binary code called Binary Coded Decimal (BCD) is converted to 7-segment code and supplied to the inputs of the display device. The protection resistors prevent burning up the device segments when signals are applied to segment inputs a through g and dp (the decimal point).The circuit that performs the conversion is called a BCD to 7-segment Display Decoder. The truth table for this Display Decoder for a commoncathode 7-segment display device is illustrated in Fig. 3.8.2. A high signal or
184
CHAPTER 3
a 1 lights a segment for a common-cathode display, while a low signal or a 0 lights a segment for a common-anode display.
Figure 3.8.2 Truth table for a BCD to 7-segment Decoder with a blanking input.
Decimal or function 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (blanking) Blanking input, BCD code BI D C B A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 - = don't care 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 - - - Common-cathode 7-segment code OA OB OC OD OE OF OG 1 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 1 1 0 1 1 0 0 0 1 1 1 1 1 0 1 1 0 Displayed character
To blank all the segments, a global control line called the blanking input labeled BI is included in the truth table. BI is an active low signal because of the overbar. When the active-low blanking input signal BI is 1 or high (inactive), all outputs will be enabled for viewing (not blanked for viewing) and go to the value determined by the BCD input code. When BI is 0 or low (active), all outputs go to 0 to disable them. When BI is active, the BCD input signals D, C, B, and A are of no importance or irrelevant and hence they are dont care inputs. The BCD input signals D through A and the output signals OA through OG are all active high signals. The active high signals are active when high or 1 and thus contain no overbars. Output signals OA through OG are of no importance or irrelevant and hence are dont care outputs when the BCD code input values exceed decimal 9. A Display System that includes a logic symbol for the BCD to 7-segment Display Decoder is shown in Fig. 3.8.3.The inputs for the Display Decoder are shown on the left and the outputs are shown on the right side of the symbol. Seven outputs are required, which means that seven equations are required, one for each output. This is a multiple function implementation. Notice that Buffer/Drivers are used between the BCD to 7-segment Display Decoder and the common-cathode 7-segment Display device to provide the necessary drive capability (current capability or oomph) required for each segment. At this time we begin a case study of the different approaches that can be used to implement a BCD to 7-segment Display Decoder.
SECTION 3.8
185
BCD to 7-segment Display Decoder
Buffer/Drivers
Common-cathode 7-segment display
Figure 3.8.3 Display system.
BI = 1
BI
OA OB OC
a b c d e f g dp e f
a b
1 0 1 0
A B C D
OD OE OF OG
c dp GND
= output with special amplification (drive capability)
3.8.1
T H E G AT E - L E V E L D E S I G N A P P R O A C H
To implement a BCD to 7-segment Display Decoder at the gate level, we must obtain the Boolean functions or equations for outputs OA through OG in terms of the inputs BI, D, C, B, and A. It is easy to compress the truth table mentally and plot 4-variable K-maps using BI as the compressed variable as shown in Fig. 3.8.4.
DC OA = 01 11 B A p1 p2 p3 00 01 11 10 00 BI
(a)
DC OB =
BA
p1
p2
p3
00 01 11 10 00 BI BI BI BI
BI BI p4
(b)
0 -
BI BI BI -
01 BI 11 -
0 -
BI -
0 -
Figure 3.8.4 Using compressed 4variable K-maps to obtain output functions OA and OB: (a) plotted and reduced function for OA, and (b) plotted and reduced function for OB.
10 BI BI
10 BI BI
OA = p1 + p2 + p3 + p4 = BICA + BICA + BIB + BID (a)
OB = p1 + p2 + p3 = BIBA + BIBA + BIC (b)
To implement the Display Decoder at the gate level we must build seven circuits, one for each of the outputs OA through OG. An example of two of the required gate-level circuits is shown in Fig. 3.8.5 for outputs OA and OB. We must implement the other five gate-level circuits for outputs OC through OG to complete the design.
BI C A BI C A BI B BI D (a) (b) BI B A BI B A BI C
Figure 3.8.5 Partial gate-level implementation for the BCD to 7segment Display Decoder.
OA
OB
186
CHAPTER 3
We can use a variety of different gate forms to implement the BCD to 7segment Display Decoder.We could also use equations for the 0s of the functions rather than equations for the 1s of the functions.
3.8.2 THE MUX DESIGN APPROACH
Figure 3.8.6 Truth table partitioned off for a Type-0, Type1, and Type-2 MUX design.
We could also use MUXs (or Data Selectors) to implement the functions. Consider the truth table for the BCD to 7-segment Display Decoder just for output OA first with no inputs partitioned off (a Type-0 MUX design), then with one input partitioned off (a Type-1 MUX design), and then with two inputs partitioned off (a Type-2 MUX design) as shown in Fig. 3.8.6.
D C B A 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 - = don't care OA 1 0 1 1 0 1 1 1 1 1 OA A B+A 1 A A+B 1 1 1 OA
Vcc
Type-0 MUX design BI

1 0 1 1 0 1 1 1 1 1 0 0 0 0 0 0 MUX EN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 3 GND
Using the three separate output columns for OA in the truth table in Fig. 3.8.7, we can implement a Type-0, Type-1, or Type-2 MUX design as shown in Fig. 3.8.7. Only one of these designs is required. This illustrates that a MUX or Data Selector can be used to implement a logic function directly from a truth table without minimizing the function. MUXs can be used to implement multiple functions, but they require one MUX per function. That can add up to a lot of MUXs (7 MUXs in this case).
Vcc Type-1 MUX design Vcc Type-2 MUX design OA BI B A

MUX EN B +A A+B 1 0 0 1 2 3
BI
D OUT
MUX EN A 1 A 1 1 0 0 0 0 1 2 3 4 5 6 7
OA
OUT
OUT S 1 0
OA
S 2 1 0 GND
S 2 1 0 GND
DC B D C B A (a) (b) (c)
DC
Figure 3.8.7 Type-0, Type-1, and Type-2 MUX designs for the OA output.
SECTION 3.8
187
In each design in Fig. 3.8.7 when the blanking input BI is active (goes low or to a 0) the MUX is not enabled and the OA output goes low or to 0 (to its inactive state). With the OA output driving a common-cathode LED, the a segment is turned off, i.e., blanked as it should be. When the blanking input BI is not active (goes high or to a 1) the MUX is enabled and the OA output follows the truth table in Fig. 3.8.6. To use the MUX without the blanking input capability simply ground the enable or strobe input (since it is an active low input). Of course this also means you must remove the blanking signal and the Inverter to which it is connected.
3.8.3 THE PLD DESIGN APPROACH
We could also use PLDs to implement the Display Decoder. We could use a PROM, a PLA, or a PAL. With the correct size PLD, i.e., one with at least 5 inputs and 7 dedicated outputs, the resulting Display Decoder design will be a single-chip design. This will save wiring time and space on a PC board. We need design tools such as schematic capture tools, or hardware description language (HDL) tools, to work with PLDs. Xilinx, Altera, and Lattice Semiconductor are a few of the many companies that make design tools that can be used to capture the design as a schematic or as an HDL and generate a fuse map. We need a Universal Programmer or a dedicated programmer to download the fuse map generated by the hardware tools into the SPLD. Many different companies manufacture SPLDs. As a simple example of a PROM design, think of the input as an address and the output of the PROM as data.The address and corresponding data for the Display Decoder in the truth table in Fig. 3.8.2 for inputs BI [MSB], D, C, B, A[LSB] can be listed as shown in Fig. 3.8.8 in hexadecimal notation.
Address: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Data: Address: 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 7E 30 6D 79 33 5B 5F 70 7F 7B 00 00 00 00 00 00 Data:
Figure 3.8.8 Fuse map for a PROM design.
For this design, the PROM needs only five inputs. If it had additional inputs, simply ground them, i.e., connect those inputs to ground. In our address representation, BI is bit position 4, D is bit position 3, C is bit position 2, B is position 1, and A is bit position 0. In our data representation, OA is bit position 6, OB is bit position 5, etc.We have arbitrarily chosen to represent each dont care as a 0. You can be creative and select the displayed character for addresses 1A through 1F as you please. For this design, the PROM only needs seven outputs. PROMs often contain eight outputs. If the PROM has eight outputs, we are assuming the output for bit position seven is 0, and this output will not be used. This representation of address and corresponding data is our fuse map for a PROM to perform the BCD to 7-segment Display Decoder function. We can use our fuse map to program the PROM with a Universal Programmer or a dedicated PROM programmer. A hardware description language (HDL) called design synthesis language (DSL) is written as shown in Fig. 3.8.9 using the software package MACHXL by Lattice Semiconductor and is called the source code file or design file.
188
CHAPTER 3
Figure 3.8.9 Source-code file for a PROM, PLA, or PAL written in DSL using the software package MACHXL.
input /BI, D, C, B, A; output OA, OB, OC, OD, OE, OF, OG; truth_table "compressed truth table " /BI, D, C, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, B 0 1 0 1 0 1 0 1 :: :: :: :: :: :: :: :: :: OA OB OC OD OE OF OG; /A, 1, A, 1, 1, 1, 1, /A, A, 1, 1, A, 1, 1, 1, /A, /A, /A, 1, A, 1, /A, 0, /A, 0, 1, 1, 0; 1; 1; 1;
/A, /A, /A, /A;
.x., .x., .x., .x., .x., .x., .x.; .x., .x., .x., .x., .x., .x., .x.; .x., .x., .x., .x., .x., .x., .x.; 0, 0, 0, 0, 0, 0, 0;
0, .x., .x., .x. :: end truth_table;
When the file is compiled, we obtain a fuse map that can be downloaded into a PROM, PLA, or PAL. The PROM, PLA, or PAL must have at least 5 inputs and at least 7 outputs. The gate structure must contain (a) enough AND forms to generate all the product terms for each function and (b) a large enough OR form (wide enough, with a large enough fan-in) to implement each output. Any PROM, PLA, or PAL that can handle these requirements will work. The PALs with part numbers PAL16P8 and PAL22V10 are popular PALs. Both of these PALs are inexpensive and readily available. Once we program a PLD such as a PROM, PLA, or PAL, we connect it as shown earlier in Fig. 3.8.3 using the Display Decoder block diagram symbol as the symbol for the PLD. We must draw a detailed logic diagram (a diagram showing pin numbers and power connections) to facilitate wiring up the circuit on the bench for hardware testing of the final design. What we have tried to make clear in this case study is that there are many ways to obtain an implementation for a design using hardware. The final design may consist of hardware chosen at the gate level, at the MUX or Data Selector level, or at the PLD level. Today, designers are choosing to implement their hardware designs at the PLD level because this generally leads to fewer packages to put on a printed circuit (PC) board.
3.8.4 THE OFF-THE-SHELF DESIGN APPROACH
Since 7-segment display devices are used so often, manufacturers offer the design of Display Decoders as off-the-shelf designs. Display Decoders are also in manufacturers parts libraries for their CAD (Computer Aided Design) tools. One such part is a 74LS49. See Appendix B for the pinout diagram of the 74 series 49 device. This Display Decoder has the same inputs and output signals as our Display Decoder, or almost. The designer of the 74LS49 elected to display the 6 without segment a lighted and to display 9 without segment d lighted, i.e., without tails. The 9 is shown displayed in Fig. 3.8.10. Later versions such as the 74LS249 have both 6 and 9 composed with tails.We must still add the protection resistors, but they must be connected directly to V . The cc Display Decoder outputs, i.e., OA, OB, etc., must also be connected directly to the segment inputs of the 7-segment display device as shown in the figure.
SECTION 3.9
WORKED EXERCISES
189
Vcc
Common-cathode 7-segment display
Figure 3.8.10 Display system using the 74LS49.
BCD to 7-segment Display Decoder
BI = 1
BI
OA OB OC
a b c d e f g dp e f
a b
1 0 0 1
A B C D
OD OE OF OG
c dp GND
= designates an open-collector output
The connections shown in Fig. 3.8.10 are the result of the open-collector outputs of the 74LS49 and will be discussed at the beginning of Chapter 4.The resistors serve two purposes: (a) to pull the segment inputs high when the outputs of the Display Decoder should go high but dont due to the open collector outputs; and (b) to provide protection for the LED segments so that they will not burn up. Since the segments are pulled high by the resistors (when used in this fashion the resistors are called pull-up resistors) there is no need for Buffer/Drivers to provide the required current capability to drive the LED segments. The designer of the 74LS49 chose to implement the equations for the 0s of the functions instead of the 1s of the function. Recall that we implemented the equations for the 1s of the function. In the design of the 74LS49 the designer used dont care outputs to form display patterns above 9 that are unique, so that the BCD input conditions for these patterns could be checked. 3.9 WORKED EXERCISES
1. Draw and label the IEC standard graphic symbols for a 3-input NAND function, 2-input OR function, Inverter function, and XNOR function.
S O L U T I O N
& 1 1 =1
NAND
OR
Inverter
XNOR
2. For each of the following functions, write the truth table, provide the function name, and draw the IEEE graphic symbol with correctly labeled inputs and output. (a) F1 = A + B (b) F2 = A B (c) F3 = B
190
CHAPTER 3
S O L U T I O N
A B 0 0 1 1 A B NAND 0 1 0 1 F1 (NAND) 1 1 1 0 F2 (NOR) F3 (Inverter) 1 0 0 0 A B NOR 1 0 1 0
F1
F2
F3
Inverter
3. Draw and name the function for each type of graphic symbol that provides complementation and show under what condition complementation (inversion) takes place. Hint: Look closely at the truth table for each of the functions.
S O L U T I O N
A A GND Inverter A A NOR NAND A A A A
A GND XOR
Vcc
XNOR
For the NOR function and the NAND function there is more than one solution. 4. Name two different types of momentary pushbutton switches and show a symbol to represent each type.
S O L U T I O N
n.o. n.c.
normally open type
normally closed type
5. What logic operation results when switches are connected in series? What logic operation results when switches are connected in parallel?
SECTION 3.9
WORKED EXERCISES
191
S O L U T I O N AND operation for switches connected in series. OR operation for switches connected in parallel. 6. Which types of transistors (MOS or BJT) are generally used in newer designs? Which type of transistor (MOS or BJT) generally requires more power to operate?
S O L U T I O N MOS transistors for newer designs. BJT transistors generally require more power to operate. 7. Which size of integrated circuit contains a larger number of equivalent circuits: an SSI, MSI, LSI, or VLSI circuit? How many equivalent circuits does the largest size contain?
S O L U T I O N VLSI circuits contain a larger number of equivalent circuits. The number of equivalent circuits for VLSI circuits is 1000 or more. 8. Write the truth table and the function name of each of the following pass logic switching circuits.
A
n.c.
A B F2
n.c.
A A
n.c.
B B
F1 0 = no continuity 1 = continuity
n.o.
F3
S O L U T I O N
A B 0 0 1 1 0 1 0 1
F1 (NOR) 1 0 0 0
F2 (NAND) F3 (XNOR) 1 1 1 0 1 0 0 1
192
CHAPTER 3
9. Write the truth table and the function name of each of the following regenerative logic switching circuits.
Vcc = H = 1 A
n.o.
Vcc = H = 1 A
n.o.
Vcc = H = 1 A
A
n.c.
n.c.
B
n.o.
F1
B
n.c.
B
n.o.
B
n.c.
A
n.c.
B
n.c.
F2 0 = L = VL 1= H = VH R GND = L = 0
F3 0 = L = VL 1= H = VH B
A
n.o.
n.o.
GND = L = 0
GND = L = 0
S O L U T I O N
A B 0 0 1 1 0 1 0 1 F1 (AND) 0 0 0 1 F2 (XOR) 0 1 1 0 F3 (NOR) 1 0 0 0
10. Draw the gate symbol for each of the following compact description names. Next draw the DeMorgan equivalent symbol for each gate symbol and list its equivalent compact description name. (a) NAND3B2 (c) NOR4 (b) AND2B2 (d) OR4B3
S O L U T I O N Each solution is shown in Fig. WE3.10.

Figure WE.3.10
Specified compact description name (a) NAND3B2 Gate symbol DeMorgan equivalent gate symbol Equivalent compact description name OR3B1
= = = =
(b)
AND2B2
NOR2
(c)
NOR4
AND4B4
(d)
OR4B3
NAND4B1
SECTION 3.9
WORKED EXERCISES
193
11. Determine the maximum number of functions that can be obtained from just 3 variables. Are they all unique? What is the number for 4 variables? Are they all unique?
S O L U T I O N The maximum number of functions for 3 variables is (2)2 = (2)2 =(2)8=256, and no, they are not unique. At the very least, gate types such as AND gates with single or two bubbles on the inputs are repeated in the list of functions along with Buffers and Inverters. The maximum number of functions for 4 variables is n 4 (2)2 = (2)2 =(2)16=65,536, and no, they are not unique. At the very least, gate types such as AND gates with single, two, or three bubbles on the inputs may be repeated in the list of functions along with Buffers and Inverters. 12. Analyze each of the following pass logic switching circuits to obtain their output functions and their truth table.
Z X Z
n.o. n.c.
n 3
n.c.
X
n.o.
Y F2
F1
S O L U T I O N F1 = A AX + ZB YB + Y writing expressions for groups of switches from left to right (by ANDing switches in series and ORing switches in parallel) or F1 = X Y + Z Y + Y writing expressions for each path separately from left to right (by ANDing switches in series, then ORing expressions for separate paths)
X Y Z 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 F1 1 1 1 1 0 1 1 1
194
CHAPTER 3
F2 = W Y AZ + XB + X Y or
writing expressions for groups of switches from left to right writing expressions for each path separately from left to right
F2 1 1 0 0 1 1 0 0 0 0 0 0 1 1 0 0
F2 = W Y Z + W Y X + X Y
WX Y Z 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1
13. Design a pass logic switching circuit for the function F1=Z Y+X Y using pushbutton switches and for the function F2=X Y Z + X Y Z + X Z using relays. S O L U T I O N Both designs are shown as in Fig. WE3.13
Figure WE3.13
Z X
n.o.
Y Y
X X X
Y Y
Z Z Z
n.c.
F1
F2
14. Show the design for an AND-gate ladder logic circuit driving a control relay. Show the circuit first in symbolic form and then using relays. S O L U T I O N Each solution is shown in Fig. WE3.14.
Figure WE3.14
A B F + A B CR Control Relay F
SECTION 3.9
WORKED EXERCISES
195
15. Show the design for a NAND-gate ladder logic circuit driving a green pilot lamp. Show the circuit first in symbolic form and then using relays. S O L U T I O N Each solution is shown in Fig. WE3.15.
+ A B A F B F G Pilot Lamp
Figure WE3.15
16. Analyze each of the following symbolic logic circuits to obtain its Boolean function and its truth table.
A B C B F1 A B C B F2
S O L U T I O N F1 = AA + BB AC + BB, or F1 = A B + C B F2 = A B + C B, or F2 = AA + BB AC + BB
A B C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 F1 F2 0 0 0 1 1 1 0 1 1 1 0 1 0 0 0 1
(in literal form) (in literal form)
17. Analyze each of the following circuits to obtain its Boolean function and its truth table.
A B W X
A C
F1
Y X
F2
196
CHAPTER 3
S O L U T I O N F1 = A B + A C, or F1 = A B + A C F2 = AW + XB AY + XB, or F2 = AW + XB AY + XB
A B C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 F1 1 1 0 0 0 1 0 1 WX Y 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 F2 0 0 1 0 1 1 1 0
(in literal form) (in literal form)
18. Write the change symbol rule in words.The change symbol rule results from the application of what theorem?
S O L U T I O N Change an AND symbol to an OR symbol (or vice versa); where bubbles exist remove them and where no bubbles exist add them. The change symbol rule is an application of DeMorgans Theorem on a graphic symbol. 19. Obtain the symbols for the following functions using the change symbol rule: (a) an OR gate with one bubbled input and a bubbled output and (b) an AND gate with one bubbled input and a bubbled output. Identify the form of the converted symbol, i.e., an AND form or an OR form and a name. S O L U T I O N Each solution is shown in Fig. WE3.19.
Figure WE3.19
(a) Symbol for specified function Converted symbol Form of converted symbol and name an AND form, AND2B1
(b)
an OR form, OR2B1
20. Name the resulting gate types for the following circuits: (a) a circuit with two external Inverters, each driving a separate input of a 2-input NOR gate and (b) a circuit with a 3-input AND gate driving an external Inverter. To determine the
SECTION 3.9
WORKED EXERCISES
197
gate types, substitute equivalent signal lines for lines that contain external Inverters. S O L U T I O N Each solution is shown in Fig. WE3.20.
Specified circuit Functionally equivalent circuit Gate type
Figure WE3.20
(a)
AND gate
(b)
NAND gate
21. Obtain a minimum SOP form for the 1s of function F(X, Y, Z)= g (0, 1, 3)+ g md(5, 6, 7) using a K-map. If you were to implement a circuit for function F with IC packages, which gate form would be preferred, NAND/NAND or NOR/NOR? Show the design for both forms. Be sure to use fan-in reduction, if you can, to reduce the IC package count.
S O L U T I O N The function is plotted and covered on the K-map shown in Fig. WE3.21(a). A minimum form for the 1s of the function is F=p1+p2=X Y + Z. Using the minimum SOP form of F, we can implement the circuit in NAND/NAND gate form and in NOR/NOR gate form as shown in Fig.WE3.21(b). NOR/NOR gate form requires only 1 IC package to implement the function and so it is the preferred gate form. One fan-in reduction is used to obtain an Inverter.
X Y Z X F1 = 0 1 YZ 1 0 p1 p2 X Y Z F F = XY + Z NAND/NAND gate form 2 gates (assuming 4 gates/package) 3 Inverters (assuming 6 Inverters/package) 2 IC packages (a) (b) AND/OR gate form X Y Z F F F = XY + Z Fan-in reduction
00 01 11 10 1 1 0 -
F = XY + Z NOR/NOR gate form 3 gates (assuming 4 gates/package) Fan-in reduction is used to obtain an Inverter 1 IC package
Figure WE3.21
198
CHAPTER 3
22. Obtain a minimum SOP form for the 0s of function F expressed as F(W, X, Y, Z)= g (0, 1, 2, 3, 4, 5, 6, 15)+ g md(7) using a K-map. If you were to implement a circuit for function F with IC packages, which gate form would be preferred, NAND/NAND or NOR/NOR? Show the design for both forms. Be sure to use fan-in reduction, if you can, to reduce the IC package count. S O L U T I O N The function is plotted and covered on the K-map shown in Fig. WE3.22(a). A minimum form for the 0s of the function is. F = r1 + r2 = W+X Y Z. Using the minimum SOP form of F, we can implement the circuit in NAND/NAND gate form and in NOR/NOR gate form as shown in Fig. WE3.22(b). The NAND/NAND gate form requires only 1 IC package to implement the function and so it is the preferred gate form. Two fan-in reductions are used to obtain the NAND/NAND gate form, one to obtain a 2-input NAND gate and the other to obtain an Inverter.
W X Y Z WX F= 00 01 11 10 YZ 00 01 11 10 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 r2 r1 X Y Z W F F = W + XYZ AND/OR gate form Fan-in reduction F W X Y Z F = W + XYZ
Fan-in reduction F
- = .X. = don't care (a)
F = W + XYZ NAND/NAND gate form NOR/NOR gate form 2 gates (assuming 3 gates/package) 2 gates (assuming 3 gates/package) Fan-in reduction is used twice Fan-in reduction is used once 1 IC package 2 IC packages (b)
Figure WE3.22
23. Design a two-1s-out-of-four event detector for inputs A, B, C, D and output F with NAND gates. Use a vertical input scheme and fan-in reduction if required for off-the-shelf IC packages. S O L U T I O N Since only two 1s out of four are detected at the input, we can write the function for the detector as follows: F = ABCD + ABCD + ABCD +A B C D + A B C D + A B C D
SECTION 3.9
WORKED EXERCISES
199
The design is shown in Fig. WE3.23 using a using a vertical input scheme.
A B C D Vertical input scheme 2 4-input NAND gates/package
Figure WE3.23
1 8-input NAND gate/package F
Fan-in reduction
24. Implement the function F = X Y + X Z in NAND/NAND gate form.Also implement the function F in NOR/NOR gate form.
S O L U T I O N Each solution is shown in Fig. WE3.24.
X X Y F X Z First draw circuit in AND/OR form X Z Use equivalent signal lines to change circuit to NAND/NAND form X Y F X Z Use equivalent signal lines to change circuit to NOR/NOR form Y F
Figure WE3.24
25. Write the function F(A, B, C, D)= g (0, 5, 7, 12, 15) in a 4-variable truth table, then compress the truth table about input variable D.
200
CHAPTER 3
S O L U T I O N
A B C 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F F 1 0 0 0 0 0 D 1 1 0 D 1 0 0 0 0 0 0 1 0 0 D 1 D D A B C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 F D 0 D D 0 0 D D
26. Write the function F(A, B, C)= g (2, 3, 5, 6) in a 1-variable compressed K-map using B and C as the compressed variables. Use K-map compression to obtain the 1-variable compressed K-map. Verify your solution using truth table compression. S O L U T I O N K-map compression for the function is shown in Fig. WE3.26.
Figure WE3.26
A F= 0 1 BC 00 01 11 10 0 0 0 1 1 0 1 1 A F= 0 B 0 0 1 1 C A F= 0 B 1 BC+BC
1 C
Truth table compression for the function is shown below:

A 0 0 0 1 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 0 0 0 1 1 1 0 C 1 1 C 0 BC + BC B 1 A 0 1 F B BC + BC F F
SECTION 3.9
WORKED EXERCISES
201
27. Plot the following 6-variable function in a 3-variable compressed K-map: F(A, B, C, D, E, G)= g A0, 1 D, 4, 6, 7 AE GBB,m=m(A, B, C). Also write the function F in terms of its input variables. S O L U T I O N The plotted 3-variable compressed K-map is shown in Fig. WE3.27.
A F= 0 1 BC 00 01 11 10 1 1 D 0 0
Figure WE3.27
0 EG 1
The function is written in terms of its input variables as follows: F(A, B, C, D, E, G) = g A0, 1 D, 4, 6, 7 AE GBB, m = m(A, B, C)
= m0 + m1 D + m4 + m6 + m7 AE GB, m = m(A, B, C) = ABC + ABCD + ABC + ABC + ABCEG
28. Obtain a minimum expression for the function F(A, B, C, D, E, G)= g A0, 1 (D G), 4, 6, 7 AE + GBB + g md(5), m=m(A, B, C). Show the plotted compressed K-map, and label the p-terms for a minimum expression on the map. S O L U T I O N The plotted compressed K-map and the p-terms are shown in Fig. WE3.28.
p5 = BC A F= 0 1 BC p1 = BDG p3 = AG 00 01 11 10 1 1
DG
Figure WE3.28
0
E+G
0 1
p2 = AE p4 = AC
A minimum expression for the function F is written as follows: F = p1 + p2 + p3 + p4 + p5 = BDG + AE + AG + AC + BC Product terms p1, p2, and p3 are obtained by applying step 1 while p4 and p5 are obtained by applying step 2 in the reduction procedure. Product terms p2 and p3 can be combined or obtained together in the compressed K-map by covering E + G together as one product term A AE + GB. 29. Obtain a minimum SOP expression for the 0s of the function F3 shown in the following compressed K-map by complementing the function and solving for its 1s. Show the plotted compressed K-map, and label the p-terms for a minimum
202
CHAPTER 3
expression. Solving for the 1s of the function F3 in the complemented map is the same as solving for the 0s of the function F3.
W F3(W, X, Y, Z) = 0 1 X 0
Y Z
0 2
1 0 1 3
S O L U T I O N The plotted compressed K-map, the labeled p-terms, and a minimum SOP expression for the 0s of the function are shown in Fig. WE3.29.
Figure WE3.29
W F3 = 0 1 X 0
Y Z
p1 = WXY 1 0 p2 = WZ F3 = p1 + p2 = WXY + WZ
30. Obtain a minimum SOP expression for the 1s of the function FMOD in the following compressed truth table. Show a compressed K-map for FMOD with p-terms labeled for a minimum expressions on the map.Also solve for a minimum SOP expression for the 0s of the function FMOD.
A B C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 F 0 0 1 1 0 1 0 1 FMOD 0 0 X YZ 0 1 0 1
S O L U T I O N The compressed K-map for the function FMOD to obtain the 1s of the function is shown in Fig. WE3.30(a). A covering for a minimum SOP expression for the 1s of the function FMOD is also shown in the figure. By complementing the function name and all the cells in the compressed K-map for the 1s of the function we can obtain a compressed K-map for the 0s of the function as shown in Fig. WE3.30(b). Solving for the 1s of the function FMOD in the complemented map is the same as solving for the 0s of the function FMOD.
A FMOD = 0 1 BC 0 0 0 1 p2 = BCYZ
YZ X
Figure WE3.30
A FMOD =
BC 0 1 1 1 0
p3 = ACY p2 = ACZ
X
00 01 11 10 p1 = ABCX
00 01 11 10
Y+Z
p1 = CX
p4 = AB
1 p5 = AC
p3 = AC FMOD = p1 + p2 + p3 = ABCX + BCYZ + AC (a)
FMOD = p1 + p2 + p3 + p4 + p5 = CX + ACZ + ACY + AB + AC (b)
SECTION 3.9
WORKED EXERCISES
203
Product terms p2 and p3 can be combined or obtained together in the compressed K-map by covering Y + Z together as one product term A C AY + ZB, which is A C Y + A C Z in SOP form. 31. Name two types of hazards in logic circuits. How do they differ, and what can result from a hazard in a circuit?
S O L U T I O N Function hazards and logic hazards. When two or more variables change at the same time, a glitch due to a function hazard can result at the output of a circuit. A glitch due to a logic hazard can occur at the output of a circuit only when one variable changes. 32. What is the chain link rule, and what is it used for? State the chain link rule.
S O L U T I O N The chain link rule is a K-map method that is used to remove logic hazards (obtain logic hazard cover terms) for a function to obtain a logic hazard-free function. To obtain all of the logic hazard cover terms for a function only requires obtaining a minimum function using a K-map and then chain linking all of the product terms together, hence the term the chain link rule. 33. Show a timing diagram for a glitch that can result from a static 0 logic hazard. Name the glitch. Show a timing diagram for a glitch that can result from a static 1 function hazard. Name the glitch. Show a timing diagram for a glitch that can result from a dynamic 0 to 1 hazard. Name the glitch and tell how it is generally produced. S O L U T I O N The solutions are shown in Fig. WE3.33.
1 F 0 Static 0 hazard (a) t (b) Logic 1 glitch F 0 t 1 Static 1 hazard Logic 0 glitch F 0 Dynamic 0 to 1 hazard (c) t 1 Logic 0 glitch
Figure WE3.33
A logic 1 glitch can be produced by either a static 0 logic hazard or a static 0 function hazard as shown in Fig. WE3.33(a). A logic 0 glitch can be produced by either a static 1 logic hazard or a static 1 function hazard as shown in Fig. WE3.33(b). A dynamic 0 to 1 hazard can result in a logic 0 glitch as shown in Fig. WE3.33(c). This glitch is generally produced by a multilevel logic circuit (a logic circuit with more than two gate levels).
204
CHAPTER 3
34. Design a logic hazard-free circuit to implement the function F(A, B, C, D)= g (0, 2, 4, 5, 6, 7, 8, 10, 11, 15) for its 1s. S O L U T I O N The 1s of the function F are plotted and a minimum covering is obtained as shown in Fig. WE3.34(a).
Figure WE3.34(a) and (b)
AB F= 00 01 11 10 1 (a) CD 1 1 1 1 1 1 1 p3 p2 AB F= 00 01 p1 11 10 1 (b) 1 1 1 CD 00 01 11 10 1 1 1 1 1 1 p5 p4 p6
00 01 11 10 1 1
In Fig. WE3.34(b) we show the chain link rule being applied to the function. The logic hazard cover terms are p4 , p5 , and p6 shown via the dashed lines.These product terms link the minimum set of product terms p1 , p2 , and p3 in Fig. WE3.34(a) as illustrated.A logic hazard-free function for F is obtained by adding the logic hazard cover terms to the minimum function for F as follows. Minimum function for F: F = p1 + p2 + p3 F = ACD + AB + BD Logic hazard-free function for F: F = p1 + p2 + p3 + p4 + p5 + p6 F = ACD + AB + BD + ABC + BCD + AD A logic hazard-free circuit for the logic hazard-free function for F is shown in Fig. WE3.34(c) in NAND/NAND form.
Figure WE3.34(c)
A B C D
SECTION 3.9
WORKED EXERCISES
205
35. Determine if there is a possibility that a glitch may occur if the inputs are changed from ABC=001 to ABC=110 in the circuit implemented for the function F = A { AB CB when the circuit is implemented with an XOR gate and a NAND gate. Is there a possibility that a glitch may occur if the inputs are changed from ABC=000 to ABC=001, from ABC=001 to ABC=010, and from ABC=110 to ABC=101? Provide your reasoning for each of the four cases. S O L U T I O N To observe the output changes for the corresponding input changes we can determine the output function in SOP form as follows and then plot that function on a K-map as shown in Fig. WE3.35. F = A { AB CB = A AB CB + A AB CB = AB + AC + ABC = A AB + CB + A B C
A F= 0 1 BC 00 01 11 10 1 0
0 4
Figure WE3.35
1 0 0 1 1 0
1 5
3 7
2 6
For Case 1: Observing the K-map for input changes from ABC=001 to ABC=110 we can see that moving from cell 1 to cell 6 has a function hazard, i.e., two or more inputs change; that is a dynamic 1 to 0 hazard, and so a logic 1 glitch is possible. For Case 2: Observing the K-map for input changes from ABC=000 to ABC=001 we can see that moving from cell 0 to cell 1 has a logic hazard, i.e., one input changes; that is a static 1 hazard, and so a logic 0 glitch is possible. If the circuit were implemented in minimum SOP form, then the two 1s in cells 0 and 1 would be covered and the logic hazard would be removed. No logic 0 glitch could then occur. For Case 3: Observing the K-map for input changes from ABC=001 to ABC=010 we can see that moving from cell 1 to cell 2 has a function hazard, i.e., two or more inputs change; that is a static 1 hazard, and so a logic 0 glitch is possible. For Case 4: Observing the K-map for input changes from ABC=110 to ABC=101 we can see that moving from cell 6 to cell 5 has a function hazard, i.e., two or more inputs change; that is a static 0 hazard, and so a logic 1 glitch is possible. 36. Draw a circuit for a function FDELAY=A with an output delay of 4tp , where tp represents the propagation delay of each single Buffer or Inverter making up the circuit. S O L U T I O N One solution is shown in Fig. WE3.36. Another solution is to use either four Inverters or four Buffers since the function would still be correct and the output delay would still be 4tp .
A FDELAY FDELAY = A Output delay = 4tp
Figure WE3.36
206
CHAPTER 3
37. Draw a circuit for the function FD1 = A B implemented with an AND gate and Inverters. Also draw a circuit for the function FD2 = X + Y implemented with an OR gate and Inverters. Determine the output delay for each circuit, assuming each circuit element has a delay of tp . S O L U T I O N Each solution is shown in Fig.WE3.37.The slowest or worst-case delay path results in an output delay of 3tp for each circuit.
Figure WE3.37
A FD1 B FD1 = AB Output delay = 3tp Y FD2 = X + Y Output delay = 3tp X FD2
38. Draw and label a gate level circuit for a 3-to-8 Decoder with active high inputs and active low outputs. Draw a logic symbol for the circuit and then show its truth table. Assuming each Inverter and gate in your 3-to-8 Decoder circuit has a propagation delay of 1tp , determine the output delay of your circuit. Use signal matching for the signal names. S O L U T I O N A circuit for the 3-to-8 Decoder is shown in Fig. WE3.38(a), and the logic symbol is shown in Fig. WE3.38(b). The output delay for the circuit (slowest or worst-case delay path) is 2tp .The signal names are chosen using signal matching, i.e., active high input signal names are chosen while active low output signal names are chosen.
Figure WE3.38
B2
B1
B0
F0 = B2B1B0 F1 = B2B1B0 F2 = B2B1B0 F3 = B2B1B0 F4 = B2B1B0 F5 = B2B1B0 F6 = B2B1B0 F7 = B2B1B0 B0 B1 B2
Decoder 0 1 2 0 1 B F 2 3 4 5 6 7
F0 F1 F2 F3 F4 F5 F6 F7
(a)
(b)
SECTION 3.9
WORKED EXERCISES
207
The truth table for the 3-to-8 Decoder with active high inputs and active low outputs is shown as follows:
B 2 B 1 B 0 F0 F1 F2 F3 F4 F5 F6 F7 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0
39. Design a circuit with an off-the-shelf Decoder that has an active low enable input, i.e., a DMUX, and an AND gate or a NAND gate that performs the function F(X, Y, Z)= g (0, 1, 5, 6, 7). Obtain the design so that the fan-in of the gate is as small as possible. S O L U T I O N Since there are fewer 0s than 1s in the function, the design is obtained for the 0s of the function rather than for the 1s, so that a gate with the smallest fan-in can be used. A NAND gate would require 5 inputs while an AND gate as shown in the circuit design in Fig.WE3.39 requires only 3 inputs.The form of the function being implemented is F(X, Y, Z) = g (2, 3, 4).
DMUX 0 1 2 3 0 4 1 5 2 6 7
Figure WE3.39
EN GND
Z Y X
40. Draw a circuit for the function FCOMP=A B C+A D implemented first as a 2-level gate circuit and also as a multilevel gate circuit. Determine the output delay for each circuit, assuming each circuit element has a delay of tp . Which circuit implementation is faster, the 2-level gate circuit or the multilevel gate circuit? Which circuit implementation requires gates with smaller fan-ins? S O L U T I O N Each solution is shown in Fig.WE3.40.The slowest or worst-case delay path for the 2-level gate circuit results in an output delay of 3tp .The slowest or worst-case delay
208
CHAPTER 3
path for the multilevel gate circuit results in an output delay of 4tp . The 2-level gate circuit is faster, but the multilevel gate circuit has smaller fan-in gates.
Figure WE3.40
A B C A D FCOMP = ABC + AD Output delay = 3tp FCOMP Fan-in = 3 B C D A FCOMP = A.(BC + D) Output delay = 4tp All gates have fan-in = 2 FCOMP
41. Draw and label a circuit for a 4-to-1 MUX (Data Selector). Draw a logic symbol for the circuit and then show its truth table. Assuming each Inverter or gate in your 4-to-1 MUX circuit has a propagation delay of 1tp , determine the output delay of your circuit. Use signal matching for the signal names. S O L U T I O N A circuit for the 4-to-1 MUX is shown in Fig.WE3.41(a).The logic symbol is shown in Fig.WE3.41(b).The output delay for the circuit (slowest or worst-case delay path) is 3tp . The signal names are chosen using signal matching, i.e., active high input signal names are chosen since there are no inputs with bubbles on the logic symbol.
D0 D1 F = D0S1S0 + D1S1S0 D2 D3 + D2S1S0 + D3S1S0 D0 D1 D2 D3
0 1 2 3 S 1 0 D OUT
MUX F or D0 D1 D2 D3
0 1 2 3 1 D S OUT 0
S1 S0 S1 S0 S1 S0
(a)
(b)
Figure WE3.41
The truth table for the 4-to-1 MUX requires 64 rows because there are 6 inputs. To save space we show the truth table as a compressed truth table.
S1 S0 0 0 1 1 0 1 0 1 F D0 D1 D2 D3
SECTION 3.9
WORKED EXERCISES
209
42. Obtain a Type-0 MUX design for the function F(X, Y, Z)= g (0, 1, 5, 6, 7) using an off-the-shelf 8-to-1 MUX with an active low strobe input. S O L U T I O N The solution is shown in Fig. WE3.42.
Vcc Type-0 MUX design
0 EN 1 2 3 4 5 S 0 6 1 7 2
Figure WE3.42
GND
XYZ
43. Obtain a Type-1 MUX design for the function F(X, Y, Z)= g (0, 1, 5, 6, 7) using an off-the-shelf 4-to-1 MUX with an active low enable input. S O L U T I O N The solution is shown in Fig. WE3.43.
Vcc X Y Z 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 F 1 1 0 0 0 1 1 1 F 1 0 Z Z 1
1 0 Z 1 0 1 2 3 EN
Figure WE3.43
Type-1 MUX design
F
S 1 0
GND
XY
44. Obtain a Type-2 MUX design for the function F(X, Y, Z)= g (0, 1, 5, 6, 7) using an off-the-shelf 2-to-1 MUX with an active low strobe input. S O L U T I O N The solution is shown in Fig. WE3.44.
X Y Z 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 F F Type-2 MUX design
GND
Figure WE3.44
1 1 Y 0 0 0 1 Y+Z 1 1
0 EN
Y Z
Y+Z 1 S 0
210
CHAPTER 3
45. Obtain the minimum SOP forms for the following functions independently: F1(A, B, C)= g (0, 1, 3, 7), and F2(A, B, C)= g (0, 1, 7). Underline all shared product terms for the independent set of reduced equations, i.e., use the productsharing approach to multiple function minimization. Provide the combined literal count for the independent minimized functions and the combined literal count after product sharing for the independent minimized functions. Show a circuit implementation for the independent set of minimized functions and also a circuit implementation for the product-sharing set of minimized functions, i.e., the set resulting from multiple function minimization. S O L U T I O N The independent minimum forms for the functions are obtained by the 3-variable K-maps shown in Fig. WE3.45(a). The combined literal count is 9 for the set of independent functions. The circuit implementation for the independent set of minimized functions is shown in Fig. 3.45(b). Observe that the output delays for F1 and F2 are 2tp .
A F1 = 0 1 BC 1 0 1 0 p1 p2 0 0 A F2 = 0 1 BC 1 0 1 0 p1 A B NOR B C AND (b) A B NOR B C A AND AND (c) OR Output delay = 2tp F2 OR Output delay = 3tp Multiple-level gate circuit F1 OR Output delay = 2tp F1 A B C AND A B NOR F2 OR Output delay = 2tp
00 01 11 10 1 1
00 01 11 10 0 1 0 0 p2
F1 = p1 + p2 = AB + BC (a)
F2 = p1 + p2 = AB + ABC
Figure WE3.45
Underlining all shared product terms for the independent functions as shown below, we obtain the following set of functions whose combined literal count is only 5. F1 = A B + B C, F2 = A B + A B C, lc=4 lc=1, combined lc=5
The circuit implementation for the product-sharing set of minimized functions is shown in Fig. WE3.45(c). Observe that the circuit for F1 is the same, but the circuit for F2 is now a multilevel gate circuit with an output delay of 3tp .
SECTION 3.9
WORKED EXERCISES
211
46. Which gate form of architecture does a PROM have? Can equations written in POS form directly fit into this architecture? S O L U T I O N A PROM, a PLA, and a PAL or GAL have an AND/OR gate form of architecture. Equation written in SOP form will directly fit into this architecture, but equations written in POS form will not. Equation written in POS form must be rewritten in SOP form to fit into these PLDs. 47. What PLD has programmable AND array connections and also programmable OR array connections? Discuss the advantages and disadvantages of having two programmable array connections. S O L U T I O N This type of PLD is called a PLA. The PLA is the more versatile than the PROM or the PAL because it has product-term sharing. Product-term sharing can reduce the number of AND gates required when fitting an equation into the device. A PROM has minterm sharing, but all minterms must be generated.A PAL does not have minterm sharing. The PLA is generally slower than the PROM or the PAL, speedwise, since its propagation delay time is longer due to its two programmable arrays.The PLA is also harder to manufacture and therefore also more costly than the PROM or PAL. Generating two fuse maps is considered harder to do than generating one fuse map. 48. Which PLD architecture is called an SPLD and, when used with multiple devices in the same package, is called a CPLD? S O L U T I O N The PLD architecture that is called a SPLD is the PAL or GAL. When multiple PALs exist in the same package (on the same chip) the device is called a CPLD or Complex Programmable Logic Device. 49. Describe the form of the equations that can be fitted into a PAL or GAL that has active high outputs (no Inverters on the outputs) such as a 16H8 or the PAL in Fig. 3.6.10. S O L U T I O N Equations expressed in the form of the 1s of the functions will directly fit only into active high output PALs. Equations expressed in the form of the 0s of the functions will fit directly only into active low output PALs. PALs or GALs that have the capability of fitting equations for either the 0s or 1s of the functions have a P or V in their nomenclature. 50. Use the same PROM architecture shown in Fig. 3.6.3(b) to design a circuit for the following functions after increasing the number of inputs by one and reducing the number of outputs by one. Show the correct intact fuse connections with * s, i.e., provide the fuse map connections, for (a) an XOR function using inputs X and Z, (b) a majority of 0s function using inputs X, Y, and Z, and (c) an
212
CHAPTER 3
AND function using inputs X, Y, and Z. Also specify the address (data) sequence for the design using octal. S O L U T I O N A truth table for the functions is shown as follows with F1=X { Z, F2=1 if the number of 0s for X Y Z is 2 or 3, else F2=0, and F3=X Y Z.
X 0 0 0 0 1 1 1 1 Y Z 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 F1 F2 F3 0 1 0 1 1 0 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1
From the table we can supply fuse connections as shown in the circuit in Fig. WE3.50.
Figure WE3.50
Fixed connections (address) XYZ = 000 XYZ = 001 XYZ = 010 XYZ = 011 XYZ = 100 XYZ = 101 XYZ = 110 XYZ = 111 X Y Z Programmed connections (data) m0 m1 m2 m3 m4 m5 m6 m7
F1
F2
F3
The address (data) sequence in octal is 0(2), 1(6), 2(2), 3(4), 4(6), 5(0), 6(4), and 7(1). 51. Design a circuit for the following functions using a PAL3L3. This PAL is too small to be commercially available. Let the PALs OR gates each be fed by four AND gates so that the PAL can handle up to four product terms for each output. Remember that the L refers to a PAL that has active low outputs. Only equations for the 0s of functions can be implemented with this PAL. Show the correct intact fuse connections with * s, i.e., provide the fuse map connections, for (a) an XNOR function using inputs Y and Z, (b) an odd number of 1s function using inputs X, Y, and Z, and (c) an OR function using inputs X, Y, and Z. If a JEDEC file is created for the fuse map, what logic value is used to represent an intact fuse in that file?
SECTION 3.9
WORKED EXERCISES
213
S O L U T I O N A truth table for the functions is shown as follows with F1 = Y { Z, F2 = 1 if there is an odd number of 1s for X Y Z, else F2=0, and F3=X+Y+Z.
X Y Z 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 F1 F2 F3 1 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 1 1 1 1 1
To implement these functions with a PAL3L3 we first obtain the functions to be implemented in a minimum SOP form for the 0s of the functions. We can write the minimum forms for two of the functions by inspection as F1 = Y { Z =Y Z + Y Z and F3 = X + Y + Z=X Y Z. The K-map shown in Fig. WE3.51(a) is used to obtain a minimum SOP form for F2. Notice that the function will not reduce since it has no adjacent 0s.
X F2 = 0 1 YZ 00 01 11 10 0 1 1 0 0 1 1 0
Figure WE3.51(a)
A minimum SOP form for the 0s of the function F2 is written as F2 = X Y Z +X Y Z+X Y Z+X Y Z. Using the minimum equations, we can construct the PAL3L3 circuit and place the intact fuses as shown in the design in Fig.WE3.51(b).
X Y Z Fixed connections YZ YZ F1 0 0 XYZ XYZ F2 XYZ XYZ XYZ 0 F3 0 0 Programmed connections Active low output Active low output Active low output
Figure WE3.51(b)
In a JEDEC file, a 0 represents a fuse that is to be left intact or not blown.
214
CHAPTER 3
52. What is the active level of a positive logic signal that contains an overbar? Provide several examples of such signals. If a polarized signal does not contain an overbar, what is its active level? Give several examples of active high and active low signals. What is the preferred way to write polarized signals? S O L U T I O N A positive logic signal with an overbar or in complemented form is an active low signal. Signals of this type have the form A, A, ~ A and A. A polarized signal is active high if it has a suffix of (H), or it is active low if it has a suffix of (L). Active high polarized signals have the form A(H), A(L), /A(L), ~ A(L), and A(L), etc., while active low polarized signals have the form B(L), B(H), /B(H), ~ B(H), and B(H). The preferred way to write polarized signals is without overbars or in noncomplemented forms such as A(H) and B(L). 53. Convert each of the following circuits into a circuit in the opposite system, i.e., from the PLC system to the DPI system or from the DPI system to the PLC system. Use polarized signals for the DPI system and positive logic signals for the PLC system. Use only preferred polarized signal names in the DPI system. Analyze each converted circuit to obtain its function and corresponding signal list.
A B F2 C D PLC Y(H) Z(L) DPI W(L) X(H) F3(H)
(a)
(b)
S O L U T I O N To change from the PLC system to the DPI system simply change all bubbles to wedges as shown in Fig. WE3.53(a). Append an H to all the positive logic signals to obtain equivalent polarized signal names. Next choose preferred polarized signal names, i.e., polarized signal names with the variable part noncomplemented, as shown in Fig. WE3.53(a). Notice that the positive logic signal A converts to A(H), a preferred polarized signal name, but B converts to B(H) and is changed to the preferred polarized signal name B(L) by double complementation.
Figure WE3.53
A(H) B(L) F2(H) C(H) D(L) DPI Y Z PLC F3 = WX + YZ or F3 = WX + YZ SL: F3, W, X, Y, Z (b) W X F3
F2(H) = (AB + CD)(H) SL: F2(H), A(H), B(L), C(H), D(L) (a)
PROBLEMS
215
To change from the DPI system to the PLC system simply change all wedges to bubbles as shown in Fig. WE3.53(b). Write the polarized signals as equivalent positive logic signals in polarized form and then delete the suffix (H). Notice that the polarized positive logic signal name X(H) converts to X, a positive logic signal, but the polarized negative logic signal name Z(L) must first be changed to the positive logic signal Z(H) and then to Z. 54. Specify the polarized signal names that could be used for the inputs and outputs for the circuits shown in Fig. 3.7.5 if all of the circuits were drawn using the DPI system. Use only preferred polarized signal names that satisfy signal matching. S O L U T I O N The solution is shown in Fig. WE3.54. Each polarized signal name is chosen to satisfy signal matching.
74LS49
BCD to 7-seg Display Decoder
74LS138
DMUX
Figure WE3.54
0 1 2 3
74LS125A G(L) A(H) F(H) DPI BI(L) A(H) B(H) C(H) D(H)
G20 1 2 4 8
a20 b20 c20 d20 e20 f20 g20
A(H) B(H) a(H) C(H) b(H) c(H) d(H) G1(H) e(H) G2A(L) f(H) G2B(L) g(H)
1 2 4
& EN
4 5 6 7
Y0(L) Y1(L) Y2(L) Y3(L) Y4(L) Y5(L) Y6(L) Y7(L)
DPI (a) (b) (c)
DPI
PROBLEMS
3.1
3.2
3.3
Draw a switching circuit using momentary pushbutton switches that will perform each of the following basic operations. (a) OR operation (b) AND operation (c) complement operation Draw a switching circuit using logic symbols that will perform each of the following basic operations. (a) OR operation (b) AND operation (c) complement operation Write a relationship for the number of different Boolean functions possible for n independent variables. How many different functions are possible for the following number of independent variables? If a function and its complement are considered as only one function, then how many functions are possible for the following number of independent variables? (a) 2 (b) 3 (c) 4 (d) 5
216
CHAPTER 3
3.4
Analyze the switching circuits shown in Fig. P3.4 to obtain the logic function for each circuit.
W
X Y Z F (a)
Z W X Z F (b) Y X
X Y W F (c)
Figure P3.4
3.5
Analyze the symbolic logic circuits shown in Fig. P3.5 to obtain the logic function for each circuit.
X Y Z F
W X F Y Z (a) (b)
X Y Z X (c) F
Figure P3.5
3.6 3.7
3.8
3.9
3.10 3.11
3.12 3.13
Draw a circuit for each of the switching circuit in Fig. P3.4 using logic symbols instead of switches. Design a switching circuit using switches that will perform each of the following functions. (a) F(X, Y, Z)=X+X Y Z (b) F(X, Y, Z)=X (X+Y+Z)+X (c) F(X, Y, Z)=X+X Y+Z Show a circuit implementation for the following functions using OR, AND, and Inverter logic symbols. (a) F(X, Y, Z)=X+X Y Z (b) F(X, Y, Z)=X (X+Y+Z)+X (c) F(X, Y, Z)=X+X Y+Z Construct a table consisting of rectangular-shape (non-shape distinctive) symbols for 2-input AND, OR, NAND, and NOR gates. Provide both the OR form and the AND form for each symbol. Design a circuit that provides at its output the 1s complement of each 3-bit binary number applied to its input. Design a circuit that provides at its output the 2s complement of each 3-bit binary number applied to its input. Only use OR, AND, and Inverter logic symbols. Design a majority of 1s circuit such that the output F is 1 when a majority of the inputs X Y Z are 1. Only use OR, AND, and Inverter logic symbols. Design a minority of 1s circuit such that the output F is 1 when a minority of the inputs A B C are 1. Only use OR, AND, and Inverter logic symbols.
PROBLEMS
217
3.14 Design a circuit that converts each 3-bit binary number applied to its input to a binary number at its output, equivalent to the square of the corresponding input binary number. Only use OR, AND, and Inverter logic symbols. 3.15 Obtain a set of minimum SOP functions for a circuit that will accept BCD code at its input and provide 2421 code at its output. Show a circuit diagram using only OR, AND, and Inverter logic symbols. 3.16 Obtain a set of minimum POS functions for a circuit that will accept XS3 code at its input and provide BCD code at its output. Show a circuit diagram using only OR, AND, and Inverter logic symbols. 3.17 For the AND form shown in Fig. P3.17, draw the circuits that result from the following substitutions, and name the normally available gate type for each circuit. (a) Substitute an equivalent signal line for input 1. (b) Substitute an equivalent signal line for input 2. (c) Substitute equivalent signal lines for input 1 and output 3. (d) Substitute equivalent signal lines for input 2 and output 3.
1 2 3
Figure P3.17
3.18 Use the AND form shown in Fig. P3.17 and equivalent signal lines to draw an equivalent circuit using each of the following gates. (a) an AND gate (b) an OR gate (c) a NAND gate (d) a NOR gate 3.19 For the AND form shown in Fig. P3.19, draw the circuits that result from the following substitutions, and name the normally available gate type for each circuit. (a) Substitute an equivalent signal line for input 1. (b) Substitute an equivalent signal line for input 2. (c) Substitute equivalent signal lines for input 1 and output 3. (d) Substitute equivalent signal lines for input 2 and output 3.
1 2 3
Figure P3.19
3.20 Use the AND form shown in Fig. P3.19 and equivalent signal lines to draw an equivalent circuit using each of the following gates. (a) an AND gate (b) an OR gate (c) a NAND gate (d) a NOR gate 3.21 For each of the circuits shown in Fig. P3.21, draw an equivalent circuit such that the logic indicators on the signal lines between the logic elements are matched, i.e., drawn using indicator matching.
(a)
(b)
(c)
(d)
Figure P3.21
218
CHAPTER 3
3.22 Draw each of the circuits shown in Fig. P3.22 as an implementation using NAND gates. Substitute only equivalent signal lines.
(a)
(b)
(c)
(d)
Figure P3.22
3.23 Draw each of the circuits shown in Fig. 3.22 as an implementation using NOR gates. Substitute only equivalent signal lines. 3.24 Solve for a minimum SOP form for the 1s of the function F(X, Y, Z)= g (1, 2, 4). Obtain implementations for the following type of gates. Inverters may be used. (a) NAND gates (b) NOR gates 3.25 Solve for a minimum SOP form for the 0s of the function F(X, Y, Z)= g (1, 2, 4). Obtain implementations for the following type of gates. Inverters may be used. (a) NAND gates (b) NOR gates 3.26 Solve for a minimum SOP equation for the function F(W, X, Y, Z)= g (2, 3, 6, 7, 8, 9, 12, 13)+ g md(0, 4, 15). Show a 2-level gate circuit implementation for the equation using only NAND gates and Inverters. 3.27 Draw a minimum NOR/NOR implementation for the Boolean function F(W, X, Y, Z)= g (0, 2, 5, 7, 8, 10, 13)+ g md(1, 9, 11). Inverters may be used. 3.28 Show a NAND/NAND implementation with a minimum number of gates for the Boolean function F(W, X, Y, Z)= g (0, 2, 5, 7, 8, 10)+ g md(12, 13). Inverters may be used. 3.29 Show a NOR/NOR implementation with a minimum number of gates for the Boolean function F(W, X, Y, Z)= g (0, 2, 5, 7, 8, 10)+ g md(12, 13). Inverters may be used. 3.30 Show 2-level gate circuit implementations with a minimum number of gates in each of the following forms for the minimum function F1 = X Y + X Y. Inverters may be used. (a) AND/OR (b) NAND/NAND (c) NOR/NOR 3.31 Draw a 2-level gate circuit implementation in NAND/NAND form for the Boolean function F=(A+C) AB + CB. Inverters may be used. 3.32 Draw a minimum 2-level gate circuit implementation in NOR/NOR form for the Boolean function F = A C + B C. Inverters may be used. 3.33 Reduce the following functions to minimum SOP expressions using mapentered variables. (a) F(X, Y, Z)= g (0, 1 Z, 2) where m=m(X, Y) (b) F(X, Y, Z)= g A1, 2 Z, 3 Z B + gmd(0) where m=m(X, Y) (c) F(X, Y, Z)= g (0 Z, 3)+ g md(1) where m=m(X, Y)
PROBLEMS
219
3.34 Reduce the following functions to minimum SOP expressions using compressed K-maps. (a) F(A, B, C, D)= g A0, 1 (C+D), 3 CB where m=m(A, B) (b) F(A, B, C, D)= g (0 C, 2 C D, 3) where m=m(A, B) (c) F(W, X, Y, Z)= g A0 Y Z, 1, 2 ZB + g md(3) where m=m(W, X) 3.35 Obtain minimum SOP expressions for the following functions using compressed K-maps. (a) F(X, Y, Z)=X Y Z + X Y Z + X Y where m=m(X, Y) (b) F(X, Y, Z)=X Y Z + X Y + X Y Z where m=m(X, Y) (c) F(X, Y, Z)=X + X Y Z where m=m(X, Y) (d) F(X, Y, Z)=X Z + X Z Y where m=m(X, Y) 3.36 Reduce the following functions to minimum SOP expressions using compressed K-maps. (a) F(A, B, C, D)= g A0, 2 D, 4 D, 6B where m=m(A, B, C) (b) F(A, B, C, D)= g (2, 4, 5, 7 D)+ g md(6) where m=m(A, B, C) (c) F(A, B, C, D)= g (1, 2 C, 5, 6 C)+ g md(7) where m=m(A, B, D) 3.37 Reduce the following functions to minimum SOP expressions using compressed K-maps. (a) F(U, V, W, X, Y, Z)= g A0 X, 1, 3 Y, 6 ZB where m=m(U, V, W) (b) F(A, B, C, D, E)= g (2, 3 D E, 7 E)+ g md(4, 6) where m=m(A, B, C) (c) F(T, U, V, W, X, Y)= g A0 W, 1 X, 3 Y, 4, 6 ZB + g md(5, 7) where m=m(T, U, V) 3.38 Obtain minimum SOP expressions for the following functions using compressed K-maps. (a) F(V, W, X, Y, Z)= g A1, 6 Z, 7 Z, 9, 10 Z, 11 Z, 15B + g md(14) where m=m(V, W, X, Y) (b) F(A, B, C, D, E, G)= g A2 (E + G), 4, 5, 9 G, 10 (E + G), 12, 13B + g md(6, 14) where m=m(A, B, C, D) 3.39 The function F1 specified by the following truth table was modified three times using the expression at the minterm location shown in each case. Find a minimum SOP expression for each of the functions F2 through F4. A dash in the table represents a dont care output.
A B C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
F1 F2 F3 0 1 0 1 0 1 0 D 0 0 1 0 1 0 0 1
F4 0 1 0 1 0 D + E
1 DE
3.40 Plot the following 3-variable functions on 2-variable K-maps and obtain minimum SOP expressions for each function. Show a circuit implementation using only NAND gates and Inverters. The dash in the table represents a dont care output.
220
CHAPTER 3
ANALYZING AND SYNTHESIZING COMBINATIONAL LOGIC CIRCUITS (a) (b) (c) F1 F2 F3 0 0 1 1 1 0 1 0 1 1 0 1 1 0 0 0 1 0 1 0 1 0 0
A B C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
3.41 For each of the K-maps in Fig. P3.41, show a reduced Karnaugh map one size smaller. Write a minimum SOP expression for each reduced map and each normal map.
Figure P3.41
AB F1 = 00 01 11 10 C 0 0 0 1 0 (a) 1 1 1 1 1 (b) A F2 = 0 1 BC 00 01 11 10 1 0 1 1 0 1 0 1 AB F3 = 00 01 11 10 CD 00 01 11 10 1 0 0 1 0 0 0 0 0 1 1 1 (c) 1 1 1 1
3.42 Plot the following four-variable functions for a BCD to XS3 code converter on three-variable K-maps and obtain minimum SOP expressions for each function. The dashes in the table represent dont care outputs.
BCD I3 I2 I1 I0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 XS3 F3 F2 F1 F0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0
=dont care
3.43 Eliminate all logic hazards that can result if the following functions are implemented. List a minimum covering and a logic hazard-free covering first for the 1s and then for the 0s for each of the following functions.
PROBLEMS
221
(a) F(A, B, C)= g (1, 3, 4, 5) (b) F(X, Y, Z)= g (1, 2, 3, 6) (c) F(X, Y, Z)= g (0, 2, 3, 4, 6) 3.44 Determine the number of logic hazards the circuit in Fig. P3.44 could contain. What product terms are necessary to eliminate these logic hazards? Write a logic hazard-free function for the circuit.
B D A B C A C D
Figure P3.44
3.45 Suppose a minimum covering is obtained when designing a circuit for the 1s of each of the following functions. Will the circuits contain logic hazards? If so, what are the logic hazard cover terms? Obtain a logic hazard-free function for each SOP form. (a) F(A, B, C, D)= g (0, 1, 2, 5, 6, 7, 15) (b) F(W, X, Y, Z)= g (0, 1, 5, 7, 8, 9, 14, 15) (c) F(A, B, C, D)= g (2, 3, 8, 9, 10, 11) 3.46 Suppose a minimum covering is obtained when designing a circuit for the 0s of each of the following functions. Will the circuits contain logic hazards? If so, what are the logic hazard cover terms? Obtain a logic hazard-free function for each SOP form. (a) F(A, B, C, D)= g (0, 1, 2, 5, 6, 7, 15) (b) F(W, X, Y, Z)= g (0, 1, 5, 7, 8, 9, 14, 15) (c) F(A, B, C, D)= g (2, 3, 8, 9, 10, 11) 3.47 Draw a 3-input AND gate as a 2-input AND gate, and a 3-input OR gate as a 2-input OR gate, using both AND and OR element symbols via fanin reduction. 3.48 Draw a 4-input NAND gate as a 3-input NAND gate, and a 4-input NOR gate as a 3-input NOR gate, using both AND and OR element symbols via fanin reduction. 3.49 Analyze the design in Fig. P3.49 to obtain the output Boolean functions in compact minterm form.
DMUX 0 1 2 3 0 4 1 5 2 6 7 EN
Figure P3.49
A B C
F2
F1
F0
3.50 Use a Decoder and an external gate to implement each of the following functions. (a) F1(A, B, C)= g (2, 5, 7) (b) F2(A, B, C, D)= g (3, 6, 9, 12, 14, 15) (c) F3(W, X, Y, Z)= g (0, 5, 8, 9, 10, 11)
222
CHAPTER 3
3.51 Implement the following set of functions using a Decoder. Use OR forms with the smallest possible number of inputs (fan-in); that is, count 1s and 0s and use the smallest number. F1(A, B, C)= g (0, 1, 2), F2(A, B, C) g (1, 2, 3, 4, 5, 7), F3(A, B, C)= g (2, 3, 5, 7). 3.52 Design a Binary-to-ASCII Hexadecimal character generator with a Decoder. Let the available inputs be A B C D and the available outputs AK6 through AK0. Let the inputs range from 0000 to 1111 and the ASCII outputs range from 0 to 9 and from A to F (refer back to Fig. 1.7.2(a) in Chapter 1 for the 7-bit ASCII charter code set to obtain the code values). (a) Obtain the truth table. (b) Obtain the SOP form of each output function in terms of the smallest number of 1s or 0s. (c) Use one gate at the output of the Decoder for each output function. 3.53 Design a BCD to 7-segment code converter with a Decoder. Use the displayed characters 0 through 9 as shown in the truth table below.Assume that the converter is designed to drive a common-cathode display (a 1 at the output lights a segment). Obtain the SOP form of each output function in term of the smallest number of 1s or 0s, and use one gate at the output of the Decoder for each output function.
Inputs DCBA 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 d e f g c b a Character OA OB OC OD OE OF OG
3.54 Use a Decoder to design the XS3-to-BCD code converter shown in the following truth table. Use OR forms with the smallest possible fan-in; that is, count the 1s and 0s. The signal list for the code converter is F3, F2, F1, F0, I3, I2, I1, I0.
XS3 I3 I2 I1 I0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 BCD F3 F2 F1 F0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1
PROBLEMS
223
3.55 Design a Decoder circuit to perform the function of the BCD-to-XS3 code converter shown in the truth table below. Use OR forms with the smallest possible fan-in. The signal list for the code converter is F3, F2, F1, F0, I3, I2, I1, I0.
BCD I3 I2 I1 I0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 XS3 F3 F2 F1 F0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0
3.56 Design a circuit to implement the following functions using a DMUX with an active low enable input and active low outputs. Use gates with the smallest possible fan-in. F1(X, Y, Z)=X Y+X Z, F2(X, Y, Z)=Y Z+X Y Z 3.57 Implement a circuit for the 2421-to-BCD code converter represented in the truth table shown below. Use a DMUX with an active low enable input and active low outputs and gates with the smallest fan-in.
2421 I3 I2 I1 I0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 1 1 1 1 0 0 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 BCD F3 F2 F1 F0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1
3.58 Analyze each circuit in Fig. P3.58 to obtain the output Boolean function F in compact minterm form.
Vcc
Figure P3.58
Vcc
EN MUX 0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 3
D F
EN MUX
F
S 2 1 0
S 2 1
GND
ABC
GND
WX Y Z
224
CHAPTER 3
3.59 Analyze the Multiplexer circuits shown in Fig. P3.59 to obtain their output functions in compact minterm form.
Figure P3.59
Vcc
MUX
EN
MUX
EN
0 1 2 3 S 1 0
Z Y
GND 0 1 S 0
GND
AB (a) (b)
3.60 Design a circuit using a 2-to-1 Multiplexer to implement each of the following functions. Use gates and Inverters if necessary. (a) F(A, B)=A B with B at the select input (b) F(A, B)=A+B with A at the select input (c) F(A, B)=A+B with B at the select input (d) F(A, B)=A { B with A at the select input 3.61 Design a circuit using a 4-to-1 Multiplexer to implement each of the following functions. Use gates and Inverters if necessary. (a) F(A, B)=A B with A and B at the select inputs (b) F(A, B)=A+B with A and B at the select inputs 3.62 Design a 2-to-1 Multiplexer circuit to implement each of the following functions. Use gates and Inverters if necessary. In each case provide X at the select input. (a) F(X, Y, Z)=X+Y Z (b) F(X, Y, Z)=X Y+X Z (c) F(X, Y, Z)= g (0, 2, 4, 5) (d) F(X, Y, Z)=X + Y Z 3.63 Repeat Problem 3.62 using a 4-to-1 MUX. In each case provide X and Y at the select inputs. 3.64 Design a circuit to implement the function F(A, B, C, D)= g (0, 2, 8, 9, 10) using an 8-to-1 Multiplexer. Use gates and Inverters if necessary. Provide A, B, and C at the select inputs. 3.65 Repeat Problem 3.64 using a 4-to-1 Multiplexer. 3.66 Design a Type-0 Multiplexer circuit for the function F(A, B, C)= g (2, 5, 7) 3.67 Repeat Problem 3.66 using a Type-1 Multiplexer circuit implementation. 3.68 Repeat Problem 3.66 using a Type-2 Multiplexer circuit implementation. 3.69 For the function F(A, B, C, D)= g (1, 3, 8, 9, 14), implement (a) a Type-1 MUX design (b) a Type-2 MUX design (c) a Type-3 MUX design 3.70 Implement a Type-1 MUX design for each of the following functions. (a) F1(A, B, C)= g (1, 3, 4, 5, 6) (b) F2(X, Y, Z)= g (0, 2, 4, 5, 7) (c) F3(A, B, C, D)= g (2, 6, 7, 8, 9, 12, 13, 14, 15)
PROBLEMS
225
3.71 Repeat Problem 3.70 for a Type-0 MUX design. 3.72 Implement a Type-1 MUX design for each of the K-maps shown in Fig. P3.72 using C and D as the map entered variable.
A F=
BC 00 01 11 10 0 1 0 1 0 0 1 1 0 1
AB F=
CD 00 01 11 10 00 01 11 10 0 1 1 0 0 0 0 1 1 0 0 0 (b) 1 1 1 0
Figure P3.72
(a)
3.73 Implement a Type-2 MUX design for each of the Karnaugh maps shown in Fig. P3.72. 3.74 Use multiple function minimization as much as possible to obtain the simplest set of SOP expressions for the 1s of the following functions. Specify the combined complexity in total literal count. (a) F1(X, Y, Z) = g (0, 2, 4, 6, 7); F2(X, Y, Z)= g (2, 6, 7) (b) F1(X, Y, Z) = g (1, 3, 4, 7); F2(X, Y, Z)= g (3, 4, 6, 7) (c) F1(A, B, C) = g (1, 2, 4, 6); F2(A, B, C)= g (0, 1, 2, 6, 7); F3(A, B, C) = g (1, 2, 6) 3.75 Use multiple function minimization as much as possible to obtain the simplest set of SOP expressions for the 0s of the following functions. Specify the combined complexity in total literal count. (a) F1(X, Y, Z) = g (0, 2, 4, 6, 7); F2(X, Y, Z)= g (2, 6, 7) (b) F1(X, Y, Z) = g (1, 3, 4, 7); F2(X, Y, Z)= g (3, 4, 6, 7) (c) F1(A, B, C) = g (1, 2, 4, 6); F2(A, B, C)= g (0, 1, 2, 6, 7); F3(A, B, C) = g (1, 2, 6) 3.76 Obtain the simplest combined set of SOP expressions for the 0s of the following functions. Find the total literal count of each combined set. (a) F1(A, B, C, D)= g (4, 5, 6, 7, 9, 14); F2(A, B, C, D)= g (0, 1, 2, 3, 9, 14) (b) F1(W, X, Y, Z)= g (0, 2, 7, 8, 10, 15); F2(W, X, Y, Z)= g (7, 9, 11, 13, 15) 3.77 Obtain the simplest combined set of SOP expressions for the 1s of the following functions. Find the total literal count of each combined set. (a) F1(A, B, C, D)= g (4, 5, 6, 7, 9, 14); F2(A, B, C, D)= g (0, 1, 2, 3, 9, 14) (b) F1(W, X, Y, Z)= g (0, 2, 7, 8, 10, 15); F2(W, X, Y, Z)= g (7, 9, 11, 13, 15) 3.78 Show an implementation for an XS3-to-BCD code converter with inputs I3 I2 I1 I0 and outputs F3 F2 F1 F0 using the simple PROM shown in Fig. P3.78 with 4 inputs and 8 outputs. The *s that indicate programmable connections in the logic diagram are not shown so that they can be manually added in the OR matrix where they are needed. List each hexadecimal address and the corresponding data required to program the OR matrix.
226
CHAPTER 3

I3 I2 I1 I0
Figure P3.78
F3 F2 F1 F0
3.79 Repeat Problem 3.78 for a BCD-to-XS3 code converter. 3.80 Show a design for the following Boolean functions using the simple PAL shown in Fig. P3.80 with 4 inputs and 4 outputs. Generate the fuse map information for the equations manually. If the PAL were commercially available, write the PAL nomenclature that could be used to describe it. F1(A, B, C, D) = g (6, 7, 9, 11, 12, 13) F2(A, B, C, D) = g (0, 2, 3, 4, 5, 10, 11, 13, 15)
Figure P3.80
F3(A, B, C, D) = g (2, 3, 6, 7, 10, 11, 14, 15)
PROBLEMS
227
3.81 Repeat Problem 3.80 using the simple 4-input, 4-output PAL shown in Fig. P3.81.
Figure P3.81
3.82 PALs are available today that have the capability to program the polarity of the output. This means that the software can choose to add or not to add an Inverter on each OR gate output. Which type of equation must have an Inverter added at the output of the OR gate (an equation for the 1s of the function or for the 0s of the function)? Provide an example that supports your answer. 3.83 Which type of output (Inverted or non-Inverted) is required when implementing a function for its 0s in a PAL? Show why, using a simple example. 3.84 Which type of output (Inverted or non-Inverted) is required when implementing a function for its 1s in a PAL? Use a simple example to show your reasoning. 3.85 Write the Boolean function F = A + B C in terms of the signals in the following signal list. (a) SL: F, A, ~ B, C (b) SL: F, ~ A, ~ B, C (c) SL: F, A, ~ B, ~ C (d) SL: ~ F, ~ A, B, C 3.86 List the input and output signals, i.e., the accessible or available signals, for the Boolean function F = ~Y Z + ~X ~ Y + W ~X ~Y. 3.87 Write the Boolean function F = X Y + Y Z + W Y Z in terms of the following accessible or available input and output signals. (a) SL: F, ~ W, ~ X, Y, Z (b) SL: ~ F, W, X, ~ Y, Z (c) SL: F, W, ~ X, Y, Z (d) SL: ~ F, W, X, ~ Y, ~ Z
228
CHAPTER 3
3.88 Obtain the signal list for Circuit 3 in the block diagram shown in Fig. P3.88. List positive logic (PL) signals without a suffix and negative logic (NL) signals with the suffix (L). (a) (b) (c) (d) (e)
Figure P3.88
Circuit 1
Circuit 1 PL PL NL NL PL
A
Circuit 2 PL PL PL NL NL
Circuit 4 PL NL PL PL NL
Circuit 3 ~B
Circuit 4
Circuit 2
3.89 Obtain the signal list for Circuit 3 in the block diagram shown in Fig. P3.89. List positive logic (PL) signals without a suffix and negative logic (NL) signals with the suffix (L). (a) (b) (c) (d) (e) (f) Circuit 1 NL PL PL NL NL PL Circuit 2 PL NL PL PL NL PL Circuit 4 Circuit 5 PL NL NL PL PL NL PL PL NL PL NL PL
Figure P3.89
Circuit 1 Circuit 2
X ~Y ~Z Circuit 3
F1 ~F2
Circuit 4 Circuit 5
3.90 A circuit designed to work with all positive logic signals at its inputs will not perform as designed when a negative logic signal is inadvertently applied to one of its inputs. What simple circuit modification can be made to allow the circuit to perform properly with the negative logic signal applied? Illustrate your reasoning using a polarized signal. 3.91 How can a positive logic output be converted to a negative logic output? Illustrate your reasoning using a polarized signal. 3.92 Convert a positive logic OR gate to the equivalent negative logic gate type. Hint: A negative logic signal applied to an Inverter is converted to a positive logic signal at the output of the Inverter. 3.93 Convert a positive logic NAND gate to the equivalent negative logic gate type. Hint:A negative logic signal applied to an Inverter is converted to a positive logic signal at the output of the Inverter. 3.94 Convert a negative logic NOR gate to the equivalent positive logic gate type. Hint: A negative logic signal applied to an Inverter is converted to a positive logic signal at the output of the Inverter.
PROBLEMS
229
3.95 Obtain the voltage truth table (a table consisting of Hs or highs and Ls or lows rather than 1s and 0s) for the logic elements shown in Fig. P3.95.
Figure P3.95
(a) (b)
3.96
3.97
3.98
3.99
Draw the AND form and the equivalent OR form for a 2-input NOR gate for the direct polarity indication system. Label the inputs A and B and the output F on each graphic symbol. Draw the AND form and the equivalent OR form for a 3-input NAND gate for the direct polarity indication system. Label the inputs X, Y, and Z and the output F on each graphic symbol. Construct a table consisting of distinctive-shape symbols using the direct polarity indication system for 2-input AND, OR, NAND, and NOR gates. Provide both the OR form and the AND form for each symbol. For each of the circuits shown in Fig. P3.99, draw an equivalent circuit with all indicators matched.
(a)
(b)
(c)
(d)
Figure P3.99
3.100 For the function ~ F(~ A, B, ~ C)= g (0, 1, 2, 3, 5) with signal list: ~ F, ~ A, B, ~ C, solve for the SOP form for the 1s of the function. Obtain implementations using the direct polarity indication system for the following type of gates. Inverters may be used. (a) NAND gates (b) NOR gates 3.101 For the function ~ F(~ A, B, ~ C)= g (0, 1, 2, 3, 5) with signal list: ~ F, ~ A, B, ~ C, solve for the SOP form for the 0s of the function. Obtain implementations using direct polarity indication for the following type of gates. Inverters may be used. (a) NAND gates (b) NOR gates 3.102 Using direct polarity indication, draw a 3-input AND gate as a 2-input AND gate, and a 3-input OR gate as a 2-input OR gate, using both AND and OR element symbols via fan-in reduction. 3.103 Using direct polarity indication, draw a 4-input NAND gate as a 3-input NAND gate, and a 4-input NOR gate as a 3-input NOR gate, using both AND and OR element symbols via fan-in reduction. 3.104 Obtain the Boolean function in SOP form and the signal list for each of the implementations shown in Fig. P3.104. For negative logic signals use the suffix (L) after each negative logic signal name.
230
CHAPTER 3
~A C
ANALYZING AND SYNTHESIZING COMBINATIONAL LOGIC CIRCUITS B C F F A PLC (a) C (b) PLC
B C
W Y Z W Z W X Y W Y Z ~F F PLC NLC W X Z W Z W Y (c) (d) F F PLC NLC
Figure P3.104
3.105 Obtain the Boolean function in SOP form and the signal list for each logic diagram shown in Fig. P3.105. For negative logic signals use the suffix (L) after each negative logic signal name.
W W NLC PLC Y NLC PLC Z X Y Y Z ~F Z W X Z F W Z W
(a)
(b)
Figure P3.105
3.106 Show that the signal names ~ A(H) and ~ A(L) are not identical and therefore may be used on the same diagram to represent two different signals.
PROBLEMS
231
3.107 Show that the signal name ~D(H) is equivalent to the signal name ~ D(L) and therefore may be used on the same diagram to identify the same signal. 3.108 Obtain the Boolean function in SOP form and the signal list for each of the implementations shown in Fig. P3.108.
X Z B A (a) DPI ~Z(L) Y(H) ~Z(L) X(H) Y(H) (d) DPI F B(H) A(H) (b) F F(H) DPI X Y (c) DPI
F(H)
Figure P3.108
3.109 Obtain the Boolean function in SOP form and the signal list for each logic diagram shown in Fig. P3.109. Hint: All signal names without a suffix have an implied high suffix (the default suffix).
W Y(L) Z W X Z ~F(H) W Z W Y(L) (a) DPI
W(L) Z(H) W(L) X(H) Y(H) W(L) Y(H) Z(H) F(H) DPI
(b)
Figure P3.109
232
CHAPTER 3
3.110 Obtain the Boolean function in SOP form and the signal list for each logic diagram shown in Fig. P3.110. All signal names without a suffix have an implied high suffix (the default suffix).
B C F A C (a) W Y Z W X Z W Z (c) (d) DPI DPI B(H) C(H) (b) DPI ~A(H) C(H) F(H)
~F(L)
W(H) X(H) Y(H) W(H) Y(H) Z(H)
F(L) DPI
Figure P3.110

Combi Logic

Загружено:

Сведения о документе

Исходное описание:

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

Combi Logic

Загружено:

Авторское право:

Доступные форматы

C H A P T E R

Analyzing and Synthesizing Combinational Logic Circuits

ANALYZING AND SYNTHESIZING COMBINATIONAL LOGIC CIRCUITS

Regenerative Logic Switching Circuit Vcc = H = 1 B

Complement (Invert, NOT) F=A A F 0 1 1 0 A F A 1 F A F

STANDARD GRAPHIC SYMBOLS AND TWO-VALUED SWITCHING CIRCUITS

Source PMOS FET n.c. pushbutton switch

Collector PNP BJT n.c. pushbutton switch

Drain Spring n.o. contacts =

Source NMOS FET n.o. pushbutton switch

Emitter NPN BJT n.o. pushbutton switch

ANALYZING AND SYNTHESIZING COMBINATIONAL LOGIC CIRCUITS

STANDARD GRAPHIC SYMBOLS AND TWO-VALUED SWITCHING CIRCUITS

Y X Vcc Power Supply + _ GND

Vcc R LED Power Supply + _ X

F = XY AND symbol R LED GND

GND (a) (b) (c)

ANALYZING AND SYNTHESIZING COMBINATIONAL LOGIC CIRCUITS

Vcc = H = 1 NAND F = AB =A+B A 0 0 1 1 B 0 1 0 1 F 1 1 1 0 A A B F A B & F B

ANALYZING AND SYNTHESIZING COMBINATIONAL LOGIC CIRCUITS

Regenerative Logic Switching Circuit Vcc = H = 1 A

0 = no continuity 1 = continuity R (a)

Vcc = H = 1 XNOR F=AB = AB + AB A 0 0 1 1 B 0 1 0 1 F 1 0 0 1 A A B F A B =1 F A

STANDARD GRAPHIC SYMBOLS AND TWO-VALUED SWITCHING CIRCUITS

where n is the number of input variable

ANALYZING AND SYNTHESIZING COMBINATIONAL LOGIC CIRCUITS

STANDARD GRAPHIC SYMBOLS AND TWO-VALUED SWITCHING CIRCUITS

F1 0 = no continuity 1 = continuity (a)

GND = L = 0 (a) (b)

(continues on next page)

ANALYZING AND SYNTHESIZING COMBINATIONAL LOGIC CIRCUITS

DESIGNING LOGIC CIRCUITS

n.c. pushbutton switch

common symbol for n.c. relay contacts

n.o. pushbutton switch

common symbol for n.o. relay contacts

DESIGNING LOGIC CIRCUITS

Figure 3.2.3 Circuits to be analyzed to obtain their Boolean functions.

ANALYZING AND SYNTHESIZING COMBINATIONAL LOGIC CIRCUITS

DESIGNING LOGIC CIRCUITS

DESIGNING IC LOGIC CIRCUITS

B C 2-input AND gate A

2-input AND gate

ANALYZING AND SYNTHESIZING COMBINATIONAL LOGIC CIRCUITS

3-input AND gate

3-input AND gate

or 3-input AND gate

DESIGNING LOGIC CIRCUITS

Y 2-input OR gate Z F2 2-input OR gate 3-input AND gate

ANALYZING AND SYNTHESIZING COMBINATIONAL LOGIC CIRCUITS

DESIGNING LOGIC CIRCUITS

Part number Pin number Vcc* GND 14 14 14 7 7 7

U1b 6 Inverters/ IC package

ANALYZING AND SYNTHESIZING COMBINATIONAL LOGIC CIRCUITS

Equivalent Graphic Symbols for NAND, NOR, AND, and OR Gates

AND form of a NAND gate

DESIGNING LOGIC CIRCUITS

ANALYZING AND SYNTHESIZING COMBINATIONAL LOGIC CIRCUITS

(Three AND forms of NAND gates)

3-input NAND gate B C

(One OR form of a NAND gate) F1

DESIGNING LOGIC CIRCUITS

C D Preferred form of AND/OR circuits