MIPI DigRF SM 3G IP Core

Features
Compliant with 3G v3.09 specification 3G (UMTS), 2.5G (GPRS/EGPRS) Release 5,6,7 SGPP UMTS (HSDPA, HSUPA) Can be upgraded to support advanced networks such as LTE, WiMax, MIMO Master and Slave Controller IP configurations are available Two unidirectional low-swing differential pair for transmit, receive data Common reference SysClk to baseband and RF IC (19.2, 26, 38.4 MHz) Basic handset and local, remote diversity are supported Can operate at either low speed mode (SysClk/4) or high speed mode 312 Mbps Transmit data link used to initialize and configure RF IC Frame assembly, transmission and reception, header parsing done in hardware Sleep and Shutdown modes to reduce power Reliable physical layer eliminates error correction, reduces protocol overhead Up to 8 logical channels share physical link Built-in DMA support Scale interface bandwidth without data loss Optional support for AXI, AHB, OCP or custom bus DigRFSM

Overview
The rising popularity of mobile phones packed with multimedia and office productivity applications has resulted in the widespread deployment of advanced networks such as 3G. In order to ease mobile platform development and simplify system-level integration, the MIPI Alliance has defined a standard protocol to connect baseband and RF components. Arasans DigRF 3G IP core is fully compliant with the DigRF 3G v3.09 specification. Both the Master and Slave Controllers are available. This IP can be used to connect chipsets that cover dual-mode 3GPP 2.5G/3G as well as 3G only implementations. The interface is designed to minimize pin count, lower power and provide an efficient protocol to transfer data between baseband and RF chips. System designers and chip manufacturers benefit by the plug and play compatibility at the physical interface level. The physical interface comprises of a two uni-directional differential pair for transmit and receive data, clock and clock enable signal. DigRF defines a simple frame based protocol that has a fixed size header followed by a variable length payload field. The interface is defined for two use cases - a compact lowend implementation with the baseband and RF chipset physically located near each other and a higher performance handset that provides local diversity for robust wireless operation. The electrical interface is robust enough so that no error correction or coding mechanisms are specified in the standard. As a result, the protocol overhead for transfers is low. The IP handles frame assembly and serialization for transmission and on the receive side it processes frames to extract the payload. Arasan provides a Total IP Solution for DigRF 3G IP core consisting of RTL source code, test environment, synthesis scripts all backed by Arasans World-class customer support.

MIPI DigRF 3G IP Block Diagram

LVDS Buffers

DATA

FIFOs (DMA Optional)

Payload Processor

DigRF Interface Serializer/ Deserializer/ Fram er

+ -

Tx Path

+ -

Rx path

uC or AHB or APB

Slave Interface

DigRF Protocol Engine

PLL/ Clock M ultiplier

SysClk SysClkEn

DigRF Master
Copyright 2009 Arasan Chip Systems, Inc. Rev 1.0

MIPI DigRF SM 3G IP Core TM

DigRF 3G Protocol Engine:
The Protocol Engine manages the operation of the IP and is fully compliant with the DigRF 3G v3.09 specification. DigRF 3G is used for interchip communication between a baseband IC and an RF IC in mobile platforms. Both data and control information are sent using a frame based data transfer format. The controller can support a peak bandwidth of 312 Mbps in the High-speed mode. ments so as not use up the timing budget defined in the protocol. The Transmit Data link can operate in either Low-speed mode (startup, 2.5G) or High-speed mode (312 Mbps). The Receive Data Link operates in three modes: Low-speed (startup). Medium-speed (2.5G) and High-speed (312 Mbps). To further reduce power, the link can enter into sleep modes or can entirely shutdown operation. The Host processor can place the link in sleep mode during lengthy gaps in data transfer.

Benefits:
Fully compliant core Premier direct support from Arasan IP core designers Easy-to-use industry standard test environment Unencrypted source code allows easy implementation Reuse Methodology Manual (RMM) compliant verilog code

Payload Processor
This block handles the assembly and processing of frames that are the unit of transfer between the baseband IC and RF IC. Both data and control information are formatted into frames that consist of a sync field, Header field followed by a variable length payload. Due to the robustness of the PHY layer, error correction mechanisms are not specified by the protocol, thereby lowering the latency and overhead.

FIFO:
FIFOs are used to transfer data from system memory for transmission and store payload for received frames.

Slave Interface:
The slave interface is used by a host cpu to configure protocol parameters as well as control information for data transfer is set by the host cpu using this interface

Deliverables:
RMM compliant synthesizable RTL design in Verilog Easy to use test environment Synthesis scripts Technical documentation

PHY Layer / Transceiver:

A common System Clock is distributed between the baseband and RF chipset. High-speed clocks required for transmission and data reception are internally generated.Transmitters adhere to strict timing require-

Clock Generator:
This module internally generates the clocks based on the external System Clock for the various operating modes of the transceiver. Clock control logic for power saving modes is also included in this block.

MIPI DigRFSM Application

Related Products

Baseband Processor
DigRF Master

RF IC
DigRF
DigRF Slave
Radio IC

MIPI Controllers MIPI D-PHY SLIMbus Analyzer

MIPI is a licensed trademark of MIPI, Inc. in the U.S. and other jurisdictions.

Arasan Chip Systems, Inc.

2010 North. First Street. Suite #510 San Jose CA 95131 Phone: 408-282-1600 Fax: 408-282-7800 E-mail: sales@arasan.com
Copyright 2009 Arasan Chip Systems, Inc.

Data Sheet Links:

Arasan DigRF 3G IP Core: www.arasan.com/datasheets/mipi.php For a complete directory of Arasan IPs, please visit: www.arasan.com