43617 Qtyp Tpc Mrk Ans Qstn MC 1 1 B 8086 has a MC MC MC 1 1 1 1 1 1 B A B In a maximum mode 8086 system, the 8086 operates

in maximum mode by strapping its MN/MX pin to8088 has a In 8086 B A 4 bytes queue 6 bytes queue logic 0 logic 1 4 bytes queue 6 bytes queue Address/ Data Address/ Data, lines are Address/Sta multiplexed tus lines are multiplexed Overflow Flag Carry Flag C 8 bytes queue NC 8 bytes queue Address/St atus, Address/Co ntrol lines are multiplexe d Interrupt Flag 95D3Fh 10 MHz Stack, Data, Base, Counter I/O D 16 bytes queue None 16 bytes queue Address/Co ntrol, Address/St atue lines are multiplexe d Sign Flag

MC

MC MC MC

1 1 1

1 1 1

C A D

Which Flags can be set or reset by the programmer and also used to control the operation of the processor? What physical address corresponds to SI:103Fh if DS=94D0h Maximum clock frequency in 8086What are the names of the 4 segment registers? BUS HIGH ENABLE of 8086 microprocessor signal is used to interface the In 8086 microprocessor one of the following statements is not true. 8088 microprocessor differs with 8086 microprocessor in An overflow flag is set if for addition

103Fh 5 MHz Data, Index, Code, Stack Even bank memory

94D0h 3 MHz Stack, Index, Extra, Code Odd bank memory

95D00h None Stack, Extra, Code, Data DMA Supports pipelining Support of MAX / MIN mode None of these

MC MC

1 1

1 1

B B

MC MC

1 1

1 1

A C

MC

When Direction flag is set

MC MC MC MC MC

1 1 1 1 1

1 1 1 1 1

C A B C C

How much memory space does the 8086 have? The segment that holds programs and procedures used by programs Refer figure 10 Refer figure 11 The queue status lines QS1=1, QS0=0 indicates

Coprocessor I/O can be Coprocessor interfaced is interfaced is interfaced in MAX / in MAX mode in MIN mode MIN mode Support of Data width on Address capability coprocesso the output r There is a There is There is no carry into carry into carry into MSB & carry MSB & no MSB & no carry out of out of MSB carry out of MSB & MSB vice-versa The string is The string The string is is processed processed processed from the from its from the higher beginning lower address with the address towards the lower address towards the first element higher having the address lowest address 1 MB of 2 MB of 4 MB of memory memory memory Extra Code segment Data segment segment Real mode Minimum mode Maximum mode Read I/O Write Read memory port memory No operation First byte Empty queue of opcode from the queue

None of these

64 KB of memory Stack segment Protected mode Write I/O port Subsequent byte from the queue

43617 Qtyp Tpc Mrk Ans Qstn MC 1 1 C One of the following pin is not available in maximum mode MC 1 1 A One of the following pin is not available in minimum mode MC 1 1 C How many bits wide is the address bus on the 8086 Processor? MC 1 The 8086 has 4 segment registers 1 D A Refer Figure 13A Refer Figure 14A 8-bits Data, Index, Code, Stack Left and Right Units B Refer Figure 13B Refer Figure 14B 16-bits C Refer Figure 13C Refer Figure 14C 20-bits D QS0 ALE 24-bits Stack, Extra, Code, Data Bus Interface Unit and Execution Unit 32-bit DMA Supports pipelining Support of MAX / MIN mode the address of the last item popped from the stack none Extra 16 bytes queue None of these

MC

The 8086/8088 architecture divided into two processing units which were known as: The 8086 is ------ bit processor? Refer figure 19 In 8086 microprocessor one of the following statements is not true. 8088 microprocessor differs with 8086 microprocessor in The stack pointer stores

Stack, Stack, Data, Index, Extra, Code Base, Counter Segment and ALU and Control Offset Unit Units 16-bit I/O

MC MC MC

1 1 1

1 1 1

C B B

MC MC

1 1

1 1

A A

8-bit Odd bank memory Coprocessor is interfaced in MIN mode Data width on Address capability the output 4-bit Even bank memory Coprocessor is interfaced in MAX mode the address of the stack in memory

I/O can be interfaced in MAX / MIN mode Support of coprocesso r address of the address of the last item pushed the next free stack on the location stack odd Stack both Code 8 bytes queue The string is processed from its beginning with the first element having lowest address Empty queue

MC MC MC MC

1 1 1 1

1 1 1 1

B D A A

If Bus high enable pin is at logic 0 then the -----memory bank is selected. For string instructions DI always addresses data in the ---------segment 8088 has a When direction flag is set

Even Data 4 byte queue

6 bytes queue The string is The string is processed processed from higher from lower address address towards the lower address towards the higher address

MC MC

1 1

1 1

C D

The queue status lines QS1=1,QS0=0 indicates The 8086/8088 architecture divided into two processing units which were known as: 8088 microprocessor differs with 8086 microprocessor in

No operation left & right units

First byte of opcode from queue ALU & segment & offset unit control units

MC MC

1 1

1 1

A B

Data width on Address capability the output odd

If bus high enable pin is at logic Even 0 then the ----------memory bank is

subsequent byte from the queue Bus interface unit & execution unit Support of Support of Coprocesso MAX/MIN mode r None both

43617 Qtyp Tpc Mrk Ans Qstn selected MC 1 1 A A 20-bit address bus allows access to a memory of capacity How many bits wide is the address MC 1 1 C bus on the 8086 Processor? How many transistors does the 8086 MC 1 1 B have? The 8086/8088 used two processoring MC 1 1 E units which were known as: A 1MB 8-Bits 10,000 Left and Right Units B 2 MB 16-Bits 29,000 C 32MB 20-Bits 110,000 D 64 MB 24-Bits 129,000 ALU and Control Unit CPU bus

MC

MC MC MC MC MC MC MC MC MC MC

1 1 1 1 1 1 1 1 2 2

2 2 2 2 2 2 2 2 1 1

A C A D C B B C D A

MC

MC MC MC MC

2 2 2 2

1 1 1 1

C B C B

MC MC MC

2 2 2

1 1 1

B C D

Segment and Bus Unit and Offset Execution Units Interface Unit belongs to belongs to belongs to The read/write line : the data bus the control the address bus bus Calculate the beginning and ending E00000,EFFFF. E10000,EEFF 00000,FFFF F. F. address of the data segment assuming register DS= E000H 157BB 123A0 46550 If (cs)=123A and (IP)=341B then physical address of instruction is CX,64K AX,64K DX,64K 8086 uses ------ register as I/O address pointer and can address upto ---- devices. O,T,S O,D,I The control flag register of 8086 CY,Z,T consists of following flags. 16,64K 16,16K Physical memory of 8086 is divided 32,64K into ----- segments and each segment size is -----32,32 16,16 In 8086, the size of ALU is ------ 32,26 size of Flag register is ----SF=1,ZF=0, SF=1,ZF=0, SF=0,ZF=0, After performing the addition of PF=1,CF=0,A PF=1,CF=0, PF=0,CF=0, 5439H + 456AH, the flags would be AF=1,OF=0 F=1,OF=1 AF=,0OF=0 157BB 123A0 46550 If (CS)=123A and (IP)=341B, then the physical address of instruction is AX=0 BX=0 DX=0 LOOP instruction loops to the specified label until What is the output of the following AL= 00000100, BL=00000100 AL=1111110 0 CF=1 , CF=0 CF=1 code AL=00110101 BL= 39H SUB AL, BL AAS What is the output of the following CF=0, OF= 1, CF=1, OF=1, CF=1, OF code? BH= 01100101 BH=01100110 =0, BH= 01001101 CF =0, BH = 179 RCL BH, 1 STD AND TEST Which is the flag manipulation instruction? JP/JPE CALL/RET JLE/JNC Which is the unconditional branch instruction? CX=1 or ZF=0 CX=0 For the instruction LOOPE/LOOPZ, ZF=1 what should be condition for exit? Signed Signed Unsigned IDIV and DIV instructions perform number & number number the same operations for? Unsigned number PF=0 SF=0 The conditional branch instruction ZF =0 JNS performs the operations whenREPZ REPE REP To repeat a string in struction while particular condition is zero use the instruction Direct Indexed The instruction MOV AX,[BX][SI] is Register

E0000,EEFF F. 341B0 AX,32K D,I,T 32,32K 16,32 SF=1,ZF=0, PF=1,CF=1, AF=1,OF=1 341B0 CX=0 BL=0000010 0, CF=1

CF=0, OF=0, BH=0010110 0 None JO CX=0 or ZF=0 None of above CF=0 C & B Based

43617 Qtyp Tpc Mrk Ans Qstn an example of MC MC MC MC 2 2 2 2 1 1 1 1 A D A A Which of following is an illegal instruction LOOP instruction loops to the specified label untill END assembler directive used to DIV instruction A indirect addressing MOV AX,30000 DX=0 End program D C B adddressing addressing Indexed addressing AND BX,DX ADD AX,CX INC AL BX=0 AX=0 End segment Divide a signed word by byte or signed double word by word DAS Replaces the number in a destinatio n with the 9s complement of that number AX or CXAX register Copy data from a port to accumulato r Copy data from a port to accumulato r Divide an signed word by a byte or signed double word by a word CX=0 None of these Divide a signed word by word or signed double word by double word DAA None of these

End procedure Divide an Divide an unsigned word unsigned word by by byte or word or unsigned unsigned double word double word by word by double word AAM Replaces the number in a destination with the 2s complement of that number AAD Replaces the number in a destination with the 1s complement of that number AX or CX-AX register Copy data from accumulator to memory Copy data from accumulator to memory Divide an unsigned word by a word or unsigned double word by a double word Divide an unsigned word by a word or unsigned double word by a double word Define Quad word End Procedure

MC MC

2 2

1 1

B A

In 8086 microprocessor one of the following instructions is executed before an arithmetic operation NEG instruction

MC MC

2 2

1 1

A C

In MUL instruction the result is stored in IN Instruction

AX or DX-AX register Copy data from memory location to accumulator Copy data from memory location to accumulator Divide an unsigned word by a byte or unsigned double word by a word

None of these

MC

OUT Instruction

MC

DIV Instruction

MC

IDIV Instruction

Divide an unsigned word by a byte or unsigned double word by a word

MC MC

2 2

1 1

C A

DT assembler directive used to END assembler directive used to

Define Doubleword End Program

Copy data from accumulato r to a port Copy data from accumulato r to a port Divide an signed word by a word or signed double word by a double word Divide an Divide an signed signed word by a word by a word or byte or signed signed double double word by a word by a double word word Define Ten Define Ten words bytes None of End these Segment

43617 Qtyp Tpc Mrk Ans Qstn MC 2 1 C Which of the following instruction used to complement the contents of carry flag CMC instruction MC 2 1 B MC MC 2 2 1 1 A A A STC Complements accumulator B CTC C CMC D CLI Compares carry Four byte instructio n The compiled assembly code ADD AX, CX is an I/O instructio n stores the instructio n that is being currently executed.

MC MC

2 2

1 1

A A

MC

MC MC MC MC

2 2 2 2

1 1 1 1

A A D A

Complements Compares accumulato carry r Three byte Two byte One byte INC instruction instruction instructio instruction n A mnemonic The value The What is opcode in which an that instruction defines a that is to be operation data size acts upon executed AND BX, MOV AX,30000 INC AL Which of the following is an DX illegal instruction modifies causes a causes an An interrupt instruction unconditional conditional the status transfer of register transfer of control control stores the stores the stores the The program counter address of next address of instruction the next the instructio to be instruction n to be executed that is executed currently being executed perform access access The call instruction is used to I/O memory subprogram Direct indexed The instruction MOV AX, [BX] is an Register addressing addressing indirect example of addressing direct indexed Register The instruction MOV AX, [BX] [SI] addressing addressing indirect is an example of addressing in the on the stack in the The call instruction stores the program memory return address for a subprogram counter address register The instruction JE label is an example of The 8086 LOOP instruction decrements register ------- and test it for 0 to decide if jump occurs. The last executable instruction in procedure is --------MOV AX, [BX][SI] denotes which type of addressing mode of 8086? FSTENV instruction means indirect addressing AX indexed addressing BX

MC MC

2 2

1 1

D C

access the stack based indexed addressing based indexed addressing does not involve using the return address Direct Relative addressing addressing DX CX

MC MC MC

2 2 2

1 1 1

B C D

IRET Relative based indexed Store even number variables Offset REP ZF =0 DX=D652 H CF=1

RET Indexed

JUMP

CALL Register Relative Store even number segment c& d CF=0 DX=EB29H CF=1

MC MC MC MC

2 2 2 2

1 1 1 2

D C B C

The instruction MOV AX, DATA moves the ________address of DATA in AX. To repeat a string instructions while particular condition is zero use the instruction The conditional branch instruction JNS performs the operations when __ Consider CF=0 MOV CL, 02

Based Indexed Floating Store environment point store s number Base E.A. REPE SF=0 DX=D652 H CF=0 REPZ PF=0 DX=EB29H CF=0

43617 Qtyp Tpc Mrk Ans Qstn H MOV DX, ACA5H SAR DX, CL What is the result Consider CF=1, BL=00111000 RCR BL, 1 What is the result after execution of this instruction Given that (BX)=0158 H, (DI)=10A5 H, Displacement=1B57 H, and (DS)=2100 H, the effective address & physical address produced by register indirect addressing mode is (Assume register BX) If AL=09H, BL=08 H Instruction sequence MUL BL , AAM will store ----in AX. Consider MOV AL, 59(BCD) MOV BL, 35(BCD) ADD AL, BL DAA What are the contents of AL after execution of these instructions ? What is the output of the following codeAL= 00110100 BL= 00111000 ADD AL, BL AAA To look up particular item in 256 byte table use ________register as index and ______ register to point to the base of the table What is the output of the following code AL= -28 decimal, BL=59 decimal IMUL BL AX=? , MSB=? What is the output of the following code AL= 49 BCD, BH= 72 BCD SUB AL, BH DAS Consider CF=1,BL=00111000 RCR BL,1 What is the result after execution of this instruction The contents of different registers are given below. Form Effective addresses for addressing modes given below :Offset = 5000H [AX]- 1000H, [BX]- 2000H, [SI]3000H, [DI]- 4000H, [BP]- 5000H, [SP]- 6000H, [CS]- 0000H, [DS]1000H, [SS]- 2000H, [IP]- 7000H A B C D

MC MC

2 2

2 2

D B

CF=1, BL=10011100 EA=1B57 H Physical Address= 22B57 0072 AL=8E H

CF=0, CF=1, BL=00011100 BL=0001110 0 EA=1CAFH EA=0158 H Physical Physical Address= Address= 22CAF 21158 0702 AL=94 BCD 0207 AL=9E H

CF=0, BL=1001110 0 None of these

MC MC

2 2

2 2

B B

48 None of these

MC

AL = 6CH

12

12H

C6H

MC

SI, BX

AL, DX

AL, BX

CL, DX

MC

AX= F98CH, MSB=1

AX= 1652, MSB=1

BX F9C8H, MSB=1

BX= 1652, MSB=1

MC

AL=D7, CF=1.

AL=7D, CF=1.

AL=77, CF=1

None

MC MC

2 2

2 2

D B

CF=1,BL=10011 CF=1,BL=000 CF=0,BL=00 CF=0,BL=10 011100 011100 11100 100 20000H 1A000H 1A00H None

MC

MC MC

2 2

2 2

C B

MOV AX, 5000H [BX] [SI] Clear BL Given that the BL register contains 1111 0000, the effect of the following instruction OR BL, 0000 1111 is to AX=1100 H Given that AX=3F0F H and the instruction XOR AX, 0098 H executed. What is the result What is the output of the following 0101110011010

Store 1111 1111 in BL

Store 0000 Leave BL 1111 in BL unchanged

AX=3F96 H

AX=3F97 H

Ax=2E97 H

11010011010 0110100010 1011100110

43617 Qtyp Tpc Mrk Ans Qstn code BX=23763 CL=8 ROL BX, CL MC 2 2 A Given that (BX)=0158 H ,(DI)=10A5 H , Displacement=1B57 H , and (DS)=2100 H, the effective address & physical address produced by direct addressing mode is MC The call instruction is used to 3 1 A MC MC MC 3 3 3 1 1 1 A B A A 011, CF=0 EA=1B57 H Physical Address= 22B57 C B 11100, CF=0 011101, CF=1 EA=0158 H Physical Address= 21158 EA=1CAFH Physical Address= 22CAF perform I/O clear it D 001100, CF=1 None of these

MC

MC MC

3 3

1 1

D A

access access memory subprograms leave it with add 4 to it its original value mov bh, To copy the hexadecimal number A to mov 0bh, ah 0ah the bh register you write read a read a The effect of the following character character instructions into dl into ah mov ah, 2h int 21h is to read a read a The effect of the following character character instructions into dl into al mov ah, 1h int 21h is to push ax ret 2 Which of the following is an illegal 8086 instruction belongs to belongs to The read/write line is the data bus the control bus The call instruction stores the return address for a subprogram on the stack in the memory address register indexed addressing mov ah, 2h Int 16h mov ah, 2h int 21h mov ah, 2h

access the stack double it

mov bh, ah mov bh, [ah] display display the the character character in dl in al display display the the character character in dl in ah mov x, ay aDd bx, 25000 belongs to CPU bus the address bus does not in the involve program using the counter return address immediate relative addressing addressing mov ah, 2h mov ah, 0h Int Int 21h 20h mov ah, 2h mov ah, 1h

MC

MC MC MC MC

3 3 3 3

1 1 1 1

A A C C

The instruction je label is an example of Given that dl contains 'x' which of the following will cause 'x' to be displayed: Which of the following will read a character into al:

indirect addressing mov ah, 1h Int 21h mov ah, 9h

int 20h Which of the following will display mov ah, 0h Int a string whose address is in the dx 21h register: The cmp instruction modifies the Conditional instructions typically inspect the The bp register is typically used for accessing The ret instruction modifies the The sp register is typically used for accessing The call instruction modifies An instruction consists of program counter program counter strings instruction register strings the flags register

MC MC MC MC MC MC MC MC

3 3 3 3 3 3 3 3

1 1 1 1 1 1 1 1

C C B B C B C A

Data and Address Macro expanded into machine code it Assembled represents when it is,

int 21h int 21h mov ah, 9h mov ah, 9h Int Int 22h Int 20h 21h segment instruction flags register register register accumulato instruction flags r register register data stack memory segment flags address program register register counter data stack memory segment none of bp program the register counter previous Opcode and Input and Register Output and Memory Operand executed Loaded Linked

43617 Qtyp Tpc Mrk Ans Qstn MC 3 1 A An assembly language program is typically A non-portable B shorter than an equivalent HLL program are portable D slower to execute than a compiled HLL program are easier Allows the programmer to write to access than the machine registers code or programs instructio ns that are not usually provided by a HLL a linker an interprete r to give used to commands start a to an program assembler .lnk .exe C harder to read than a machine code program 40H in al 0100 0001 in al a linker

MC

Programs are written in assembly language because they

runs faster than HLL

MC MC

3 3

1 1

A D

An assembly language program is translated to machine code by An assembly language directive is

an assembler the same as an instruction .lis

a compiler used to define space for variables .obj

MC MC MC MC MC MC MC MC MC

3 3 3 3 3 3 3 3 3

1 1 1 1 1 1 1 1 2

D D A D B D C B B

The output of the linker (LINK command) is stored in a file with the extension The result of mov al, 65 is to store Assembly language program is translated to machine code by

0100 0010 in 42H in al al An assembler a compiler 42h in al mov bh,0ah push ax mov ah,02h int 20h program counter INC AL

MC

The result of MOV AL,65 is to store 01000010 i n al To copy hexadecimal number A to BH mov 0bh,ah register you write ret 2 Which of the following is an illegal 8086 instruction Which of the following will display mov ah,0ah int 21h a string whose address is in DX register instruction The RET instruction modifies the register Instructions INC AL and ADD AL,01H ADD AL,01 incrtements AL register by 1. From point of view of execution time, which instruction is preferable. The near jump is ________ while far intersegment, jump is________ intrasegment In case of 8086, near jump modifies the program address by changing which register or registers In case of 8086, Far jump modifies the program address by changing which register or registers In JMP AX instruction, AX holds ----- address and is ----- type of the jump. Which conditional jump instructions test both the Z and C flag bits. The near jump is -----------IP IP offset, FAR JG & JBE

an interprete r 40h in al 01000001 in al mov bh,ah mov bh,[ah] mov x,ay aDd bx,25000 mov ah,9h mov ah,9h int int 22h 21h flag address register register

MC MC MC MC MC

3 3 3 3 3

2 2 2 2 2

A B B B D

intersegmen t, intersegmen t CS &IP CS &IP offset, NEAR JA & JBE

intrasegme nt, intrasegme nt CS CS segment, NEAR JC & JBE

intrasegme nt, intersegme nt CS or IP CS or IP segment, FAR JC & JA

intersegment, intersegmen intrasegme intrasegme

43617 A Qtyp Tpc Mrk Ans Qstn while far jump is ----------------- intrasegment . MC MC 3 3 2 2 B C What is the output of the following code AL=88 BCD, CL=49 BCD ADD AL, CL DAA What is the output of the following code? AL= 49 BCD, BH= 72 BCD SUB AL, BH DAS What is the output of the following code? AL= -28 decimal, BL=59 decimal IMUL BL AX=? , MSB=? What is the output of the following code AL= 00110100 BL= 00111000 ADD AL, BL AAA What is the output of the following code? AL=00110101 BL= 39H SUB AL, BL AAS What is the output of the following code? CF =0, BH = 179 RCL BH, 1 What is the output of the following code? SI=10010011 10101101, CF=0 SHR SI, 1 What is the output of the following code? BX=23763 CL=8 ROL BX, CL What is the output of the following code? AX = 37D7H, BH = 151 decimal DIV BH In case of 8086, the LOOP instruction decrements -----register and jumps to the label when register is ------ 0. What is meant by Maskable interrupts? D7, CF=1 AL=D7, CF=1. B t, intersegmen t 37, CF=1 AL=7D, CF=1. C nt, intrasegme nt 73, CF=1 AL=77, CF=1 D nt, intersegme nt 7D, CF=1 none of them

MC

AX= F98CH, MSB=1.

) AX= 1652, BX F9C8H, MSB=1. MSB=1

BX= 1652, MSB=1

MC

AL = 6CH

12H

12

C6H

MC

AL= 00000100, BL=00000100 AL=1111110 ) BL= 00000100, 0 CF=1 , CF=0 CF=1 CF=1

MC

CF=0, OF= 1, BH= 01100101 37805, CF=1, OF=1

CF=1, OF=1, CF=1, OF BH=01100110 =0, BH= 01001101 18902, CF=1, OF=1

MC

CF=0, OF=0, BH=0010110 0 53708, 19820, CF=1, OF=1 CF=1, OF=1

MC

0101110011010 11010011010 0110100010 1011100110 001100, 11100, CF=0 011101, 011, CF=0 CF=1 CF=1 AL = 65H, AH= AL= 5EH, AH= 101 94 decimal decimal DX, not equal CX, equal to to An interrupt that can be turned off by the programmer Int21 An interrupt that cannot be turned off by the programmer. Int21H AH= E5H, AL= 5EH CX, not equal to An interrupt that can be turned off by the system. Int42H AL= 56H, AH= 5EH DX, equal to An interrupt that cannot be turned off by the system. none of these DX Exit to DOS 8

MC

MC

MC

MC

MC MC MC

4 4 4

1 1 1

B D A

to transfer control to the address stored I double word beginning at address 0084 H the software interrupt _________ must be used. Which base register addresses data in stack? What does the INT21H instruction accomplish if AH contains 4CH? The Push & POP instruction always transfer ________ bits between

BX Read a character 16

SP Display a character 24

BP Print a character 32

43617 Qtyp Tpc Mrk Ans Qstn stack & register or memory In RST interrupts, RST stands for MC 4 1 B MC 4 1 A What is meant by Maskable interrupts? A B C D

Repeat Start Test An interrupt that can be turned off by the programmer.

Restart An interrupt that cannot be turned off by the programmer.

Start An interrupt that can be turned off by the system. An interrupt that cannot be turned off by the system. subroutine it is executing RST 5.5

MC

MC MC

4 4

1 1

A A

When an interrupt occurs, the processor completes the current ___________ before jumping to the interrupt service subroutine In case of 8086, out of given options which interrupt requires acknowledgement An interrupt instruction

microinstruct instruction macro it is it is ion it is executing executing executing INTR causes an unconditional transfer of control Hardware interrupts NMI causes a conditional transfer of control Software interrupts RTS 7.5

is an I/O modifies the status instructio n register none of the above

MC

MC

MC

MC MC MC

4 4 4

1 1 1

A C B

MC

MC

MC MC

4 4

1 1

B D

Hardware interrupts and Software interrupts Modifies Causes an Causes an An interrupt instruction unconditional conditional the Status transfer of register transfer of control control Execute an Executes a The NMI interrupts mechanism of the Execute an instruction NOP instruction 8086 microprocessor from memory supplied by location an external 20h device through the INTA signal RST 6.5 RST 6 NMI Which interrupt have the highest priority? Hardware & software Hardware Interrupts are classified as software interrupts Interrupts nterrupts Microinstruct instruction Macro it When an Interrupt occurs the is it is processor completes the current --- ion it is executing executing -- before jumping to the interrupt executing service routine microinstruct instruction macro it When an interrupt occurs, the is it is ion it is processor completes the current executing executing executing ___________ before jumping to the interrupt service subroutine Decrement What is the output of the following Decrement SP Increment SP by 2 & by 2 & push a SP by 2 & code word to stack push a word push a AL to stack to stack none of NonWhich interrupts are generally used Maskable the above Maskable interrupts for critical events such as Power interrupts failure, Emergency, Shut off etc.? execute an executes a The NMI interrupts mechanism of the execute an instruction NOP instruction 8086 microprocessor from memory supplied by location an external 20H device through the Interrupts are classified as

Is an I/O instructio n None of the above

INTR None of the above Subroutine it is executing subroutine it is executing Illegal

none of the above

43617 Qtyp Tpc Mrk Ans Qstn MC MC MC MC 4 4 4 4 1 1 1 1 C B A A DMA stands for In RST interrupts, RST stands for Which interrupt has the highest priority? An assembly language instruction B A INTA signal Direct Memory Distinct Memory Allocation Allocation Repeat Start Restart Test RST 6 NMI always takes at least one operand causes a causes an unconditional conditional transfer of transfer of control control are run faster portable than Highlevel language always has a label C Direct Memory Access Start RST 6.5 always has an operation field modifies the status register easier to write than machine code programs D Distinct Memory Access INTR always modifies the status register is an I/O instructio n

MC

An interrupt instruction

MC

Programs are written in assembly language because they

MC

Interrupts are classified as

Hardware interrupts

Software interrupts

MC MC MC MC MC

4 4 4 4 4

2 2 2 2 2

C B A C B

MC MC MC MC MC MC

4 4 4 5 5 5

2 2 2 1 1 1

A C D B C C

The Interrupt vector table in 8086 is stored sequentially from-----to ------ h. NMI interrupt is of ------ type while INT instruction is ---------- type of interrupt. Divide by zero interrupt is of ----- type while single step interrupt is of ----------- type The interrupt vector table in 8086 is stored sequentially from -----to ------ H 8086 supports ------ number of interrupts and ------- locations are reserved for interrupt vector table. INTR interrupt is --------interrupt and has -------- types. PUSH operation --------- the SP by ----------- bytes. Registers --- and ----- are used for accessing stack elements 80286 having physical memory Operating system extensions are having ------- privilage level. In 80286, the size of segment descriptor cache register assigned to each of the segment is -----byte.

0000,0000 to 0000,003F 1,2 0,1 0000:0000 to 0000:003F 128, 1024

0000,0000 to 0000,033F 2,3 1,2 0000:0000 to 0000:033F 255, 1024

they allow the programmer access to registers or instructio ns that are not usually provided by a Highlevel none of Hardware interrupts the above and Software interrupts 0000,0000 None of the above to 0000,03FF 1,4 3,4 0,2 0000:0000 to 0000:03FF 255, 255 0,3 None of the option 64, 64

Maskable, 255 Maskable, 64 increment, 1 CS,SS 1MByte 0 4 increment, 2 CS,IP 16 M Byte 1 5

NonMaskable, 64 decrement, 2 SS,IP 24M Byte 2 6

NonMaskable, 255 decrement, 1 SS,SP 32 M Byte 3 8

43617 A Qtyp Tpc Mrk Ans Qstn 1 MC 5 1 B The 80286 supports -------- types of descriptor tables. After reset, 80286 starts execution real MC 5 1 A in --------- adress mode. MC MC MC MC MC MC MC MC MC MC MC MC MC MC MC MC MC MC MC MC MC MC MC MC MC MC MC MC 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 B D C D A D C B A B C A B A B A B B A A D D A B D D C A The flag useful to switch the 80286 from real mode to protected mode is 80286 processor consists of following modes. Application services are having ------ privilage level. Base address of Segment in PVAM mode of 80286 is If TI=0 The descriptor table selected is In 80286 the size of segment register is of After reset the first instruction feched by 80286 is from address Physical memory of 80286 in PVAM mode Stack registers of 80287 is of In 80386 processor the size of all general purpose register is of In protected addressing modeof 80386 the size of all segment reguster is of Base address of segment in PVAM mode of 80286 is How many Global Descriptors can be stored in GDT. Operating system routines are having ------ privilege level The flag useful to switch the 80286 from real mode to protected mode is In 80286 the size of segment descriptor cache register assigned to each of te segment is ----- byte In real mode 80386 address upto physical memory How many Global Descriptors can be stored in GDT Operating system routines are having ------- privilage level. System sevices routines are having ------- privilage level. In real mode 80386 address up to physical memory. In 80286 CPU, the address bus is of ------ bit and can address -----MB of memory. In 80286, size of base and limit field in segment descriptor is In real address mode of 80286, memory address range reserved for system initialization is In real address mode of 80286, memory address range reserved for interupt vector table is The MSW od 80286 consist of following flags. The MSW od 80286 consist of following flags. 80286 consist of ----- segment VM Real mode 0 20 bit GDT 32 bit FFFFFF 64 KB 7 bytes 32 bits 32 bits 20 bit 4K 0 VM 4 1Mb 4K 0 0 1 MB 24, 32 16 bits & 32 bits FFFF0H to FFFFFH 00000H to 003FFH P,C AC,C 4,16 B 2 protected PE protected mode 1 32 bit LDT 16 bit 0FFFFF 4 GB 4 bytes 16 bits 24 bits 32 bit 8K 1 PE 5 4Mb 8K 1 1 4MB 24,16 16 bits & 24 bits 00000H to 003FFH 00100H to 003FFH P,EM AC,PE 8,16 C 3 virtual address CY Virtual 2 24 bit GDT& LDT 24 bit F00000 16 MB 6 bytes 24 bits 20 bits 24 bit 64K 2 CY 6 1Gb 64K 2 2 1GB 32,32 D 4 none of the a,b & c. OE real & protected 3 16 bit NONE OF a,b &c 8 bit FFFFF0 1GB 8 bytes 20 bits 16 bits 16 bit 1M 3 OE 8 16Mb 1M 3 3 16MB 32,16

24 bits & 16 bits & 16 bits 24 bits FFF00H to FFFF0H to FFFFFH FFFFFH 01000H to 00000H to 002FFH 003FFH P,TS AC,MP 6,16 PE,MP PE,MP 8,32

43617 Qtyp Tpc Mrk Ans Qstn registers and size of each register is ----- bit. 80286 consist of ----- general MC 5 2 B purpose registers and size of each register is ----- bit. 80286 consists of ----- general MC 5 2 D purpose registers & size of each register is ----- bit In 80386 maximum size of each page MC 6 1 C can be The 80386 enters into virtual 8086 MC 6 1 C mode when ______ flag is set Which register in 80386 is used as MC 6 1 D page directory physical base address register The on chip cache in 80486 is used MC 6 1 C to store 80386 support MC 6 1 C overall_____addressing modes to facililtate efficient execution of higher level language programs he 80386 enters into virtual 8086 MC 6 1 C mode when ------- flag is set In 80386, GDTR and IDTR are called MC 6 1 B as -------------- registers In 80386, LDTR and TR are called as MC 6 1 C -------------- registers The 80386 utilizes the ----------MC 6 1 B types of descriptor tables. The 80386 supports -------- types MC 6 1 B of descriptors. Which register in 80386 is used as MC 6 1 D page directory physical base address register. Physical memory of 80386 in PVAM MC 6 1 B mode is Size of Cache memory in 80486 is MC 6 1 C of size of instruction queue in 80486 MC 6 1 A is The pins used in bank selection of MC 6 1 D 80486 are The 80486 can handle --------MC 6 1 B number of hardware interrupts. After reset, 80486 starts execution MC 6 1 A in --------- adress mode. The on-chip cache in 80486 is used MC 6 1 C to store 80386 having Instruction queue of MC 6 1 D size 80386 addresses ______ bytes of MC 6 1 B Virtual Memory through its Memory Management unit The Cache inside 80486 is -----MC 6 1 A Kbytes Segmentation unit allows segments MC 6 1 B of _____ size at maximum. The ___ bit decides whether it is a MC 6 1 B system descriptor or code/data segment descriptor 80386 support overall ___ MC 6 1 C addressing modes to facilitate efficient execution of higher level language programs. A B C D

4,16 4,16 1 KB Carry cr0 code 9

8,16 8,16 2KB Trap cr1 data 10

6,16 6,16 4KB Virtual cr2 code & data 11

8,32 8,32 8KB Overflow cr3 code or data 12

Carry address address 2 4 CR0 1 GB 4K 32 bytes DP0 to DP3 128 Real Code 6 Byte 64 GB 8 4Gbytes P 9

trap system address system address 3 5 CR1 4 GB 16K 16 bytes BREQ 256 Protected data 4 Byte 64 16 6Mbytes S 10 TB

virtual system system segment 4 6 CR2 16 KB 8K 6 bytes BRDY 16K Virtual Code and data 32 Byte 4 GB 32 4Mbytes D 11

overflow segment segment 5 8 CR3 2 GB 10K 4 bytes BE0 to BE3 512 Virtual 8086 code or data 16 Byte 16 GB 64 6Gbytes G 12

43617 Qtyp Tpc Mrk Ans Qstn In 80386, the maximum size of 1 C 6 MC segment can be In 80386, the maximum size of each 1 C 6 MC page can be In 80486 the pin is used to clear 2 C 6 MC the content of cache is The 80386 CPU can support -------2 C 6 MC number of segmnets and each segment size is -----The 80386 have ------ control 2 B 6 MC registers and size of each register is ------- bits. The 80386 consist of ---------2 D 6 MC debug registers and ---------- test registers. The 80386 descrptors have a -----2 B 6 MC bit segment limit and -------- bit segment address. In 80486 the pin used to clear the 2 C 6 MC content of cache is Error of FPU unit in 80486 is 2 B 6 MC indicated by ----- pin. The first processor to include 2 B 6 MC Virtual memory in the Intel microprocessor family was: To access any segment in 80386 2 C 6 MC privlage rule is If ______input pin of 80386 is 2 B 6 MC activated, it allows address pipelining during 80386 bus cycles. Virtual Mode Flag bit can be set 2 C 6 MC using ____ instruction or any task switch operation only in the _____ mode The interrupt vector table of 80386 2 A 6 MC has been allocated ______ space starting from _______ to _______. _____is used to control the cache 2 A 6 MC with two new control bits not present in the 80386 Microprocessor. What are the bits used to control the 8K byte cache? To prevent another master from 2 A 6 MC taking over the bus during a critical operation, the 486 can assert its _____signal. The execution unit of 80386 consist 2 D MC 6 of ----- general purpose and -----special purpose registers. With ----- bit address bus, 80386 6 2 A MC can address upto -------- of the physical memory. The size of flag register in 80386 2 D 6 MC is ----- bit and reseved bits in flag register are always set to The number stages in FPU pipeline 1 B MC 7 of pentium are The memory data bus width is -----7 1 B MC ---in Pentium In pentium, Compare instructions 1 A 7 MC are executed by In pentium, Square root 1 C 7 MC A 1GB 1KB KEN 12K, 4GB 4,32 8,3 32,32 KEN KEN 8086 CPL=DPL BS16 B 2GB 2KB FERR 16K, 2GB 3,32 8,4 20,32 FERR FERR 80286 CPL<=DPL NA C 4GB 4KB FLUSH 16K, 4GB 2,32 4,4 24,32 FLUSH PCD 80386 CPL=>DPL PEREQ IRET, protected 3Kbyte, 01000H, 007FFH CR0, PWT, PCD D 8GB 8KB FADS 16K,8GB 2,16 8,2 24,16 FADS AHOLD 80486 none ADS POPF, protected 4Kbyte, 01000H, 009FFH none

IRET, Virtual POPF, Real

1Kbyte, 00000H, 003FFH CR0, CD, NW

2Kbyte, 10000H, 004FFH CR0, NW, PWT

LOCK# or PLOCK# 8,6. 32,4GB 16,0 4 32 b FADD FADD

HOLD or BOFF 6,8. 32,2GB 32,0 8 64b FAND FAND

HLDA

HOLD

6,6. 32,4MB 16,1 5 128b FDD FDD

8,8. 32,32MB 32,1 6 256b FEXP FEXP

43617 A Qtyp Tpc Mrk Ans Qstn instructions are executed by 2D imaging MC 7 1 D MMX architecture is most sutaible for MC 7 1 B The sizes of level 2 cache in P-III 256 KB processor is 450 MHz MC 7 1 D The operating frequency of P-III processor is MC MC MC MC 7 7 7 7 1 1 1 1 C A B D The speed of pentium-pro processor is ------ times that of pentium. RAT translates ------ register reference to -------- register. Multiple instructions are issued for execution at run time by The performnace of pentium is improved because of it's The use of BTB improves the performance of the pentium by FYL2X calculates SIMD type architecture perform ------ operation on ------ data In pentium, number of registers available for MMX programmer are Instruction EMMS implies The performance of Pentium is improved because of its The number stages in FPU pipeline of Pentium are SIMD type architecture perform_____ operation on_______ Pentium Pro rocessor uses _____stages pipeline MMX architecture is most suitable for Pentium-pro processor uses ----stages pipeline. Pentium-Pro implements speculative instruction execution by looking ahead for Pentium-pro processor uses dual independent bus for simultaneous access of The sizes of code cache and data cache in pentium processor are The number of entries that BTB in Pentium can hold is FPATAN calculates -------- of X where X is -------For multimedia application, X-86 CPU can manipulate ----- pixels at a time while MMX architecture allows manipulation of ------pixels at a time. The number of integer pipelines in pentium processor are ------- and same Logical, physical VLIW architcture superscalar architecture 25% Y*log2X different, single 2 Load MMX stack superscalar architecture 4 B 3D imaging 512 KB 500 MHz C D

2D and 3D Speech processing imaging 64 KB 128 KB 550 MHz All options are applicable 2.5

1.5 physical, logical superscalar architectur e massive pipelining 28% Y*log2(X+1) same, multiple 4 Empty MMX stack Massive pipelining 8

logical,lo physical,p hysical gical

on-chip FLU 23% arctan(X) same, single 6

MC MC MC MC MC MC

7 7 7 7 7 7

1 1 1 1 1 1

A A B D B D

All options are applicable 45% 2x-1 different, multiple 8

MC MC MC MC MC MC MC MC MC MC

7 7 7 7 7 7 7 7 7 7

1 1 1 1 1 1 2 2 2 2

B B C D C D C D B C

Empty MMX Load MMX register register onchip FLU All options are aaplicable 6 5 Same, single 12 different, multiple 16

Different,Sin Same, multiple gle 10 8 2D imaging 8 10-20 instructions main memory, virtual memory 8K,4K 128 tan, angle 3D imaging 10 15-25 instruction s main memory, RAM 8K,16K 256 arctan, angle 4,8

2D & 3D Speech processing imaging 16 12 25-35 instructio ns main memory, CACHE 4K,4K 512 arctan, floatingpoint number 4,4 20-30 instructio ns No any option is applicable 8K,8K 64 tan, floatingpoint number 1,8

MC

2,8

MC

2,4

1,4

2,3

2,2

43617 Qtyp Tpc Mrk Ans Qstn each pipeline has ------- stages. MC 7 2 B The number of entries that BTB in pentium can hold is In pentium, which of the following MC 7 2 D floating point exception can be detected even before actual floating point calculation Execution trace cache of Pentium4 MC 8 1 A can store upto______ decoded micro operation RAT (Register Alias table) is part MC 8 1 D of processor On chip multiprocessing switches MC 8 1 B the ----------- processsors between different process threads Time slice multithreading switches MC 8 1 A the ----------- processsors between different process threads IA-32 architecture's paging MC 8 1 C mechanism includes extention PSE to address physical address space greater than --------- bytes. IA-32 architecture's paging MC 8 1 B mechanism includes extention PAE to address physical address space greater than --------- bytes. The function of Instruction MC 8 1 B Scheduling in P4 is to schedule different ----------- to an appropriate execution engine. The P4 BHT can hold maximum ------MC 8 1 B -- entries. The P4 has a minimum loss of ---MC 8 1 C clock cycles if branch prediction is not correct. The Micro-Code ROM in Pentium-4 MC 8 1 A consist of --------A 128 Divide by zero 12000 Pentium-I single single 4K B 256 Denormal operand 10000 Pentium-II two two 4G C 512 Invalid operation 256 PentiumIII three three 4M D 64 All options are applicable 512 Pentium-IV four four 4

4K

4G

4M

Instructions

microoperations 4000 18 Microopeartions of simple instruction Level-2 code

data

tasks

2000 20 Microopeartions of complex instruction

8000 19

1000 10

MC MC

8 8

1 1

B D

Level-1 In case Trace cache miss, the instructions are fetched from -------- cache in Pentium-4. instruction The Trace Cache in Pentium-4 does not store ----The role of______is to decode instruction & translate it into microoperation Pentium4 processor is designed with______ architecture Pentium pro processor is designed with ------- architecture Pentium-4 processor is designed with ------- architecture Clock speed of Pentium-4 varies from The pipeline depth in Pentium-4 processor extends upto -----stages Execution trace cache of Pentium-4 can store upto ----- decoded microIA 32 instruction decoder MII MII MII 1.3 GHz to 1.6 GHz 4 12000

Data Microopeartions of instructio n Level-4 Level-3 Data

MC

MC MC MC MC MC MC

8 8 8 8 8 8

1 1 1 1 1 1

D C D B C A

All options are applicable Trace cache Micro code All options ROM are applicable NET burst P6MICRO VLIW VLIW VLIW 1.4 GHz to 1.7 GHz 15 10000 P6 micro P6 micro Net Burst Net Burst

1.1 GHz to 1.5 GHz to 1.6 GHz 1.6 GHz 8 20 256 512

43617 Qtyp Tpc Mrk Ans Qstn ops. MC 8 1 B Basic integer instructions such as Add, subtract etc. are get executed on Pentium-4 in ------ clock cycles. The role of ------- is to decode MC 8 1 A the instruction and translate it to micro-operations. MC 8 1 D In case of Pentium-4, the instruction is called as complex if it is required to be translated into more than --------- microoperations. Static prediction scheme works well in P4 for ------- branches but its performance is get degraded for ---- branches. SSF2 instructions can perform ------- bit SIMD integer arithmetic and -------- bit SIMD double-precision floating-point operations. P4 connsist of ----- ALUs, -------AGUs and they operate at --------times faster than processor. Pentium-4 consists of L1 data cache of size ------ KB and L2-cache of size ------- KB. Hyperthreading executes multiple threads on --------- processors ----------- switching. Pentium4 consistes of L1 data cache of size______ KB & L2 cache of size______ KB The function of Trace cache in Pentium-4 is to store ---- and it can store maximum --------Each logical processor in P4 can use upto maximum of ----------- reorder buffer entries, -------buffers and ------ store buffer entries. P4 supports ------ number of logical processors and each logical processor has its own set of two ------- byte streaming buffers. Multiple number of threads ---------the performance and ----------time in context switching. The cache integrated in the chip is called as ----- level cache while cache external to chip is called as ----- level cache The register rename logic in P4 allows -------- general use IA-32 registers to be dynamically expanded to use the available -------- physical registers. MII microprocessor are capable of issueing multiple instructions per single processor cycle Context of the process reflects all A 1 B 0.5 C 1.5 D 2

IA-32 Instruction Decoder 6

Trace Cache Micro-Code All ROM options are applicable 4 5 7

MC

Forward, Backward 80,16

Backward, Forward. 128,128 64,64 64,128

MC

MC MC MC MC MC

8 8 8 8 8

2 2 2 2 2

B B A B A

1,1,2 128,256 single, without 128,256

2,2,2 8,256 single, with 8,256

2,2,3 256,256

1,2,2 512,256

two,withou two, with t 256,256 512,256 Microoperation, 11 K microoperations 10,20,30

Instruction MicroMicrooperation, operation, 12 , 12 Instruction 1 K microK microoperations operations 24,12,63 63,24,12 12,24,63

MC

MC

4,128

2,128

2,64

2,32

MC MC

8 8

2 2

A A

Increases, Increases L1,L2

Increases, Decreases L2,L3

Decreases, Decreases, Increases Decreases L1,L3 L1,L4

MC

4,128

4,64

8,128

8,64

TF TF

7 8

1 1

A A

TRUE TRUE

FALSE FALSE

43617 Qtyp Tpc Mrk Ans Qstn the information that describes the current state of the process completely. TF 8 1 B The scheduler selects the microopeartions based on wheather they belong to one logical processor or the other. TF The scheduler selects the micro8 1 A opeartions based on dependent inputs and availability of execution resources.. 8088 microprocessor accepts the YN 1 1 A program written for 8086 without any changes? A B C D

TRUE

FALSE

TRUE

FALSE

Yes

No