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CPE 408340 Computer Organization Chapter 2: Instructions: Language of the Computer

Saed R. Abed
[Computer Engineering Department, Hashemite University] [Adapted from Otmane Ait Mohamed Slides & Computer Organization and Design, Patterson & Hennessy, 2005, UCB] 1

(vonNeumann) Processor Organization

Control needs to
1. 2.

CPU Control Datapath

Memory

Devices Input Output

input instructions from Memory issue signals to control the information flow between the Datapath components and to control what operations they perform control instruction sequencing

Fetch

3.

Datapath needs to have the

Exec

Decode

components the functional units and storage (e.g., register file) needed to execute instructions interconnects - components connected so that the instructions can be accomplished and so that data can be loaded from and stored to Memory
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For a given level of function, however, that system is best in which one can specify things with the most simplicity and straightforwardness. Simplicity and straightforwardness proceed from conceptual integrity. Ease of use, then, dictates unity of design, conceptual integrity.

The Mythical Man-Month, Brooks, pg 44

RISC - Reduced Instruction Set Computer

RISC philosophy

fixed instruction lengths load-store instruction sets limited addressing modes limited operations

MIPS, Sun SPARC, HP PA-RISC, IBM PowerPC, Intel (Compaq) Alpha, Instruction sets are measured by how well compilers use them as opposed to how well assembly language programmers use them

Design goals: simplicity, speed, cost (design, fabrication, test, packaging), size, power consumption, reliability, memory space (embedded systems)
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MIPS R3000 Instruction Set Architecture (ISA)

Instruction Categories

Registers R0 - R31

Computational Load/Store Jump and Branch Floating Point


coprocessor

Memory Management Special

PC HI LO

3 Instruction Formats: all 32 bits wide OP OP OP rs rs rt rt rd sa funct R format I format J format 5

immediate

jump target

Review: Unsigned Binary Representation


Hex
0x00000000 0x00000001 0x00000002 0x00000003 0x00000004 0x00000005 0x00000006 0x00000007 0x00000008 0x00000009 0xFFFFFFFC 0xFFFFFFFD 0xFFFFFFFE 0xFFFFFFFF

Binary
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 11100 11101 11110 11111

Decimal
0 1 2 3 4 5 6 7 8 9 232 - 4 232 - 3 232 - 2 232 - 1
231 230 229 31 30 29 ... ... 23 22 21 3 2 1 20 0 bit weight bit position

1 1 1

...

1 1 1 1

bit

1 0 0 0

...

0 0 0 0

232 - 1

Aside: Beyond Numbers

American Std Code for Info Interchange (ASCII): 8-bit bytes representing characters
Char ASCII Char ASCII Char ASCII Char ASCII Char ASCII Char

ASCII

0 1 2 3 4 5 6 7 8 9 10 11 12 15

Null

32 33 34 35

space ! # $ % & ( ) * + , /

48 49 50 51 52 53 54 55 56 57 58 59 60 63

0 1 2 3 4 5 6 7 8 9 : ; < ?

64 65 66 67 68 69 70 71 72 73 74 75 76 79

@ A B C D E F G H I J K L O

96 97 98 99 100 101 102 103 104 105 106 107 108 111

` a b c d e f g h i j k l o

112 113 114 115 116 117 118 119 120 121 122 123 124 127

p q r s t u v w x y z { | DEL

EOT ACK bksp tab LF FF

36 37 38 39 40 41 42 43 44 47

MIPS Arithmetic Instructions

MIPS assembly language arithmetic statement add sub $t0, $s1, $s2 $t0, $s1, $s2

Each arithmetic instruction performs only one operation Each arithmetic instruction fits in 32 bits and specifies exactly three operands
destination source1 op source2

Operand order is fixed (destination first) Those operands are all contained in the datapaths register file ($t0,$s1,$s2) indicated by $
9

Design Principles

Simplicity favors regularity

Of course this complicates some things... C code: MIPS code: a = b + c + d; add a, b, c add a, a, d

Smaller is faster. Why?


Arithmetic instructions operands must be registers, only 32 registers provided Compiler associates variables with registers What about programs with lots of variables?

10

Naming Conventions for Registers


0 1 2 3 4 5 6 7 8 ... 15 $t7 $zero constant 0 (Hdware) $at reserved for assembler $v0 expression evaluation & $v1 function results $a0 arguments $a1 $a2 $a3 $t0 temporary: caller saves (callee can clobber) 16 $s0 callee saves ... 23 $s7 24 $t8 temporary (contd) 25 $t9 26 $k0 reserved for OS kernel 27 $k1 28 $gp pointer to global area 29 $sp stack pointer 30 $fp frame pointer 31 $ra return address (Hdware) (caller can clobber)

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Aside: MIPS Register Convention


Register Number $zero 0 $at 1 $v0 - $v1 2-3 $a0 - $a3 4-7 $t0 - $t7 8-15 $s0 - $s7 16-23 $t8 - $t9 24-25 $gp 28 $sp 29 $fp 30 $ra 31 Name Preserve on call? constant 0 (hardware) n.a. reserved for assembler n.a. returned values no arguments yes temporaries no saved values yes temporaries no global pointer yes stack pointer yes frame pointer yes return addr (hardware) yes
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Usage

MIPS Reference Data Sheet

13

MIPS Reference Data Sheet

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MIPS Register File

Holds thirty-two 32-bit registers


Register File
32 bits 5 5 5 32 32 locations 32 src2 32 src1

Two read ports and One write port

src1 addr src2 addr dst addr write data

data

Registers are

Faster than main memory

data

- But register files with more locations write control are slower (e.g., a 64 word file could be as much as 50% slower than a 32 word file) - Read/write port increase impacts speed quadratically

Easier for a compiler to use


- e.g., (A*B) (C*D) (E*F) can do multiplies in any order vs. stack

Can hold variables so that


- code density improves (since register are named with fewer bits than a memory location) 15

Machine Language - Add Instruction

Instructions, like registers and words of data, are 32 bits long Arithmetic Instruction Format (R format): add $t0, $s1, $s2
op rs rt rd shamt funct

op rs rt rd funct

6-bits 5-bits 5-bits 5-bits 6-bits

opcode that specifies the operation register file address of the first source operand register file address of the second source operand register file address of the results destination shift amount (for shift instructions) function code augmenting the opcode
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shamt 5-bits

Processor Memory Interconnections


Memory is a large, single-dimensional array An address acts as the index into the memory array
Memory read addr/ write addr Processor read data write data
10 101 1

? locations

32 bits

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Processor Memory Interconnections


Memory is a large, single-dimensional array An address acts as the index into the memory array
The word address of the data

Memory read addr/ 32 write addr Processor read data 32


32write data 10 101 1 8 4 0

? locations 232 Bytes (4 GB) 230 Words (1 GW)

The data stored in the memory

32 bits

= 4 Bytes = 1 Word 18

MIPS Memory Access Instructions

MIPS has two basic data transfer instructions for accessing memory lw sw $t0, 4($s3) $t0, 8($s3) #load word from memory #store word to memory

The data is loaded into (lw) or stored from (sw) a register in the register file a 5 bit address The memory address a 32 bit address is formed by adding the contents of the base address register to the offset value

A 16-bit field meaning access is limited to memory locations within a region of 213 or 8,192 words (215 or 32,768 bytes) of the address in the base register Note that the offset can be positive or negative
19

Machine Language - Load Instruction

Load/Store Instruction Format (I format): lw $t0, 24($s2)


op rs rt 16 bit offset Memory

2410 + $s2 =

0xf f f f f f f f

. . . 0001 1000 + . . . 1001 0100 . . . 1010 1100 = 0x120040ac

$t0 $s2

0x120040ac 0x12004094 0x0000000c 0x00000008 0x00000004 0x00000000 word address (hex) 20

data

Memory Organization

Viewed as a large, single-dimension array, with an address. A memory address is an index into the array "Byte addressing" means that the index points to a byte of memory.
0 1 2 3 4 5 6 ...
8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data

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Memory Organization

Bytes are nice, but most data items use larger "words" For MIPS, a word is 32 bits or 4 bytes.
0 4 8 12 ...
32 bits of data 32 bits of data 32 bits of data 32 bits of data

Registers hold 32 bits of data

232 bytes with byte addresses from 0 to 232-1 230 words with byte addresses 0, 4, 8, ... 232-4 Words are aligned
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Byte Addresses

Since 8-bit bytes are so useful, most architectures address individual bytes in memory

The memory address of a word must be a multiple of 4 (alignment restriction)

Big Endian: Little Endian:

leftmost byte is word address rightmost byte is word address


little endian byte 0

IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA

Intel 80x86, DEC Vax, DEC Alpha (Windows NT) 3 msb 0 1 2 3 2 1 0 lsb

Aligned

big endian byte 0

Alignment: require that objects fall on address Not that is multiple of their size. Aligned

Machine Language - Load Instruction

Example: C code: A[12] = h + A[8];

MIPS code: lw $t0, 32($s3) add $t0, $s2, $t0 sw $t0, 48($s3)

Can refer to registers by name (e.g., $s2, $t2) instead of number Store word has destination last Remember arithmetic operands are registers, not memory! Cant write: add 48($s3), $s2, 32($s3)
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Aside: Loading and Storing Bytes

MIPS provides special instructions to move bytes lb sb $t0, 1($s3) $t0, 6($s3)
op rs rt

#load byte from memory #store byte to


16 bit offset

memory

What 8 bits get loaded and stored?

load byte places the byte from memory in the rightmost 8 bits of the destination register
- what happens to the other bits in the register?

store byte takes the byte from the rightmost 8 bits of a register and writes it to a byte in memory
- what happens to the other bits in the memory word? 25

Loading and Storing Half Words

MIPS also provides special instructions to move half words $t0, 1($s3) $t0, 6($s3)
op rs

lh sh

#load half word from memory #store half word to


rt 16 bit number

memory

What

16 bits get loaded and stored?

load half word places the half word from memory in the rightmost 16 bits of the destination register
- what happens to the other bits in the register?

store half word takes the half word from the rightmost 16 bits of the register and writes it to the half word in memory
- leaving the other half word in the memory word unchanged
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So far weve learned:

MIPS loading words but addressing bytes arithmetic on registers only Instruction add $s1, $s2, $s3 sub $s1, $s2, $s3 lw $s1, 100($s2) sw $s1, 100($s2) muli $s1, $s2, 4 Meaning $s1 = $s2 + $s3 $s1 = $s2 $s3 $s1 = Memory[$s2+100] Memory[$s2+100] = $s1 $s1 = $s2 * 4

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MIPS Instructions, so far

Category

Instr

Example

Meaning

Arithmetic add subtract add immediate Data transfer load word store word

add $s1, $s2, $s3 $s1 = $s2 + $s3 sub $s1, $s2, $s3 $s1 = $s2 - $s3 addi $s1, $s2, 4 lw $s1, 32($s2) $s1 = $s2 + 4 $s1 = Memory($s2+32) Memory($s2+32) = $s1

sw $s1, 32($s2)

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MIPS Control Flow Instructions

MIPS conditional branch instructions: bne $s0, $s1, Lbl #go to Lbl if $s0$s1 beq $s0, $s1, Lbl #go to Lbl if $s0=$s1

Ex:

if (i==j) h = i + j; bne $s0, $s1, Lbl1 add $s3, $s0, $s1 ...

Lbl1:

Instruction Format (I format):


op rs rt 16 bit offset

How is the branch destination address specified?


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Specifying Branch Destinations

Use a register (like in lw and sw) added to the 16-bit offset

which register? Instruction Address Register (the PC)


- its use is automatically implied by instruction - PC gets updated (PC+4) during the fetch cycle so that it holds the address of the next instruction

limits the branch distance to -215 to +215-1 instructions from the (instruction after the) branch instruction, but most branches are local anyway
from the low order 16 bits of the branch instruction
16

offset sign-extend
00 32 32 Add 32 4 32 Add 32

branch dst address


32

PC
32

? 32

More Branch Instructions

We have beq, bne, but what about other kinds of brances (e.g., branch-if-less-than)? For this, we need yet another instruction, slt Set on less than instruction:
slt $t0, $s0, $s1 # if $s0 < $s1 # $t0 = 1 # $t0 = 0 then else

Instruction format (R format):


op rs rt rd funct

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More Branch Instructions, Cont

Can use slt, beq, bne, and the fixed value of 0 in register $zero to create other conditions

less than slt bne

blt $s1, $s2, Label $at, $s1, $s2 $at, $zero, Label #$at set to 1 if # $s1 < $s2

less than or equal to greater than great than or equal to

ble $s1, $s2, Label bgt $s1, $s2, Label bge $s1, $s2, Label

Such branches are included in the instruction set as pseudo instructions - recognized (and expanded) by the assembler

Its why the assembler needs a reserved register ($at)


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Other Control Flow Instructions

MIPS also has an unconditional branch instruction or jump instruction: j label #go to label

Instruction Format (J Format):


op 26-bit address

from the low order 26 bits of the jump instruction


26

00 32

PC

32

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Aside: Branching Far Away

What if the branch destination is further away than can be captured in 16 bits?

The assembler comes to the rescue it inserts an unconditional jump to the branch target and inverts the condition beq $s0, $s1, L1

becomes bne j L2:


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$s0, $s1, L2 L1

Programming Styles

Procedures (subroutines, functions) allow the programmer to structure programs making them

easier to understand and debug and allowing code to be reused

Procedures allow the programmer to concentrate on one portion of the code at a time

parameters act as barriers between the procedure and the rest of the program and data, allowing the procedure to be passed values (arguments) and to return values (results)

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Six Steps in Execution of a Procedure


1.

Main routine (caller) places parameters in a place where the procedure (callee) can access them

$a0 - $a3: four argument registers

2. 3. 4. 5.

Caller transfers control to the callee Callee acquires the storage resources needed Callee performs the desired task Callee places the result value in a place where the caller can access it

$v0 - $v1: two value registers for result values

6.

Callee returns control to the caller

$ra: one return address register to return to the point of origin

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Instructions for Accessing Procedures

MIPS procedure call instruction: jal ProcedureAddress #jump and link

Saves PC+4 in register $ra to have a link to the next instruction for the procedure return Machine format (J format):
op 26 bit address

Then can do procedure return with a jr $ra #return

Instruction format (R format):


op rs funct 39

Basic Procedure Flow

For a procedure that computes the GCD of two values i (in $t0) and j (in $t1) gcd(i,j);

The

caller puts the i and j (the parameters values) in $a0 and $a1 and issues a jal gcd #jump to routine gcd

The

callee computes the GCD, puts the result in $v0, and returns control to the caller using gcd: . . . #code to compute gcd jr $ra #return
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Aside: Spilling Registers

What if the callee needs more registers? What if the procedure is recursive?

uses a stack a last-in-first-out queue in memory for passing additional values or saving (recursive) return address(es)

high addr

One of the general registers, $sp, is used to address the stack (which grows from high address to low address)

add data onto the stack push $sp = $sp 4 data on stack at new $sp

top of stack

$sp

remove data from the stack pop data from stack at $sp $sp = $sp + 4
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low addr

MIPS Immediate Instructions


Small constants are used often in typical code Possible approaches?


put typical constants in memory and load them create hard-wired registers (like $zero) for constants like 1 have special instructions that contain constants !

addi $sp, $sp, 4 slti $t0, $s2, 15

#$sp = $sp + 4 #$t0 = 1 if $s2<15

Machine format (I format):


op rs rt 16 bit immediate

I format

The constant is kept inside the instruction itself!

Immediate format limits values to the range +2151 to -215


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Logical Operations

There are a number of bit-wise logical operations in the MIPS ISA and $t0, $t1, $t2 #$t0 = $t1 & $t2 or $t0, $t1, $t2 #$t0 = $t1 | $t2

nor $t0, $t1, $t2 #$t0 = not($t1 | $t2)


op rs rt rd shamt funct

R format

10

0x24

andi $t0, $t1, 0xff00 ori $t0, $t1, 0xff00

#$t0 = $t1 & ff00 #$t0 = $t1 | ff00


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Logic Operations

Logic operations operate on individual bits of the operand.


$t2 = 00 0000 1101 0000 $t1 = 00 0011 1100 0000 and or nor $t0, $t1, $t2 $t0 = $t0, $t1 $t2 $t0 = 00 0000 1100 0000 00 0011 1101 0000 11 1100 0010 1111

$t0, $t1, $t2 $t0 =

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Design Principles

Simplicity favors regularity

Of course this complicates some things... C code: MIPS code: a = b + c + d; add a, b, c add a, a, d

Smaller is faster. Why?


Arithmetic instructions operands must be registers, only 32 registers provided Compiler associates variables with registers What about programs with lots of variables?

Make the common case fast

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Aside: How About Larger Constants?

We'd also like to be able to load a 32 bit constant into a register, for this we must use two instructions a new "load upper immediate" instruction lui $t0, 1010101010101010
16 0 8 1010101010101010

Then must get the lower order bits right, use ori $t0, $t0, 1010101010101010
1010101010101010 0000000000000000 1010101010101010 0000000000000000 1010101010101010 1010101010101010 47

MIPS Organization So Far


Processor
Register File src1 addr src2 addr 5 dst addr write data 5 32 32 bits branch offset 32 PC 4 32 Add 32 Add 32 32 ALU 32 32 32 5 32 registers ($zero - $ra) src1 data 32

Memory
11100

src2 32 data

read/write addr
32

230 words

read data
32

Fetch PC = PC+4 Exec

write data
32 32 4 0 5 1 6 2 7 3

Decode

32 bits byte address (big Endian)

01100 01000 00100 00000 word address (binary)

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Review: MIPS Instructions, so far


Category Instr OpC Example Meaning

Arithmetic add (R & I format) subtract add immediate shift left logical shift right logical shift right arithmetic and or nor and immediate or immediate load upper immediate

0 & 20 add $s1, $s2, $s3 0 & 22 sub $s1, $s2, $s3 8 addi $s1, $s2, 4 $s1, $s2, 4 $s1, $s2, 4 0 & 00 sll 0 & 02 srl

$s1 = $s2 + $s3 $s1 = $s2 - $s3 $s1 = $s2 + 4 $s1 = $s2 << 4 $s1 = $s2 >> 4 (fill with zeros) $s1 = $s2 >> 4 (fill with sign bit) $s1 = $s2 & $s3 $s1 = $s2 | $s3 $s1 = not ($s2 | $s3) $s1 = $s2 & 0xff00 $s1 = $s2 | 0xff00 $s1 = 0xffff0000 49

0 & 03 sra $s1, $s2, 4 0 & 24 and $s1, $s2, $s3 0 & 25 or c d f $s1, $s2, $s3 0 & 27 nor $s1, $s2, $s3 and $s1, $s2, ff00 or $s1, $s2, ff00 lui $s1, 0xffff

Review: MIPS Instructions, so far


Category Instr OpC Example Meaning

Data transfer (I format)

load word store word load byte store byte load half store half

23 2b 20 28 21 29 4 5 a

lw lb lh

$s1, 100($s2) $s1 = Memory($s2+100) $s1, 101($s2) $s1, 101($s2) $s1 = Memory($s2+101) Memory($s2+101) = $s1 $s1 = Memory($s2+102) Memory($s2+102) = $s1 if ($s1==$s2) go to L if ($s1 !=$s2) go to L

sw $s1, 100($s2) Memory($s2+100) = $s1 sb $s1, 101($s2) sh $s1, 101($s2) beq $s1, $s2, L bne $s1, $s2, L

Cond. branch (I & R format)

br on equal br on not equal set on less than immediate set on less than

slti $s1, $s2, 100 if ($s2<100) $s1=1; else $s1=0 if ($s2<$s3) $s1=1; else $s1=0 go to 10000 go to $t1 50

0 & 2a slt $s1, $s2, $s3 2 j 2500 $t1

Uncond. jump

jump jump register

0 & 08 jr

Machine Language - Load Instruction

Consider the load-word and store-word instrs

What would the regularity principle have us do?

- But . . . Good design demands compromise

Introduce a new type of instruction format

I-type for data transfer instructions (previous format was Rtype for register)

Example: lw $t0, 24($s2)


op 23hex 100011 rs 18 10010 rt 8 01000 16 bit number 24 0000000000011000

53

Machine Language

Instructions, like registers and words of data, are also 32 bits long

Example: add $t1, $s1, $s2 registers have numbers, $t1=9, $s1=17, $s2=18

Fieldsize:

Instruction Format:
6 bits 5 bits

5 bits

5 bits

5 bits

6 bits

000000 1000110010 01001 00000 100000

op

rs

rt

rd shamt funct

Can you guess what the field names stand for?

54

Hardware implements semantics ...


Syntax: ADD $8 $9 $10 Semantics: $8 = $9 + $10

R-Format
Fieldsize: Bitfield: Binary: 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

opcode

rs

rt

rd
01000

shamt funct
00000 100000

01010 000000 01001 In Hexadecimal: 012A4020

55

Hardware implements semantics ...


Syntax: ADD $8 $9 $10
Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction

($8 = $9 + $10)

Fetch next inst from memory:012A4020

opcode

rs

rt

rd

shamt funct

Decode fields to get : ADD $8 $9 $10 Retrieve register values: $9 $10 Add $9 to $10 Place this sum in $8 Prepare to fetch instruction that follows the ADD in the program.

56

Machine Language - Store Instruction

Example: sw $t0, 24($s2)


op rs rt 16 bit number

43

18

24

101011

10010

01000

0000000000011000

A 16-bit offset means access is limited to memory locations within a range of +213-1 to -213 (~8,192) words (+215-1 to -215 (~32,768) bytes) of the address in the base register $s2

2s complement (1 sign bit + 15 magnitude bits)


58

Memory Instructions: LW $1,32($2)


Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction

Fetch the load inst from memory opcode rs rt offset

I-Format

Decode fields to get : LW $1, 32($2) Retrieve register value: $2 Compute memory address: 32 + $2 Load memory address contents into: $1 Prepare to fetch instr that follows the LW in the program.

59

Machine Language Immediate Instructions

What instruction format is used for the addi ? addi $s3, $s3, 4 #$s3 = $s3 + 4 Machine format:
op 8 rs 19 rt 19 16 bit immediate 4

I format

The constant is kept inside the instruction itself!


So must use the I format Immediate format Limits immediate values to the range +2151 to -215
61

Branch Instructions: BEQ $1,$2,25


Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction

Fetch branch inst from memory opcode rs rt offset

I-Format

Decode fields to get: BEQ $1, $2, 25 Retrieve register values: $1, $2 Compute if we take branch: $1 == $2 ?

ALWAYS prepare to fetch instr that follows the BEQ in the program (delayed branch). IF we take branch, the instr we fetch AFTER that instruction is PC + 4 + 100.

PC == Program Counter
62

Assembling Code

Remember the assembler code we compiled last lecture for the C statement
A[8] = A[2] - b $t0, 8($s3) #load A[2] into $t0 $t0, $t0, $s2 $t0, 32($s3) #subtract b from A[2] #store result in A[8]

lw sub sw

Assemble the MIPS object code for these three instructions (decimal is fine)
lw sub sw
35 0 43 19 8 19 8 18 8 8 8 0 32 64 34

MIPS Addressing Modes


Register addressing operand is in a register Base (displacement) addressing operand is at the memory location whose address is the sum of a register and a 16-bit constant contained within the instruction Immediate addressing operand is a 16-bit constant contained within the instruction PC-relative addressing instruction address is the sum of the PC and a 16-bit constant contained within the instruction Pseudo-direct addressing instruction address is the 26-bit constant contained within the instruction concatenated with the upper 4 bits of the PC

65

Review of MIPS Operand Addressing Modes

Register addressing operand is in a register


rs rt rd funct

op

Register
word operand

Base (displacement) addressing operand is at the memory location whose address is the sum of a register and a 16-bit constant contained within the instruction
rs rt offset

op

Memory
word or byte operand

base register

Register relative (indirect) with Pseudo-direct with

0($a0) addr($zero)

Immediate addressing operand is a 16-bit constant contained within the instruction


rs rt operand 66

op

Review of MIPS Instruction Addressing Modes

PC-relative addressing instruction address is the sum of the PC and a 16-bit constant contained within the instruction
rs rt offset

op

Memory
branch destination instruction

Program Counter (PC)

Pseudo-direct addressing instruction address is the 26bit constant contained within the instruction concatenated with the upper 4 bits of the PC
jump address || Program Counter (PC)

op

Memory
jump destination instruction

67

MIPS (RISC) Design Principles

Simplicity favors regularity


fixed size instructions 32-bits small number of instruction formats opcode always the first 6 bits

Good design demands good compromises

three instruction formats

Smaller is faster

limited instruction set limited number of registers in register file limited number of addressing modes

Make the common case fast


arithmetic operands from the register file (load-store machine) allow instructions to contain immediate operands
68

Next Lecture and Reminders

Sections 2.10 & 2.11: Translation & Compiler optimization

Software: Read them for your knowledge!

Next lecture

MIPS ALU Review


- Reading assignment PH, Chapter 3

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