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Expt No: 1 Aim: CURRENT-SERIES FEEDBACK AMPLIFIER To design and test the current-series feedback amplifier and to calculate the following parameters with and without feedback. 1. Mid band gain. 2. Bandwidth and cut-off frequencies. 3. Input and output impedance. Components & Equipment required: Sl. No. 1 2 3 4 5 6 7 Circuit diagram: (i) Without feedback: Vcc = +12V Components / Equipment Power supply Function generator CRO Transistor Resistors Capacitors Connecting wires Range / Specifications (0-30)V (0-20M)Hz BC107 Quantity 1 1 1 1 Accordingly R1 RC Cout Cin B C BC107 E RL CRO Vin=50mV f=(1-3M)Hz R2 RE CE 0 (ii) With feedback: Vcc = +12V R1 RC Cout Cin B C BC107 E RL CRO Vin=50mV f=(1-3M)Hz R2 RE 0 Theory: The current series feedback amplifier is characterized by having shunt sampling and series mixing. In amplifiers, there is a sampling network, which samples the output and gives to the feedback network. The feedback signal is mixed with input signal by either shunt or series mixing technique. Due to shunt sampling the output resistance increases by a factor of ‘D’ and the input resistance is also increased by the same factor due to series mixing. This is basically transconductance amplifier. Its input is voltage which is amplified as current. Design: (i) Without feedback: VCC = 12V; IC = 1mA; fL = 50Hz; S = 2; RL = 4.7KΩ; hfe = re = 26mV / IC = 26Ω; hie = hfe re = VCE= Vcc/2 (transistor Active) = VE = IERE = Vcc/10 Applying KVL to output loop, we get VCC = ICRC + VCE + IERE RC = Since IB is very small when compare with IC, IC ≈ IE RE = VE / IE = S = 1+ RB / RE = 2 RB = VB = VCC R2 / (R1 + R2) RB = R1 || R2 R1 = R2 = XCi = Zi / 10 = (hie || RB) / 10 = Ci = 1 / (2πf XCi) = Xco = (RC || RL)/10 = Co = 1 / (2πf XCo) = XCE = RE/10 = CE = 1 / (2πf XCE) = (ii) With feedback (Remove the Emitter Capacitor, CE): Feedback factor, β = -RE = Gm = -hfe / (hie + RE) = Desensitivity factor, D = 1 + β Gm = Transconductance with feedback, Gmf = Gm / D = Input impedance with feedback, Zif = Zi D Output impedance with feedback, Z0f = Z0 D Procedure: 1. Connect the circuit as per the circuit diagram. 2. Keeping the input voltage constant, vary the frequency from 50Hz to 3MHz in regular steps and note down the corresponding output voltage. 3. Plot the graph: Gain (dB) Vs Frequency 4. Calculate the bandwidth from the graph. 5. Calculate the input and output impedance. 6. Remove Emitter Capacitance, and follow the same procedures (1 to 5). Tabular column: (i) Without feedback: Sl. No Frequency (Hz) Vi = Output Voltage (V0) (volts) Gain = V0/Vi Gain = 20 log(V0/Vi) (dB) (ii) With feedback: Sl. No Frequency (Hz) Vi = Output Voltage (V0) (volts) Gain = V0/Vi Gain = 20 log(V0/Vi) (dB) Model graph: (frequency response) Gain in dB Without feedback With feedback Frequency in Hz Result: Thus the current series feedback amplifier is designed and constructed and the following parameters are calculated. With feedback Input impedance Output impedance Gain (midband) Bandwidth Without feedback Expt. No. 2 Aim: VOLTAGE SHUNT FEEDBACK AMPLIFIER To design and test the voltage-shunt feedback amplifier and to calculate the following parameters with and without feedback. 1. Mid band gain. 2. Bandwidth and cut-off frequencies. 3. Input and output impedance. Components & Equipment required: Sl. No. 1 2 3 4 5 6 7 Components / Equipment Power supply Function generator CRO Transistor Resistors Capacitors Connecting wires Range / Specifications (0-30)V (0-20M)Hz BC107 Quantity 1 1 1 1 Circuit Diagram: (i) Without Feedback: Vcc = +12V R1 RC Cout Cin B C BC107 E CRO RE Vin=50mV f=(1-3M)Hz R2 CE 0 (ii) With Feedback: Vcc = +12V R1 Rf Cin B E RC Cf C BC107 Cout CRO Vin=50mV f=(1-3M)Hz R2 RE CE 0 Theory: In voltage shunt feedback amplifier, the feedback signal voltage is given to the base of the transistor in shunt through the base resistor RB. This shunt connection tends to decrease the input resistance and the voltage feedback tends to decrease the output resistance. In the circuit RB appears directly across the input base terminal and output collector terminal. A part of output is feedback to input through RB and increase in IC decreases IB. Thus negative feedback exists in the circuit. So this circuit is also called voltage feedback bias circuit. This feedback amplifier is known an transresistance amplifier. It amplifies the input current to required voltage levels. The feedback path consists of a resistor and a capacitor. Design (i) Without Feedback: VCC = 12V; IC = 1mA; AV = 30; Rf = 2.5KΩ; S = 2; hfe = re = 26mV / IC = 26Ω; hie = hfe re = VCE= Vcc/2 (transistor Active) = VE = IERE = Vcc/10 = ; β=1/ Rf = 0.0004 Applying KVL to output loop, we get RC = VCC = ICRC + VCE + IERE Since IB is very small when compare with IC, IC ≈ IE RE = VE / IE = S = 1+ RB / RE RB = VB = VCC R2 / (R1 + R2) RB = R1 || R2 R1 = R2 = (ii) With feedback: RO = RC || Rf = Ri = (RB || hie ) || Rf = Rm = -(hfe (RB || Rf) (RC || Rf)) / ((RB || Rf) + hie) = Desensitivity factor, D = 1 + β Rm Rif = Ri / D = Rof = Ro / D = Rmf = Rm / D = XCi = Rif /10 = Ci = 1 / (2πf XCi) = Xco = Rof /10 = Co = 1 / (2πf XCo) = RE’ = RE || ((RB + hie) / (1+hfe)) XCE = RE’/10 = CE = 1 / (2πf XCE) = XCf = Rf/10 Cf = 1 / (2πf XCf) = Procedure: 1. Connect the circuit as per the circuit diagram. 2. Keeping the input voltage constant, vary the frequency from 50Hz to 3MHz in regular steps and note down the corresponding output voltage. 3. Plot the graph: Gain (dB) Vs Frequency 4. Calculate the bandwidth from the graph. 5. Calculate the input and output impedance. 6. Remove Emitter Capacitance, and follow the same procedures (1 to 5). Tabular Column: (i) Without Feedback: Frequency V0 (volts) Vi = Gain = V0/Vi Gain (dB) = 20 log(V0/Vi) (ii) With Feedback: Frequency V0 (volts) Vi = Gain = V0/Vi Gain (dB) = 20 log(V0/Vi) Model graph: (frequency response) Gain in dB Without feedback With feedback Frequency in Hz Result: Thus the current series feedback amplifier is designed and constructed and the following parameters are calculated. With feedback Without feedback Input impedance Output impedance Gain (midband) Bandwidth Expt. No. 3 Aim: RC PHASE SHIFT OSCILLATOR To design and construct a RC phase shift oscillator for the given frequency (f0) Components & Equipment required: Sl. No. 1 2 3 4 5 6 Components / Equipment Power supply CRO Transistor Resistors Capacitors Connecting wires Range / Specifications (0-30) V BC107 Quantity 1 1 1 Accordingly Circuit Diagram: Vcc = +12V R1 RC Cout Cin C B E BC107 CRO RE R2 CE 0 C R R C R C 0 Theory: In the RC phase shift oscillator, the required phase shift of 180˚ in the feedback loop from the output to input is obtained by using R and C components, instead of tank circuit. Here a common emitter amplifier is used in forward path followed by three sections of RC phase network in the reverse path with the output of the last section being returned to the input of the amplifier. The phase shift Ф is given by each RC section Ф=tan¯1 (1/ωrc). In practice R-value is adjusted such that Ф becomes 60˚. If the value of R and C are chosen such that the given frequency for the phase shift of each RC section is 60˚. Therefore at a specific frequency the total phase shift from base to transistor’s around circuit and back to base is exactly 360˚ or 0˚. Thus the Barkhausen criterion for oscillation is satisfied Design: VCC = 12V; IC = 1mA; C = 0.01µF; fo = re = 26mV / IC = 26Ω; hie = hfe re = VCE= Vcc/2 (transistor Active) = VE = IERE = Vcc/10 Applying KVL to output loop, we get VCC = ICRC + VCE + IERE RC = Since IB is very small when compare with IC, IC ≈ IE RE = VE / IE = S = 1+ RB / RE = 2 RB = VB = VBE + VE = VB = VCC R2 / (R1 + R2) RB = R1 || R2 R1 = R2 = Gain formula is given by, − h fe R Leff AV = (Av = -29, design given) h ie Effective load resistance is given by, Rleff = Rc || RL RL = ; S = 2; hfe = XCi = {[hie+(1+hfe)RE] || RB}/10 = Ci = 1 / (2πf XCi) = Xco = Rleff /10 = Co = 1 / (2πf XCo) = XCE = RE/10 = CE = 1 / (2πf XCE) = Feedback Network: f0 = fo = R= ; C = 0.01µf; 1 2π 6RC Procedure: 1. Connections are made as per the circuit diagram. 2. Switch on the power supply and observe the output on the CRO (sine wave). 3. Note down the practical frequency and compare with its theoretical frequency. Model Graph: Vout (Voltage) Time(ms) Result: Thus RC phase shift oscillator is designed and constructed and the output sine wave frequency is calculated as Theoretical Frequency Practical Expt. No. 4 Aim: WEIN BRIDGE OSCILLATOR To design and construct a Wein Bridge oscillator for the given frequency (f0) Components & Equipment required: Sl. No. 1 2 3 4 5 6 Components / Equipment Power supply CRO Transistor Resistors Capacitors Connecting wires Range / Specifications (0-30) V (0-20M0Hz SL100 Quantity 1 1 1 Accordingly Circuit Diagram: Theory: Wein bridge oscillator is one of the low frequency audio oscillators. The feedback loop in this oscillator consists of a lead lag network, i.e., a series R and C cascaded with a parallel combination of R and C (frequency sensitive arms of the bridge). This network does not introduce any phase shift and so the total phase shift in the feedback path is zero. So we use a two stage CE amplifier in the forward path that also introduces zero phase shifts. Hence the total phase shift around the loop is zero and the Barkhausen condition for sustained oscillation is satisfied. The feedback is taken from the collector of Q2 and given to the bridge using a coupling capacitor. The RE1 serves for dual purpose i.e., it acts as RE for Q1 and forms R4 for the wein bridge network. The last bridge arm is given by R3.The oscillation frequency is given by f=1/2πRC. Design: VCC = ; IC = mA; fo = ;S= ; hfe = re = 26mV / IC = 26Ω; hie = hfe re = VCE= Vcc/2 (transistor Active) = VE = IERE = Vcc/10 Applying KVL to output loop, we get VCC = ICRC + VCE + IERE RC1 = RC2 = (VCC - VCE - VE)/ IC Since IB is very small when compare with IC, IC ≈ IE RE = VE / IE = S = 1+ RB / RE = RB = VB = VBE + VE = VB = VCC R22 / (R11 + R22)= R11= VCC RB/ VB R11 = R33= R22 = R44= Feedback Network: f0 = ; C=C1=C2= 0.1µf; For Wein Bridge Oscillator, f 0 = R =R1=R2= 1 2πRC R3 = 2 × R4 = 1k Let R4=500 Procedure: 1. Connections are made as per the circuit diagram. 2. Switch on the power supply and observe the output on the CRO (sine wave). 3. Note down the practical frequency and compare with its theoretical frequency. Model Graph: Vout (Voltage) Time (ms) Result: Thus the Wein Bridge oscillator is designed and constructed and the output sine wave frequency is calculated . Theoretical Frequency Amplitude Practical Expt. No.5 Aim: HARTELY OSCILLATOR To design and construct the given oscillator for the given frequency (fO). Components & Equipment required: Sl. No. 1 2 3 4 5 6 7 8 Components / Equipment Power supply CRO Transistor Resistors Capacitors DIB DCB Connecting wires Range / Specifications (0-30)V BC107 Quantity 1 1 1 Accordingly Circuit Diagram: Vcc = +12V R1 RC Cout Cin C B BC107 E CRO RL R2 RE CE 0 L1 C L2 0 Theory: Hartley oscillator is a type of sine wave generator. The oscillator derives its initial output from the noise signals present in the circuit. After considerable time, it gains strength and thereby producing sustained oscillations. Hartley Oscillator have two major parts namely – amplifier part and feedback part. The amplifier part has a typically CE amplifier with voltage divider bias. In the feedback path, there is a LCL network. The feedback network generally provides a fraction of output as feedback. Design: VCC = 12V; IC = 1mA; fo = re = 26mV / IC = 26Ω; hie = hfe re = VCE= Vcc/2 (transistor Active) = VE = IERE = Vcc/10 Applying KVL to output loop, we get VCC = ICRC + VCE + IERE RC = Since IB is very small when compare with IC, IC ≈ IE RE = VE / IE = S = 1+ RB / RE = 2 RB = VB = VBE + VE = VB = VCC R2 / (R1 + R2) RB = R1 || R2 R1 = R2 = Gain formula is given by, − h fe R Leff AV = (Av = -29, design given) h ie Effective load resistance is given by, Rleff = Rc || RL RL = XCi = {[hie+(1+hfe)RE] || RB}/10 = Ci = 1 / (2πf XCi) = Xco = Rleff /10 = ; S = 2; hfe = Co = 1 / (2πf XCo) = XCE = RE/10 = CE = 1 / (2πf XCE) = Feedback Network: f0 = ; L1 = 1mH; L2 = 10mH L 1 A= =− 1 β L2 1 f= 2π (L1 + L 2 )C C= Procedure: 1. Connections are made as per the circuit diagram. 2. Switch on the power supply and observe the output on the CRO (sine wave). 3. Note down the practical frequency and compare with its theoretical frequency. Model Graph: Vout (Voltage) Time(ms) Result: Thus Hartley oscillator is designed and constructed and the output sine wave frequency is calculated as Theoretical Frequency Practical Expt. No.6 COLPITTS OSCILLATOR Aim: To design and construct the given oscillator at the given operating frequency. Equipments required: Sl. No. 1 2 3 4 5 6 7 8 9 Components / Equipment Power supply Function generator CRO Transistor Resistors Capacitors DIB DCB Connecting wires Range / Specifications (0-30)V (0-20M)Hz BC107 Quantity 1 1 1 1 Circuit Diagram: Vcc = +12V R1 RC Cout Cin C B BC107 E CRO RL R2 RE CE 0 L C1 C2 0 Theory: A Colpitts oscillator is the electrical dual of a Hartley oscillator. In the Colpitts circuit, two capacitors and one inductor determine the frequency of oscillation. The oscillator derives its initial output from the noise signals present in the circuit. After considerable time, it gains strength and thereby producing sustained oscillations. It has two major parts namely – amplifier part and feedback part. The amplifier part has a typically CE amplifier with voltage divider bias. In the feedback path, there is a CLC network. The feedback network generally provides a fraction of output as feedback. Design: VCC = 12V; IC = 1mA; fo = re = 26mV / IC = 26Ω; hie = hfe re = VCE= Vcc/2 (transistor Active) = VE = IERE = Vcc/10 Applying KVL to output loop, we get VCC = ICRC + VCE + IERE RC = Since IB is very small when compare with IC, IC ≈ IE RE = VE / IE = S = 1+ RB / RE = 2 RB = VB = VBE + VE = VB = VCC R2 / (R1 + R2) RB = R1 || R2 R1 = R2 = Gain formula is given by, − h fe R Leff AV = (Av = -29, design given) h ie Effective load resistance is given by, Rleff = Rc || RL RL = XCi = {[hie+(1+hfe) RE] || RB}/10 = Ci = 1 / (2πf XCi) = Xco = Rleff /10 = ; S = 2; hfe = Co = 1 / (2πf XCo) = XCE = RE/10 = CE = 1 / (2πf XCE) = Feedback Network: f0 = A= f= L= ; C1 = 1 = ; C2 = β 1 2π C2 C1 C1 + C 2 LC1C 2 Procedure: 1. Rig up the circuit as per the circuit diagrams (both oscillators). 2. Switches on the power supply and observe the output on the CRO (sine wave). 3. Note down the practical frequency and compare with its theoretical frequency. Model Graph: Vout (Voltage) Time(ms) Result: Thus Colpitts oscillator is designed and constructed and the output sine wave frequency is calculated as Theoretical Frequency Practical Expt. No. 7(a) CMOS Inverter, NAND and NOR using PSPICE Aim: To plot the transient characteristics of output voltage for the given CMOS inverter, NAND and NOR from 0 to 80µs in steps of 1µs. To calculate the voltage gain, input impedance and output impedance for the input voltage of 5V. Parameter Table: Parameters L W VTO KP CBD CBS RD RS RB RG RDS CGSO CGDO CGBO PMOS 1µ 20µ -2 4.5E-4 5p 2p 5 2 0 0 1Meg 1p 1p 1p NMOS 1µ 5µ 2 2 5p 2p 5 2 0 0 1Meg 1p 1p 1p Circuit Diagram: (i) Inverter: VDD = +5V 3 S G D 1 Vin 2 D Q2 G S RL = 100K Vout Q1 0 (ii) NAND VDD = +5V 2 G Q1 D D 4 D Vin1 G 1 S D 3 G Q4 S Q3 RL = 100K Vout S G S Q2 Vin2 (iii) NOR VDD = +5V 3 Vin1 1 G Q1 S D S Q2 D 4 D G Q3 S G D Q4 S RL = 100K Vout 2 Vin2 G Theory: (i) Inverter CMOS is widely used in digital IC’s because of their high speed, low power dissipation and it can be operated at high voltages resulting in improved noise immunity. The inverter consists of two MOSFETs. The source of p-channel device is connected to +VDD and that of n-channel device is connected to ground. The gates of two devices are connected as common input. (ii) NAND It consists of two p-channel MOSFETs connected in parallel and two n-channel MOSFETs connected in series. P-channel MOSFET is ON when gate is negative and Nchannel MOSFET is ON when gate is positive. Thus when both input is low and when either of input is low, the output is high. (iii) NOR It consists of two p-channel MOSFETs connected in series and two n-channel MOSFETs connected in parallel. P-channel MOSFET is ON when gate is negative and N-channel MOSFET is ON when gate is positive. Thus when both inputs are high and when either of input is high, the output is low. When both the inputs are low, the output is high. Procedure: 1. Draw the circuit diagram and mark the nodes. 2. Go to start – program – Orcas release9.1-pspiceA/D and open the new text file. 3. Type the PSPICE program on the text window 4. Save the program in any location with CIR extension 5. Go to file – open simulation and create a new simulation file 6. Go to simulation – run. Now the result can be viewed either in the output file or in graphical simulation file. Truth Table: (i) Inverter Input Output 0 1 1 0 (ii) NAND V1 V2 Output 0 0 1 0 1 1 1 0 1 1 1 0 (iii) NOR V1 V2 Output 0 0 1 0 1 0 1 0 0 1 1 0 Model Graph: (i) Inverter Voltage Input Waveform 5V time (µs) 0 10 20 30 40 50 60 70 80 Output Waveform 5V time (µs) 0 10 20 30 40 50 60 70 80 (ii) NAND Voltage Input Waveform time (µs) 0 10 20 30 40 50 60 70 80 Output Waveform time (µs) 0 10 20 30 40 50 60 70 80 time (µs) 0 10 20 30 40 50 60 70 80 (iii) NOR Voltage Input Waveform time (µs) 0 10 20 30 40 50 60 70 80 Output Waveform 0 10 20 30 40 50 60 70 80 time (µs) time (µs) 0 10 20 30 40 50 60 70 80 Output: (i) Inverter Gain = V (2)/Vin = Input Resistance at Vin = Output Resistance at V (2) = (ii) NAND Gain = V (4)/Vin1 = V(4)/Vin2 = Input Resistance at Vin1 = Input Resistance at Vin2 = Output Resistance at V (4) = (iii) NOR Gain = V (4)/Vin1 = V (4)/Vin2 = Input Resistance at Vin1 = Input Resistance at Vin2 = Output Resistance at V (4) = Result: Thus the transient characteristics of output voltage for the given CMOS inverter, NAND and NOR is plotted and the voltage gain, input impedance and output impedance are calculated. Expt. No.7 (b) SECOND ORDER BUTTERWORTH - LOW PASS FILTER Aim: To design and implement the second order butterworth Low pass filter using PSpice. Circuit Diagram: RIN 1K 2 RF 586 ohm 0 V+ 7 + 4 V6 LM741 RL 6 VOUT 2 R1 1 1.59K 5 R2 1.59K C2 C1 1V (100 - 10K)Hz 0 0.1u 0.1u 3 3 VIN 10K Theory: A Low pass filter has a constant gain from 0 to fH. Hence the bandwidth of the filter is fH. The range of frequency from 0 to fH is called pass band. The range of frequencies beyond fH is completely attenuated and it is called as stop band. Procedure: 1. Draw the circuit diagram and mark the nodes. 2. Go to start – program – orcad release9.1-pspiceA/D and open the new text file. 3. Type the PSPICE program on the text window 4. Save the program in any location with CIR extension 5. Go to file – open simulation and create a new simulation file 6. Go to simulation – run. Now the result can be viewed either in the output file or in graphical simulation file Design: fH = 1000HZ C1= C2 =0.1µF fH = 1 / 2πRC R = 1 / 2πCfH R = R1 = R2 = 1592Ω Gain = 1.586 1.586 = 1 + (RF / RIN) RF = 586Ω Model Graph: Gain (dB) RIN=1000Ω 3dB Frequency (HZ) fH Result: Thus Low pass filter is designed and implemented using PSpice. Expt. No.8 (a) Aim: DIFFERENTIAL AMPLIFIER To implement the differential amplifier using PSpice. Circuit Diagram: RF 10K V+ RIN 10K VIN 1 VIN 2 1 2 2 3 + 7 6 6 LM741 Vout 5 R2 10K RCOMP 10K 3 4 V- Theory: A differential amplifier amplifies the difference between two voltages V1 and V2. The output of the differential amplifier is dependent on the difference between two signals and the common mode signal since it finds the difference between two inputs it can be used as a subtractor. The output of differential amplifier is RF VO = R1 (V2 – V1) Procedure: 1. 2. 3. 4. 5. 6. Draw the circuit diagram and mark the nodes. Go to start – program – Orcad release9.1-pspiceA/D and open the new text file. Type the PSPICE program on the text window Save the program in any location with CIR extension Go to file – open simulation and create a new simulation file Go to simulation – run. Now the result can be viewed either in the output file or in graphical simulation file Model Graph: Voltage V1 time V2 time V3 time Calculation: V1 = 5V V2 = 10V 10K RF VO = (V2 – V1) = (10 – 5) R1 10K VO = 5V Output: Result: VO = 5V Thus a differential amplifier using op-amp is implemented in PSpice. Expt. No.8 (b) SECOND ORDER BUTTERWORTH - HIGH PASS FILTER Aim: To design and implement the second order butterworth High pass filter using PSpice. Circuit Diagram: Theory: A high pass filter passes "high frequencies" and attenuates low frequencies. Ideally, any frequencies above a specified "cutoff frequency" are passed. The cutoff is determined by circuit components and can vary greatly. A high-pass filter, roughly, is characterized by two things: its cutoff frequency, and its order. The cutoff frequency of the above high-pass filter is fc = 1/(2πRC). The order of the filter determines how steeply the filter cuts off high frequencies; a first-order filter reduces signal power by 20 dB per decade once the frequencies are below the cutoff frequency; that is, if the input signal frequency goes down by a factor of 10, the input will be attenuated roughly by factor of 8 more than before. A second-order filter will attenuate at 40 dB per decade, and so on. Procedure: 1. 2. 3. 4. 5. Draw the circuit diagram and mark the nodes. Go to start – program – Orcad release9.1-PspiceA/D and open the new text file. Type the PSPICE program on the text window Save the program in any location with .CIR extension Go to file – open simulation and create a new simulation file 6. Go to Simulation – Run. Now the result can be viewed either in the output file or in graphical simulation file Design: FL = 1000HZ C1= C2 =0.1µF FL = 1 / 2πRC R = 1 / 2πCfL R = R1 = R2 = 1592Ω Gain = 1.586 1.586 = 1 + (RF / RIN) RF = 586Ω RIN=1000Ω Result: Thus the second order high pass filter is designed and implemented using PSpice.