Basic Design Flow

POWER OPTIMIZATION STRATEGIES IN VLSI ARCHITECTURE DESIGN

SYSTEM SPECIFICATION

(Algorithmic Level)

ARCHITECTURAL DESIGN (Register Transfer Level) LOGIC DESIGN CIRCUIT DESIGN (Gate Level) (Transistor Level) -----------------Physical Design

ANINDYA SUNDAR DHAR

Dept. of E&ECE IIT Kharagpur

DEVICE DESIGN LAYOUT

..

Optimization is possible at every level ALGORITHMIC LEVEL ARCHITECTURAL LEVEL LOGIC LEVEL CIRCUIT LEVEL DEVICE LEVEL

Major Issues SPEED POWER AREA

Must satisfy the throughput requirement Power consumption should be within prescribed limit Should occupy minimum possible silicon area

..

The actual cost function involving these factors depends on specific application.

A 0

Y 1 0

To design Low Power Architectures efficiently, knowledge in the digital logic is not sufficient.
VDD A A Y A CL B B

How much power does it consume ?

VDD

To design Low Power Architectures efficiently, the designer must have a good understanding of analog circuits as well.

CL

CMOS INVERTER

CMOS 2 INPUT NAND GATE

SOURCES OF POWER DISSIPATION

1. DYNAMIC SWITCHING POWER

A

VDD A Y A CL CL B B Y

VDD

2. SHORT-CIRCUIT CURRENT POWER 3. LEAKAGE CURRENT POWER

CMOS INVERTER

CMOS 2 INPUT NAND GATE

PSwitching = fClk CLVDD2

VDD A A Y A CL B CL CL B B Y A Y A CL VDD VDD A B Y VDD

CMOS INVERTER

CMOS 2 INPUT NAND GATE

CMOS INVERTER

CMOS 2 INPUT NAND GATE

Short circuit current

PSwitching = fClk CLVDD2

Normalized resistance

Various Possibilities Reduction of the clock frequency Reduction of switching activities Reduction of node capacitances Reduction of the supply voltage

VDD

CL

Time Transition begins

PARALLEL PROCESSING AT LOWER SUPPLY VOLTAGE Propagation Delay vs. Supply Voltage

PSwitching = fClk CLVDD2

Propagation delay (td) 50 MSPS 20 nS 2.5 V 2 mW

INPUT

Processor

OUTPUT

Processor
100 MSPS 10 nS 5V 16 mW Supply voltage (VDD)

INPUT 100 MSPS 10 nS 2.5 V 4 mW

OUTPUT

Processor

50 MSPS 20 nS 2.5 V 2 mW

PARALLEL PROCESSING AT LOWER SUPPLY VOLTAGE

An Example
DCBA

PSwitching = fClk CLVDD2

INPUT

Processor

OUTPUT

Processor

INPUT

OUTPUT

Processor
Achievement: LOW POWER CONSUMPTION Disadvantage: OCCUPIES MORE AREA

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

D C Y B A

D C B A

Proper ordering of the inputs can reduce the switching power consumption

Memory
Leakage current is significant

VDD

Memory
2 MSbits

Power Management Block 00 01

Address

Core Memory (Bit cells)

Address

Can work in the

POWERDOWN

10

11

mode !

Sense Amplifier Sense Amplifier

Data

RAM
0000 GRAY BINARY COUNTER 0001 0010 0011 f(0) f(1) f(3) f(2) Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Gray 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Number of transitions
Bits Binary Gray

4 8 16

30 510

16 256

. . .
Reduction in the number of transitions in the Address Bus

131070 65536

Conclusion
Power consumption can be decreased by reducing the unnecessary switching Other methods include reduction of the power supply voltage and minimizing the node capacitances Understanding analog electronics is essential for designing low power circuits efficiently Quantum devices will possibly take over in near future

Thank You