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74LS163: Synchronous 4-Bit Binary Counters

Prapun Suksompong
May 18, 2004
This article summarizes various important properties of the 74163
synchronous binary counter. The author then attempts to give several
examples to illustrate how this MSI can be used to generate more
complicated sequences.
The following figures show the connection diagrams and logic diagram of the 74LS163
counter:
Its important properties are:
- Synchronous Reset (Clear) input which overrides all other control inputs, but is
active only during the rising clock edge.
- Clear if CLR is asserted (overrides loading and counting).
- Synchronous Counting and Loading
- Count if ENP and ENT are both asserted.
- Load if LD is asserted (overrides counting).
- RCO is asserted only if ENT is asserted. So, we can set the counter to stop
counting at 15 by setting ENP = 0. Then, RCO = ENT.
- Example: Count from 0 to 10. Then, repeat.
Here, to detect 10 = 1010, we use Q
D
Q
B
. Note that we dont have to care about the
value of Q
A
and Q
C
because, besides 1010, the numbers that satisfy 1x1x are 1011,
1110, 1111 which are all > 1010, and not in the sequence (i.e., never reached in
normal operation.)
- Example: Count from 5 to 15. Then repeat.
Here, to detect 15, we use the RCO. To load 5, we set DCBA = 0101 = 5
10
.
- Example: Count from 3 to 12. Then repeat.
- Example: 8-bit binary counter.
- Example: Count from 0 to 15, skipping 4, 8, 12.
Here, we have to detect 3, 7, 11 which are Q = Q
3
Q
2
Q
1
Q
0
= 0011, 0111, 1011. Hence,
we want the LDN to be 1 for these cases and 0 otherwise. Using K-map, (or by
observation), we have LDN =
( ) 3 2 1 0
Q Q QQ .
Now, when the output is 3, 7, 11, we want to load I = I
3
I
2
I
1
I
0
= 5, 9, 13, respectively.
Q
3
Q
2
Q
1
Q
0
I
3
I
2
I
1
I
0
0011 0101
0111 1001
1011 1101
Otherwise dddd
Note that we dont care about the value of the when LD is not 1. From the truth table
above, we then have
0
1
2 2
3 2 3
1
0
I
I
I Q
I Q Q
=
=
=
= +
0
d
4
d
1
d
5
d
12
d
8
d
13
d
9
d
Q3
Q1
Q2
3
0
7
1
2
d
6
d
15
d
11
1
14
d
10
d
Q0
01 00 10 11
11
10
00
01
Q3Q2
Q1Q0
K-map for I
3
Hence, we have the following design:
Q3
Q1
Q2
Q3
Q2 Q0
8
VCC
12
GND
VCC 7 CLK
INPUT
1
A
QA
QB
QC
QD
B
C
D
ENT
RCO ENP
CLK
CLRN
LDN
74163
COUNTER
18
NOT
14 LD
OUTPUT
10 Q[3..0]
OUTPUT
19
OR2 13
NOT
11
NAND2
17
NAND3
- Example: Count from 0 to 13, then count from 1 to 13, and then from 3 to 13, and
then repeat this sequence.
Here, we detect Q = Q
3
Q
2
Q
1
Q
0
= 13 = 1101 at the outputs of the counters. The LD
then becomes
3 2 1 0
Q Q QQ or just
3 2 0
Q Q Q because 1111 is not in the sequence. The
first part of the design is shown below:
Q1
Q2
Q3
I0
I1 Q0
8
VCC
12
GND
34 D[1..0]
OUTPUT
VCC 7 CLK
INPUT
1
A
QA
QB
QC
QD
B
C
D
ENT
RCO ENP
CLK
CLRN
LDN
74163
COUNTER
18
NOT
14 LD
OUTPUT
30 I[1..0]
OUTPUT
10 Q[3..0]
OUTPUT
35
NAND3
The loaded inputs I = I
3
I
2
I
1
I
0
cycles from 0 1 3. So, I
3
I
2
= 00, and we need to
build a state machine (basically a counter), which is triggered by the LD signal, and
goes from 00 01 11.
So, we have 3 states: 00, 01, 11. Now, we will consider what would be the value that
get loaded into the counter. Note that the LD signal will be high when the counter
reach 13 with some small delay. Let t
0
+c be the time that the counter output values
change to 13, where t
0
is the time of positive clock tick, and c is the delay of the
counter. Then, it will stay 13 from time t
0
+c to t
0
+c+T, where T is the period of the
clock. The LD, will go high at t
0
+c+o, where o is the small delay of the combinational
logic (LD-check logic) that we use to test for 13. (It is safe to assume c+o < T.) So,
LD is high from t
0
+c+o to t
0
+c+o+T, i.e., the clock tick that matches LD = 1 is at t
0
+T
and not t
0
. If we set the state machine to cycle at the click tick with LD = 1, then it
will change at time t
0
+T+ where is the delay introduced by the state machine. So,
the value that get loaded into the counter when LD goes high, is the outputs of the
state machine at time t
0
+T which is the old state values.
Counter Delay
LD check delay
FFs delay
Outputs of the state at
this time are loaded
into the counter
We shall present two solutions here:
1) Set the outputs of the state machine to be the next state, instead of directly output
the current state. This is shown below.
State = D
1
D
0
* *
1 0
D D SMs output
1 0
I I
00 01 01
01 11 11
11 00 00
10 dd dd
By observation (or K-map) we then have
( )
*
1 1 1 0 1 0
or D I D D D D = = , and
*
0 0 1
D I D = = ,
which is implemented below:
I1
D1
LD CLK
D0
I0
AS+BS'
28
Y
A
B
S
21mux
MULTIPLEXER
21
D
DFF
CLRN
Q
PRN
24
AND2 20
D
DFF
CLRN
Q
PRN 23
NOT
27
Y
A
B
S
21mux
MULTIPLEXER
Note that we dont want to put the LD signal directly into the clocks of the D-FFs
because LD can have glitches (since it is an output from combinational logic with
multiple inputs). Here we implement the circuit with the help of 2:1 mux. The D-
FFs grab the outputs of the muxs every clock tick. When LD is 0, we set the
mux to pass the old state, so the FF state remain unchanged. When LD is 1, the
state is updated. (So, now we only concern about the values of the LD at the clock
ticks, and hence the LD glitch problem is eliminated.)
The combination of mux and the D-FF above is exactly the D-FF with EN. So,
another implementation is shown below
I1 D1
CLK
LD
I0 D0
37
D
DFFE
ENA
CLRN
Q
PRN
24
AND2 36
D
DFFE
ENA
CLRN
Q
PRN
23
NOT
2) Another method is to try to get the state machine to update faster. This can be
done by feeding the CLK_L into each FFs clock. The effect of this is to shift the
clock tick corresponding to LD = 1 for the state machine to the time
0
2
T
t + . Since
the counter loads the new values at t
0
+T, the state now get updated before being
loaded.
CLK_L
I1
LD
CLK_L
I0
CLK CLK_L
24
AND2
35
D
DFFE
ENA
CLRN
Q
PRN
34
D
DFFE
ENA
CLRN
Q
PRN
23
NOT
31
NOT
- Example: Count from 0 to 10, then count from 3 to 11, and then from 1 to 10, and
then repeat this sequence.
Since we need to deal with three subsequences, we shall define state machine which
has three states. Note here that we detect 10 = 1010
2
and 11 = 1011
2
. So, we always
detects
3 2 1
Q Q Q = 101, and then Q
0
= 0 or 1 depending on what state that counter is in.
State =
1 0
D D Detect
* *
1 0
D D Load =
1 0
I I
00 1010 01 3 = 11
01 1011 10 1 = 01
11 dddd dd d = dd
10 1010 00 0 = 00
Observe that the value of the Q
0
that we want to detect is the same as D
0
. It is then
obvious that we can use
( ) 3 2 1 0 0
Q Q Q D Q to check for 10 and 11. The first part of
the circuit then becomes the following:
Q3
Q2
LD
I0
I1
Q1
Q0 D0
8
VCC
12
GND
VCC 7 CLK
INPUT
1
A
QA
QB
QC
QD
B
C
D
ENT
RCO ENP
CLK
CLRN
LDN
74163
COUNTER
30 I[1..0]
OUTPUT
10 Q[3..0]
OUTPUT
41 D[1..0]
OUTPUT
34
NOT
63
NAND4
14 LD
OUTPUT
38
NOT
64
XNOR
Also, by observation (or K-map), we have
*
1 0
D D = ,
*
0 1 1 0
D I D D = = ,
0 1
I D = . Hence,
the state machine is the following:
CLK
D1
LD
CLK
D0
D1
D0
I0
I1
66
D
DFFE
ENA
CLRN
Q
PRN
65
D
DFFE
ENA
CLRN
Q
PRN
60
NOT
58
NOT
59
AND2
- Example: Count from 2 to 13, then count from 1 to 13, and then from 3 to 13, and
then repeat this sequence.
Here, we detect Q = Q
3
Q
2
Q
1
Q
0
= 13 = 1101 at the outputs of the counters. The LD
then becomes
3 2 1 0
Q Q QQ . The first part of the design is shown below:
Q3
Q2
Q1
I0
I1 Q0
8
VCC
12
GND
34 D[1..0]
OUTPUT
VCC 7 CLK
INPUT
1
A
QA
QB
QC
QD
B
C
D
ENT
RCO ENP
CLK
CLRN
LDN
74163
COUNTER
18
NOT
39 I[1..0]
OUTPUT
10 Q[3..0]
OUTPUT
14 LD
OUTPUT
46
NAND3
Now, we set the outputs of the state machine to be the next state.
State = D
1
D
0
* *
1 0
D D SMs output
1 0
I I
00 11 01
01 dd dd
11 10 11
10 00 10
By observation (or K-map) we then have
*
0 1
D D = ,
*
1 0 1 0
D I D D = = ,
1 1
I D = .
CLK
I0 D1
LD
CLK
D0
D1 I1
45
D
DFFE
ENA
CLRN
Q
PRN
40
XNOR
44
D
DFFE
ENA
CLRN
Q
PRN
43
WIRE
41
NOT
The problem with this design is that when we start the machine, it counts from 0. To
solve this, we shall use a reset input. So, when reset goes high, we shall load 2 into
the counter. Because we want to set BA = 10 when RESET is high, we have
0 0
0 A I RESET RESET I RESET = + = , and
1 1
1 B I RESET RESET I RESET = + = + .
Also, we need to modify the input to the load so that it will also load when the reset is
high. This can be achieve by just OR the old LD with the RESET.
I1
RESET
I0
Q3
Q2
Q1
Q0
RESET
RESET_L
RESET_L
64
GND
69
VCC
71
A
QA
QB
QC
QD
B
C
D
ENT
RCO ENP
CLK
CLRN
LDN
74163
COUNTER 59 I[1..0]
OUTPUT
61
D[1..0]
OUTPUT
VCC 70 CLK
INPUT
60 LD
OUTPUT
58 Q[3..0]
OUTPUT
55
OR2
56
AND2
72
AND3
5
7
N
O
R
2
VCC 44 RESET INPUT
47 NOT
- Example: Count from 2 to 10, then count from 1 to 11, and then from 3 to 10, and
then repeat this sequence.
State =
1 0
D D Detect
* *
1 0
D D Load =
1 0
I I
00 1010 01 1 = 01
01 1011 10 3 = 11
11 dddd dd d = dd
10 1010 00 2 = 10
Again, observe that the value of the Q
0
that we want to detect is the same as D
0
. It is
then obvious that we can use
( ) 3 2 1 0 0
Q Q Q D Q to check for 10 and 11.
We also have (from the table):
*
1 0
D D = ,
*
0 1 0
D D D = ,
0 1
I D = ,
1 1 0
I D D = .
Again, we introduce the RESET to start the counter with 2:
0 0
1 1
0
1
A I RESET RESET I RESET
B I RESET RESET I RESET
= + =
= + = +
CLK CLK_L
RESET
Q3
Q2
LD
D0
I1
Q1
Q0
D0
D1 I0
RESET
31
NOT
8
VCC
12
GND
41 D[1..0]
OUTPUT
VCC 7 CLK
INPUT
1
A
QA
QB
QC
QD
B
C
D
ENT
RCO ENP
CLK
CLRN
LDN
74163
COUNTER
10 Q[3..0]
OUTPUT
14 LD
OUTPUT
30 I[1..0]
OUTPUT
34
NOT
59
AND4
46
XOR
45
NOT
51
OR2
58
XNOR
55
OR2
57
NOT
VCC 48 RESET
INPUT
50
NOT
49
AND2
D1
CLK
LD
CLK
D0
61
D
DFFE
ENA
CLRN
Q
PRN
40
XNOR
60
D
DFFE
ENA
CLRN
Q
PRN
- Example: Triangle Counter counts the following sequence (in the left to right, top to
bottom order)
0, 1, 2, , 14, 15
1, 2, , 14, 15
2, , 14, 15
%
13, 14,15
14,15
15
and repeats starting at 0. (note that each time the counter reaches 15, it resets to one
more than it reset to the previous time it reset.
Here, it is obvious that we will detect 15, and hence we can directly use the RCO
signal. The load sequences consist of 16 state, 0 1 2 " 15 0. What we
should do is then to construct a state machine that give the sequence 1 2 "
15 0 1. Note that we start with 1 because the second subsequence starts with 1.
Now, this is almost a 4-bit counter. Lets consider he following circuit
Then, at the clock tick that LD = 1, the value of the helper counter still doesnt
change because of the delay in the counter (FFs).
To solve this problem, we just drive this helper counter by CLK_L. (Recall that we
have two options, either construct a state machine that give the next state (i.e. for
state 0, output 1), or drive it by CLK_L. Here, since we already have the state
machine (the counter), it is easier to directly use it.)
Note also that we want the helper counter to count when its clock ticks and RCO = 1.
The AND is implemented by feeding the RCO into the ENT of the helper counter.
Note that, if somehow, we can grab the inputs to the FFs (i.e. the next state value)
from the helper counter (instead of the current state value), then we dont need to
feed it by CLK_L:
1
Q3
CLK
RCO NQ[3..0]
NQ0
NQ1
NQ2
NQ3 Q2
Q1
Q0
RCO
VCC 4 CLK
INPUT
5
Q[3..0]
OUTPUT
2
A
QA
QB
QC
QD
B
C
D
ENT
RCO ENP
CLK
CLRN
LDN
74163
COUNTER
10
CLK Q[3..0]
EN NQ[3..0]
counter4
8
V
C
C
7
N
O
T
where in the above figure, counter4 has an extra output vector NQ which outputs the
next state value.
References:
- Logic 74xxxx Series,
http://www.ee.washington.edu/stores/DataSheets/74ls/74ls161.pdf
- http://ece.rose-hulman.edu/labs/dataSheets/74ls163.pdf
- http://focus.ti.com/lit/ds/symlink/sn74ls163a.pdf
- Wes Swartz, ENGRD 230: Introduction to Digital Logic Design, Final exam, Cornell
University, Fall 2003.
- Evan Speight, ENGRD 230: Introduction to Digital Logic Design, Final exam,
Cornell University, Fall 2002.
- Doug Long, ENGRD 230: Introduction to Digital Logic Design, Final exam, Cornell
University, Spring 2004.
- John F. Wakerly, Digital Design: Principles and Practices, 3/e, Prentice Hall.
- M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals
2nd Edition.