HT9170B/HT9170D DTMF Receiver

Features
Operating voltage: 2.5V~5.5V Minimal external components No external filter is required Low standby current (on power down mode) Excellent performance Tristate data output for MCU interface 3.58MHz crystal or ceramic resonator 1633Hz can be inhibited by the INH pin HT9170B: 18-pin DIP package

HT9170D: 18-pin SOP package

General Description
The HT9170B/D are Dual Tone Multi Frequency (DTMF) receivers integrated with digital decoder and bandsplit filter functions as well as power-down mode and inhibit mode operations. Such devices use digital counting techniques to detect and decode all the 16 DTMF tone pairs into a 4-bit code output. Highly accurate switched capacitor filters are implemented to divide tone signals into low and high group signals. A built-in dial tone rejection circuit is provided to eliminate the need for pre-filtering.

Selection Table
Function Part No. HT9170B HT9170D Operating Voltage 2.5V~5.5V 2.5V~5.5V OSC Frequency 3.58MHz 3.58MHz Tristate Data Output Power Down 1633Hz Inhibit DV DVB Package 18 DIP 18 SOP

Block Diagram
P W D N X 2 X 1 3 .5 8 M H z C ry s ta l O s c illa to r B ia s C ir c u it V re f G e n e ra to r S te e r in g C o n tr o l C ir c u it V R E F R T /G T E S T D V D V B

V P V N G S

L o w G ro u p F ilte r O P A P r e - F ilte r H ig h G r o u p F ilte r

F re q u e n c y D e te c to r

C o d e D e te c to r

L a tc h & O u tp u t B u ffe r

D 0 D 1 D 2 D 3

IN H

O E

Rev. 1.11

February 23, 2009

HT9170B/HT9170D
Pin Assignment
V P 1 2 3 4 5 6 7 8 9 V N G S V R E F IN H P W D N X 1 X 2 V S S 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 V D D R T /G T E S T D V D 3 D 2 D 1 D 0 O E V P 1 2 3 4 5 6 7 8 9 V N G S V R E F IN H P W D N X 1 X 2 V S S 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 V D D R T /G T E S T D V D 3 D 2 D 1 D 0 O E

H T 9 1 7 0 B 1 8 D IP -A

H T 9 1 7 0 D 1 8 S O P -A

Pin Description
Pin Name VP VN GS VREEF X1 X2 PWDN INH VSS OE I/O I I O O I O I I I oscillator VREF Internal Connection Operational Amplifier Description Operational amplifier non-inverting input Operational amplifier inverting input Operational amplifier output terminal Reference voltage output, normally VDD/2 The system oscillator consists of an inverter, a bias resistor and the necessary load capacitor on chip. A standard 3.579545MHz crystal connected to X1 and X2 terminals implements the oscillator function. Active high. This enables the device to go into power down mode and inhibits the oscillator. This pin input is internally pulled down. Logic high. This inhibits the detection of tones representing characters A, B, C and D. This pin input is internally pulled down. Negative power supply, ground D0~D3 output enable, high active Receiving data output terminals OE=H: Output enable OE=L: High impedance Data valid output When the chip receives a valid tone (DTMF) signal, the DV goes high; otherwise it remains low. Early steering output (see Functional Description) Tone acquisition time and release time can be set through connection with external resistor and capacitor. Positive power supply, 2.5V~5.5V for normal operation

CMOS IN Pull-low CMOS IN Pull-low CMOS IN Pull-high CMOS OUT Tristate

D0~D3

DV EST RT/GT VDD

O O I/O

CMOS OUT CMOS OUT CMOS IN/OUT

Rev. 1.11

February 23, 2009

HT9170B/HT9170D
Approximate internal connection circuits
O P E R A T IO N A L A M P L IF IE R V R E F
X 1 V N V P
V O P A V +

O S C IL L A T O R
X 2

C M O S IN P u ll- h ig h
E N

C M O S O U T T r is ta te

G S

O P A

2 0 p F

1 0 M

1 0 p F

C M O S O U T

C M O S IN /O U T

C M O S IN P u ll- lo w

Absolute Maximum Ratings

Supply Voltage ............................................-0.3V to 6V Input Voltage..............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...........................-20C to 75C

Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

D.C. Characteristics
Symbol VDD IDD ISTB VIL VIH IIL IIH ROE RIN IOH IOL fOSC Parameter Operating Voltage Operating Current Standby Current Low Input Voltage High Input Voltage Low Input Current High Input Current Pull-high Resistance (OE) Input Impedance (VN, VP) Source Current (D0~D3, EST, DV) Sink Current (D0~D3, EST, DV) System Frequency Test Conditions VDD 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V Conditions PWDN=5V VVP=VVN=0V VVP=VVN=5V VOE=0V VOUT =4.5V VOUT =0.5V Crystal=3.5795MHz Min. 2.5 4.0 60 -0.4 1.0 3.5759 Typ. 5 3.0 10 100 10 -0.8 2.5 3.5795 Max. 5.5 7 25 1.0 0.1 0.1 150 3.5831

Ta=25C Unit V mA mA V V mA mA kW MW mA mA MHz

Rev. 1.11

February 23, 2009

HT9170B/HT9170D
A.C. Characteristics
Symbol DTMF Signal 3V Input Signal Level 5V Twist Accept Limit (Positive) Twist Accept Limit (Negative) Dial Tone Tolerance Noise Tolerance Third Tone Tolerance Frequency Deviation Acceptance Frequency Deviation Rejection tPU Power Up Time (See Figure 4.) 5V 5V 5V 5V 5V 5V 5V 5V -36 -29 3.5 VSS<(VVP,VVN)<VDD 100 Hz -3V<VIN<3V RL>100kW No load 5 20 20 10 10 18 -12 -16 30 -6 1 1.5 22 8.5 42 42 11 60 dB dB dB dB dB % % ms dBm Parameter Test Conditions VDD Conditions Min. fOSC=3.5795MHz, Ta=25C Typ. Max. Unit

Gain Setting Amplifier RIN IIN VOS PSRR CMRR AVO fT VOUT RL CL VCM Input Resistance Input Leakage Current Offset Voltage Power Supply Rejection Common Mode Rejection Open Loop Gain Gain Band Width Output Voltage Swing Load Resistance (GS) Load Capacitance (GS) Common Mode Range 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 10 0.1 25 60 60 65 1.5 4.5 50 100 3.0 MW mA mV dB dB dB MHz VPP kW pF VPP

Steering Control tDP tDA tACC tREJ tIA tIR tPDO tPDV tDOV tDDO tEDO Tone Present Detection Time Tone Absent Detection Time Acceptable Tone Duration Rejected Tone Duration Acceptable Inter-digit Pause Rejected Inter-digit Pause Propagation Delay (RT/GT to DO) Propagation Delay (RT/GT to DV) Output Data Set Up (DO to DV) Disable Delay (OE to DO) Enable Delay (OE to DO) 16 4 8 12 4.5 300 50 ms ms ms ms ms ms ms ms ms ns ns

Note: DO=D0~D3

Rev. 1.11

February 23, 2009

HT9170B/HT9170D
V 1 2 3 1 0 0 k W 5 3 .5 7 9 5 4 5 M H z 7 8 2 0 p F 2 0 p F 9 6 4 V P V N G S V R E F IN H P W D N X 1 X 2 V S S V D D R T /G T E S T D V D 3 D 2 D 1 D 0 O E 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 3 0 0 k W
D D

0 .1 m F

T o n e 0 .1 m F

1 0 0 k W

H T 9 1 7 0 B /D

Figure 1. Test circuit

Functional Description
Overview The HT9170B/D tone decoders consist of three band pass filters and two digital decode circuits to convert a tone (DTMF) signal into digital code output. An operational amplifier is built-in to adjust the input signal (refer to Figure 2).
C V
i

When input signals are recognized to be effective, DV becomes high, and the correct tone code (DTMF) digit is transferred. Steering control circuit The steering control circuit is used for measuring the effective signal duration and for protecting against drop out of valid signals. It employs the analog delay by external RC time-constant controlled by EST. The timing is shown in Figure 3. The EST pin is normally low and draws the RT/GT pin to keep low through discharge of external RC. When a valid tone input is detected, EST goes high to charge RT/GT through RC. When the voltage of RT/GT changes from 0 to VTRT (2.35V for 5V supply), the input signal is effective, and the correct code will be created by the code detector. After D0~D3 are completely latched, DV output becomes high. When the voltage of RT/GT falls down from VDD to VTRT (i.e.., when there is no input tone), DV output becomes low, and D0~D3 keeps data until a next valid tone input is produced. By selecting adequate external RC value, the minimum acceptable input tone duration (tACC) and the minimum acceptable inter-tone rejection (tIR) can be set. External components (R, C) are chosen by the formula (refer to Figure 5.): tACC=tDP+tGTP; tIR=tDA+tGTA; where tACC: Tone duration acceptable time tDP: EST output delay time (LH) tGTP: Tone present time tIR: Inter-digit pause rejection time tDA: EST output delay time (HL) tGTA: Tone absent time

R 1

V P V N

R F

G S V R E F

H T 9 1 7 0 B /D

( a ) S ta n d a r d in p u t c ir c u it
C 1 V V
i1 i2

R 1 R 2 R 3 R 4 R 5

V P V N

C 2

G S V R E F

H T 9 1 7 0 B /D

( b ) D iffe r e n tia l in p u t c ir c u it
Figure 2. Input operation for amplifier application circuits The pre-filter is a band rejection filter which reduces the dialing tone from 350Hz to 400Hz. The low group filter filters low group frequency signal output whereas the high group filter filters high group frequency signal output. Each filter output is followed by a zero-crossing detector with hysteresis. When each signal amplitude at the output exceeds the specified level, it is transferred to full swing logic signal.

Rev. 1.11

February 23, 2009

HT9170B/HT9170D
Timing Diagrams
tR T o n e tD
P E J

t IA T o n e n tD
P

t IR T o n e n + 1

tD
A

tD
P

E S T tA V
C C

R T /G T

T R T

tG tP
D O

T P

tG

T A

D 0 ~ D 3

T o n e C o d e n tP
D V

1 tD

T o n e C o d e n
O V

T o n e C o d e n + 1 tP
D V

D V tD O E
D O

tE

D O

Figure 3. Steering timing

T o n e

T o n e

P W D N

E S T tP
U

Figure 4. Power up timing

Rev. 1.11

February 23, 2009

HT9170B/HT9170D
V V D D
D D

V V D D C

D D

H T 9 1 7 0 B /D
R T /G T E S T R

H T 9 1 7 0 B /D
C R 1 D 1 R 2 R T /G T E S T

(a) Fundamental circuit: tGTP = R C Ln (VDD / (VDD - VTRT)) tGTA = R C Ln (VDD / VTRT)
V V D D
D D

(c) tGTP > tGTA : tGTP = R1 C Ln (VDD / (VDD - VTRT)) tGTA = (R1 // R2) C Ln (VDD / VTRT)

H T 9 1 7 0 B /D
C R 1 D 1 R 2 R T /G T E S T

(b) tGTP < tGTA : tGTP = (R1 // R2) C Ln (VDD - VTRT)) tGTA = R1 C Ln (VDD / VTRT) Figure 5. Steering time adjustment circuits DTMF dialing matrix
C O L 1 C O L 2 R O W 1 R O W 2 R O W 3 R O W 4 7 * 0 4 8 # 1 5 9 D 2 6 C C O L 3 3 B C O L 4 A

DTMF data output table Low Group (Hz) 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 Note: Z High impedance; Rev. 1.11 High Group (Hz) 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633 ANY Any digit 7 February 23, 2009 Digit 1 2 3 4 5 6 7 8 9 0 * # A B C D ANY OE H H H H H H H H H H H H H H H H L D3 L L L L L L L H H H H H H H H L Z D2 L L L H H H H L L L L H H H H L Z D1 L H H L L H H L L H H L L H H L Z D0 H L H L H L H L H L H L H L H L Z

HT9170B/HT9170D
Data output The data outputs (D0~D3) are tristate outputs. When OE input becomes low, the data outputs (D0~D3) are high impedance.

Application Circuits
Application Circuit 1
V 1 2 3 1 0 0 k W 5 6 7 X 't a l 9 C 1 C 2 V S S 8 4 V P V N G S V R E F IN H P W D N X 1 X 2 V S S V D D R T /G T E S T D V D 3 D 2 D 1 D 0 O E 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 T o o th e r d e v ic e 3 0 0 k W
D D

0 .1 m F

D T M F 0 .1 m F

1 0 0 k W

T o o th e r d e v ic e

H T 9 1 7 0 B /D

Note:

Xtal = 3.579545MHz crystal C1 = C2 @ 20pF Xtal = 3.58MHz ceramic resonator C1 = C2 @ 39pF

Application Circuit 2
V 0 .1 m F D T M F 0 .1 m F R 2 R 3 R 4 5 T o o th e r d e v ic e 6 7 8 9 V S S R 1 1 8 0 p F 2 3 4 R 5 1 V P V N G S V R E F IN H P W D N X 1 X 2 V S S D 3 D 2 D 1 D 0 O E D V V D D R T /G T E S T 1 8 1 7 1 6 3 0 0 k W 1 5 1 4 1 3 1 2 1 1 1 0 T o o th e r d e v ic e
D D

0 .1 m F

R 3 + R 5 = R 2 R 1 + R 3 R 2 R 4 R 3 = R 2 + R 4 A v =

R 5

E x a m p le : A v R 1 R 2 R 3 R 4 R 5

= 3 = 6 = 1 = 6 = 1 = 3

0 k W 0 0 k W 0 k W 5 0 k W 0 0 k W

X 't a l C 1 C 2

H T 9 1 7 0 B /D

Note:

Xtal = 3.579545MHz crystal C1 = C2 @ 20pF Xtal = 3.58MHz ceramic resonator C1 = C2 @ 39pF

Rev. 1.11

February 23, 2009

HT9170B/HT9170D
Package Information
18-pin DIP (300mil) Outline Dimensions
A
1 8 1 0 9 1

A
1 8 1 0 9 1

H C

C D

D
E G F I

E G F

Fig1. Full Lead Packages

Fig2. 1/2 Lead Packages

MS-001d (see fig1)

Symbol A B C D E F G H I
MS-001d (see fig2)

Dimensions in mil Min. 880 240 115 115 14 45 300 Nom. 100 Max. 920 280 195 150 22 70 325 430

Symbol A B C D E F G H I

Dimensions in mil Min. 845 240 115 115 14 45 300 Nom. 100 Max. 880 280 195 150 22 70 325 430

Rev. 1.11

February 23, 2009

HT9170B/HT9170D
MO-095a (see fig2)

Symbol A B C D E F G H I

Dimensions in mil Min. 845 275 120 110 14 45 300 Nom. 100 Max. 885 295 150 150 22 60 325 430

Rev. 1.11

10

February 23, 2009

HT9170B/HT9170D
18-pin SOP (300mil) Outline Dimensions

1 8 A 1

1 0 B 9

C C ' G H D E F

MS-013

Symbol A B C C D E F G H a

Dimensions in mil Min. 393 256 12 447 4 16 8 0 Nom. 50 Max. 419 300 20 463 104 12 50 13 8

Rev. 1.11

11

February 23, 2009

HT9170B/HT9170D
Product Tape and Reel Specifications
Reel Dimensions
T 2 D

T 1

SOP 18W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.01.5 13.0
+0.5/-0.2

2.00.5 24.8
+0.3/-0.2

30.20.2

Rev. 1.11

12

February 23, 2009

HT9170B/HT9170D
Carrier Tape Dimensions

D
E F

P 0

P 1
t

W C

B 0

D 1

P A 0

K 0

R e e l H o le IC p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e .

SOP 18W Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.0
+0.3/-0.1

16.00.1 1.750.1 11.50.1 1.50.1 1.50

+0.25/-0.00

4.00.1 2.00.1 10.90.1 12.00.1 2.80.1 0.300.05 21.30.1

Rev. 1.11

13

February 23, 2009

HT9170B/HT9170D

Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) G Room, 3 Floor, No.1 Building, No.2016 Yi-Shan Road, Minhang District, Shanghai, China 201103 Tel: 86-21-5422-4590 Fax: 86-21-5422-4705 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, Gaoxin M 2nd, Middle Zone Of High-Tech Industrial Park, ShenZhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com

Copyright 2009 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

Rev. 1.11

14

February 23, 2009