From Nano Devices to Nano Circuits: A long way still ahead

Jos L. Huertas
IMSEIMSE-CNM

U e s dad Universidad de Se a & CS C Sevilla CSIC

Acknowledgement for the RTD material to J.M. Quintana and M.J. Avedillo, IMSEM J Avedillo, IMSE-CNM
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Goal
Through an overview of problems and p potential solutions solutions Motivate a discussion on how future devices, devices, beyond MOS might be accepted MOS, by the designer community. community.

Outline
Microelectronics today: needs and trends
Limitations Predictions

Extending MOS beyond its limits New Paradigms Challenges to enable new devices Conclusions
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Introduction
Feature size approaching th physical f ti F t i hi the h i l frontiers Fabrication process reaching limits Power cons mption Po er consumption a main concern Quantum effects need to be accounted for Solution? Nanotechnology? A diversity of solutions are emerging Is any of the new devices feasible for being incorporated into the design flow? What is needed?

Todays Today s Systems

( , , ) Multimedia (Audio, Video, Radar) Computing (Portable, Powerful, Friendly) C i i (Body, Home, C Offi Connectivity (B d H Car, Office, W ld) World)

All-inAll-in-One:
One device. One Operating System One human interface

Ultra Low Power Power. Very High Speed Very Reliable Performance Low Cost
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Moores Law (# transistors) Moore s

100b 10b 1b 100,000 10,000 1,000 1 000 100 4004 10 8080 1 '70 '75 '80 '85 '90 '95 '00 '05 '10 '15 20 25 30
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Number of transistors on a chip in thousands

Moores law prediction processors

??
1-billion transistors Pentium III Xeon

100-billion transistors

80386 80286 8086 80486

Pentium III

Pentium II Pentium Pro Pentium

Moore s Law referred to Gate Length Moores In the future More Moore??

Downscaling vs Lithography
10 um Motivation:
Modern CMOS Beginning of Submicron CMOS

density speed functionality cost/bit

1 um 34 Years of Scaling History 100 nm

Deep UV Litho 90 nm in 2004

10 nm

Every generation Feature size shrinks by 70% Transistor density doubles Wafer cost increases by 20% Chip cost comes down by 40% Generations occur regularly On average every 2 9 years over 2.9 the past 34 years Recently every 2 years

Presumed Limit to Scaling

1 nm 1970

1980

1990

2000

2010

2020
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Source: Dennis Buss, TI, 2005

TopTop-down & Bottom-up Views Bottom-

Convergence: Nano/Tera

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However besides Digital Digital

the World is continuous as well as the ways we interact with it

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The Electronic Paradigm

12

A typical System

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Future Roadmap: 2D
MOS Transistor

in the future? i th f t ?
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What is Industry trying?

Todays MOS Todays MOS

2014 MOS

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MOS: the Main Character

Capabilities: C biliti
Switching: 2 well-defined, noise-inmune, stable wellnoisestates Amplification: Local power gain (negative)

WellWell-tailored to the Electronics needs Backed by an extensive know-how at device, knowcircuit and system levels Approaching important botlenecks Interconnects are becoming another problem Is there a limit for its supremacy?
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Hierarchy of Limits
System Circuit Device D i Material Fundamental

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NanoNano-Scale MOSFET
Ph hoto Courte esy: Fujitsu Labs u

Metal Oxide Semiconductor Field Effect Transistor

Th t i ld i Three terminal device Source, gate and drain Vg controls the conduction from source to drain g Half thickness of the gate is called Feature size Current feature sizes in production 45nm (TSMC) Demonstrated feature sizes up to 10-20nm (IBM, et al ) 10(IBM al.).
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NanoNano-Scale MOSFETs

UltraUltra-thin Body SOI MOS Band- g Band-Engineered Transistor Vertical Transistor FINFET DoubleDouble-gate Transistor ...

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Predicted MOS Evolution: SIA

Year of Production Technology Node MPU Physical Gate Length (nm)

2010
hp45

2012

2013
hp32

2015

2016
hp22

2018

18

14

13

10

Nominal gate leakage current 1.9E+03 2.4E+03 7.7E+03 1.0E+04 1.9E+04 2.4E+04 density limit (at 25 C) (A/cm2) 25C) Nominal power supply voltage 1.0 0.9 0.9 0.8 0.8 0.7 (Vdd) (V) Nominal high-performance NMOS sub-threshold leakage 0.1 0.1 0.3 0.3 0.5 0.5 current, Isd,leak (at 25C) (mA/m) Nominal high-performance high performance NMOS drive current, Id,sat (at 1900 1790 2050 2110 2400 2190 Vdd, at 25C) (mA/m) High-performance NMOS 0.39 0.30 0.26 0.18 0.15 0.11 intrinsic delay, = Cgate * Vdd / Id,sat (ps) NMOSFET static power dissipation due to drain and gate 1 10E-06 9 90E-07 2 97E-06 2 64E-06 4 40E-06 3 85E-06 1.10E-06 9.90E-07 2.97E-06 2.64E-06 4.40E-06 3.85E-06 leakage (W/m)

IOFF IOFF ION ION IOFF

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Device Summary

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Challenges
Difficulties
High l t i fi ld Hi h electric fields Power supply vs. threshold voltage Heat dissipation Interconnect delays Vanishing bulk properties Shrinkage of gate oxide layer Too many problems to continue miniaturization as physical limits approach Proposed solutions are short term

Open Problems
Improve lithographic precision (eBeam) Explore new materials (GaAs, SiGe, etc.) As a long term goal explore new devices
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Sequels: a designer viewpoint

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Sequels: a designer viewpoint

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Circuit Design has to alleviate

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Circuit Design has to alleviate

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Reaching the limits

Then, MOS transistors and Moores law are alive but their limits are coming fast Fundamental
Thermodynamics QuantumQuantum-mechanics Electromagnetics

Technology
Variability Lithography

Power density Cost: ~2B/fab /x2 per each generation

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Hierarchy of Limits
System Circuit Device D i Material Fundamental

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Fundamental Limits

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Fundamental Device Limits

90 nm

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Generic Device Limits

Lithography Variability MOS Switching Energy MOS Transit Time Parameter Fluctuations Interconnect Response Time Interconnect Crosstalk
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The Interconnect Delay Problem

32

Interconnect new opportunities

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Generic System Limits

34

A System Example

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Summary of Limits

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However, However Variability is Increasing

Printing
Layout 0.25 0.18

Oxide variations

0.13

90-nm

65-nm

Figures courtesy Synopsys Inc.

http://vlsicad.ucsd.edu

ICCAD 2003

Discrete dopants

Chandu Visweswariah, 2004

Statistical Analysis and Design: From Picoseconds to Probabilities

2 of 86

249,403,263 Si atoms 68,743 donors 13,042 acceptors

D. J. Frank et al, Symp. VLSI Tech., 1999

Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 3 of 86

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The Subwavelength Crisis

38

CMOS Power/Speed Issues

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The Power Crisis

Year of Production 2010 2012 2013 2015 2016 2018

Watts/cm2

155

171 530

178 552

-----

205 635

-----

Watts/Chip W tt /Chi 480

Derived from ITRS data

We d W do not t know how to remove this much heat!

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Can we continue without limit?

Todays MOS Todays MOS

NO!!

2020 MOS

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Perhaps Nanoelectronics

will provide a solution p

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43

Nanoscale electronics involves new challenges

Deep submicron physical effects again threatening circuit performance and reliability More than Moore opportunities still require More Moore coexistence with conventional MOS circuits Emergence of new, very promising nano-sacle nanostructures (nano-wires, carbon tubes,...) must be (nanotubes,...) used to build new transistor-like devices, at least transistorin a first phase
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Computing Devices: a Roadmap

Switching d i S it hi devices of nanometer (below 100nm, f t (b l 100 typically 10nm) dimensions define nanotechnology.
Solid State Devices Molecular Devices

CMOS Devices

Quantum Devices

Nano CMOS

CNFET

SpinT

Quantum Dot

RTD

SET

Quantum

Electromechanical

Photoactive

Electrochemical
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Carbon Nanotube FET

Court tesy: IBM

CNT can be used as the conducting channel of a MOSFET. b d th d ti h l f MOSFET These new devices are very similar to the CMOS FETs. All CNFETs are pFETs by nature. nFETs can be made through Annealing Doping p g Very low current and power consumption Although tubes are 3nm thick CNFETs are still the size of the contacts, about 20nm. ,
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CNT Transistor
Questions for CNT FETs
1) Can CNT FET be smaller, faster and dissipate less energy than Si FET? 2) Is it possible t integrate individual CNT I ibl to i t t i di id l components in a complex circuit (billions of components per cm2)? 3) Is Ballistic Transport a big advantage?

j = env
S. J. Wind,J. Appenzeller, R. Martel, V. Derycke, and Ph. Avouris, Appl. Phys. Lett 80 (2002) 3817

vdrift = F

ndrift>nbal

e vb = t F m

For long channels, is ballistic transport possible in the high-current regime? 47 7th ICCDCS

Summary a d Challenges Su a y and C a e ges

CNTs are flexible tubes that can be made conducting or semiconducting. NanoNano-scale, strong and flexible. Challenges:
Multilevel interconnects not available Chip density still limited to the density of contacts. Tube density not entirely exploited Fabrication i till F b i ti is still a stochastic process t h ti Alternatives to gold contacts need to be found.

Open Problems and Initiatives: p

Fabrication using DNA for self assembly (Technion-Israel; (TechnionScience, Nov 2003) Memory array of nanotubes using j y y g junctions as bit storages (Lieber at Harvard) Using nanotube arrays to make computing elements (DeHon at Caltech) Fabricate FPGAs using CNFETs and STM (Avouris at IBM)
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Solid State Quantum Devices

Energy Bar rrier
Allowed Energy Levels

Bar rrier

Occupied Energy Levels

Occupied Energy Levels

Source S

Island I l d

Drain D i

Distance

Quantum effects used to build devices. Electrons confined on an island

Island can be created by using different band-gap d i I l d b db i diff bandb d devices in succession i i Island has certain allowed energy levels If allowed energy levels are filled then the device is in conduction

Types of devices
Resonant Tunneling Diode (RTD) Single Electron Transistor (SET) Quantum Dot (QD)

Blocking conduction due to unavailable energy levels is called coulomb blockade

Conduction can occur by y
Increasing source to drain voltage Applying Gate Bias
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Single Electron Transistors (SET)

Source Gate Cg Island

Drain Conductance changes in spurts as energy levels are discrete g p gy To go from conducting to non-conducting stage, it requires voltage nonsufficient for one electron to cross This is achieved by applying gate bias enough for just one electron charge -- hence the name SET Bias required for conduction is coulomb gap voltage Same device can act as pFET or nFET based on the barrier strength Applications: Extra sensitive charge meters CMOS style conducting devices

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Single Electron Transistor

g ( ) Single electron transistor (SET) Electron movements are controlled with single electron precision p Tunneling and Coulomb blockade
island gate

Single Electron Single-Electron Transistor has all problems of charge-based devices The Fan Out requirement is not satisfied? Fan-Out

source

drain

High error rate? Low speed? What about FET in single electron mode? single-electron
(FET will be 32-electron transistor by 2018)
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Resonant Tunneling Devices (diodes and t (di d d transistors) i t )

Many years of experimental studies of resonant tunneling structures
1974 1986 1986 1988 1990 1990 1991 1991 1992 1995 1999 2000 2001 2002 2002 2002 2002 2002 2003 2003 2004 Chang Reed Reed Broekaert Broekaert Mehdi Chen Smet Watanabe Moise Miyamoto Watanabe Ishikawa Kikuchi Kado Wernersson Malindretos Bjork Wang Ikeda Xu

1.00E 07 1.00E+07 1.00E+05 Jpeak, A/c cm2 1.00E+03 1.00E+01 1.00E-01 1.00E-03 1.00E-05 1.00E-07 1 10

FET
Jpeak Jvalley

100 1000 10000 Peak-to-Valley Ratio

100000 1000000

Can RTDs match FETs both in ION and IOFF?

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Spin transistors: Spin Transport

vs. Ch Charge T Transport? t?
Spin is a property of material particles (e.g. electron, proton etc.) To move spin from point A to point B requires moving material particle Question: Even if we are controlling spin we have still moving electrons. Dont we have the same problems as with charge-based devices? Don t chargeExamples of proposed Spin transistors:
Johnson tranistor Miziushima FIFS transistor SPICE transistor Ounadjela-Hehn transistor j Datta-Das transistor

Operation principle: control of spinpolarized flow of electrons Spin-valve (GMR) Magnetic tunnel junction M ti t lj ti Spin Transport in 2DEG
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Quantum Dots and Arrays

Dot occupied by Electron Dot unoccupied Inter-dot Barriers B i Outer Barriers

Courtesy: vortex.tn.tudelft.nl/ grkouwen/kouwen.html

3-dimensional island tunneling barrier State determined by presence of electron and not by conduction. Quantum cell array (QCA) is a lattice of these cells with 2 electrons confined. Occupied electrons are furthest from each other due to repulsive forces.
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An example: Quantum Cellular Automata

1 1 0 Stable 1 Unstable QCA Inverter 0 QCA Wi Wire 1

2 states 1 and 0. Electrostatic interaction of nearby cells makes the bits y flip. Input to the cell is by manipulating the Inter-dot barriers. InterLogic gates can be constructed. constructed
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Summary and Challenges

Summary
Electrons confined on an island. Allowed energy levels are discrete and allow the device to fluctuate between conducting and non-conducting states. nonSET 2 dimensional device with gate bias control. QD device with electron presence as state. QCA Arrays of QDs used for computing.

Challenges
Background charge may offset states (noise sensitivity) Sensitivity of tunneling current to barrier width (lithographic accuracy) Sensitivity to barrier widths Cryogenic operation

Open Problems
Lithographic methods with guaranteed accuracy g p g y Self assembly of systems Background charge elimination Synthesis and verification techniques needed Testing of these devices as stuck-at models may be inadequate. stuck56

Molecular Electronics
Incentives
Molecules are nano-scale M l l nanol Self assembly is achievable Very low-power operation lowHighly uniform devices

Quantum Effect Devices

Building quantum wells using molecules

Electromechanical Devices
Using mechanical switching of atoms or molecules

Electrochemical Devices
Chemical interactions to change shape or orientation

Photoactive Devices Ph t ti D i
Light frequency changes shape and orientation.

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Molecular Electronics

Thiol Thi l

Acetylene linkage Benzene ring

Mechanical synthesis
Molecules aligned using a scanning tunneling microscope (STM) Fabrication done molecule by molecule using STM

Chemical synthesis
Molecules aligned in place by chemical interactions Self assembly Parallel fabrication
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Example: An Atomic Relay

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Summary and Challenges

Summary
Parallel self assembly Very regular structures Many alternatives proposed but inherent problems Very low energy operation

Challenges
Signal restoration and gain Finding non-interacting chemicals nonChemical reactions stochastic with by-products bySlow operating speeds

Open Problems
Self assembling of devices Increased speed of operation Guaranteed switching of molecules (HP- UCLA devices) (HPSimulation models and CAD

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Emerging Device Summary

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New Devices are useful to Designers?

Research In Nanodevices will have a value if and only if We can find a way to cost-effectively build working costcircuits by connecting together TRILLIONS of such devices The new devices will be rid off the problems associated with scaled MOS Only those devices able to co-exist with MOS technologies cowill have a chance (at least for decades) Nanoelectronics technologies require Designers who are aware of manufacturing constraints Manufacturers who are aware of design needs However, However if new devices are available why not change the available, design paradigm to be rid off the slavery from MOS?
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LongLong-term Electronics

What Paradigm may be changed?

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Representation Levels
Multicore Von Neuman Analog Digital Scaled MOS Silicon Electric Charge

Architecture Architect re Data R D Representation i Device Material Supporting Variable

64

Now and Tomorrow: Alternative paradigms

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Emerging Architecture Summary

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Which of Current Nanoelectronic Concepts Will Become the NEW SWITCH?

QCA

Spintronics

FILTER
Molecular M l l Electronics 1D-devices 1D d i

???
NEW SWITCH

RTD RSFQ
Single Electronics

ANSWER: ANSWER

NONE YET!
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Nanoelectronics Evolution
RTD Single Electronics
RTD

Vertical Gate Structure

RTD

Molecular Switch

Bulk CMOS

SOI

Nanotubes N b

Today

2020

2040
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Why i Wh is so diffi lt t fi d a difficult to find successful substitute to traditional MOS? traditional Because size, speed & power are j t parts of the problem just t f th bl
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Multilevel Constraints for the Winner

Operation at room temperature Competitive yield Power efficiency (essentially at system level) Compatibility or Complementarity with MOS Speed advantage (at least, no disadvantage) Cost reduction Inclusion in conventional design flows
Electrical models Compatibility with standard simulators

Handling continuous and discrete-time signals discreteAdded value compared to scaled MOS in terms of density
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Complementary Criteria
SystemSystem-ability CoCo-hosting memory, logic, communication g y g Handling device variability Handling analog and digital signals Combining More Moore with More than Moore Complementing the other platforms (sensors, actuators, antennas, special functions) Efficient interconnect
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Main conclusion:

It is not a simple task to prove a device d i can b accepted!! be t d!!

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Device Lifecycle: from an Idea to its widespread use

Operation principle proven Technical feasibility Prototyping and measurements Productization
Is the device repeatable? A high yield is achievable?

Embeddability in the design flow y g Reasonable Design Productivity y Viability for basic circuits Use of basic circuits in systems
Are systems beneffitting somehow from the new device? D i titi d t ? Does it give any competitive advantage?
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Focusing on Design Productivity

Is it feasible to design g a 100-Billion-Transistor SOC in less than 100 days? d ? Are new devices fully embedded in the design flow? A/MS=analog/mixed signal ASIC = application-specific IC li i ifi CPU = central processing unit PLD = programmable logic device

I/O pads CPU core I/O pads DSP core DSP book

Memory I/O pads O

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Control A/MS I/O pads

Simplified Design Flow

System Conception & Partition

Models for new devices

Sensors, Sensors etc

Analog & RF

Digital

Simulation Simulation

Simulation

Simulation

Integration I t ti Global Simulation

Lay-Out
75

Simulation Strategy
QmQm-Effects in MOS devices QuantumQuantum-mechanical modeling a d u e ca s u at o and numerical simulation Spice circuit models Circuit Simulation

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Simulation Strategy
QmQm-Effects in MOS devices QuantumQuantum-mechanical modeling a d u e ca s u at o and numerical simulation Spice circuit models Circuit Simulation

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Simulation Strategy
QmQm-Effects in MOS devices QuantumQuantum-mechanical modeling a d u e ca s u at o and numerical simulation Spice circuit models Circuit Simulation

78

Simulation Strategy
QmQm-Effects in MOS devices QuantumQuantum-mechanical modeling a d u e ca s u at o and numerical simulation Spice circuit models Circuit Simulation

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How to proceed when a device does seem mature?

Using RTDs in Circuits: An U i RTD i Ci it A example of enabling new devices

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Device Validation Procedure Validation

Physical Mechanism: RTD principle of Mechanism: operation p Basic Device Concept: MOBILE Modelling electrical) M d lli (electrical) l ti l l) Basic Building Blocks: Threshold gates as c u d g oc s es o d Simulation models Use in Systems A detailed view will be given later in this subject

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General Conclusions
MOS technology is approaching saturation problems/limits in the nanometer range Several new possibilities emerging Validation of the new devices must be done at system level Competitive circuit structures, Spicestructures Spicecompatible simulation models, and MOSmodels, MOScompatibility are a demand for the emerging devices.
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