Scheme of valuation

Code No: L0422

R07

Set No. 3

IV B.Tech II Semester Examinations, APRIL 2012 DIGITAL DESIGN THROUGH VERILOG

(Common to Bio-Medical Engineering, Electronics and Computer Engineering, Electronics and Communication Engineering) 1.a) What is verilog HDL? (2marks)

Discussion of Various modeling styles available in verilog HDL Circuit level Gate level Data Flow Behavioral Level Description of each level
1b)Logic values available in verilog HDL

(2marks) (4marks) (4 marks)

Logic values Signal lines, logic values appearing on signal lines, etc., can normally take two logic levels: 1 signifies the 1 or high or true level 0 signifies the 0 or low or false level. Two additional levels are also possible designated as x and z. Here x represents an unknown or an uninitialized value. This corresponds to the dont care case in logic circuits. z represents / signifies a high impedance state. This is possible when a signal line is tri-stated or left floating. The following are noteworthy here: When a variable in an expression is in the z state, the effect is the same as it having z value. But when an input to a gate is in the z state, it is equivalent to having the x value. If the input to a MOS switch is in the z state, its output too remains at the z state. With a few exceptions all data types in Verilog can take on all the 4 logic values or levels. It cannot store any value. The trireg cannot take on the z value
Types of constants in verilog HDL + Example for each (2marks+ 2marks)

There are three kinds of constants in verilog HDL: integer, real and string. Real and String constants are not supported for synthesis. An integer can be written either in simple decimal or base format

2 a).What are the built-in primitive gates available in Verilog HDL? Explain how these can be used to describe hardware. (2marks+ 6marks)

Primitive logic gates are part of the Verilog language. Any circuit can be modeled by using continuous assignment of the primitive gates. They can be instantiated directly in other modules using the gate instantiation. The syntax for instantiation of gate Syntax Gate type [instance_name] (output, input_1, input_2,..., input_N), Syntax Gate_type (drive_strength) # (delays) instance_name1(output_1, output_2, ..., output_n, input), instance_name2(out1, out2, ..., outN, in); Basic gate primitives in Verilog Gate Mode of instantiation AND and ga ( o, i1, i2, . . . i8); OR or gr ( o, i1, i2, . . . i8); NAND nand gna ( o, i1, i2, . . . i8); NOR nor gnr ( o, i1, i2, . . . i8); XOR xor gxr ( o, i1, i2, . . . i8); XNOR xnor gxn ( o, i1, i2, . . . i8); BUF buf gb ( o1, o2, . i); NOT not gn (o1, o2, o3, . . . i);
2. b). Implement the gate level description of 4-to-1 multiplexer with relevant logic diagram and verilog source code (2marks+ 6marks) Logic diagram

Verilog source code for 4-to-1 multiplexer module mux4( input a, b, c, d) input [1:0] sel, output out ); wire [1:0] sel_b; not not0( sel_b[0], sel[0] ); not not1( sel_b[1], sel[1] ); Basic logic gates are built-in primitives meaning there is no need to define a module for these gates wire n0, n1, n2, n3; and and0( n0, c, sel[1] ); and and1( n1, a, sel_b[1] ); sel[0] and and2( n2, d, sel[1] ); and and3( n3, b, sel_b[1] ); sel[1] wire x0, x1; nor nor0( x0, n0, n1 ); c nor nor1( x1, n2, n3 ); a out wire y0, y1; d or or0( y0, x0, sel[0] ); b or or1( y1, x1, sel_b[0] ); nand nand0( out, y0, y1 ); endmodule

3.a) What are the primary mechanisms for modeling the behavior of a logic design using Verilog HDL? Explain them with necessary syntax and suitable example. (3marks+ 5marks) The behavior of the entity is expressed using sequentially executed, procedural code, which is very similar in syntax and semantics to that of a high level programming languages such as C or Pascal. Process statement is the primary mechanism used to model the behavior of an entity. Process statement has a declarative part (before the keyword begin) and a statement part (between the keywords begin and end process). The statements appearing within the statement part are sequential statements and are executed sequentially . The procedure assignment is characterized by the following: The assignment is done through the = symbol (or the <= symbol) as was the case with the continuous assignment earlier. An operation is carried out and the result assigned through the = operator to an operand specified on the left side of the = sign for example,N = ~N; Here the content of reg N is complemented and assigned to the reg N itself.The assignment is essentially an updating activity.

The operation on the right can involve operands and operators. The operands can be of different types logical variables, numbers real or integer and so on. All the operands are given in Tables 6.1 to 6.9. The format of using them and the rules of precedence remain the same. The operands on the right side can be of the net or variable type. They can be scalars or vectors. It is necessary to maintain consistency of the operands in the operation expression e.g., N = m / l; Here m and l have to be same types of quantities specifically a reg, integer, time, real, realtime, or memory type of data declared inadvance. The operand to the left of the = operator has to be of the variable (e.g., reg) type. It has to be specifically declared accordingly. It can be a scalar, a vector, a part vector, or a concatenated vector.

3.b).What is the difference between an intra-statement delay and an inter-statement delay? Explain using an example. (4marks+ 4marks) Delays can be specified in two different forms: Inter-statement delay. This is the delay by which a statements execution is delayed. Intra-statement delay. This is the delay between completing the value of the righthand side expression and its assignment to the left-hand side. Here is an example of an inter-statement delay. \ sum = (a ^ b) ^ cin; #4 t1 = a & cin; The delay in the second statement specifies that the execution of the assignment is to be delayed by 4 time units. That is, after the first statement executes, wait for 4 time units, and then execute the second assignment. Here is an example of intra-statement delay. sum = #3(a ^ b) ^ cin; i. ii. The delay in this assignment means that the values of the right-hand side expression is to the computed first, wait for 3 time units, and then assign the value to sum. If no delays are specified in a blocking procedural assignment, zero delay is the default that is assignment occurs instantaneously. If no delay is specified in a nonblocking assignment, the assignment occurs at the end of the time step that is after all events that occur at that time have been completed. 4.a) Describe the continuous assignment feature of Verilog HDL with suitable example. Continuous Assignment Structures (4marks) Continuous assignments are the most basic assignment I data flow modeling. They are used to model combinational logic circuits. example A simple two input AND gate in data flow format has the form assign c = a && b; Here

assign is the keyword carrying out the assignment operation. This type of assignment is called a continuous assignment. a and b are operands typically single-bit logic variables. && is a logic operator. It does the bit-wise AND operation on the two operands a and b. = is an assignment activity carried out. c is a net representing the signal which is the result of the assignment. Continuous Assignments and Strengths (4marks) A net to which a continuous assignment is being made can be assigned strengths for its logic levels. The procedure is akin to the strength allocation to the outputs Delays can be incorporated at the data flow level in different ways. Consider the combination of statements given bellow The assignment takes effect with a time delay of 2 time steps. If a or b changes in value, the program waits for 2 time steps, computes the value of c based on the values of a and b at the time of computation, and assigns it to c. In the interim period, a or b may change further, but c changes and takes the new value only 2 time steps after the change in a or b initiates it. wire c,a,b; assign#2 c=2&b;

Illustration of combining delays with assignments b) What are the switch level primitives and give their instantiations. Draw the basic switch circuit and its Verilog HDL code. (2marks+ 2marks +4marks) Verilog has the two basic switch level primitives nmos and pmos to do the design description at the switch level. Basic Switch Primitives Different switch primitives are available in Verilog. Consider an nmos switch. A typical instantiation has the form nmos (out, in, control); pmos (out, in, control); nmos a keyword represents an NMOS transistor functioning as a switch. The switch has three terminals in, out, and control. When the control input is at 1 (high) state, the switch is on. It connects the input lead to the output side and offers zero impedance. When the control input is low, the switch is OFF and output is left floating (z state). If the control is in the z or the x state, output may take corresponding values.

An NMOS switch An PMOS switch In the most general form of instantiation, strength values and delay values can be combined. For example, the instantiation

nmos (strong1, strong0) (delay_r, delay_f, delay_o ) gg (s1, s2, ctrl) ; means the following: It has strength strong0 when in the low state and strength strong1 when in the high state. When output changes state from low to high, it has a delay time of delay_r. When the output changes state from high to low, it has a delay time of delay_f. When output turns-off it has a turn-off delay time of delay _o. rnmos, pmos, and rpmos switches too can be instantiated in the general form in the same manner. 5. a) Can a function call a task? Can a task have delays? Illustrate them with suitable examples (2marks+2marks+4marks) A Verilog HDL function is same as task, with very little difference, like function cannot drive more then one output, can not contain delays. Functions are defined in the module in which they are used. it is possible to define function in separate file and use compile directive 'include to include the function in the file which instantiates the task. Function cannot include timing delays, like posedge, negedge, # delay. Which means that function should be executed in "zero" time delay. Function can have any number of inputs and but only one output. The variables declared within the function are local to that function. The order of declaration within the function defines how the variables passed to the function by the Syntax function Function begin with key word function and ends with end function Inputs are declared after the key word function Example module simple_function(); function myfunction; input a,b,c,d; output[7:0] temp_out; begin myfunction=(a+b)*(c-d)); end endfunction endmodule . Task Tasks are used in all programming languages, generally known as Procedures or sub routines. Many lines of code are enclosed in task....end task brackets. Data is passed to the task, the processing done, and the result returned to a specified value. They have to be specifically called, with data in and outs, rather than just wired in to the general netlist. Included in the main body of code they can be called many times, reducing code repetition. Task is defined in the module in which they are used. it is possible to define task in separate file and use compile directive 'include to include the task in the file which instantiates the task. Task can include timing delays, like posedge, negedge, # delay.

gned output only at the end of task execution. Task can call another task or function. Task can be used for modeling both combinational and sequential logic. A task must be specifically called with a statement; it cannot be used within an expression as a function can. Syntax task Task begin with key word task ends Inputs and outputs are declared with end task after the key word Example module simple_task(); task convert; input[7:0] temp_in; output[7:0] temp_out; begin temp_out=(234)*temp_+32)) end endtask endmodule b) Define user-defined primitives with their syntax. Give an example of 4-to-1 multiplexer built using UDPs. (4marks+ 4marks) Verilog has the provision for the user to define primitives called user defined primitive (UDP) and use them. A UDP can be defined anywhere in a source text and instantiated in any of the modules. Their definition is in the form of a table in a specific format. It makes the UDP types of functions simple, elegant, and attractive. UDPs are basically of two types combinational and sequential. A combinational UDP is used to define a combinational scalar function and a sequential UDP for a sequential function Combinational UDPs (2marks) A combinational UDP accepts a set of scalar inputs and gives a scalar output. An inout declaration is not supported by a UDP. The UDP definition is on par with that of a module; that is, it is defined independently like a module and can be used in any other module. The definition cannot be within any other module. syntax Primitive udp-and(out,in1, in2); Sequential UDPs (2marks) Any sequential circuit has a set of possible states. When it is in one of the specified states, the next state to be taken is described as a function of the input logic variables and the present state. A positive or a negative going edge or a simple change in a logic variable can trigger the transition from the present state of the circuit to the next state. A sequential UDP can accommodate all these. syntax Primitive dlatch(q, din1, clk); Block diagram and truth table 4-to-1 multiplexer (2marks+ 2marks)

// 4-to-1 multiplexer. Define it as a primitive primitive mux4_to_1 ( output out,input ,i0, i1, i2, i3, s1, s0); table// i0 i1 i2 i3, s1 s0 : out 1 ? ? ? 0 0:1; 0 ? ? ? 0 0:0; ? 1 ? ? 0 1:1; ? 0 ? ? 0 1:0; ? ? 1 ? 1 0:1; ? ? 0 ? 1 0:0; ? ? ? 1 1 1:1; ? ? ? 0 1 1:0; ? ? ? ? x ?: x; ? ? ? ? ? x:x; Endtable endprimitive 6. a) Explain the concept of state machine chart realization through MUX and PLD devices. [4+4] b) Draw an ASM chart to describe a state machine that detects a sequence of three logic is occurring at the input and that asserts logic 1 at the output during the last state of the sequence. Write a two-process Verilog HDL description of the state machine.
(4marks+ 4marks)

An ASM chart that describe a mealy state machine which detects a sequence of 101 and that asserts a logical 1 at the output during the last state of the sequence is given below

Finite State Machine (FSM) Using Two Processes Diagram

7. Explain the design flow for FPGAs. By consider suitable example perform the design with the necessary design specifications, logic /state diagram, excitation/state table and relevant Verilog HDL source code, simulation and synthesis processes Design flow for FPGAs. Any example of the design with the necessary design specification logic /state diagram Excitation/state table Verilog HDL source code, simulation and synthesis processes (6marks) (2marks) (2marks) (2marks) (2marks) (2marks)

8. Write a Verilog HDL model that describes the behavior of a simplified 486 bus model with necessary state machine diagram. Test the model using a test bench. (8marks+8marks) SM diagram for 486 bus model