SARDAR RAJA COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING MICRO LESSON PLAN

SUBJECT NAME SUBJECT CODE YEAR / SEM

: DIGITAL ELECTRONICS : EC 2203 : II / III

COURSE / BRANCH: B.E / E.C.E

Handled By Mr.A.KARTHEESWARAN Asst.Prof / ECE

EC 2203 DIGITAL ELECTRONICS AIM To learn the basic methods for the design of digital circuits and provide the fundamental concepts used in the design of digital systems. OBJECTIVES To introduce basic postulates of Boolean algebra and shows the correlation between Boolean expressions To introduce the methods for simplifying Boolean expressions To outline the formal procedures for the analysis and design of combinational circuits and sequential circuits To introduce the concept of memories and programmable logic devices. To illustrate the concept of synchronous and asynchronous sequential circuits

TEXT BOOKS 1. M. Morris Mano, Digital Design, 3rd Edition, Prentice Hall of India Pvt. Ltd., 2003 / Pearson Education (Singapore) Pvt. Ltd., New Delhi, 2003. 2. S. Salivahanan and S. Arivazhagan, Digital Circuits and Design, 3rd Edition., Vikas Publishing House Pvt. Ltd, New Delhi, 2006 REFERENCES 1. John F.Wakerly, Digital Design, Fourth Edition, Pearson/PHI, 2006 2. John.M Yarbrough, Digital Logic Applications and Design, Thomson Learning, 2002. 3. Charles H.Roth. Fundamentals of Logic Design, Thomson Learning, 2003. 4. Donald P.Leach and Albert Paul Malvino, Digital Principles and Applications, 6th Edition, TMH, 2003. 5. William H. Gothmann, Digital Electronics, 2nd Edition, PHI, 1982. 6. Thomas L. Floyd, Digital Fundamentals, 8th Edition, Pearson Education Inc, New Delhi, 2003 7. Donald D.Givone, Digital Principles and Design, TMH, 2003.

EC 2203 DIGITAL ELECTRONICS UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES

LTPC 3104 12

Minimization Techniques: Boolean postulates and laws De-Morgans Theorem - Principle of Duality - Boolean expression - Minimization of Boolean expressions Minterm Maxterm Sum of Products (SOP) Product of Sums (POS) Karnaugh map Minimization Dont care conditions - Quine-McCluskey method of minimization. Logic Gates: AND, OR, NOT, NAND, NOR, ExclusiveOR and ExclusiveNOR Implementations of Logic Functions using gates, NANDNOR implementations Multi level gate implementations- Multi output gate implementations. TTL and CMOS Logic and their characteristics Tristate gates. UNIT II COMBINATIONAL CIRCUITS 12

Design procedure Half adder Full Adder Half subtractor Full subtractor Parallel binary adder, parallel binary Subtractor Fast Adder - Carry Look Ahead adder Serial Adder/Subtractor - BCD adder Binary Multiplier Binary Divider - Multiplexer/ Demultiplexer decoder encoder parity checker parity generators code converters - Magnitude Comparator. UNIT III SEQUENTIAL CIRCUITS 12

Latches, Flip-flops - SR, JK, D, T, and Master-Slave Characteristic table and equation Application table Edge triggering Level Triggering Realization of one flip flop using other flip flops serial adder/subtractor- Asynchronous Ripple or serial counter Asynchronous Up/Down counter - Synchronous counters Synchronous Up/Down counters Programmable counters Design of Synchronous counters: state diagram- State table State minimization State assignment - Excitation table and maps-Circuit implementation - Modulon counter, Registers shift registers - Universal shift registers Shift register counters Ring counter Shift counters Sequence generators. UNIT IV MEMORY DEVICES 12

Classification of memories ROM - ROM organization - PROM EPROM EEPROM EAPROM, RAM RAM organization Write operation Read operation Memory cycle -Timing wave forms Memory decoding memory expansion Static RAM Cell- Bipolar RAM cell MOSFET RAM cell Dynamic RAM cell Programmable Logic Devices Programmable Logic Array (PLA) - Programmable Array Logic (PAL) Field Programmable Gate Arrays (FPGA) - Implementation of combinational logic circuits using ROM, PLA, PAL UNIT V SYNCHRONOUS AND AYNCHRONOUS SEQUENTIAL CIRCUITS 12

Synchronous Sequential Circuits: General Model Classification Design Use of Algorithmic State Machine Analysis of Synchronous Sequential Circuits Asynchronous Sequential Circuits: Design of fundamental mode and pulse mode circuits Incompletely specified State Machines Problems in Asynchronous Circuits Design of Hazard Free Switching circuits. Design of Combinational and Sequential circuits using VERILOG TUTORIAL = 15 Hrs. TOTAL: 60 Hrs. MICRO LESSON PLAN

HOUR NO.

WEEK NO

1. 2. 3. I 4. 5. 6. 7. 8. 9. II 10. 11. 12 13 14 15 16 17 18 19 20 21 22 V 23 24 25 VI IV III

T/ R BOOK PAGE.NO NO UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES Minimization Techniques: Boolean T1 33 to 34 postulates and laws De-Morgans Theorem T1 34 to 37 Principle of Duality Boolean expression - Minimization of T1 40 to 44 Boolean expressions Minterm Maxterm - Sum of Products T1 51 to 59 (SOP) Product of Sums (POS) Karnaugh map Minimization Dont care conditionsT1 64 to 80 Quine-McCluskey method of minimization. Logic Gates: AND, OR, NOT, NAND, NOR, ExclusiveOR and Exclusive T1 80 to 82 NOR Implementations of Logic Functions using gates, T1 82 to 89 NANDNOR implementations Multi level gate implementations- Multi T1 89 to 94 output gate implementations. TTL and CMOS Logic and their characteristics Tristate T1 94 to 99 gates. UNIT II -COMBINATIONAL CIRCUITS Design procedure Half adder Full T1 111 to 112 Adder Half subtractor Full subtractor T1 112 to 113 Parallel T1 113 to 114 binary adder parallel binary Subtractor T1 114 to 115 Fast Adder T1 115 to 116 Carry Look Ahead adder T1 116 to 117 Serial T1 117 to 118 Adder/Subtractor BCD adder T1 118 to 119 Binary Multiplier T1 119 to 129 Binary Divider T1 129 to 131 Multiplexer/ T1 131 to 133 Demultiplexer decoder - encoder T1 133 to 134 parity checker T1 134 to 139 parity generators T1 139 to141 code T1 141 to 145 converters Magnitude Comparator T1 145 to 147 UNIT III - SEQUENTIAL CIRCUITS TOPIC

A/ V CLASS

Yes

Yes

Yes

Yes

Yes

26 27 28 29 30 31 32 33 VII 34 35 36 VIII 37 VI

Latches, Flip-flops - SR, JK, D, T, and Master-Slave Characteristic table and equation Application table Edge triggering Level Triggering Realization of one flip flop using other flip flops serial adder/subtractor- Asynchronous Ripple or serial counter Asynchronous Up/Down counter Synchronous counters Synchronous Up/Down counters Programmable counters Design of Synchronous counters: state diagramState table State minimization State assignment Excitation table and maps-Circuit implementation Modulon counter, Registers shift registers - Universal shift registers

T1 T2 T2 T1 T1 T1 T1 T1 T1 T1

167 to 180 180 to 203 217 to 219 219 to 220 220 to 225 225 to 227 227 to 232 232 to 236 236 to 239 239 to 240 240to 244 Yes Yes

38 39 40 41 42 43 44 45 46 47 48 49 X IX VIII

Shift register counters Ring counter T1 Shift counters - Sequence generators. UNIT IV - MEMORY DEVICES Classification of memories ROM T1 ROM organization PROM EPROM EEPROM T1 EAPROM, RAM RAM organization Write operation T1 Read operation Memory T1 cycle - Timing wave forms T1 Memory decoding memory expansion Static RAM CellBipolar RAM cell MOSFET RAM cell Dynamic RAM cell Programmable Logic Devices Programmable Logic Array (PLA) Programmable Array Logic (PAL) Field Programmable Gate Arrays (FPGA) Implementation of combinational logic circuits using ROM, PLA, PAL T1 T1 T1 T1 T1 T1 T1 T1

255 to 256 256 to 257 257 to 258 258 to 260 260 to 262 262 to 263 263 to 265 265 to 267 267 to 270 270 to 276 276 to 280 280 to 283 Yes Yes Yes

50 51 52 53 54 55 56 57 58 59 60 61

UNIT V SYNCHRONOUS AND AYNCHRONOUS SEQUENTIAL CIRCUITS Synchronous Sequential Circuits: T1 342 to 344 General Model T1 Classification 344 to 360 XI Design Use of Algorithmic State Machine Analysis of Synchronous Sequential Circuits Asynchronous Sequential Circuits: Design of fundamental mode and pulse mode circuits Incompletely specified State Machines XII Problems in Asynchronous Circuits Design of Hazard Free Switching circuits. Design of Combinational and Sequential circuits using VERILOG T1 T1 T1 T1 T1 T1 T1 T1 T1 398 to 400 400 to 404 404 to 408 408 to 420 420 to 430 Yes Yes 360 to 367 267 to 379 379 to 384 Yes

T1: M. Morris Mano, Digital Design, 3rd Edition, Prentice Hall of India Pvt. Ltd., 2003 / Pearson Education (Singapore) Pvt. Ltd., New Delhi, 2003.

ASSIGNMENT I

1. Using the Quine-Mc cluskey method,obtain all the prime implicants for the following

Boolean function.

F(v,w,x,y,z)= m (4,5,6,7,9,10,14,19,26,30,31). (16)

2. Simplify the following function and implement it as (i) two level AND OR gate network (ii) Multilevel NAND-NAND gate network (iii) Multilevel NOR-NOR gate network. F= (0, 2, 3, 6, 8, 11, 14, 15). (16)

ASSIGNMENT II

1. i Design a fill subtractor circuit using only NOR gates. (8) ii. Design a BCD adder using full adders and explain its operation. (8) 2. i Use IC7485 coparators to form a twelve bit comparator. Illustrate with a diagram. (8) ii. Show how a 16- input MUX such as IC74150 is used to generate the following function. Y=ABCD+BCD+ABC+ABCD (8)

ASSIGNMENT III

1. i. Realise T flip flop using JK flip flop. (10) ii. Write short notes on master slave flip flop. (6) 2. Design a sequence generator to generate the sequence 111101 using counter. (16)

ASSIGNMENT IV

1. a. The following function are to be realized with PLAs having both true and

complemented form. BY considering just the prime implicants of the individual function and their complements, determine the minimal number of product terms needed for each realization. In each case draw the logic diagram of the realization in PLD notations and show the corresponding PLA table
(i) (ii)

f1 (x,y,z)=m (3,6,7); f2 (x,y,z)=m (0,1,2,6,7); f13(x,y,z)=m (0,1,3,4,5); f1 (x,y,z)=m (0,1,2,5,7); f1 (x,y,z)=m (3,4,5,6) (16)

b.Explain in detail the PROM and PROM programming. (16)

ASSIGNMENT V

1. Determine static-1 hazard and static 0 hazards for the following function and obtain the

hazard free circuit. Z = x1x2+x2y (16)

2. Obtain a primitive flow table,a minimal row flow table and transition table for a fundamental mode asynchronous sequential network meeting the following requirement.

a. There are 2 inputs x1 and x2 and a single output z.

b.The inputs never change simultaneously.

c.The output is always to be 0 when x1=0,independent of the value of x2.

d.The output is to become 1 if x2 changes while x1=1 and is to remain 1 until x1 becomes 0 again. (16)

QUESTION BANK Unit I PART-A (2 Marks) 1) Prove that the logical sum of all minterms of a Boolean function of 2 variables is 1. 2) Show that a positive logic NAND gate is a negative logic NOR gate. 3) State De Morgan's theorem. 4) Draw an active high tri state buffer and write its truth table. 5) State the steps involved in Gray to binary conversion. 6) What is meant by bit & byte? 7) List the different number systems. 8) State the abbreviations of ASCII and EBCDIC code. 9) What are the different types of number complements? 10)State the associative property of Boolean algebra. 11)State the different classification of binary codes. 12)Simplify the following using De Morgan's theorem [((AB)'C)'' D]'. 13) What is a Karnaugh map? 14)Find the minterms & maxterms of the logical expression. 15) What are called dont care conditions? 16) Define binary logic. 17)Convert (634)8 to binary. 18)Convert 0.640625 decimal numbers to its octal equivalent. 19) What are the types of TTL logic? 20)State the advantages and disadvantages of TTL. 21) What are Logic gates? 22) What are the basic digital logic gates? 23) Which gates are called as the universal gates? What are its advantages? PART-B
1. (i) Express the Boolean function F= XY+XZ in product of maxterm. (6)

(ii)Reduce the following function using K-map technique. (10) the following Boolean function by using Quine-Mcclusky method F(A,B,C,D)=(0,2,3,6,7,8,10,12,13). (16) 3. (i) express the Boolean function as (1) POS form (2) SOP form D=(A+B)(B+C) . (4) (ii) minimize the given terms M(0,1,4,11,13,15)+ d(5,7,8) using Quine-Mcclusky method and verify the result using K-map technique. (12) 4. (i) implement the following function using NOR gates output= 1 when the input are m(0,1,2,3,4) output = 0 when the input are m(5,6,7) (8) (ii) Discuss the general characteristics of TTL and CMOS logic families. (8) 5. Determine the prime implicants of the function F (W,X,Y,Z) = _ m (1,4,6,7,8,9,10,11,15). (16)
2. Simplify 6. Reduce the following function using k-map technique

f(A,B,C,D)= _ M(0,3,4,7,8,10,12,14)+d(2,6).

(16)

7. Reduce the following function using K-map technique

F(A,B,C,D,E)= _ M(0,4,5,6,7,8,12,15,21,26,27,30)+d(1,9,17,19,25,29).
8. Explain in detail about interfacing CMOS and TTL device. (16) 9. Give the comparison between TTL and CMOS families. (16) 10. Explain with necessary diagrams MOS. (16)

(16)

Unit II PART-A (2 Marks)

1. Suggest a solution to overcome the limitation on the speed of an adder.

2. 3. 4. 5.

Differentiate a decoder from a demultiplexer. Write an expression for borrow and difference in a full subtractor circuit. Draw the circuits diagram for 4bit odd parity generator. Mention the classification of saturated bipolar logic families 6. Mention the different IC packages. 7. Define power dissipation. 8. What is propagation delay? 9. Write the truth table and logic circuit for half adder. 10. Explain the condition for parallel adder/subtractor. 11. Draw the logic circuit of full adder using half adder. 12. Explain the carry generate and carry propagate. 13. Define parity generator. 14. Draw the block diagram of multiplexers. 15. Define parity checker. 16. Explain even and odd parity. 17. Define combinational logic. 18. Explain the design procedure for combinational circuits. 19. Define decoder & binary decoder. 20. Define Encoder & priority Encoder.

PART-B (16 Marks) 1. Design a carry look ahead adder with necessary diagrams. (16) 2. (i) Implement full subtractor using demultiplexer.(10) (ii) Implement the given Boolean function using 8:1 multiplexer F (A, B, C) = (1, 3, 5, 6). (6) 3. (i) Drive the equation for a4bit look ahead carry adder circuit. (6) (ii) Draw and explain the block diagram of a 4bit serial adder to add the contents of two registers. (10) 4. (i) Multiply (1011)2 by (1101)2 using addition and shifting operation also draw block diagram of the 4bit by 4bit parallel multiplier. (8) (ii) Design and implement the conversion circuits for binary code to gray code. (8) 5. Explain the binary division and also explain the Non restoring division and Restoring division with Example. (16) 6. Design a logic circuit to convert the BCD code to Excess 3 codes. (16) 7. Explain the carry look ahead adder. (16) 8. Explain the BCD adder with examples. (16) 9. Explain the any two code converters. (16)

Unit III PART-A (2 Marks) 1. 2. 3. 4. Write down the characteristics equation for JK flipflop. Distinguish between synchronous and asynchronous sequential circuits. Mention any two differences between the edge triggering and level triggering. What is meant by programmable counter? Mention its application. 5. Define multiplexer. 6. What do you mean by comparator? 7. Define carry propagation delay. 8. Define race around condition. 9. What is edge-triggered flip-flop? 10. What is a master-slave flip-flop? 11. Define rise time & fall time. 12. Define skew and clock skew. 13. Define setup time and hold time. 14. Define register. 15. Define shift registers. 16. What are the different types of shift type? 17. Define synchronous & asynchronous sequential circuit. 18. What are the classifications of sequential circuits? 19. Define Flip flop. 20. What is the operation of JK flip-flop?

PART-B (16 Marks)

1. (i) Construct a clocked JK flipflop which is triggered at the positive edge of the clock

2.
3.

4.
5. 6.

pulse from a clocked SR flipflop consisting of NOR gate. (4) (ii) Design a synchronous up/down counter that will count up from zero to one to two to three, and will repeat whenever an external input x is logic0 and will count down from three to two to one to zero and will repeat whenever the external input x is logic 1. Implement your circuit with one TTL SN74LS76 device and one TTL SN74LS00 device. (12) (i) Write down the characteristic table for the JK flipflop with NOR gates. (4) (ii) What is meant by universal shift register? Explain the principle of operation of 4bit universal shift register? (12) (i) How will you convert a D flipflop into JK flipflop? (8) (ii) Explain the operation of a JK master slave flipflop. (8) Explain in detail the operation of a 4bit binary ripple counter. (16) Design an asynchronous sequential circuit with 2 inputs T and C. The output attains a value of 1 when T = 1 & C moves from 1 to 0. Otherwise the output is 0. (16) A asynchronous sequential machine has one input line where 0s and 1s are being

incident.The machine has to produce a output of 1 only when exactly two 0s are followed by a 1 or exactly two 1s are followed by a 0.Using any state assignment and JK flipflop, synthesize the machine (16) 7. Explain in detail about shift register. (16) 8. Design and explain the working of a synchronous mod 7 counters (16) 9. Develop the state diagram and primitive flow table for a logic system that has 2 inputs, x and y and an output z. And reduce primitive flow table. The behavior of the circuit is stated as follows. Initially x=y=0. Whenever x=1 and y = 0 then z=1, whenever x = 0 and y = 1 then z = 0.When x=y=0 or x=y=1 no change in z to remains in the previous state. The logic system has edge triggered inputs without having a clock .the logic system changes state on the rising edges of the 2 inputs. Static input values are not to have any effect in changing the Z output (16) 10. Obtain the primitive flow table for an asynchronous circuit that has two inputs x, y and one output Z. An output z =1 is to occur only during the input state xy = 01 and then if the only if the input state xy =01 is preceded by the input sequence. (16) Unit IV PART-A (2 Marks)
1. Compare and contrast static RAM and dynamic RAM.

2. What is PAL? How does it differ from PLA? 3. What are meant by memory expansion? Mention its limit. 4. What are the advantages of static RAM compared to Dynamic RAM? 5. What is programmable logic array? How it differs from ROM? 6. Give the classification of PLDs. 7. Define PLA 8. Define PAL 9. Why was PAL developed? 10. Define GAL 11. What is CPLD? 12. What is Read and Write operation? 13. Define Static RAM and dynamic RAM. 14. Define Cache memory. 15. Give the feature of flash memory. 16. What are the types of ROM? 17. Explain any two types of ROM. PART-B (16 Marks)
1. (i) We can expand the word size of a RAM by combining two or more RAM chips. For

instance, we can use two 328 memory chips where the number 32 represents the number of words and 8 represents the number of bits per word, to obtain a 3216 RAM. In this case the number of words remains the same but the length of each word will two bytes long. Draw a block diagram to show how we can use two 164 memory chips to obtain a 168 RAM. (8) (ii)Explain the principle of operation of bipolar SRAM cell. (8) 2. (i) A combinational circuits is defined as the functions F1=ABC+ABC+ABC F2=A BC+ABC+ABC implement the digital circuit with a PLA having 3 input, 3 product terms, and 2 output. (8) (ii) Write a note on SRAM based FPGA. (8)

3. Implement the following Boolean function with a PLA F1(A,B,C) = (0,1,2,4) F2(A,B,C) = (0,5,6,7) F3(A,B,C) = (0,3,5,7). (16) 4. Design combinational circuits using a ROM. The circuit accepts a three bit number and outputs a binary number equal to the square of the input number. (16) 5. Explain the analysis of clocked sequential circuits with examples. (16) 6. Explain with neat diagrams RAM architecture. (16) 7. Explain in detail about PLA and PAL. (16) 8. Explain with neat diagrams a ROM architecture. (16) 9. Explain and draw the memory cycles and timing waveforms. (16) 10. Details briefly about Field programmable gate arrays. (16) 11. Explain in detail about memory decoding. (16)

Unit V PART-A (2 Marks) 1. What are hazards? 2. Compare the ASM char with a conventional flow chart. 3. Draw the block diagram for Moore model. 4. What are hazard free digital circuits? 5. What is race? 6. What is a flow table? 7. What is excitation table? 8. Explain dynamic hazards.

PART B 1. For the circuit shown in figure write down the state table and draw the state diagram and analyze the operation. (16)

2. What are called as essential hazards? How does the hazard occur in sequential circuits? How can the same be eliminated using SR latches? Give an example. (16) 3. Design a three bit binary counter using T flipflop. (16) 4. Design a negative edge triggered T flipflop. (16) 5. What are hazards? Explain in detail with a suitable example. 6. Draw the fundamental mode and pulse mode asynchronous circuit and explain in detail. (16) 7. Design a T-FF giving the flow table, state table, state assignment, excitation table and excitation map. (16) **********