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Technical Note

Speed vs phase noise


Low-noise signal generation combined with fast frequency settling time overcoming the conflict

The S-Series SGA combines a frequency switching speed of 100 s with a phase noise of -135 dBc/Hz. This technical note describes the key techniques employed in the synthesizer design which make such a step-change in signal generator performance possible.

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The performance requirements for signal generators have continued to become more demanding as the quality of receivers and the speed of test have increased in line with the advances in all aspects of communications. The spectrum is becoming increasingly congested, new modulation techniques are being developed, components are advancing in speed and performance, and manufacturing volumes are increasing demands on cost-effective quality signal generation have never been higher. This has created a fiercely competitive market where signal generator performance continues to improve and the price reduces a familiar scenario with all aspects of technology, from motor cars to mobile phones. Customers and consumers continue to expect more for less.

The test requirements found in RFIC design and manufacture call for signal sources with both low phase noise and high frequency switching speed, requirements that are invariably in conflict resulting in performance being optimized for one or the other of the requirements. Aeroflexs latest synthesizer design used in its S-Series signal generators has been optimized for class-leading performance in both areas, with frequency switching speeds of less than 100 s and typical phase noise at 1 GHz of -135 dBc/Hz at 20 kHz offset. Advances in technology have enabled the synthesizer design to be miniaturized and simplified so that it is a fraction of the size and cost of its predecessors. While enabling the signal generator to be light and compact, it also provides space for future expansion as the range of products expands.

Figure 1: Graph of typical phase noise performance

Multi-loop synthesizer
To achieve a wide frequency range (up to 6 GHz) with fine frequency resolution a multi-loop synthesizer design was chosen. In this particular design, two PLL loops are used: one provides a low-noise RF signal capable of stepping across the required range in coarse steps, while the second loop provides interpolation between the steps with a fine frequency resolution. Both loops are bought together to make the final output signal.

reference oscillator, and as a result, the frequency is accurately known. The deviation is then corrected in real time by dynamically programming the interpolation synthesizer.

Interpolation synthesizer
The interpolation synthesizer provides a tuning range of 11.25 MHz in order to interpolate the 22.5 MHz steps of the high frequency signal. The output loop can subtract as well as add frequencies, so the required range is only half of the coarse step size. Other essential functions that the interpolation synthesizer is required to provide are as follows: a) Fine resolution for the synthesizer of 0.01 Hz when multiplied up to 6 GHz b) To offset the VCXO deviation from nominal frequency c) To apply wideband FM A 720 MHz Voltage Controlled SAW Oscillator (VCSO) is phaselocked to the 10 MHz reference oscillator and used as the clock for a Direct Digital Synthesizer (DDS). When the synthesizer is producing unmodulated CW, the DDS output has its already low spurious signals further reduced by a stage of addition to the 720 MHz signal, filtering and fractional division back down to low frequency. In this mode it covers 22.5 MHz to 33.75 MHz. When the synthesizer is required to produce wide deviation FM, the nominal interpolation frequency is changed to the range 33.75 MHz to 45 MHz, in order that the interpolation signal can swing a further 10 MHz to handle the wide frequency deviation. The DDS output is then used directly, to cover the frequency range from 23.75 MHz (33.75 MHz - 10 MHz) to 55 MHz (45 MHz + 10 MHz).

Low noise high frequency generation


Although SAW oscillators have long promised low noise generation for signals in the region of 1 GHz, the best method still continues to be by multiplication of a high power VHF crystal oscillator. There is a conflict between starting with a high frequency crystal for low noise, which will provide large and difficult to interpolate steps, and using a lower frequency crystal which provides smaller steps at the cost of increased noise multiplication. This conflict was resolved by using a 135 MHz crystal and a fractional multiplier, which provides a signal that covers 967 MHz to 1350 MHz in steps of 22.5 MHz. Starting from a 135 MHz crystal results in a noise floor some 16 dB better than would be obtained by using a 22.5 MHz crystal. The designer of the crystal oscillator faces conflicting requirements. Good phase noise demands high power operation and a narrow tuning range. The ability to lock the Voltage Controlled Crystal Oscillator (VCXO) to a specific frequency over the life of the instrument in the face of crystal ageing demands low power operation and a relatively wide tuning range. This has been resolved by running the oscillator at high power for low noise performance, and then handling the crystal ageing digitally. The 135 MHz crystal is phase-compared against the 10 MHz standard

Figure 2: Block diagram of Aeroflex S-Series SGA Analog Signal Generator

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Output addition loop


The output loop adds the two low-noise signals together. A fundamental low-noise Voltage Controlled Oscillator (VCO) covering a nominal 500 MHz to 667 MHz is doubled to 1000 MHz to 1333 MHz. This signal is mixed with the low noise high frequency signal. The difference frequency is then phase compared against the interpolation signal. The phase detector output is low-pass filtered and fed back to control the VCO to complete the PLL. An octave synthesizer would typically use a bank of VCOs to cover the output range, as achieving an octave tuning range with low noise is not straightforward. To achieve the required tuning range, a 1/3 octave VCO is used, which is then multiplied by 3, 4 or 5, to cover the octave. This multiplier uses a lower noise approach than has been used in previous designs. The 1000 MHz to 1333 MHz signal is doubled again to 4 times the VCO frequency. This signal is used directly for the 4 times output, or is mixed with the fundamental VCO to produce 3 and 5 times the VCO frequency. The upper or lower sideband is then selected by a tunable bandpass filter. This use of doublers and mixers permits a lower noise floor to be maintained throughout the multiplication than would be the case with other methods.

ing is then achieved before phase lock by using a digital discriminator technique (patent applied for). An FPGA compares the frequency of the two signals at the phase detector, and brings the VCO to the correct frequency by modifying the pre-steer voltage. Once the VCOs are close enough to lock, they lock and settle very quickly, due to minimum PLL bandwidths of 200 kHz, achieving frequency settling to 0.1 ppm in 100 us. This represents an error band of only 100 Hz at a 1 GHz carrier frequency.

Frequency modulation
The synthesizer is capable of producing wideband, wide deviation frequency modulation, using standard two-point modulation. The FM system takes advantage of modern low cost digital processing to set the overall FM gain, and to match the gain and delay of the two paths. Calibration of the two paths is handled internally. The modulation signal is applied simultaneously to the output VCO, and to the interpolation synthesizer. As they vary together, the output PLL sees no error at the phase detector. AC and DC input coupling, as well as phase modulation, are also handled digitally.

Conclusion
The synthesizer achieves its design objectives by using a combination of innovative analog and digital techniques to provide class-leading performance for the Aeroflex S-Series signal generators. This continues the evolution of generator technology which has been the hallmark of the Aeroflex product lines over several decades.

Design for speed


To achieve a fully settled frequency transition within 100 S, while maintaining low noise, introduces a further set of challenges. Analog voltages are used in several places in the synthesizer to pre-tune VCOs and to frequency tune varactor bandpass filters. The tuning voltages have the conflicting requirements of being agile enough to move in microseconds, yet being quiet to sub-nanovolt level and free of drift once settled. We achieve this by using carefully selected low-noise DACs, switched bandwidth passive filters, and filter capacitors with low dielectric absorption. The PLLs in the fractional multiplier and the output addition loop use mixer-based phase detectors. While these have a very low noise floor, they have the disadvantage of a limited capture range, which is of the order of the PLL loop bandwidth. Conventional methods of acquiring lock, such as search oscillators, would be far too slow for this application. After a coarse pre-steer phase has steered the VCO frequency into the correct region, accurate tun-

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As we are always seeking to improve our products, the information in this document gives only a general indication of the product capacity, performance and suitability, none of which shall form part of any contract. We reserve the right to make design changes without notice. All trademarks are acknowledged. Parent company Aeroflex, Inc. Aeroflex 2011.

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Part No. 46891/623, Issue 1, 1/11

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