Design Test

Eight deadly sins in scan-based designs

odays complex IC designs require good test design strategies to ensure high quality. There are many test methodologies that can be used when designing for test. These include full-scan, partial-scan, IDDQ, and built-in self test (BIST). Of these, scan methodologies are the most popular. To ensure a successful scan-based designthat is, achieve high fault coverageyou must design with testability in mind throughout the design process. If you are aware of design structures that can derail testing efforts, you can adopt alternative design techniques whenever possible. There are eight deadly design sins that are particularly hazardous to the scan-based testing process.

Scan-based designs are hindered by several structures that you must avoid during the design-for-testability process. If these structures are unavoidable, you may use alternative techniques but at the cost of affecting timing and area.
By Dr. Samy Makar
Cirrus Logic Corp., and

Dr. L.T. Wang & Benson Cheung

SynTest Technologies, Inc.

These sins violate key testability rules and should be avoided whenever possible. In scan-based designs, memory elements in a circuit (latches or flipflops) are replaced with their scan equivalent parts. These equivalent parts have two data inputs: one for normal functional operation, and

Q
Test_Enable

D EN Test_Enable

EN

Figure 1: The OR gates make the S/R latches behave like buffers or inverters during test. In general, you can halt the propagation of fault effects through latches by making them transparent during test mode. But faults on the enable logic of latches become impossible to test.
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the other for forming a chain of shift registers out of the memory elements. This shift register chain is called a scan chain. Use the Scan_Enable of each scan flip-flop to select the input and the process is automatically controlled by the test patterns during testing. The scan chain allows you to directly apply logic values to the inputs of the combinational logic as well as capture the outputs of that logic so they can be scanned-off the chip and compared with expected values on the tester. This allows the use of fast combinational Automatic Test Pattern Generation (ATPG) tools. In full-scan methodology, all the memory elements in the design are included in the scan chain. When area or timing constraints make this impractical, use a subset of the memory elementsthis results in a partial-scan design. Latches are scanned using the level-sensitive scan design methodology (LSSD) invented by IBM. Although this approach prevents timing problems, it is area intensive. Most designs are flip-flop based, and the scan flip-flops are used in the scan chains. Note that the design structures discussed here can seriously reduce

Design Test
gates (figure 1A). When the Test_ Enable signal is set to 1 during test, the circuit converts the cross-coupled gates into two inverters.

D 0 MUX D0 SD D Z CLK
Scan_Enable D1

Avoiding latches
The second sin is the use of latches in generalyou cannot scan them unless you have converted them to scan latches. This conversion creates a large area overhead. If the latches are part of an embedded memory, you can model all the latches together as a memory. Using a memory model can ease the generation of patterns for faults near the latches.

Test_Enable

CK SEL

Figure 2: Adding the test logic as shown allows a combinational feedback loop to be broken during test by using a scan flip-flop.

the effectiveness of using scan by preventing the scan chain from properly shifting in patterns and by making it almost impossible to generate test patterns. Avoid using these structuresthey serve only as illustrations of the eight deadly sins The work. arounds we show are aids to discussionthey add area to the design, and they may impact timing.

Gated clock In

Solution #1
D Q CLK CK Enable Test_Enable CK
In

CLK Enable

Solution #2
Multiplexer In

The first sin

You often use S/R latches to reduce the number of gates in a design. They are simple to implement and are inexpensive. However, they cause testability problems. These latches are sequential elements; when b oth inputs of a crosscoupled NAND gate are 1, its output remains the same as the previous state. It is, therefore, difficult to test with combinational ATPG.

0 1

Enable CK CLK

Figure 3: You can add an OR gate at the EN pin to allow the external clock to connect to the flip-flops clock input. Alternatively, MUX the data with the flip-flop output.

When possible, avoid crosscoupled S/R latches. Use D latches instead. If you cannot avoid crosscoupled S/R latches, insert two OR

D Q
Clock Frequency CLK2
divider

Multiplexer
Clock Frequency CLK2
divider

D Q CK

CK D Q CK

0 1

But remember, special tests are required for the latches. When latches are not part of the memory, a more general solution is to make the latches transparent during test mode (figure 1B). However, the best solution is to avoid using latches in designs as much as possible.

Feedback loops
D Q CK

Test_Enable

Figure 4: If you are already using a MUX to select different derived clocks, then you can expand it to handle one more clock input from a primary input. This saves you any timing problems the additional MUX could have caused.
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Combinational feedback loops introduce sequential behavior to otherwise combinational logic, making it difficult to use combinational tools. Moreover, these loops may lead to races and hazards, and result in unpredictable circuit behavior. These loops are generally delay-de-

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Design Test
FF1 D Q D DFF2 Q

CLR
A Test_Enable DFF1 D Q

CLR

DFF2 D Q

On the other hand, a derived clock is generated by a flip-flop, a latch, or any internal clock generatora PLL, a frequency divider, or a pulse generatorin the circuit. These clocks can render a large part of the design untestable because you cannot control the flip-flops from any primary inputyou cannot scan in values. This problem can be addressed by adding a MUX in front of the clock pin (figure 4).

Resetting problems
Sequentially controlled asynchronous SET or RESET can destroy the data during scan operation because some patterns may cause the SET/RESET signals to go active. As a result, you may not be able to scan certain pattern combinations, and the coverage drops dramatically. It is best to avoid this design style. However, in case this style is necessary, you can disable the synchronous SET/RESET during test mode (figure 5A). Notice the test mode is always high during test. A better solution is to add a capture signal, which is an additional external input pin controlled by the test pattern. This allows the fault at the Q output of DFF1 to be propagated through DFF2.

CLR
Capture

CLR

Figure 5: With solution A, the fault at the Q output of DFF1 cannot be tested. Although solution B solves this problem, it requires an additional external pin thereby increasing overhead.

pendent and, thus, cannot be tested with any ATPG algorithm. There are instances when such loops are unknowingly created. Say, your design team is working on an IC with a large bus to which numerous signals are tied. Designers may carefully avoid combinational feedback loops in their portion of the design, yet when the portions are integrated, you may end up with these loops. If you cannot avoid combinational feedback loops, then youll need to fix the problem (figure 2).

inputs, the gated clocks make it impossible to scan in data. You may remove these flip-flops from the scan chain, but this will decrease fault coverage. If you must use gated clocks, then you have the choice between using a multiplexer (MUX) and an OR gate (figure 3). The MUX approach does not save on power consumption.

Clocking up testability
There are two common types of internally generated clocks found in an IC: gated clocks and derived clocks. Gated clocks are often used to reduce power consumption by temporarily turning off part of the circuit when it is not in use. This type of clock is generated internally from an external clock, and goes through at least one combinational gate other than buffers and inverters. If the clocks of these flip-flops cannot be controlled from primary
ELECTRONICS ENGINEER/APRIL, 1998

CK

D Q SEL SD CK

Q D SEL SD CK
Scan_Enable

CK

Figure 6: Bus contentions, which are easily avoided during normal operation, need special attention and solution for scan-mode operation.

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Bidirectional I/Os
Scan_Enable D D Q BO CLK BI I/O

Figure 7: During capture, the test pattern determines how to use a bidirectional portfor input or for output.

Bus contention
Bus contention occurs when two drivers are driving different values on the same bus. It can cause severe damage to the chip. Therefore, you must prevent bus conflicts during both normal operation and scan operation. Make sure only one tri-state gate is selected at any given time

Each bidirectional I/O port must be externally controllable to be in input or output mode during scan shift to avoid contention with the tester. Achieve this using the Scan_Enable signal (figure 7). Implementing scan implies using scan flip-flops that are larger than the flip-flops typically used. There may be an impact on performance owing to the MUX in the scan flip-flop data path. However, you can always take the performance penalty into account during synthesis and can thus, AEE in theory, eliminate it. This updated article includes material previously published by ISD magazine in August 1997. Please e-mail your comments on this article to Dr. Samy Makar at samy@cirrus.com, or fax: 1-510-2526070. You may also contact Dr. L.T. Wang or Mr. Benson Cheung at info@syntest.com, fax: 1408-7209960.

during normal operation. During scan operation, if the enable signals are derived from scan flip-flops, it is possible that a scan pattern may cause more than one driver active at the same time. To avoid this p roblem, combinational logic gated with a Scan_Enable signal must be added to the enable logic (figure 6).

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