Design and control of a direct drive wind turbine equipped with

multilevel converters
Mohamed Abbes
a
, Jamel Belhadj
a, b,
*
, Afef Ben Abdelghani Bennani
a, c
a
LSE-ENIT, P.O Box 37, Belvede`re, 1002 Tunis, Tunisia
b
ESSTT, P.O. Box 56, Moneury, 1008 Tunis, Tunisia
c
INSAT, P.O. Box 676, North Urban Centre, 1080 Tunis, Tunisia
a r t i c l e i n f o
Article history:
Received 10 September 2008
Accepted 18 October 2009
Available online 20 November 2009
Keywords:
Direct drive wind turbine
NPC
Multilevel converters
Phase locked loop
Voltage dips
G.C.R
a b s t r a c t
This paper concentrates on the design and control of a three-level grid side converter (GSC) for direct
drive high power wind turbines. The three-level, neutral point clamped (NPC) topology was investigated.
The proposed control scheme, based on vector current control, offers very satisfying performances
regarding to structure stability and grid connection requirements (GCR). In order to have an accurate
evaluation of grid voltage source, two grid synchronization methods are developed and their perfor-
mances are compared. The GSC performances are evaluated under both normal and grid fault conditions.
Simulation results show that stability is maintained during voltage dips and that the proposed direct
drive wind turbine satises completely GCR.
2009 Elsevier Ltd. All rights reserved.
1. Introduction
Wind power is one of the most attractive renewable energy
sources since it does not emit pollutant and many countries have
a high level of wind potential. As a consequence, wind turbine
generator systems are coming into wide use in electricity genera-
tion. Today, there are many wind turbine manufacturers worldwide
and different generator and power electronics congurations are
used. The most commonly used concepts are the xed speed
squirrel-cage induction generator, the doubly fed induction
generator (DFIG) and the direct drive topology using a permanent
magnet synchronous generator (PMSG). For the latter concept, the
gearbox is removed and replaced by a multi-poles permanent
magnet synchronous generator. Gearbox removal saves the costs of
lubrication, maintenance, and installation [1]. In addition, the
direct drive structure can operate without any reactive power
consumption and its performances agree perfectly with grid
interconnection guidelines for wind power plants [2]. Up to now,
major technological developments in the wind turbine industry
focus on cost reduction and operational reliability. In addition to
these basic targets, the principal concern of manufacturers at
present is to increase wind turbine production capacity. However,
design of more powerful wind turbines often leads to high values of
the DC bus voltage. These values could exceed voltage blocking
capacities of currently available power devices, and particularly for
direct drive structure since this topology is based on full-sized
power converters. Even if high power semiconductors can be used
in some cases, these components are characterized by high
conduction and commutation losses. Therefore, utilization of
multilevel converters in large sized wind turbines seems to be very
interesting. As for all other applications, integration of multilevel
topologies withinwindturbines wouldalsoreduce output harmonic
distortionandconsequentlyoutput lter size, reduce dV/dt andthen
improve the whole structure electromagnetic compatibility
characteristics.
In this paper, a three-level grid side converter design for a 2MW
direct drive wind turbine fully satisfying GCR is presented (Fig. 3). A
three-level NPC converter model and simulation is discussed in
section II. The general control scheme of the multilevel Grid Side
Converter is given in section III. This scheme should particularly
control the produced power at the point of common connection
and minimize DC bus voltage ripple. To achieve these perfor-
mances, control method uses an inner grid current controller
combined with an outer DC bus voltage controller based on
instantaneous active and reactive powers. Section _V deals with the
grid synchronization issue. Two methods are described and their
performances under distorted utility conditions are evaluated.
* Corresponding author. ESSTT, Electrical (GE), BP 56, Bab Menera, Tunis 1008,
Tunisia. Tel.: 216 98 560 665; fax: 216 71 391 166.
E-mail address: Jamel.Belhadj@esstt.rnu.tn (J. Belhadj).
Contents lists available at ScienceDirect
Renewable Energy
j ournal homepage: www. el sevi er. com/ l ocat e/ renene
0960-1481/$ see front matter 2009 Elsevier Ltd. All rights reserved.
doi:10.1016/j.renene.2009.10.021
Renewable Energy 35 (2010) 936945
Section V focuses on the proposed structure behaviour under
voltage dips conditions: Performances are then evaluated taking
into account stability and compliance with GCR.
2. Three-level NPC inverter topology and modeling
Multilevel converters offer many advantages for high power
electronics applications. In particular, they permit operation at
higher DC voltage using series connected power semiconductors.
Today, many topologies of multilevel converters are available.
The diode-clamped was one of the rst developed [3]. It provides
more than two voltage levels by connecting the output voltage to
series connected DC bus capacitors. This is achieved by clamping
diodes. Fig. 1 depicts the three-level NPC inverter topology: Each
of the three legs can provide one additional output voltage level
to that of the classical two-level inverter. The neutral point
voltage, corresponding to one half of the DC bus voltage, is
available at the output of each phase when appropriate diodes
are clamped.
For phase a for example, Table 1 gives for each state S
a
, the
switching signals T
a1
, T
a2
and the output voltage V
ag
. Current i
adc1
is
the a-phase component to the junction current i
dc1
.
According to table I, output voltages V
(a,b,c)g
can be expressed as:
V
ag

i 2
i 1
T
ai
V
ci
(1)
In the case of a three phase balanced load, expressions of phase
voltages are:
_
_
V
an
V
bn
V
cn
_
_

1
3

_
_
1 0 1
1 1 0
0 1 1
_
_

_
_
V
ab
V
bc
V
ca
_
_
(2)
_
_
V
ab
V
bc
V
ca
_
_

_
_
1 1 0
0 1 1
1 0 1
_
_

_
_
V
ag
V
bg
V
cg
_
_
(3)
Equations (2) and (3) give:
_
_
V
an
V
bn
V
cn
_
_

1
3

_
_
2 1 1
1 2 1
1 1 2
_
_

_
_
V
ag
V
bg
V
cg
_
_
(4)
Then, inverter phase to line voltages are related to the switching
signals by:
_
_
V
an
V
bn
V
cn
_
_

1
3

_
_
2 1 1
1 2 1
1 1 2
_
_

_
_
_
_
_
_
_
_
_
_

i 2
i 1
T
ai
V
ci

i 2
i 1
T
bi
V
ci

i 2
i 1
T
ci
V
ci
_
_
_
_
_
_
_
_
_
_
(5)
Moreover, neutral point current idc1 expression can be written as
(Table 1):
i
dc1
T
a1
T
a2
i
a
T
b1
T
b2
i
b
T
c1
T
c2
i
c
i
c1
i
c2
6
Voltage ripples of the two DC bus capacitors are calculated as follows
(Herein, DC bus voltage is assumed constant and C
1
C
2
C):
i
c1
C
dV
c1
dt
C
dU
dc
V
c2

dt
C
dV
c2
dt
i
c2
(7)
Then:
dV
c1
dt

1
C

i
dc1
2
(8)
dV
c2
dt

1
C

i
dc1
2
(9)
Simulation results, carried on with a sine triangle modulation, are
given in Fig. 2. The voltage balance between DC bus capacitors is
>
>
ic2
ic1
d0
d2
d1
g
c
b
a idc1
idc2
+
- Udc
Vc2
Vc1
Ta1
T'a2
T'a1
Ta2
Tc1
T'c2
T'c1
Tc2 Tb2
T'b1
T'b2
Tb1
a b c
i
a
i
b
i
c
C
1
C
2
Fig. 1. Three-level NPC inverter topology.
Table 1
Three-level inverter states (phase a).
S
a
T
a2
T
a1
V
ag
i
adc1
0 0 0 0 0
1 0 1 V
c1
i
a
2 1 1 V
c1
V
c2
0
M. Abbes et al. / Renewable Energy 35 (2010) 936945 937
maintained (Fig. 2b). The simulation parameters are: U
dc
3KV,
C
1
C
2
2.5 mF for the DC bus and R 10U, L 0.1H, for the load.
3. Control strategy of the three-level grid side converter
The main attention of this paper is the design and control of the
GSC, so the power chain was simplied by replacing the turbine
generator-rectier group by an equivalent current source (Fig. 3).
The proposed control strategy aims to keep DC bus voltage constant
and impose PQ (active and reactive) powers injected to the grid.
Connection to the grid is achieved through an inductor lter and
a transformer. A PI-regulator was implemented to control DC bus
voltage. Output of this rst controller is taken as the active power
reference at the point of common connexion. Reference grid
currents, i
2d_ref
and i
2q_ref
, are calculated through active and reactive
power references, and grid voltages V
2d
, V
2q
. Then, an appropriate
control loop for these grid currents is used to provide reference
voltages, V
1d_ref
and V
1q_ref
, for the three-level PWM-inverter.
3.1. Vector current controller
GSC is connected to the grid through an inductor lter and
a transformer (Fig. 4). This connection is described by equations
(10), and (11):
V
1
t r
T1
$i1t
_
l
T1
L
f
_
$
di
1
t
dt
L
m
$
di
1
tm$i
2
t
dt
(10)
V
2
t r
T2
$i2t l
T2
$
di2t
dt
e
0
2t (11)
with:
e
0
2t m$e
0
1t m$L
m
$
di
1
t m$i
2
t
dt
This gives:
V
1
t r
T1
$i1t L
1
$
di1t
dt
M$
di2t
dt
(12)
V
2
t r
T2
$i2t L
2
$
di2t
dt
M$
di1t
dt
(13)
With:
L
2
m
2
$Lm l
T2
: Secondary cyclic inductance, Mm$Lm:
transformer mutual inductance, L
1
l
T1
L
f
Lm(L
f
: lter induc-
tance). In the synchronous reference frame dq equations (12) and
(13) are written as:
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
-2
-1

1
2
0
1.45
1.50
1.55
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
1.45
1.50
1.55
Vc1
Vc2
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
-50
0
50
Time [s]
Time [s]
Time [s]
10
3
10
3
a
b
c
Fig. 2. a) a-phase line to neutral voltage (V). b) Capacitors voltages (V). c) Load Currents (A).
M. Abbes et al. / Renewable Energy 35 (2010) 936945 938
V
1d
r
T1
$i
1d
L
1
$
di
1d
dt
L
1
uS$i
1q
M$
di
2d
dt
MuS$i
2q
(14)
V
1q
r
T1
$i
1q
L
1
$
di
1q
dt
L
1
uS$i
1d
M$
di
2q
dt
MuS$i
2d
(15)
V
2d
r
T2
$i
2d
L2$
di
2d
dt
L
2
uS$i
2q
M$
di
1d
dt
MuS$i
1q
(16)
V
2q
r
T2
$i
2q
L
2
$
di
2q
dt
L
2
uS$i
2d
M$
di
1q
dt
MuS$i
1d
(17)
Introducing (16) into (14) and (17) into (15), the control system is
expressed as:
V
1d;q

L
1
$r
T2
M
$i
2d;q

L
1
M
$
_
L
2

M
2
L
1
_
$
di
2d;q
dt

L
1
M
$V
2d;q

L
1
M
$
_
L
2

M
2
L
1
_
uS$i
2q;d
r
T1
$i
1d;q
18
Considering the termse
cd
and e
cq
dened as:
e
cd;q

L
1
M
$V
2d;q

L
1
M
$
_
L
2

M
2
L
1
_
uS$i
2q;d
r
T1
$i
1d;q
(_),(__)
And assuming that:
V
bd;q

L
1
$r
T2
M
$i
2d;q

L
1
M
$
_
L
2

M
2
L
1
_
$
di
2d;q
dt
The block diagram modeling the grid connection can be described
as illustrated in Fig. 5:
With: K
M
L
1
r
T2
and sS
L2
M
2
L1

r
T2
.
V
1d_c
V
1q_c
3L_Inverter
V
2a
V
2b
V
2c

C
C
P
L_filter
IGBT
TR

d
i
r
G
I
rec
V
1a_ref
i
1c
V
1dq_ref
V
2d
3
2
s
Pulse Width
Modulation
i
1b
i
1a
i
1d
i
1q
3
2
s
e
cd e
cq
+ +
i
2a
i
2
3
2
i
2c
V
2q
+
-
PI
PI
+
-
LP
U
dc
i
2dq_ref
reference
currents
generation
Q
ref P
ref
U
dc_ref
PI
P
cond ref
i
c_ref
-
+
-
P
red
= U
dc
I
rec
+ +
+
i
2d
i
2q
PLL
Fig. 3. Grid Side Converter structure and block scheme of control algorithm.
Fig. 4. Inverter connection to the grid. Fig. 5. Grid connection block diagram.
M. Abbes et al. / Renewable Energy 35 (2010) 936945 939
The above diagramshows that control voltages V
1d
and V
1q
affect
both grid current components i
2d
and i
2q
. Therefore, d and q axes
need to be decoupled to achieve grid currents control. This will be
done by introducing two new control inputsV
1d_c
andV
1q_c
. Control
voltages V
1d
andV
1q
are then derived from these control inputs and
compensation terms e
cd,q
as shown in Fig. 6:
Hence, the grid connection model is simplied to the new
system depicted by Fig. 7:
In this way, axes d and q are decoupled. Grid currents
control is achieved simply by deriving PI-regulators gains for each
of the above independent rst order transfer functions. This is
performed by placing the zero of the PI controller over the pole of
the system:
TF
OL

K
I
1 s
i
s
s

K
1 s
s
s
(19)
Consequently, system closed loop transfer function will be:
TF
CL

i
2d
i
2d ref

1
1 s
c
s
(20)
scis the closed loop time constant. Its expression is given by:
s
c

1
K K
I
(21)
3.2. Generation of grid current references
Reference currents, i
2d,q_ref
, are deduced through the point of
common connection voltages and power references as follows:
i
2d ref

P
ref
$V
2d
Q
ref
$V
2q
V
2
2d
V
2
2q
(22)
i
2q ref

P
ref
$V
2q
Q
ref
$V
2d
V
2
2d
V
2
2q
(23)
3.3. DC bus voltage controller
The DC bus model for the back to back NPC converters is
described by Fig. 8:
In Fig. 8, R
1
and R
2
stand for the capacitors leakage resistances.
Assuming thatR
1
R
2
R, and C
1
C
2
C, DC bus voltage ripple is
given by:
C
dU
dc
dt
C
dV
c1
dt
C
dV
c2
dt
i
c1
i
c2
(24)
According to the model represented in Fig. 8, equations (25) and
(26) can be deduced:
I
red
I
ond
i
c2
i
r2
(25)
i
c2
i
r2
i
c1
i
r1
i
dc1
(26)
Introducing (25) and (26) into (24) the model is simplied to:
Fig. 6. Control voltages reconstruction.
Fig. 7. Decoupled control of grid current components.
I
rec
i
r1
R
2
R
1 C
1
C
2
i
r2
i
c1
i
c2
I
ond
I
dc1
I
b
Fig. 8. Simplied diagram of the NPC back to back converters.
PI
U
dc_ref
U
dc
U
dc
i
b_ref
+
-
+
_
1
2
dc i
2
1
R
RCs
Fig. 9. DC bus control.
V
2a

V
2b

V
2c

RF
V
2

V
2

3
2
2
( ) S
V
arctg
V

=
S
~
Fig. 10. ab lter algorithm block scheme.
+
V2d
-
PI
+
v2d_ref = 0
1
s
n

s
V2q
V2a
V2b
V2c

dq
3
~
2
1
V
2
V
n
2
V
+

Fig. 11. dq Phase Locked Loop synchronization method.

M. Abbes et al. / Renewable Energy 35 (2010) 936945 940
C
dU
dc
dt
2I
red
I
ond
i
r2
i
r1
i
dc1
(27)
Thus, DC bus voltage is calculated as:
C
dU
dc
dt
2I
red
I
ond

_
V
c1
R

V
c2
R
_
i
dc1
(28)
As U
dc
V
c1
V
c2
, (28) gives:
C
dU
dc
dt

U
dc
R
2I
rec
I
inv
i
dc1
(29)
Introducing PI-regulator, the DC bus voltage control loop is
described by Fig. 9 (With i
b
IrecIinv). The neutral point current is
seen as a constant perturbation, so the zero of the PI controller is
placed over the systempole and the closed loop transfer function is
obtained (eq. 30).
TF
CL

1
1
K
I
2R
s 1
(30)
The DC bus voltage controller is the outer loop, whereas the two
current loops are the inner ones. These are designed to reach
settling times very quickly. On the other hand, the outer controller
aims are stability and optimal regulation, and therefore it is
designed to have a bigger settling time, at least 10 times bigger than
for the inner loops. So, the inner and the outer loops can be
considered independent, and therefore, the current transfer func-
tion is not considered when the DC bus controller is designed.
4. Wind turbine grid synchronization
In order to calculate and control the PQ power ow to the
electrical grid and avoid wind turbines tripping, the phase angle of
utility voltage must be accurately detected. Several grid synchroni-
zation methods are proposed in [4]. In this section two synchroni-
zation algorithms will be analysed: the ltering in the ab stationary
frame and the phase locked loop (PLL). The last one is implemented
in the dq synchronous rotating reference frame (called also dqPLL).
4.1. ab lter algorithm
The phase angle of the utility grid can be obtained by ltering
input voltage signals as depicted in Fig. 10. The two voltage
components obtained from three phase transformation are ltered
in order to avoid angle detection errors due to voltage harmonics.
However, ltering will introduce signal delay which is unaccept-
able for angle detection accuracy. Therefore a proper lter design
has to be made. A resonance lter is used to lter the ab voltages
(Resonance frequency is equal to the grid frequency). Then, grid
angle is obtained by using the arctg function.
4.2. dq Phase locked loop
PLL technique is based on the synchronism between the utility
voltage vector and the synchronous reference frame dq (Fig. 11).
After transformation of grid voltages to the ab frame, voltage
components are normalized to the magnitude of the grid voltage
vector
_
kV2
ab
k

V
2
2a
V
2
2b
_ _
.
Then, Park transformation is applied to the normalized
components to obtain dq voltages in the synchronous rotating
reference frame. The lock is realized by settling V
2d_ref
to zero. A PI-
regulator is used to control error between V
2d
and V
2d_ref
. This
regulator output is the grid angular frequency variationDu
s
and it
is added to the nominal grid angular frequency u
n
. The grid angle
estimation

q
s
is obtained by integrating this summation. This angle
detection method can be directly implemented. However, for
Fig. 12. dq reference frame and grid voltage vector synchronisation.
Fig. 13. Voltage dips classication [5].
M. Abbes et al. / Renewable Energy 35 (2010) 936945 941
Time [s]
10
4
0.2 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28
-2
0
2
]
V
[

e
g
a
t
l
o
v

d
i
r
G
0.2 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28
0
2
4
6
]
s
/
d
a
r
[
0.2 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28
0
2
4
6
]
s
/
d
a
r
[
a
b
c
Fig. 14. Behaviour of the synchronization algorithm in the case of 50% unbalanced voltage dip (Type C). (a) Grid voltages. (b) ab lter algorithm signal (c) dqPLL signal.
0.2 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28
-2
0
2
]
V
[

e
g
a
t
l
o
v

d
i
r
G
a
0.2 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28
0
2
4
6
]
s
/
d
a
r
[
b
0.2 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28
0
2
4
6
]
s
/
d
a
r
[
c
Time [s]
10
4
estimated angle
grid angle
estimated angle
grid angle
Fig. 15. Synchronization algorithms behaviour during frequency variation (f47Hz). (a) Grid voltages. (b) ab lter algorithm signal. (c) dqPLL signal.
deriving PI-regulator parameters, a linear model for this structure
needs to be developed.
A linear model is developed as follows: After normalization, ab
grid voltage components expressions become:
V
n
2a

V
2a
kV2
ab
k

V
2a

V
2
2a
V
2
2b
_ cosq
s
(31)
V
n
2b

V
2b
kV2
ab
k

V
2b

V
2
2a
V
2
2b
_ sinq
s
(32)
With:q
s
the grid angle as depicted in Fig. 12.
Considering that

q
s


q
dq

2
, Park transformation applied to
the normalized voltage components gives:
V
2d
cos
_

q
s

2
_
V
n
2a
sin
_

q
s

2
_
V
n
2b
(33)
V
2q
sin
_

q
s

2
_
V
n
2a
cos
_

q
s

2
_
V
n
2b
(34)
Introducing (31) and (32) into (33) and (34), expressions of grid
voltages in the synchronous reference frame dq are:
V
2d
sin
_

q
s
_
V
n
2a
cos
_

q
s
_
V
n
2b
sin
_

q
s
q
s
_
(35)
V
2q
cos
_

q
s
_
V
n
2a
sin
_

q
s
_
V
n
2b
cos
_

q
s
q
s
_
(36)
Assuming that the difference

q
s
q
s
remains close to zero, voltage
direct component can be written as follows:
Time [s]
Order of Harmonic
0.26 0.27 0.28 0.29 0.3
-40
-20
20
40
]
A
[

t
n
e
r
r
u
C

d
i
r
G
0 20 40 60 80 100
0
20
40
e
d
u
t
i
n
g
a
M

c
i
n
o
m
r
a
H
THD = 1.2%
a
0 20 40 60 80 100
0
1
2
e
d
u
t
i
n
g
a
M

c
i
n
o
m
r
a
H
THD = 2.7%
Time [s]
Order of Harmonic
0.26 0.27 0.28 0.29 0.3
-2
0
2
]
V
[

e
g
a
t
l
o
V

d
i
r
G
10
3
b
0
Fig. 16. Grid current and voltage spectrum analysis. a) Grid current b) Grid voltage.
M. Abbes et al. / Renewable Energy 35 (2010) 936945 943
V
2d
z

q
s
q
s
(37)
Consequently, the linear model transfer function of the dqPLL
structure is given by:
Hs

q
s
q
s

K
pS
K
I
s
2
K
pS
K
I
(38)
4.3. Evaluation of the studied synchronization algorithms
In order to test angle estimation precision, several types of grid
voltage dips have to be considered. Voltage dips are dened as
a drop in voltage magnitude which is a consequence of short-circuit
fault on the grid. Fig. 13 gives six of the most common voltage sags
as dened by Bollen [5].
Simulation results presented below show synchronization
algorithms behaviour under a 50% unbalanced voltage dip, type C
(Fig14) andinthe case of gridfrequencyvariation, a commonfault in
the power system(Fig. 15). Fig. 14b shows that during type C voltage
dip, ab lter algorithmfails to provide correct angle estimation. The
100 Hz frequency negative sequence due to the unbalanced fault is
ltered by the resonance lter but difference inamplitudes of the ab
Fig. 17. Proposed low voltage ride through requirement (E. ON Netz) [7].
Fig. 18. GSC response during type C voltage dip. a) DC bus capacitor voltages, b) DC bus voltage. c) Produced power PQ. d) Produced power PQ (different time scale).
M. Abbes et al. / Renewable Energy 35 (2010) 936945 944
voltage components produces perturbation in synchronization
signal. In addition, for the frequency variation fault, a time lag is
introduced between the estimated angle and the grid phase angle.
This is a natural consequence of delay caused by the resonance lter.
On the other hand, dqPLL algorithmis able to track grid phase angle
in both fault cases (Figs. 14c and 15c). In consequence of these
results, dqPLL is selected to achieve GSC control.
5. Performances of the NPC-GSC under grid disturbance
5.1. Power quality
The system power quality is analysed in comparison with the
IEEE 519 standards [6]. These codes dene harmonic distortion
limits for distributed power systems such as wind turbines, PV or
fuel cells systems. Spectrum analysis of grid currents and voltages
at the point of common connection has shown that the total
harmonic distortion (THD) is about 1.2% for current and 2.7% for
voltage. This is less than the 5% rate recommended by the IEEE
standards for both current and voltage. Thus, the produced power
complies with IEEE recommendations (Fig. 16).
5.2. Low voltage ride through (LVRT) capability of the wind turbine
based on NPC-GSC
In this section, the behaviour of the proposed NPC-GSC structure
under voltage dips is investigated. In this work, structure perfor-
mances are evaluated in comparison with the requirements of the
Germanic system operator E. ON Netz [7]. According to these
standards, wind turbines must withstand all types of voltage dips.
Dips magnitude is described based on a time diagram which
species voltage drop limits (Fig. 17).
The GSC model was subjected to several network disturbances
to analyse its performances. As an example, Fig. 18 shows operation
when an unbalanced, type C, voltage dip occurs at the point of
common connection. At the fault beginning, voltage falls to 20% of
the grid nominal voltage then it starts to recover after a 150 ms
time delay as depicted by Fig. 17. Fig. 18a shows DC bus capacitor
voltages, which are disturbed by the voltage dip. Nevertheless, they
come back to their rated value after the fault is cleared. Thus,
capacitor voltage balance is kept. Also, DC bus voltage ripple does
not exceed 5% of its rated value (Fig. 18b). This ripple decreases
gradually and it is eliminated after the end of voltage disturbance.
According to these results, it is concluded that the PWM-GSC
equipped with an NPC three-level converter keeps its stability and
can stay connected to the grid during the total period of the low
voltage fault.
6. Conclusion
In this paper, a three-level NPC Grid Side Converter for direct
drive wind turbine was investigated. A general control scheme for
this GSC was dened and a-Phase Locked Loop algorithm is
developed to ensure its synchronization with grid voltage. The
designed dqPLL has overcome all test conditions and estimated
angle

q
s
tracks exactly the real grid angleqs. Transient operation of
the multilevel PWM-GSC under unbalanced voltage conditions is
analysed. The importance of ride through capability is increasing,
because the amount of wind power connected to the grid is in
constant growth. To test the robustness of the GSC control algo-
rithm during unbalanced voltage conditions, different voltage dips
were applied to this structure. Simulation results show that
stability is maintained during voltage dips and DC bus voltages
return to their rated value after the end of the fault. This means that
generation is not lost because of temporary excursions of voltage.
The Produced power has an acceptable quality since grid current
and voltage distortion is under standard harmonic limits. In
conclusion, this structure satises completely GCR and it provides
all advantages of multilevel converters to direct drive wind
turbines.
References
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Denmark: Ris National Laboratory; 2001.
[3] Nabae A, Takahashi I, Akagi H. A new neutral point clamped PWM inverter. On
Industry applications. IEEE Trans 1981;1:51823.
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M. Abbes et al. / Renewable Energy 35 (2010) 936945 945