7LB176

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 DIFFERENTIAL BUS TRANSCEIVERS
SLLS067G AUGUST 1990 REVISED APRIL 2006
D Bidirectional Transceiver D Meets or Exceeds the Requirements of D D D D D D D D D D D D D D

ANSI Standard TIA/EIA485A and ISO 8482:1987(E) High-Speed Low-Power LinBiCMOS Circuitry Designed for High-Speed Operation in Both Serial and Parallel Applications Low Skew Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments Very Low Disabled Supply Current . . . 200 A Maximum Wide Positive and Negative Input/Output Bus Voltage Ranges Thermal-Shutdown Protection Driver Positive-and Negative-Current Limiting Open-Circuit Failsafe Receiver Design Receiver Input Sensitivity . . . 200 mV Max Receiver Input Hysteresis . . . 50 mV Typ Operates From a Single 5-V Supply Glitch-Free Power-Up and Power-Down Protection Available in Q-Temp Automotive HighRel Automotive Applications Configuration Control / Print Support Qualification to Automotive Standards
D, JG, OR P PACKAGE (TOP VIEW)
R RE DE D
1 2 3 4
8 7 6 5
VCC B A GND
FK PACKAGE (TOP VIEW)
NC RE NC DE NC
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
NC R NC VCC NC NC B NC A NC
NC No internal connection
Function Tables
DRIVER INPUT D H L X ENABLE DE H H L OUTPUTS A B H L L H Z Z
description
The SN55LBC176, SN65LBC176, SN65LBC176Q, and SN75LBC176 differential bus transceivers are monolithic, integrated circuits designed for bidirectional data communication on multipoint bus-transmission lines. They are designed for balanced transmission lines and meet ANSI Standard TIA/EIA485A (RS-485) and ISO 8482:1987(E).
NC D NC GND NC
RECEIVER DIFFERENTIAL INPUTS VID = VIA VIB VID 0.2 V 0.2 V < VID < 0.2 V VID 0.2 V X Open H = high level, X = irrelevant, ENABLE RE L L L H L OUTPUT R H ? L Z H L = low level, ? = indeterminate, Z = high impedance (off)
Copyright 20002006, Texas Instruments Incorporated
On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinBiCMOS and LinASIC are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265

description (continued)
The SN55LBC176, SN65LBC176, SN65LBC176Q, and SN75LBC176 combine a 3-state, differential line driver and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables, respectively, which can externally connect together to function as a direction control. The driver differential outputs and the receiver differential inputs connect internally to form a differential input /output (I/O) bus port that is designed to offer minimum loading to the bus whenever the driver is disabled or VCC = 0. This port features wide positive and negative common-mode voltage ranges, making the device suitable for party-line applications. Very low device supply current can be achieved by disabling the driver and the receiver. These transceivers are suitable for ANSI Standard TIA/EIA485 (RS-485) and ISO 8482 applications to the extent that they are specified in the operating conditions and characteristics section of this data sheet. Certain limits contained in TIA/EIA485A and ISO 8482:1987 (E) are not met or cannot be tested over the entire military temperature range. The SN55LBC176 is characterized for operation from 55C to 125C. The SN65LBC176 is characterized for operation from 40C to 85C, and the SN65LBC176Q is characterized for operation from 40C to 125C. The SN75LBC176 is characterized for operation from 0C to 70C.
logic symbol
DE RE 3 2 EN1 EN2 6 D 4 1 1 7
logic diagram (positive logic)

DE D A B RE R 2 6 1 7 A B Bus 3 4
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
AVAILABLE OPTIONS TA 0C to 70C 40C to 85C 40C to 110C 55C to 125C PACKAGE SOP PDIP SOP PDIP SOP SOP LCCC CDIP PART NUMBER SN75LBC176D SN75LBC176P SN65LBC176D SN65LBC176P SN65LBC176QD SN65LBC176QDR SNJ55LBC176FK SNJ55LBC176JG PART MARKING 7LB176 75LBC176 6LB176 65LBC176 LB176Q LB176Q SNJ55LBC176FK SNJ55LBC176
DALLAS, TEXAS 75265

schematics of inputs and outputs

EQUIVALENT OF D, RE, and DE INPUTS VCC TYPICAL OF A AND B I/O PORTS VCC VCC TYPICAL OF RECEIVER OUTPUT
100 k NOM A Port Only A or B Input 18 k NOM
3 k NOM Output
100 k NOM B Port Only
1.1 k NOM
absolute maximum ratings

Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage range at any bus terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V to 15 V Input voltage, VI (D, DE, R, or RE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to VCC + 0.5 V Receiver output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $10 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential I/O bus voltage, are with respect to network ground terminal. DISSIPATION RATING TABLE PACKAGE D P JG FK THERMAL MODEL Low K High K TA < 25C POWER RATING 526 mW 882 mW 840 mW 1050 mW 1375 mW DERATING FACTOR ABOVE TA = 25C 5.0 mW/C 8.4 mW/C 8.0 mW/C 8.4 mW/C 11.0 mW/C TA = 70C POWER RATING 301 mW 504 mW 480 mW 672 mW 880 mW TA = 85C POWER RATING 226 mW 378 mW 360 mW 546 mW 715 mW TA = 110C POWER RATING 210 mW 440 mW
In accordance with the low effective thermal conductivity metric definitions of EIA/JESD 513. In accordance with the high effective thermal conductivity metric definitions of EIA/JESD 517.
DALLAS, TEXAS 75265

recommended operating conditions

MIN Supply voltage, VCC Voltage at any bus terminal (separately or common mode), VI or VIC High-level input voltage, VIH Low-level input voltage, VIL Differential input voltage, VID (see Note 2) Driver High-level output current, IOH Low-level output current, IOL Junction temperature, TJ SN55LBC176 Operating free-air temperature, TA SN65LBC176 SN65LBC176Q SN75LBC176 55 40 40 0 Receiver Driver Receiver D, DE, and RE D, DE, and RE 12 60 400 60 8 140 125 85 125 70 C mA C 4.75 7 2 0.8 12 NOM 5 MAX 5.25 12 UNIT V V V V V mA A
NOTE 2: Differential input /output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
DALLAS, TEXAS 75265

DRIVER SECTION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VIK VO | VOD1 | Input clamp voltage Output voltage Differential output voltage II = 18 mA IO = 0 IO = 0 RL = 54 , See Note 3 See Figure 1, 55LBC176, 65LBC176, 65LBC176Q 75LBC176 Vtest = 7 V to 12 V, See Note 3 See Figure 2, 55LCB176, 65LCB176, 65LBC176Q 75LBC176 | VOD | VOC | VOC | IO IIH IIL Change in magnitude of differential output voltage Common-mode output voltage Change in magnitude of common-mode output voltage Output current High-level input current Low-level input current Output disabled, See Note 4 VI = 2.4 V VI = 0.4 V VO = 7 V VO = 0 VO = VCC VO = 12 V Receiver disabled and driver enabled ICC Supply current VI = 0 or VCC, No load Receiver and driver disabled 55LBC176, 65LBC176Q 65LBC176, 75LBC176 55LBC176, 65LBC176Q 65LBC176, 75LBC176 VO = 12 V VO = 7 V RL = 54 or 100 , See Figure 1 TEST CONDITIONS MIN 1.5 0 1.5 1.1 1.5 1.1 1.5 0.2 1 0.2 5 0.2 3 0.2 1 0.8 100 100 250 150 mA 250 1.75 1.5 mA 0.25 0.2 mA A A V V V 5 6 6 MAX UNIT V V V
| VOD2 |
Differential output voltage
VOD3
Differential output voltage
IOS
Short-circuit output current
| VOD | and | VOC | are the changes in magnitude of VOD and VOC, respectively, that occur when the input changes from a high level to a low level. NOTES: 3. This device meets the VOD requirements of TIA/EIA485A above 0C only. 4. This applies for both power on and off; refer to TIA/EIA485A for exact conditions.
DALLAS, TEXAS 75265

switching characteristics over recommended ranges of supply voltage and operating free-air temperature
PARAMETER td(OD) tt(OD) tsk(p) tPZH tPZL tPHZ Differential output delay time Differential output transition time Pulse skew ( | td(ODH) td(ODL) | ) Output enable time to high level Output enable time to low level Output disable time from high level RL = 110 , RL = 110 , RL = 110 , See Figure 4 See Figure 5 See Figure 4 See Figure 5 TEST CONDITIONS SN55LBC176 SN65LBC176Q MIN RL = 54 , See Figure 3 8 CL = 50 pF, 12 6 65 65 105 105 TYP MAX 31 SN65LBC176 SN75LBC176 MIN 8 12 0 6 35 35 60 35 TYP MAX 25 ns ns ns ns ns ns ns UNIT
tPLZ Output disable time from low level RL = 110 , All typical values are at VCC = 5 V, TA = 25C.
SYMBOL EQUIVALENTS DATA SHEET PARAMETER VO | VOD1 | | VOD2 | | VOD3 | | VOD | VOC | VOC | IOS IO RS-485 Voa, Vob Vo Vt (RL = 54 ) Vt (test termination measurement 2) | | Vt | | Vt | | | Vos | | Vos Vos | None Iia, Iib
DALLAS, TEXAS 75265

RECEIVER SECTION electrical characteristics over recommended ranges of common-mode input voltage, supply voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER VIT + VIT Vhys VIK VOH VOL IOZ II IIH IIL rI Positive-going input threshold voltage Negative-going input threshold voltage Hysteresis voltage (VIT + VIT ) (see Figure 4) Enable-input clamp voltage High-level output voltage Low-level output voltage High-impedance-state output current Line input current High-level enable-input current Low-level enable-input current Input resistance Receiver enabled and driver disabled ICC Supply current VI = 0 or VCC, No load Receiver and driver disabled SN55LBC176, SN65LBC176, SN65LBC176Q II = 18 mA VID = 200 mV, See Figure 6 VID = 200 mV, See Figure 6 VO = 0.4 V to 2.4 V Other input = 0 V, See Note 5 VIH = 2.7 V VIL = 0.4 V VI = 12 V VI = 7 V IOH = 400 A, IOL = 8 mA, 1.5 2.7 0.45 20 20 1 0.8 100 100 12 3.9 mA A A k mA VO = 2.7 V, VO = 0.5 V, TEST CONDITIONS IO = 0.4 mA IO = 8 mA 0.2 50 MIN TYP MAX 0.2 UNIT V V mV V V V A
0.25 0.2
mA
SN75LBC176 All typical values are at VCC = 5 V, TA = 25C. The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet. NOTE 5: This applies for both power on and power off. Refer to ANSI Standard RS-485 for exact conditions.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 15 pF
PARAMETER Propagation delay time, low- to high-level single-ended output Propagation delay time, high- to low-level single-ended output Pulse skew ( | tPLH tPHL | ) Output enable time to high level Output enable time to low level Output disable time from high level See Figure 8 See Figure 8 VID = 1.5 V to 1.5 V, See Figure 7 TEST CONDITIONS SN55LBC176 SN65LBC176Q MIN tPLH tPHL tsk(p) tPZH tPZL tPHZ 11 11 MAX 37 37 10 35 35 35 35 SN65LBC176 SN75LBC176 MIN 11 11 3 TYP MAX 33 33 6 35 30 35 30 ns ns ns ns ns ns ns UNIT
tPLZ Output disable time from low level All typical values are at VCC = 5 V, TA = 25C.
DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

375 RL VOD2 2 RL 2 VOC 375 VOD3 60 Vtest
Figure 1. Driver VOD and VOC
Figure 2. Driver VOD3

3V Input CL = 50 pF (see Note B) Output td(ODH) 50% 90% 10% 1.5 V 1.5 V 0V td(ODL) 2.5 V 50%
Generator (see Note A)
50 3V
RL = 54
Output
tt(OD) TEST CIRCUIT
2.5 V tt(OD) VOLTAGE WAVEFORMS
Figure 3. Driver Test Circuit and Voltage Waveforms

Output S1 0 V or 3 V CL = 50 pF (see Note B) RL = 110 Output tPZH 2.3 V tPHZ VOLTAGE WAVEFORMS Input 1.5 V 1.5 V 0V 0.5 V VOH Voff 0 V 3V
50
TEST CIRCUIT

5V RL = 110 Output tPZL CL = 50 pF (see Note B) Output 2.3 V Input 1.5 V 1.5 V 0V tPLZ 5V 0.5 V VOL TEST CIRCUIT VOLTAGE WAVEFORMS 3V
S1 3 V or 0 V
50

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, tr 6 ns, tf 6 ns, ZO = 50 . B. CL includes probe and jig capacitance.
DALLAS, TEXAS 75265

VID VOH VOL + IOL IOH
Figure 6. Receiver VOH and VOL

3V Input Generator (see Note A) 51 1.5 V Output CL = 15 pF (see Note B) tPLH Output 1.3 V tPHL VOH 1.3 V VOL TEST CIRCUIT VOLTAGE WAVEFORMS 1.5 V 1.5 V 0V
0V
Figure 7. Receiver Test Circuit and Voltage Waveforms

THERMAL CHARACTERISTICS D PACKAGE PARAMETER Junctiontoambient thermal reisistance, JA Junctiontoboard thermal reisistance, JB Junctiontocase thermal reisistance, JC Average power dissipation, P(AVG) RL = 54 , input to D is 10 Mbps 50% duty cycle square wave, VCC = 5.25 V, TJ = 130 C. TEST CONDITIONS Low-K board, no air flow High-K board, no air flow High-K board, no air flow MIN TYP 199.4 119 67 46.6 330 mW C/W MAX UNIT
Thermal shutdown junction temperature, TSD 165 C See TI application note literature number SZZA003, Package Thermal Characterization Methodologies, for an explanation of this parameter.
DALLAS, TEXAS 75265


1.5 V 1.5 V S1 2 k S2 5V
CL = 15 pF (see Note B) Generator (see Note A)
5 k
1N916 or Equivalent
50 S3 TEST CIRCUIT
Input
1.5 V
3V S1 to 1.5 V S2 Open S3 Closed 0V
Input
1.5 V
3V S1 to 1.5 V S2 Closed S3 Opened 0V
tPZH VOH Output 1.5 V 0V Output
tPZL 4.5 V 1.5 V VOL
Input
1.5 V
3V S1 to 1.5 V S2 Closed S3 Closed 0V
Input
1.5 V
3V S1 to 1.5 V S2 Closed S3 Closed 0V
tPHZ VOH Output 0.5 V 1.3 V Output
tPLZ 1.3 V 0.5 V VOL VOLTAGE WAVEFORMS
Figure 8. Receiver Test Circuit and Voltage Waveforms

10
DALLAS, TEXAS 75265

THERMAL CHARACTERISTICS OF IC PACKAGES

JA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient temperature divided by the operating power JA is NOT a constant and is a strong function of
D D D
the PCB design (50% variation) altitude (20% variation) device power (5% variation)
JA can be used to compare the thermal performance of packages if the specific test conditions are defined and used. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations, and the thermal characteristics of holding fixtures. JA is often misused when it is used to calculate junction temperatures for other installations. TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition thermal performance and consists of a single trace layer 25 mm long and 2-oz thick copper. The high-k board gives best case inuse condition and consists of two 1-oz buried power planes with a single trace layer 25 mm long with 2-oz thick copper. A 4% to 50% difference in JA can be measured between these two test cards JC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by the operating power. It is measured by putting the mounted package up against a copper block cold plate to force heat to flow from die, through the mold compound into the copper block. JC is a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic to predict junction temperature as it provides pessimistic numbers if the case temperature is measured in a non-standard system and junction temperatures are backed out. It can be used with JB in 1-dimensional thermal simulation of a package system. JB (Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a coldplate structure. JB is only defined for the high-k test card. JB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal resistance (especially for BGAs with thermal balls) and can be used for simple 1-dimensional network analysis of package system (see Figure 1).
Ambient Node qCA Calculated Surface Node qJC Calculated/Measured Junction qJB Calculated/Measured
PC Board
Figure 1. Thermal Resistance
DALLAS, TEXAS 75265
11

MECHANICAL INFORMATION
D (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.010 (0,25) M
Gage Plane
0.010 (0,25) 1 A 7 08 0.044 (1,12) 0.016 (0,40)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX
8 0.197 (5,00) 0.189 (4,80)
14 0.344 (8,75) 0.337 (8,55)
16 0.394 (10,00) 0.386 (9,80) 4040047 / D 10/96
A MIN
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012
12
DALLAS, TEXAS 75265

FK (S-CQCC-N**)
28 TERMINALS SHOWN
LEADLESS CERAMIC CHIP CARRIER
18
17
16
15
14
13
12
NO. OF TERMINALS ** 11 10 28 9 8 7 6 68 5 84 44 52 20
A MIN 0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.740 (18,78) 0.938 (23,83) 1.141 (28,99) MAX 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) MIN 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6)
B MAX 0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0)
19 20 21 B SQ 22 A SQ 23 24 25
26
27
28
4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25)
0.020 (0,51) 0.010 (0,25)
0.055 (1,40) 0.045 (1,14)
0.045 (1,14) 0.035 (0,89)
0.028 (0,71) 0.022 (0,54) 0.050 (1,27)
0.045 (1,14) 0.035 (0,89)
4040140 / C 11/95 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold-plated. Falls within JEDEC MS-004
DALLAS, TEXAS 75265
13

JG (R-GDIP-T8)
0.400 (10,20) 0.355 (9,00) 8 5
CERAMIC DUAL-IN-LINE PACKAGE
0.280 (7,11) 0.245 (6,22)
4 0.065 (1,65) 0.045 (1,14)
0.020 (0,51) MIN
0.310 (7,87) 0.290 (7,37)
0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN
0.063 (1,60) 0.015 (0,38) 0.100 (2,54)
0.023 (0,58) 0.015 (0,38) 0.014 (0,36) 0.008 (0,20)
015
4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only. Falls within MIL-STD-1835 GDIP1-T8
14
DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI001A JANUARY 1995 REVISED JUNE 1999
P (R-PDIP-T8)
0.400 (10,60) 0.355 (9,02) 8 5
PLASTIC DUAL-IN-LINE
0.260 (6,60) 0.240 (6,10)
4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.010 (0,25) NOM Gage Plane
0.020 (0,51) MIN
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M
0.430 (10,92) MAX
4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
DALLAS, TEXAS 75265
15
PACKAGE OPTION ADDENDUM

www.ti.com
12-Jan-2007
PACKAGING INFORMATION
Orderable Device 5962-9318301Q2A 5962-9318301QPA SN65LBC176D SN65LBC176DG4 SN65LBC176DR SN65LBC176DRG4 SN65LBC176P SN65LBC176PE4 SN65LBC176QD SN65LBC176QDR SN75LBC176D SN75LBC176DG4 SN75LBC176DR SN75LBC176DRG4 SN75LBC176P SN75LBC176PE4 SNJ55LBC176FK SNJ55LBC176JG
(1)
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type LCCC CDIP SOIC SOIC SOIC SOIC PDIP PDIP SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP LCCC CDIP
Package Drawing FK JG D D D D P P D D D D D D P P FK JG
Pins Package Eco Plan (2) Qty 20 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 20 8 1 1 75 75 TBD TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
POST-PLATE N / A for Pkg Type A42 SNPB CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-220C-UNLIM Level-1-220C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type
2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 50 50 75 2500 75 75 Pb-Free (RoHS) Pb-Free (RoHS) TBD TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 50 50 1 1 Pb-Free (RoHS) Pb-Free (RoHS) TBD TBD
POST-PLATE N / A for Pkg Type A42 SNPB N / A for Pkg Type
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com
12-Jan-2007
temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MCER001A JANUARY 1995 REVISED JANUARY 1997
JG (R-GDIP-T8)
0.400 (10,16) 0.355 (9,00) 8 5
CERAMIC DUAL-IN-LINE
0.280 (7,11) 0.245 (6,22)
4 0.065 (1,65) 0.045 (1,14)
0.063 (1,60) 0.015 (0,38)
0.020 (0,51) MIN
0.310 (7,87) 0.290 (7,37)
0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN
0.023 (0,58) 0.015 (0,38) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20)
015
4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8
DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B OCTOBER 1996
FK (S-CQCC-N**)
28 TERMINAL SHOWN
LEADLESS CERAMIC CHIP CARRIER
18
17
16
15
14
13
12
NO. OF TERMINALS ** 11 10 28 9 8 7 6 68 5 84 44 52 20
A MIN 0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.739 (18,78) 0.938 (23,83) 1.141 (28,99) MAX 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) MIN 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6)
B MAX 0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0)
19 20 21 B SQ 22 A SQ 23 24 25
26
27
28
4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25)
0.020 (0,51) 0.010 (0,25)
0.055 (1,40) 0.045 (1,14)
0.045 (1,14) 0.035 (0,89)
0.028 (0,71) 0.022 (0,54) 0.050 (1,27)
0.045 (1,14) 0.035 (0,89)
4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004
DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI001A JANUARY 1995 REVISED JUNE 1999
P (R-PDIP-T8)
0.400 (10,60) 0.355 (9,02) 8 5
PLASTIC DUAL-IN-LINE
0.260 (6,60) 0.240 (6,10)
4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.010 (0,25) NOM Gage Plane
0.020 (0,51) MIN
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M
0.430 (10,92) MAX
4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TIs terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TIs standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers Low Power Wireless amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti.com/lpw Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
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SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 DIFFERENTIAL BUS TRANSCEIVERS

SLLS067G AUGUST 1990 REVISED APRIL 2006

D Bidirectional Transceiver D Meets or Exceeds the Requirements of D D D D D D D D D D D D D D

D, JG, OR P PACKAGE (TOP VIEW)

FK PACKAGE (TOP VIEW)

LinBiCMOS and LinASIC are trademarks of Texas Instruments Incorporated.

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 DIFFERENTIAL BUS TRANSCEIVERS

logic diagram (positive logic)

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 DIFFERENTIAL BUS TRANSCEIVERS

schematics of inputs and outputs

100 k NOM A Port Only A or B Input 18 k NOM

100 k NOM B Port Only

absolute maximum ratings

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 DIFFERENTIAL BUS TRANSCEIVERS

recommended operating conditions

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 DIFFERENTIAL BUS TRANSCEIVERS

Differential output voltage

Differential output voltage

Short-circuit output current

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 DIFFERENTIAL BUS TRANSCEIVERS

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 DIFFERENTIAL BUS TRANSCEIVERS

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 DIFFERENTIAL BUS TRANSCEIVERS

PARAMETER MEASUREMENT INFORMATION

Figure 1. Driver VOD and VOC

Figure 2. Driver VOD3

Generator (see Note A)

tt(OD) TEST CIRCUIT

2.5 V tt(OD) VOLTAGE WAVEFORMS

Figure 3. Driver Test Circuit and Voltage Waveforms

Generator (see Note A)

Figure 4. Driver Test Circuit and Voltage Waveforms

Generator (see Note A)

Figure 5. Driver Test Circuit and Voltage Waveforms

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 DIFFERENTIAL BUS TRANSCEIVERS

PARAMETER MEASUREMENT INFORMATION

VID VOH VOL + IOL IOH

Figure 6. Receiver VOH and VOL

Figure 7. Receiver Test Circuit and Voltage Waveforms

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SN55LBC176, SN65LBC176, SN65LBC176Q, SN75LBC176 DIFFERENTIAL BUS TRANSCEIVERS

PARAMETER MEASUREMENT INFORMATION

CL = 15 pF (see Note B) Generator (see Note A)

3V S1 to 1.5 V S2 Open S3 Closed 0V

3V S1 to 1.5 V S2 Closed S3 Opened 0V

tPZH VOH Output 1.5 V 0V Output

tPZL 4.5 V 1.5 V VOL

3V S1 to 1.5 V S2 Closed S3 Closed 0V