Devices & Circuit Simulation Lab( 10B17EC471) Experiment 1 Note: Students will perform the experiment according to their

group number given below. Group-1

(a) Introduction to P-spice Software. (b) Simulate the following circuit using PSpice to find out voltage at all the nodes and current flowing in all branches. Verify the results obtained from the simulation by using Pspice, Nodal analysis and Mesh analysis.

(c) Simulate the following circuit using Pspice and analyze the transient response of it.

Group-2
(a) Introduction to P-spice Software. (b) Simulate the following circuit using PSpice to find out voltage at all the nodes and current flowing in all branches. Verify the results obtained from the simulation by using Pspice, Nodal analysis and Mesh analysis.

(c) Simulate the following circuit using Pspice and analyze the transient response of it.

Group-3
(a) Introduction to P-spice Software. (b) Simulate the following circuit using PSpice to find out voltage at all the nodes and current flowing in all branches. Verify the results obtained from the simulation by using Pspice, Nodal analysis and Mesh analysis.

(c) Simulate the following circuit using Pspice and analyze the transient response of it.

Group-4
(a) Introduction to P-spice Software. (b) Simulate the following circuit using PSpice to find out voltage at all the nodes and current flowing in all branches. Verify the results obtained from the simulation by using Pspice, Nodal analysis and Mesh analysis.

(c) Simulate the following circuit using Pspice and analyze the transient response of it.

Group-5
(a) Introduction to P-spice Software. (b) Simulate the following circuit using PSpice to find out voltage at all the nodes and current flowing in all branches. Verify the results obtained from the simulation by using Pspice, Nodal analysis and Mesh analysis.

(c) Simulate the following circuit using Pspice and analyze the transient response of it.

Group-6
(a) Introduction to P-spice Software. (b) Simulate the following circuit using P-Spice to find out voltage at all the nodes and current flowing in all branches. Verify the results obtained from the simulation by using Pspice, Nodal analysis and Mesh analysis.

(c) Simulate the following circuit using Pspice and analyze the transient response of it.

Group-7
(a) Introduction to P-spice Software. (b) Simulate the following circuit using P-Spice to find out voltage at all the nodes and current flowing in all branches. Verify the results obtained from the simulation by using Pspice, Nodal analysis and Mesh analysis.

(c) Simulate the following circuit using Pspice and analyze the transient response of it.

Group-8
(a) Introduction to P-spice Software. (b) Simulate the following circuit using P-Spice to find out voltage at all the nodes and current flowing in all branches. Verify the results obtained from the simulation by using Pspice, Nodal analysis and Mesh analysis.

(c) Simulate the following circuit using Pspice and analyze the transient response of it.

Experiment-2
Group1: Design a ac to dc converter using full wave rectifier circuit for following specifications: Vdc=3.5V, load current IL= 50mA and a ripple factor r=2% . Group2: Design a ac to dc converter using full wave rectifier circuit for following specifications: Vdc=4.0V, load current IL= 50mA and a ripple factor r=3%. Group3: Design a ac to dc converter using full wave rectifier circuit for following specifications: Vdc=4.5V, load current IL= 50mA and a ripple factor r=4%. Group4: Design a ac to dc converter using full wave rectifier circuit for following specifications: Vdc=5V, load current IL= 50mA and a ripple factor r=5%. Group5: Design a ac to dc converter using full wave rectifier circuit for following specifications: Vdc=3.5V, load current IL= 60mA and a ripple factor r=2% . Group6: Design a ac to dc converter using full wave rectifier circuit for following specifications: Vdc=4.0V, load current IL= 70mA and a ripple factor r=3%. Group7: Design a ac to dc converter using full wave rectifier circuit for following specifications: Vdc=4.5V, load current IL= 80mA and a ripple factor r=4%. Group8: Design a ac to dc converter using full wave rectifier circuit for following specifications: Vdc=5V, load current IL= 90mA and a ripple factor r=5%.

Experiment 3
Group 1: Design voltage doublers and Tripler using full wave rectifier circuit to produce a dc output voltage of 12 & 18 volts respectively using an appropriate voltage source. Group 2: Design voltage doublers and Tripler using full wave rectifier circuit to produce a dc output voltage of 14 & 15 volts respectively using an appropriate voltage source. Group 3: Design voltage doublers and Tripler using full wave rectifier circuit to produce a dc output voltage of 10 & 18 volts respectively using an appropriate voltage source. Group 4: Design voltage doublers and Tripler using full wave rectifier circuit to produce a dc output voltage of 8 & 12 volts respectively using an appropriate voltage source. Group 5: Design voltage doublers and Tripler using full wave rectifier circuit to produce a dc output voltage of 12 & 18 volts respectively using an appropriate voltage source. Group 6: Design voltage doublers and Tripler using full wave rectifier circuit to produce a dc output voltage of 14 & 15 volts respectively using an appropriate voltage source. Group 7: Design voltage doublers and Tripler using full wave rectifier circuit to produce a dc output voltage of 10 & 18 volts respectively using an appropriate voltage source. Group 8: Design voltage doublers and Tripler using full wave rectifier circuit to produce a dc output voltage of 8 & 12 volts respectively using an appropriate voltage source.

Experiment-4
Group 1 : Design a CE, BJT (BC 548A, =200) amplifier with voltage divider bias for the following specification Av=10, Ri > 2 kohms, Ro< 2k ohms. Simulate it using Pspice and explain the effect of by passing the emitter resistance via capacitor. Also show its AC analysis, DC analysis and Bias point calculation. Group 2 : Design a CE, BJT (BC 548A, =190) amplifier with voltage divider bias for the following specification Av=11, Ri > 2.2kohms, Ro< 2.50 k ohms. Simulate it using Pspice and explain the effect of by passing the emitter resistance via capacitor. Also show its AC analysis, DC analysis and Bias point calculation. Group 3 : Design a CE, BJT (BC 548A, =180) amplifier with voltage divider bias for the following specification Av=12, Ri > 2.4kohms, Ro< 3.0 k ohms. Simulate it using Pspice and explain the effect of by passing the emitter resistance via capacitor. Also show its AC analysis, DC analysis and Bias point calculation. Group 4 : Design a CE, BJT (BC 548A, =170) amplifier with voltage divider bias for the following specification Av=13, Ri > 2.6kohms, Ro< 3.50 k ohms. Simulate it using Pspice and explain the effect of by passing the emitter resistance via capacitor. Also show its AC analysis, DC analysis and Bias point calculation. Group 5 : Design a CE, BJT (BC 548A, =160) amplifier with voltage divider bias for the following specification Av=14, Ri > 2.8kohms, Ro< = 4.00 k ohms. Simulate it using Pspice and explain the effect of by passing the emitter resistance via capacitor. Also show its AC analysis, DC analysis and Bias point calculation. Group 6 : Design a CE, BJT (BC 548A, , =150) amplifier with voltage divider bias for the following specification Av=15, Ri > 3kohms, Ro< 4.50 k ohms. Simulate it using Pspice and explain the effect of by passing the emitter resistance via capacitor. Also show its AC analysis, DC analysis and Bias point calculation. Group 7 : Design a CE, BJT (BC 548A, =200) amplifier with voltage divider bias for the following specification Av=16, Ri > 2kohms, Ro< 2.00 k ohms. Simulate it using Pspice and explain the effect of by passing the emitter resistance via capacitor. Also show its AC analysis, DC analysis and Bias point calculation. Group 8 : Design a CE, BJT (BC 548A, =190) amplifier with voltage divider bias for the following specification Av=17, Ri > 2.2kohms, Ro< 2.50 k ohms. Simulate it using Pspice and explain the effect of by passing the emitter resistance via capacitor. Also show its AC analysis, DC analysis and Bias point calculation.

Experiment-5
Group 1: Design the following active filters and plot their frequency response (a) 1st order low pass filter with cut-off frequency fc= 1 kHz and pass-band gain =2 (b) 2nd order high pass filter with cut-off frequency fc= 11 kHz (c) 2nd order Band pass filter with cut-off frequencies fL=200Hz and fH= 2.2 kHz Group 2: Design the following active filters and plot their frequency response (a) 1st order low pass filter with cut-off frequency fc= 1.5 kHz and pass-band gain =2.5 (b) 2nd order high pass filter with cut-off frequency fc= 12 kHz (c) 2nd order Band pass filter with cut-off frequencies fL=250Hz and fH= 2.250 kHz Group 3: Design the following active filters and plot their frequency response (a) 1st order low pass filter with cut-off frequency fc= 2 kHz and pass-band gain =1.5 (b) 2nd order high pass filter with cut-off frequency fc= 13 kHz (c) 2nd order Band pass filter with cut-off frequencies fL=300Hz and fH= 2.3 kHz Group 4: Design the following active filters and plot their frequency response (a) 1st order low pass filter with cut-off frequency fc= 3 kHz and pass-band gain =3 (b) 2nd order high pass filter with cut-off frequency fc= 15 kHz (c) 2nd order Band pass filter with cut-off frequencies fL=400Hz and fH= 2.5 kHz Group 5: Design the following active filters and plot their frequency response (a) 1st order low pass filter with cut-off frequency fc= 3.5 kHz and pass-band gain =2.5 (b) 2nd order high pass filter with cut-off frequency fc= 10 kHz (c) 2nd order Band pass filter with cut-off frequencies fL=450Hz and fH= 2.550 kHz Group 6: Design the following active filters and plot their frequency response (a) 1st order low pass filter with cut-off frequency fc= 4 kHz and pass-band gain =1.5 (b) 2nd order high pass filter with cut-off frequency fc= 9 kHz (c) 2nd order Band pass filter with cut-off frequencies fL=500Hz and fH= 3 kHz Group 7: Design the following active filters and plot their frequency response (a) 1st order low pass filter with cut-off frequency fc= 4.5 kHz and pass-band gain =2.0 (b) 2nd order high pass filter with cut-off frequency fc= 20 kHz (c) 2nd order Band pass filter with cut-off frequencies fL=1 kHz and fH= 4 kHz Group 8: Design the following active filters and plot their frequency response (a) 1st order low pass filter with cut-off frequency fc= 5.5 kHz and pass-band gain =2.5 (b) 2nd order high pass filter with cut-off frequency fc= 18 kHz (c) 2nd order Band pass filter with cut-off frequencies fL=2 kHz and fH= 4 kHz

Experiment-6
Group-1: Design the oscillator circuits for following specifications (a) Phase shift oscillator with oscillation frequency f0 = 5 kHz (b) Wein bridge oscillator with oscillation frequency f0 = 100 kHz Group-2: Design the oscillator circuits for following specifications (a)Phase shift oscillator with oscillation frequency f0 = 6 kHz (b)Wein bridge oscillator with oscillation frequency f0 = 120 kHz Group-3: Design the oscillator circuits for following specifications (a)Phase shift oscillator with oscillation frequency f0 = 7 kHz (b)Wein bridge oscillator with oscillation frequency f0 = 140 kHz Group-4 :Design the oscillator circuits for following specifications (a)Phase shift oscillator with oscillation frequency f0 = 8 kHz (b)Wein bridge oscillator with oscillation frequency f0 = 160 kHz Group-5: Design the oscillator circuits for following specifications (a) Phase shift oscillator with oscillation frequency f0 = 5.5 kHz (b) Wein bridge oscillator with oscillation frequency f0 = 110 kHz Group-6: Design the oscillator circuits for following specifications (a)Phase shift oscillator with oscillation frequency f0 = 6.5 kHz (b)Wein bridge oscillator with oscillation frequency f0 = 130 kHz Group-7: Design the oscillator circuits for following specifications (a)Phase shift oscillator with oscillation frequency f0 = 7.5 kHz (b)Wein bridge oscillator with oscillation frequency f0 = 150 kHz Group-8:Design the oscillator circuits for following specifications (a)Phase shift oscillator with oscillation frequency f0 = 8.5 kHz (b)Wein bridge oscillator with oscillation frequency f0 = 170 kHz

Experiment-7
Group 1: (a) Design an amplitude modulator circuit using AD633 to amplitude modulate a sinusoidal carrier signal of 50 kHz by a sinusoidal message signal to produce a modulation index of 0.5. The upper and lower side band frequencies are 55 kHz & 45 kHz respectively. (b) Design an envelope detector circuit to demodulate the amplitude modulated signal obtained in part (a) Group 2: (a) Design an amplitude modulator circuit using AD633 to amplitude modulate a sinusoidal carrier signal of 50 kHz by a sinusoidal message signal to produce a modulation index of 0.4. The upper and lower side band frequencies are 52 kHz & 48 kHz respectively. (b) Design an envelope detector circuit to demodulate the amplitude modulated signal obtained in part (a) Group 3: (a) Design an amplitude modulator circuit using AD633 to amplitude modulate a sinusoidal carrier signal of 55 kHz by a sinusoidal message signal to produce a modulation index of 0.6. The upper and lower side band frequencies are 57 kHz & 53 kHz respectively. (b) Design an envelope detector circuit to demodulate the amplitude modulated signal obtained in part (a) Group 4: (a) Design an amplitude modulator circuit using AD633 to amplitude modulate a sinusoidal carrier signal of 52 kHz by a sinusoidal message signal to produce a modulation index of 0.3. The upper and lower side band frequencies are 56 kHz & 48 kHz respectively. (b) Design an envelope detector circuit to demodulate the amplitude modulated signal obtained in part (a) Group 5: (a) Design an amplitude modulator circuit using AD633 to amplitude modulate a sinusoidal carrier signal of 60 kHz by a sinusoidal message signal to produce a modulation index of 0.2. The upper and lower side band frequencies are 63 kHz & 57 kHz respectively. (b) Design an envelope detector circuit to demodulate the amplitude modulated signal obtained in part (a) Group 6: (a) Design an amplitude modulator circuit using AD633 to amplitude modulate a sinusoidal carrier signal of 58 kHz by a sinusoidal message signal to produce a modulation index of 0.5. The upper and lower side band frequencies are 56 kHz & 54 kHz respectively. (b) Design an envelope detector circuit to demodulate the amplitude modulated signal obtained in part (a)

Group 7: (a) Design an amplitude modulator circuit using AD633 to amplitude modulate a sinusoidal carrier signal of 40 kHz by a sinusoidal message signal to produce a modulation index of 0.2. The upper and lower side band frequencies are 42 kHz & 38 kHz respectively. (b) Design an envelope detector circuit to demodulate the amplitude modulated signal obtained in part (a) Group 8: (a) Design an amplitude modulator circuit using AD633 to amplitude modulate a sinusoidal carrier signal of 46 kHz by a sinusoidal message signal to produce a modulation index of 0.6. The upper and lower side band frequencies are 50 kHz & 42 kHz respectively. (b) Design an envelope detector circuit to demodulate the amplitude modulated signal obtained in part (a)

Experimrnt-8
Group 1: Design a circuit for PWM generation using 555 timer to modulating a square wave of 5V amplitude and 2kHz frequency by sinusoidal signal of frequency of 50Hz to produce duty cycle in a range of 10% to 90%. Group 2: Design a circuit for PWM generation using 555 timer to modulating a square wave of 5V amplitude and 2.5 kHz frequency by sinusoidal signal of frequency of 50Hz to produce duty cycle in a range of 20% to 80%. Group 3: Design a circuit for PWM generation using 555 timer to modulating a square wave of 5V amplitude and 2.0 kHz frequency by sinusoidal signal of frequency of 50Hz to produce duty cycle in a range of 30% to 70%. Group 4: Design a circuit for PWM generation using 555 timer to modulating a square wave of 5V amplitude and 1 kHz frequency by sinusoidal signal of frequency of 50Hz to produce duty cycle in a range of 20% to 80%. Group 5: Design a circuit for PWM generation using 555 timer to modulating a square wave of 5V amplitude and 2kHz frequency by sinusoidal signal of frequency of 50Hz to produce duty cycle in a range of 10% to 80%. Group 6: Design a circuit for PWM generation using 555 timer to modulating a square wave of 5V amplitude and 2.5 kHz frequency by sinusoidal signal of frequency of 50Hz to produce duty cycle in a range of 15% to 85%. Group 7: Design a circuit for PWM generation using 555 timer to modulating a square wave of 5V amplitude and 2.0 kHz frequency by sinusoidal signal of frequency of 50Hz to produce duty cycle in a range of 30% to 75%. Group 8: Design a circuit for PWM generation using 555 timer to modulating a square wave of 5V amplitude and 1 kHz frequency by sinusoidal signal of frequency of 50Hz to produce duty cycle in a range of 25% to 85%.

Experiment-9
Group1: Design a Mod-8 up/down Counter using J-K flip flop. Group2: Design a Mod-7 up/down Counter using J-K flip flop. Group3: Design a Mod-10 up/down Counter using J-K flip flop. Group4: Design a Mod-12 up/down Counter using J-K flip flop. Group5: Design a Mod-6 up/down Counter using J-K flip flop. Group6: Design a Mod-5 up/down Counter using J-K flip flop. Group7: Design a Mod-11 up/down Counter using J-K flip flop. Group8: Design a Mod-13 up/down Counter using J-K flip flop.

Experiment-10
Design the following shift registers (same for all groups) (a) 4-bit serial in serial out (SISO) (b) 4-bit serial in serial out (SIPO) (c) 4-bit bidirectional

Experiment- 11
Find out the lock range, capture range and free running frequency of the PLL (LM-565). Also study its non linear characteristics. (same for all groups)

Experiment- 12
Mini Project