2010 19th IEEE Asian Test Symposium

New Microcodes Generation Technique for Programmable Memory Built-In Self Test
NurQamarina MohdNoor Azilah Saparon Yusrina Yusof
Universiti Teknologi MARA 40450 Shah Alam Selangor, Malaysia nurqamarina@isiswa.uitm.edu.my
AbstractMemory Built-in Self Test (MBIST) is the popular approach to test embedded memories. There are two types of MBIST controllers; the state-machine based and the microcode-based where the microcode-based controllers are commonly designed as programmable memory BIST (PMBIST). Most microcode-based P-MBISTs [2, 5] employ one instruction per MARCH operation. Latest microcodebased PMBIST [6] utilizes only one instruction per MARCH element. This technique certainly decreases the area overhead because the numbers of required instructions are reduced. However, numbers of operations per sequence cause the instruction lengths to be varied. This unfixed microcodes instruction length still results in higher area overhead. To overcome this problem, a new way of microcoding the test instruction is created. The components of the proposed P-MBIST controller are designed and explained. These controllers are written using Verilog HDL and implemented in ALTERA Cyclone II FPGA. Analysis on the architectures of the proposed P-MBIST and P-MBIST [6] is performed. The simulation and synthesis result of the proposed P-MBIST controller is presented and discussed. KeywordsVerilog; area; programmable; MBIST; microcode-based;

Mahmud Adnan
INTEL Penang, Malaysia mahmud.adnan@intel.com

I.

INTRODUCTION

System-on-chip (SoC) designs are moving from logic dominant chips to memory dominant chips to be able to meet future application requirements. This trend results in the dependence of the overall SoC yield on the memory yield [1]. In order to achieve good memory yield, an atspeed test technique such as built-in self test (BIST) must be implemented to test these embedded memories. Memory built-in self test (MBIST) is said to be programmable if it allows the modification of the test algorithm during the test application [1] without major changes to the BIST design. MBIST usually use the deterministic pattern such as MARCH test algorithm to test memories. In MARCH test algorithm, the patterns are generated according to specified predetermined values [1]. Basically, there are two types of BISTs; state machines (FSM)-based and microcode-based. In FSM-based controller, the control signals for the operation of BIST controller are defined as state machines [2, 3, 4]. For microcode-based controller, memory test patterns are written as sets of instructions and loaded into the memory
1081-7735/10 $26.00 2010 IEEE DOI 10.1109/ATS.2010.76 407

BIST controller [2, 5, 6]. FSM-based controllers are usually hardwired BISTs (non-programmable memory BIST) but latest FSM-based controllers are designed to be programmable [7, 8]. For microcode-based controllers, they are typically designed as programmable memory BIST (P-MBIST) where they are flexible in selecting the instructions from the instructions storage. However, the flexibility results in higher area usage for the P-MBIST controllers because the storage area of these instructions microcodes. Microcode-based P-MBIST [2] is designed by having a two dimensional Z * Y buffer to store the instructions microcodes. The supported microcode is 10-bit wide which consists of 2-bit for address generation, 2-bit for data generation, 1-bit for compare, 2-bit for read/write operation and 3-bit for controlling the flow of the microcode. Another microcode-based P-MBIST [5] is developed to have a microcode controller which uses instruction register to store the instructions. This controller is claimed to have the instructions microcode to be set as same as the microcode-based P-MBIST in [2]. The special feature of both of the controllers lies in the 3-bit microcode for flow control where this 3-bit microcode lets certain instructions to be saved in the reference register for repetition in case of symmetric MARCH operation in an MARCH element. However, this special feature is less significant in minimizing the silicon area usage because there are still large numbers of instructions need to be generated for these controllers [2, 5]. Latest microcode-based P-MBIST [6] employs only one instruction per MARCH element and the instruction is fed to the controller using serial shift operation from scan path [6]. The technique certainly reduces area overhead compared to P-MBIST [2, 5] due to less numbers of instructions generated and the elimination of the instruction storage. The microcode of MARCH operation in this controller is set as 2-bit wide where the first bit represents the MARCH operation (e.g. read or writes) and the second bit indicates the polarity of the test data associated with the MARCH operation. For example, two MARCH operations per MARCH element produce 4-bit microcode while six MARCH operations per MARCH element yield 12-bit microcode. Uncertainty in the numbers of operations in a MARCH element causes the

length of the instructions microcode to be varied and increases the area overhead. Thus, lower area usage can be achieved if the improvement is made on the microcodes generation technique by reducing and fixing the length of the microcode generated. In this paper, a new microcode technique for P-MBIST is proposed. The proposed P-MBIST replaces the instruction register in [6] by utilizing a state-machine based instruction encoder to encode the instruction as cluster of microcode and a state-machine based operation decoder to decode the MARCH operation and test data to be applied to the memory under test (MUT). This technique produces a P-MBIST controller that has lower area overhead than P-MBIST controller in [6]. The paper is organized as follows; Section 2 introduces the proposed P-MBIST controllers and compares its architecture with the architecture of P-MBIST which also used one instruction per MARCH element. The simulation and synthesis results are discussed in Section 3 while Section 4 concludes the paper. II. PROPOSED MBIST ARCHICTECTURE In this section, the proposed P-MBIST architecture is divided in two sub-sections; the proposed microcodes generation technique and the proposed P-MBIST controller.. A. Proposed microcodes generation technique In order to illustrate the development of this new microcode technique, eight typical MARCH algorithm tests ranging from the early algorithms to the latest algorithms are tabulated.
TABLE I. Algorithm MATS+ (3n) MARCH X (4n) MARCH C(6n) MARCH A (5n) MARCH B (5n) MARCH U (5n) MARCH LR (6n) MARCH SS (6n) DESRIPTION OF TEST PATTERNS USED March Elements (w0); (r0,w1); (r1,w0) (w0); (r0,w1); (r1,w0); (r0) (w0); (r0,w1); (r1,w0); (r0,w1); (r1,w0); (r0) (w0); (r0,w1,w0,w1); (r1,w0,w1); (r1,w0,w1,w0); (r0,w1,w0) (w0); (r0,w1,r1,w0,r0,w1); (r1,w0,w1); (r1,w0,w1,w0); (r0;w1,w0) (w0); (r0,w1,r1,w0); (r0,w1); (r1,w0,r0,w1); (r0) (w0); (r0,w1); (r1,w0,r0,w1); (r1,w0); (r0,w1,r1,w0); (r0) (w0); (r0,r0,w0,r0,w1); (r1,r1,w1,r1,w0); (r0,r0,w0,r0,w1); (r1,r1,w1,r1,w0); (r0)

the bracket consist of read or write operations (r or w) and the test data (0 or 1). There are 13 distinct MARCH elements which are used repetitively in these eight MARCH test algorithms.
TABLE II. MARCH ELEMENTS ARE DIVIDED INTO THREE CLUSTERS

R/W Operations and Test Data in an Element

Cluster 1 Cluster 2 Cluster 3

1 2 3 4 5 6 7 8 9 10 11 12 13

w0 r0,w1 r1,w0 r0 r0,w1, r1,w0, r1,w0, r0,w1, r0,w1, r0,w1, r1,w0, r0, r1, w0,w1 w1 w1,w0 w0 r1,w0, r1,w0 r0,w1 r0,w0, r1,w1, r0,w1 r1,w0 r0,w1

Table II describes the read/write operations in the MARCH elements which divided into three clusters. Each cluster comprises of single MARCH operation or double MARCH operation. Single operation class signifies only one read or writes operation in a cluster (e.g. w0 or r0) and double operation class indicates a couple of read-writes operation or writes-writes operation in a cluster (e.g. r0w1 or w1w0). It could be seen that there are ten MARCH operations in Table II totaled from four distinct single operations; w0, r0, w1 and r1 and six different double operations; r0w1, w0w1, r0w0, r1w0, w1w0 and r1w1 can be extracted from all eight MARCH test algorithm.
TABLE III. Notations S1~S1 S0~S0 D0~D0 D1~D1 D2~D2 MARCH OPERATIONS AND THEIR NOTATIONS Operations w0w1 r0r1 r0,w1r1,w0 w0,w1w1,w0 r1,w1r0,w0

Table I shows the MARCH test algorithms with their MARCH elements. The arrows are the addressing orders; indicates ascending address order, designates descending address order and represents either both direction of addressing orders. The MARCH elements in
408

The MARCH operation and their equivalent notations are shown in Table III. The S stands for single operation while D indicates the double operation. The left right arrow () represents complement action performed on the left side operation. The complement of the left side

operation is the right side operation. As mentioned previously, there are four single operations. These four operations can further be reduced to only two operations which are S1 (w0) and S0 (r0) because the other two operations (w1 and r1) are the complements of former two classes respectively (~S1 and ~S0). For double operations, the six operations are reduced to three operations which are D0 (r0w1), D1 (w0w1) and D2 (r0w0) where the other three operations (r1w0, w0w1 and r1w1) are the complements of the former three operations respectively (~D0, ~D1 and ~D2).
TABLE IV. TABLE II IS REWRITTEN USING NOTATION CREATED FOR MARCH OPERATIONS R/W Operations and Test Data in an Element
Cluster 1 Cluster 2 Cluster 3

Macro Operation Code D1 !D1 D2 !D2

Operation class (0= single or 1= double) 1 1 1 1

Operation class (0= true op or 1= complement op) 0 1 0 1

Operation type 10 10 00 00

1 2 3 4 5 6 7 8 9 10 11 12 13

S1 D0 !D0 S0 D0, !D0, !D0, D0, D0, D0, !D0, S0, !S0, D1 !S1 !D1 S1 !D0, !D0 D0 !D2, D2, D0 D0 D0

The technique of creating new microcode from the simplified MARCH operations is explained in Table V. The first bit represents the operation classes where 0 means single operation and 1 denotes double operation. The second bit indicates the true or complement of the operation where 0 is the true operation and 1 is the complement operation. The third and fourth bits signify MARCH operation types. For single operation class, 10 represents the writes operation (w) and 01 indicates the read operation. For double operation class, 10 characterizes the writes-writes operation while 01 and 00 denote the read-writes operation where the test data are of inverted values and equal values respectively. B. Proposed MBIST Controller There are a minimum of one cluster and a maximum of three clusters of MARCH operations as discussed in the previous section. Each cluster is represented by 4-bit microcode. By taking the maximum number of operation clusters, the microcode for one MARCH element is 12-bit wide. This microcode increases to 15-bit wide because each cluster needs 1-bit microcode to indicate the last or not the last operation performed on an address. Then, another 1 bit is added to signify the addressing order. Now, the complete microcode for 1 MARCH element can be rearranged as following 16-bit microcode as shown in Figure 1. The MSB represents the addressing order and the remaining 15-bit wide are further divided into three 5-bit wide; bit 14 to bit 10, bit 9 to bit 5 and bit 4 to bit 0. The 5bit cluster is divided into three parts. The first part is the operation class (opcls) which is represented by bit 5 and bit 4. The second part is the operation type which is characterized by bit 3 and bit 2 and the final part is the last cluster run on the address which is determined by the last bit.

Table IV shows the revised version of Table II using the notation in Table III. Previous ten MARCH operations are simplified to five major MARCH operations and each comes with their complements. From the above simplified MARCH operations, a new microcode is created.
TABLE V. Macro Operation Code S1 !S1 S0 !S0 D0 !D0 Operation class (0= single or 1= double) 0 0 0 0 1 1 TABLE TYPE STYLES Operation class (0= true op or 1= complement op) 0 1 0 1 0 1

Operation type 10 10 01 01 01 01

Figure 1. The instructions microcode.

409

The controller comprises of 3 blocks; Addr Dec block to decode the address, Inst Enc block to encode the instruction, Inst Dec block to decode the read/write operation and test data for each of the MARCH element. The test management unit (Test Mgr) block is used to generate the injected test data to the memory under test (MUT) from the 2-bit controllers test data (data_i) and compare the injected data and the acquired data from the MUT. Figure 2 portrays the block diagram of the controller.

increment or decrement the address depending on the addressing order set by ado signal. In the test management unit (Test Mgr), the 2-bit test data (data_i) is replicated according to the number of bits of input data (data_o16) of memory under test (MUT).In this case, the MUT has 16-bit data width and 8-bit address width. The data_o16 is sent to the MUT along with read/write enable signal (we) which is directly fed from the instruction decoder (Inst Dec). The output data (q16) from the MUT is re-fed to the test management unit (Test Mgr) to be compared with the input data (data_o16).The fail indicator signal (flind) goes high if there is a discrepancy between the output data from the MUT and the input data from the controller. C. Comparison between controllers Two major factors that contribute to the reduction of the area overhead in the proposed controller are the microcode length and the controllers component blocks. First, lets take a look on the instructions microcode length factor. In the proposed controller, the microcode is set as 16 bits microcode where the MSB represents the addressing order and the remaining 15-bits are further divided into three 5-bits microcode consists of operation class, operation type and last cluster-on-test. However, for P-MBIST [6], the microcode is set as 20-bits where the MSB represents the addressing order, bits [18:7] indicate the MARCH operation and their test data polarity, bits [6:4] signify the limit of the cycle controllers counter and bits [3:0] represent the test data. The microcode in [6] can be longer than 20 bits since there are some extra features such as wait (W) signal for delay test, address modes (@modes) for different addressing modes and end-of-test signal (TE).These extra features are excluded from their microcode to ensure the comparison is valid because our proposed controller does not run the delay test and uses only up/down addressing mode. Hence, it is proved that under the same constraints, our proposed instructions microcode has low number of bits as compared to the microcode in [6]. Figure 3 depicts the instructions microcode of P-MBIST [6].

Figure 2. Block diagram of the proposed PMBIST.

The instruction is fed from the instruction storage to the address decoder (Addr Dec) and instruction encoder (Inst Enc) when the endel signal is high. The MSB of the instruction goes to the ado signal in the address decoder (Addr Dec) to indicate the addressing order of the MARCH element. The rest of the instruction is fed to the inst signal in the instruction decoder (Inst Enc).This block is controlled by the endrw signal fed from the instruction decoder (Inst Dec). The instruction is segregated into three microcodes clusters in this block. By referring to Table 6, the 2-bit opcls signal represents the operation class while the 2-bit optyp signal signifies the operation type. The lc signal indicates whether the microcodes cluster is the last cluster or not. The instruction decoder (Inst Dec) receives the opcode signal which is generated from the opcls and optyp signals in the BIST Controller. The opcode signal contains values of read/write enable signal (we) and the test data (data_i) of the MARCH operation in a cluster. The endrw signal designates the end of read/write operation and test data run in a cluster. The activation of endrw and lc signals

Figure 3. The instructions microcode from P-MBIST [6].

In our proposed controller, there are two major components of the design; instruction encoder (Inst Enc) and instruction decoder (Inst Dec). Figure 4 and Figure 5 shows the state machine of the instruction encoder and instruction decoder respectively. The Inst Enc consists of three encoding states; ucode enc1, ucode enc2 and ucode enc3. In each state, the operation class signal (opcls),

410

operation type (optyp) and the last cluster (lc) signals are encoded from the cluster of microcode. The opcls and the optyp signals are decoded as the read/write enable signal and the test data by the Inst Dec. The Inst Dec comprises of two states; ucode dec1 and ucode dec2 to decode the single (S#) or double operation (D#).Both states are activated for double operation but for single operation, only ucode dec1 is activated.

this simulation, 7-bit addressing scheme are used. Figure 6 depicts the simulation of the controller by inserting instructions microcode for element 9 (refer to Table 5) which is 110010_11010_10011. The underscore (_) is used to separate a microcodes cluster from another microcodes cluster. For element 9, all three microcodes cluster are decoded to their specific opcode; 1001(r0w1), 1100(r1w0) and 1001(r0w1). The input data is written to or read from the memory under test (MUT) after 1 clock cycle. The flind signal produces value 0 since the test is run on the normal memory unit which yields the desired output data.

Figure 4. State-machine of instruction encoder.

Figure 6. Simulation result of good memory unit

To further test the capability of the controller to detect fault, the faulty memory unit with stuck-at 1fault is used as memory under test. From Figure 7, it is observed that the memory has a stuck-at-1 fault. The flind signal generates value 1 since there is a discrepancy between the test data from the controller and the output data from the memory.

Figure 5. State-machine of instruction decoder.

Comparing P-MBIST in [6] to our proposed P-MBIST controller, our controller is more simpler and utilizes fewer number of logics because it utilizes only two component; instruction encoder (Inst Enc) and the instruction decoder (Inst Dec) to control the what operations and data to be tested on the memory from the instruction given. III. EXPERIMENTAL RESULT
Figure 7. Simulation result of faulty memory unit

RTL simulation and synthesis of the proposed PMBIST controller is performed and the results are explained in detail in the subsequent sub-sections. A. Simulation Result In the first experiment, the RTL model of the proposed P-MBIST is developed and simulated using MODELSIMALTERA to observe its functionality. All MARCH elements in all eight MARCH test algorithms are simulated on the good memory unit and the faulty memory unit to ensure the correct operation of this controller. In

B. Synthesis Result In the second experiment, the proposed P-MBIST controller and the previous P-MBIST controllers [6] are synthesized using Mentor Graphics Precision Synthesis Tool and targeted to ALTERAs Cyclone II (EP2C20P484C) device. In this experiment, the complete

411

test instructions for both P-MBIST controllers are stored in ROM. The area and speed of each of the proposed PMBIST controller together with the ROM area is compared to the P-MBIST controllers [6].
TABLE VI. Controllers Proposed PMBIST PMBIST[6] AREA AND SPEED COMPARISON Storage Area (LEs) Speed (MHz)

[5]

[6]

Controller Area(LEs)

[7]

16 27

40 61

195.01 195.01

[8]

Haron. Z,Ibrahim.M, FPGA Implementation of Microcode-based and FSM-based Memory Built In Self Test , in IASTED International Conference Advances in Computer Science and Technology (ACST), 2008. Slimane Boutobza, Michael Nicolaidis, Kheiredine M.Lamara and Andrea Costa, Programmable Memory BIST, in Proc. IEEE International Test Conference (ITC), 2005. WonGi Hong, JungDai Choi, Hoon Chang, A Programmable Memory BIST for Embedded Memory in Proc. IEEE International SoC Design Conference (SoCC), 2008. Po-Chang Tsai, Sying-Jyan Wang and Feng-Ming Chang, FSMBased Programmable Memory BIST with Macro Command in Proc. IEEE International Workshop on Memory Technology, Design, and Testing (MTDT), 2005.

The first column (see Table VI) lists the BIST controllers used for comparison in this experiment. The second, third and fourth columns show BIST controller area, instruction ROM storage area and speed of each controller consecutively. The area is determined in terms of logic elements (LE) whilst the speed is evaluated megahertz (MHz). From Table VI, it is observed that there is 41 percent of the controller area reduction when the proposed P-MBIST is compared to the P-MBIST2 [6]. The ROM storage area is also reduced to 34 percent compared to the P-MBIST [6].Both controllers performed on the same speed when run on the memory under test (MUT). IV. CONCLUSION The proposed P-MBIST is designed to have a reduced and fixed microcodes instruction length. The controllers component blocks are also optimized to eliminate unnecessary logics. These techniques produce a microcode-PMBIST controller that employs lower number of logic elements as compared to the previous P-MBISTs [6]. The simulation result proves that the proposed PMBIST controller functions as intended whilst the synthesis result justifies that an area-efficient P-MBIST design can be achieved by improving the instructions microcode generation technique accompanied by optimizing the controllers components block. ACKNOWLEDGMENT This paper is part of the research project which is funded under academic research grant (PROJECT CODE 600IRDC/INTEL 16/6/2(11/2008)) supplied by INTEL Malaysia. REFERENCES
[1] Said Hamdioui, Georgi Gaydadjiev, Ad J. Van de Goor The State-of-Art and Future Trends in Testing Embedded Memories in Proc. IEEE International Workshop on Memory Technology, Design, and Testing (MTDT), 2004. K.Zarrineh, and S.J. Upadhyaya, On programmable memory built in-self test architecture in Proc. IEEE Design, Automation and Test Conference (DATE), 1999. R. Dean Adam, High Performance Memory Testing, Chapter 11: State Machine BIST, Kluwer Academic Publisher, 2003. Charles E.Stroud, A Designers Guide to Built-In Self Test, Chapter 12: BIST for Regular Structure, Kluwer Academic Publisher, 2002.

[2]

[3] [4]

412