A-Si TFT LCD Single Chip Driver 240Rgbx320 Resolution and 262K Color Datasheet

ILI9331
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Datasheet
Version: V0.09 Document No.: ILI9331DS_V0.09.pdf
ILI TECHNOLOGY CORP.

8F, No.38, Taiyuan St., Jhubei City, Hsinchu County 302, Taiwan, R.O.C Tel.886-3-5600099; Fax.886-3-5600055 http://www.ilitek.com
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Table of Contents Section
ILI9331
Page
1. Introduction.................................................................................................................................................... 5 2. Features ........................................................................................................................................................ 5 3. Block Diagram ............................................................................................................................................... 5 4. Pin Descriptions ............................................................................................................................................ 5 5. Pad Arrangement and Coordination.............................................................................................................. 5 6. Block Description .......................................................................................................................................... 5 7. System Interface ........................................................................................................................................... 5 7.1. 7.2. Interface Specifications .................................................................................................................... 5 Input Interfaces ................................................................................................................................ 5 7.2.1. 7.2.2. 7.2.3. 7.2.4. 7.3. 7.4. 7.5. i80/18-bit System Interface.................................................................................................... 5 i80/16-bit System Interface.................................................................................................... 5 i80/9-bit System Interface...................................................................................................... 5 i80/8-bit System Interface...................................................................................................... 5
Serial Peripheral Interface (SPI) ...................................................................................................... 5 VSYNC Interface.............................................................................................................................. 5 RGB Input Interface ......................................................................................................................... 5 7.5.1. 7.5.2. 7.5.3. 7.5.4. 7.5.5. 7.5.6. RGB Interface........................................................................................................................ 5 RGB Interface Timing ............................................................................................................ 5 Moving Picture Mode............................................................................................................. 5 6-bit RGB Interface................................................................................................................ 5 16-bit RGB Interface.............................................................................................................. 5 18-bit RGB Interface.............................................................................................................. 5 ILI9331 MDDI Specifications ................................................................................................. 5 MDDI Link Protocol (Packets Supported by the ILI9331)...................................................... 5 MDDI Instruction Setting........................................................................................................ 5
7.6.
MDDI (Mobile Display Digital Interface) ........................................................................................... 5 7.6.1. 7.6.2. 7.6.3.
7.7. 7.8. 8.1. 8.2.
Interface Timing................................................................................................................................ 5 CABC (Content Adaptive Brightness Control) ................................................................................. 5 Registers Access.............................................................................................................................. 5 Instruction Descriptions.................................................................................................................... 5 8.2.1. 8.2.2. 8.2.3. 8.2.4. 8.2.5. 8.2.6. Index (IR)............................................................................................................................... 5 ID code (R00h) ...................................................................................................................... 5 Driver Output Control (R01h) ................................................................................................ 5 LCD Driving Wave Control (R02h) ........................................................................................ 5 Entry Mode (R03h) ................................................................................................................ 5 Display Control 1 (R07h) ....................................................................................................... 5
8. Register Descriptions .................................................................................................................................... 5
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 2 of 133 Version: 0.09
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 8.2.7. 8.2.8. 8.2.9.
ILI9331
Display Control 2 (R08h) ....................................................................................................... 5 Display Control 3 (R09h) ....................................................................................................... 5 Display Control 4 (R0Ah)....................................................................................................... 5
8.2.10. RGB Display Interface Control 1 (R0Ch)............................................................................... 5 8.2.11. Frame Marker Position (R0Dh) ............................................................................................. 5 8.2.12. RGB Display Interface Control 2 (R0Fh) ............................................................................... 5 8.2.13. Power Control 1 (R10h)......................................................................................................... 5 8.2.14. Power Control 2 (R11h) ......................................................................................................... 5 8.2.15. Power Control 3 (R12h)......................................................................................................... 5 8.2.16. Power Control 4 (R13h)......................................................................................................... 5 8.2.17. GRAM Horizontal/Vertical Address Set (R20h, R21h) .......................................................... 5 8.2.18. Write Data to GRAM (R22h).................................................................................................. 5 8.2.19. Read Data from GRAM (R22h) ............................................................................................. 5 8.2.20. Power Control 7 (R29h)......................................................................................................... 5 8.2.21. Frame Rate and Color Control (R2Bh).................................................................................. 5 8.2.22. Gamma Control (R30h ~ R3Dh)............................................................................................ 5 8.2.23. Horizontal and Vertical RAM Address Position (R50h, R51h, R52h, R53h) ......................... 5 8.2.24. Gate Scan Control (R60h, R61h, R6Ah) ............................................................................... 5 8.2.25. Partial Image 1 Display Position (R80h)................................................................................ 5 8.2.26. Partial Image 1 RAM Start/End Address (R81h, R82h)......................................................... 5 8.2.27. Partial Image 2 Display Position (R83h)................................................................................ 5 8.2.28. Partial Image 2 RAM Start/End Address (R84h, R85h)......................................................... 5 8.2.29. Panel Interface Control 1 (R90h)........................................................................................... 5 8.2.30. Panel Interface Control 2 (R92h)........................................................................................... 5 8.2.31. Panel Interface Control 4 (R95h)........................................................................................... 5 8.2.32. Panel Interface Control 5 (R97h)........................................................................................... 5 8.2.33. OTP VCM Programming Control (RA1h) .............................................................................. 5 8.2.34. OTP VCM Status and Enable (RA2h) ................................................................................... 5 8.2.35. OTP Programming ID Key (RA5h) ........................................................................................ 5 8.2.36. Write Display Brightness Value (RB1h) ................................................................................. 5 8.2.37. Read Display Brightness Value (RB2h)................................................................................. 5 8.2.38. Write CTRL Display Value (RB3h)......................................................................................... 5 8.2.39. Read CTRL Display Value (RB4h) ........................................................................................ 5 8.2.40. Write Content Adaptive Brightness Control Value (RB5h) .................................................... 5 8.2.41. Read Content Adaptive Brightness Control Value (RB6h) .................................................... 5 8.2.42. Write CABC Minimum Brightness (RBEh)............................................................................. 5 8.2.43. Read CABC Minimum Brightness (RBFh)............................................................................. 5 8.2.44. CABC Control 1 (RC8h) ........................................................................................................ 5 8.2.45. CABC Control 2 (RC9h) ........................................................................................................ 5 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color
ILI9331
8.2.46. CABC Control 3 (RCAh) ........................................................................................................ 5 8.2.47. CABC Control 4 (RCBh) ........................................................................................................ 5 8.2.48. CABC Control 5 (RCCh)........................................................................................................ 5 8.2.49. CABC Control 6 (RCDh)........................................................................................................ 5 8.2.50. CABC Control 7 (RCEh) ........................................................................................................ 5 9. OTP Programming Flow................................................................................................................................ 5 10. GRAM Address Map & Read/Write ............................................................................................................... 5 11. Window Address Function............................................................................................................................. 5 12. Gamma Correction........................................................................................................................................ 5 13. Application..................................................................................................................................................... 5 13.1. Configuration of Power Supply Circuit ............................................................................................. 5 13.2. Display ON/OFF Sequence ............................................................................................................. 5 13.3. Standby and Sleep Mode ................................................................................................................. 5 13.4. Power Supply Configuration ............................................................................................................ 5 13.5. Voltage Generation .......................................................................................................................... 5 13.6. Applied Voltage to the TFT panel..................................................................................................... 5 13.7. Partial Display Function ................................................................................................................... 5 14. Electrical Characteristics............................................................................................................................... 5 14.1. Absolute Maximum Ratings ............................................................................................................. 5 14.2. DC Characteristics ........................................................................................................................... 5 14.3. Reset Timing Characteristics ........................................................................................................... 5 14.4. AC Characteristics ........................................................................................................................... 5 14.4.1. i80-System Interface Timing Characteristics ......................................................................... 5 14.4.2. Serial Data Transfer Interface Timing Characteristics........................................................... 5 14.4.3. RGB Interface Timing Characteristics ................................................................................... 5 15. Revision History ............................................................................................................................................ 5
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Figures
ILI9331
FIGURE1 SYSTEM INTERFACE AND RGB INTERFACE CONNECTION ...................................................................................... 5 FIGURE2 18-BIT SYSTEM INTERFACE DATA FORMAT ........................................................................................................... 5 FIGURE3 16-BIT SYSTEM INTERFACE DATA FORMAT ........................................................................................................... 5 FIGURE4 9-BIT SYSTEM INTERFACE DATA FORMAT ............................................................................................................. 5 FIGURE5 8-BIT SYSTEM INTERFACE DATA FORMAT ............................................................................................................. 5 FIGURE 6 DATA FORMAT OF SPI INTERFACE ....................................................................................................................... 5 FIGURE7 DATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI) ................................................................. 5 FIGURE8 DATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI), TRI=1 AND DFM=10)...................... 5 FIGURE9 DATA TRANSMISSION THROUGH VSYNC INTERFACE)........................................................................................... 5 FIGURE10 MOVING PICTURE DATA TRANSMISSION THROUGH VSYNC INTERFACE .............................................................. 5 FIGURE11 OPERATION THROUGH VSYNC INTERFACE......................................................................................................... 5 FIGURE12 TRANSITION FLOW BETWEEN VSYNC AND INTERNAL CLOCK OPERATION MODES .............................................. 5 FIGURE13 RGB INTERFACE DATA FORMAT ........................................................................................................................ 5 FIGURE14 GRAM ACCESS AREA BY RGB INTERFACE ....................................................................................................... 5 FIGURE15 TIMING CHART OF SIGNALS IN 18-/16-BIT RGB INTERFACE MODE .................................................................... 5 FIGURE16 TIMING CHART OF SIGNALS IN 6-BIT RGB INTERFACE MODE .............................................................................. 5 FIGURE17 EXAMPLE OF UPDATE THE STILL AND MOVING PICTURE ...................................................................................... 5 FIGURE18 INTERNAL CLOCK OPERATION/RGB INTERFACE MODE SWITCHING ..................................................................... 5 FIGURE19 GRAM ACCESS BETWEEN SYSTEM INTERFACE AND RGB INTERFACE ................................................................ 5 FIGURE20 MDDI ARCHITECTURE ........................................................................................................................................ 5 FIGURE21 RELATIONSHIP BETWEEN RGB I/F SIGNALS AND LCD DRIVING SIGNALS FOR PANEL ....................................... 5 FIGURE22 REGISTER SETTING WITH SERIAL PERIPHERAL INTERFACE (SPI)........................................................................ 5 FIGURE23 REGISTER SETTING WITH I80 SYSTEM INTERFACE .............................................................................................. 5 FIGURE 24 REGISTER READ/WRITE TIMING OF I80 SYSTEM INTERFACE ............................................................................. 5 FIGURE25 GRAM ACCESS DIRECTION SETTING ................................................................................................................. 5 FIGURE26 16-BIT MPU SYSTEM INTERFACE DATA FORMAT............................................................................................... 5 FIGURE27 8-BIT MPU SYSTEM INTERFACE DATA FORMAT................................................................................................. 5 FIGURE 28 DATA READ FROM GRAM THROUGH READ DATA REGISTER IN 18-/16-/9-/8-BIT INTERFACE MODE ................ 5 FIGURE 29 GRAM DATA READ BACK FLOW CHART .......................................................................................................... 5 FIGURE 30 GRAM ACCESS RANGE CONFIGURATION .......................................................................................................... 5 FIGURE31 GRAM READ/WRITE TIMING OF I80-SYSTEM INTERFACE ................................................................................. 5 FIGURE32 I80-SYSTEM INTERFACE WITH 18-/16-/9-BIT DATA BUS (SS=0, BGR=0) ................................................... 5 FIGURE33 I80-SYSTEM INTERFACE WITH 8-BIT DATA BUS (SS=0, BGR=0) ................................................................ 5 FIGURE 34 I80-SYSTEM INTERFACE WITH 18-/9-BIT DATA BUS (SS=1, BGR=1) ......................................................... 5 FIGURE 35 GRAM ACCESS WINDOW MAP ......................................................................................................................... 5 FIGURE 36 GRAYSCALE VOLTAGE GENERATION ................................................................................................................. 5 FIGURE 37 GRAYSCALE VOLTAGE ADJUSTMENT ................................................................................................................ 5 FIGURE 38 GAMMA CURVE ADJUSTMENT ........................................................................................................................... 5 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9331
FIGURE 39 EXAMPLE OF RMP(N)0~5 DEFINITION ............................................................................................................... 5 FIGURE 40 RELATIONSHIP BETWEEN SOURCE OUTPUT AND VCOM ................................................................................... 5 FIGURE 41 RELATIONSHIP BETWEEN GRAM DATA AND OUTPUT LEVEL............................................................................ 5 FIGURE 42 POWER SUPPLY CIRCUIT BLOCK ........................................................................................................................ 5 FIGURE 43 DISPLAY ON/OFF REGISTER SETTING SEQUENCE .............................................................................................. 5 FIGURE 44 STANDBY/SLEEP MODE REGISTER SETTING SEQUENCE ............................................................................... 5 FIGURE 45 POWER SUPPLY ON/OFF SEQUENCE ................................................................................................................. 5 FIGURE 46 VOLTAGE CONFIGURATION DIAGRAM ............................................................................................................... 5 FIGURE 47 VOLTAGE OUTPUT TO TFT LCD PANEL ............................................................................................................ 5 FIGURE 48 PARTIAL DISPLAY EXAMPLE .............................................................................................................................. 5 FIGURE 49 I80-SYSTEM BUS TIMING ................................................................................................................................... 5 FIGURE 50 SPI SYSTEM BUS TIMING ................................................................................................................................... 5 FIGURE51 RGB INTERFACE TIMING .................................................................................................................................... 5
ILI9331
1. Introduction
ILI9331 is a 262,144-color one-chip SoC driver for a-TFT liquid crystal display with resolution of 240RGBx320 dots, comprising a 720-channel source driver, a 320-channel gate driver, 172,800 bytes RAM for graphic data of 240RGBx320 dots, and power supply circuit. ILI9331 has five kinds of system interfaces which are i80-system MPU interface (8-/9-/16-/18-bit bus width), VSYNC interface (system interface + VSYNC, internal clock, DB[17:0]), serial data transfer interface (SPI), RGB 6-/16-/18-bit interface (DOTCLK, VSYNC, HSYNC, ENABLE, DB[17:0]) and MDDI. In RGB interface and VSYNC interface mode, the combined use of high-speed RAM write function and widow address function enables to display a moving picture at a position specified by a user and still pictures in other areas on the screen simultaneously, which makes it possible to transfer display the refresh data only to minimize data transfers and power consumption. ILI9331 can operate with 1.65V I/O interface voltage, and an incorporated voltage follower circuit to generate voltage levels for driving an LCD. The ILI9331 also supports a function to display in 8 colors and a sleep mode, allowing for precise power control by software and these features make the ILI9331 an ideal LCD driver for medium or small size portable products such as digital cellular phones, smart phone, PDA and PMP where long battery life is a major concern.
ILI9331
2. Features
Single chip solution for a liquid crystal QVGA TFT LCD display 240RGBx320-dot resolution capable with real 262,144 display color Support MVA (Multi-domain Vertical Alignment) wide view display Incorporate 720-channel source driver and 320-channel gate driver Internal 172,800 bytes graphic RAM CABC (Content Adaptive Brightness Control) System interfaces i80 system interface with 8-/ 9-/16-/18-bit bus width Serial Peripheral Interface (SPI) RGB interface with 6-/16-/18-bit bus width (VSYNC, HSYNC, DOTCLK, ENABLE, DB[17:0]) VSYNC interface (System interface + VSYNC) MDDI (Mobile Display Digital Interface) Internal oscillator and hardware reset Reversible source/gate driver shift direction Window address function to specify a rectangular area for internal GRAM access Bit operation function for facilitating graphics data processing Bit-unit write data mask function Pixel-unit logical/conditional write function Abundant functions for color display control -correction function enabling display in 262,144 colors Line-unit vertical scrolling function Partial drive function, enabling partially driving an LCD panel at positions specified by user Incorporate step-up circuits for stepping up a liquid crystal drive voltage level up to 6 times (x6) Power saving functions 8-color mode standby mode sleep mode Low -power consumption architecture Low operating power supplies: IOVcc = 1.65V ~ 3.3 V (interface I/O) VCI = 2.5V ~ 3.3 V (analog) LCD Voltage drive: Source/VCOM power supply voltage DDVDH - GND = 4.5V ~ 6.0 VCL GND = -2.0V ~ -3.0V VCI VCL 6.0V Gate driver output voltage VGH - GND = 10V ~ 20V The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color VGL GND = -5V ~ -15V VGH VGL 30V VCOM driver output voltage VCOMH = (VCI+0.2)V ~ (DDVDH-0.2)V VCOML = (VCL+0.2)V ~ 0V VCOMH-VCOML 6.0V a-TFT LCD storage capacitor: Cst only
ILI9331
ILI9331
3. Block Diagram
IOVCC IM[3:0] nRESET nCS nWR/SCL nRD RS SDI SDO DB[17:0] HSYNC VSYNC DOTCLK ENABLE TEST1 TEST2 TEST3 TS[8:0] MDDI_DATA_N MDDI_DATA_P MDDI_STB_N MDDI_STB_P VCC VDDD GND LEDPWM
Index Register (IR) MPU I/F 18-bit 16-bit 9-bit 8-bit SPI I/F RGB I/F 18-bit 16-bit 6-bit VSYNC I/F MDDI
18 7
18
Control Register (CR)
Address Counter (AC)
LCD Source Driver
S[720:1]
Graphics Operation
18
V63 ~ 0 18
Read Latch
18
Write Latch
18
VREG1OUT
Grayscale Reference Voltage
VGS
Graphics RAM (GRAM) CABC Block Brightness control LCD Gate Driver
DUMMY20~27
Regulator
RC-OSC.
DUMMY1~15 VCI VCI1
Timing Controller
G[320:1]
Charge-pump Power Circuit

GND
VCOM Generator
VCOM
C21B
C21A
C22A
C22B
VCL
VCOMH
VCOML
C11A
C11B
DDVDH
C12B
C12A
C13A
C13B
VGH VGL
ILI9331
4. Pin Descriptions
Pin Name I/O Type Input Interface Select the MPU system interface mode IM3 0 0 0 0 IM3, IM2, IM1, IM0/ID I IOVcc 0 0 1 1 1 1 1 setting. A chip select signal. nCS I MPU IOVcc Low: the ILI9331 is selected and accessible High: the ILI9331 is not selected and not accessible Fix to the GND level when not in use. A register select signal. RS I MPU IOVcc Low: select an index or status register High: select a control register Fix to either IOVcc or GND level when not in use. A write strobe signal and enables an operation to write data when the signal is low. nWR/SCL I MPU IOVcc Fix to either IOVcc or GND level when not in use. SPI Mode: Synchronizing clock signal in SPI mode. nRD I MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc Let SDO as floating when not used. An 18-bit parallel bi-directional data bus for MPU system interface mode 8-bit I/F: DB[17:10] is used. 9-bit I/F: DB[17:9] is used. 16-bit I/F: DB[17:10] and DB[8:1] is used. DB[17:0] I/O MPU IOVcc 18-bit I/F: DB[17:0] is used. 18-bit parallel bi-directional data bus for RGB interface operation 6-bit RGB I/F: DB[17:12] are used. 16-bit RGB I/F: DB[17:13] and DB[11:1] are used. 18-bit RGB I/F: DB[17:0] are used. Unused pins must be fixed to GND level. A read strobe signal and enables an operation to read out data when the signal is low. Fix to either IOVcc or GND level when not in use. A reset pin. Initializes the ILI9331 with a low input. Be sure to execute a power-on reset after supplying power. SPI interface input pin. The data is latched on the rising edge of the SCL signal. SPI interface output pin. SDO O The data is outputted on the falling edge of the SCL signal. IM2 0 0 0 0 1 1 0 0 0 0 1 IM1 0 0 1 1 0 1 0 0 1 1 * IM0 0 1 0 1 ID * 0 1 0 1 * MPU-Interface Mode Setting invalid Setting invalid i80-system 16-bit interface i80-system 8-bit interface Serial Peripheral Interface (SPI) Setting invalid MDDI Setting invalid i80-system 18-bit interface i80-system 9-bit interface Setting invalid DB[17:0] DB[17:9] DB[17:10], DB[8:1] DB[17:10] SDI, SDO DB Pin in use Descriptions
When the serial peripheral interface is selected, IM0 pin is used for the device code ID
nRESET
SDI
Pin Name I/O Type Low: Select (access enabled) ENABLE I MPU IOVcc High: Not select (access inhibited) The EPL bit inverts the polarity of the ENABLE signal. Fix to either IOVcc or GND level when not in use. Dot clock signal for RGB interface operation. DOTCLK I MPU IOVcc DPL = 0: Input data on the rising edge of DOTCLK DPL = 1: Input data on the falling edge of DOTCLK Fix to the GND level when not in use Frame synchronizing signal for RGB interface operation. VSYNC I MPU IOVcc VSPL = 0: Active low. VSPL = 1: Active high. Fix to the GND level when not in use. Line synchronizing signal for RGB interface operation. HSYNC I MPU IOVcc HSPL = 0: Active low. HSPL = 1: Active high. Fix to the GND level when not in use FMARK O MPU IOVcc Output a frame head pulse signal. Descriptions Data ENEABLE signal for RGB interface operation.
ILI9331
The FMARK signal is used when writing RAM data in synchronization with frame. Leave the pin open when not in use. MDDI data signal lines. Data+ (MDDI_DATA_P) and data- (MDDI_DATA_M) are differential small swing
MDDI_DATA_P MDDI_DATA_M
I/O
MDDI
signals. Make the wiring as short as possible so that the COG resistance becomes less 60 ohm. The specifications of interface must be compliant with the MDDI specification. NOTE: these pins are used the same pin in CPU mode. MDDI strobe signal lines. Stb+ (MDDI_STB_P) and Stb- (MDDI_STB_M) are differential small swing
MDDI_STB_P MDDI_STB_M
MDDI
signals. Make the wiring as short as possible so that the COG resistance becomes less 100ohm. The specifications of interface must be compliant with the MDDI specification. NOTE: these pins are used the same pin in CPU mode. When MDDI interface is selected, connect this pin to GND or leave it open. NOTE: these pins are used the same pin in CPU mode. LCD Driving signals Source output voltage signals applied to liquid crystal. To change the shift direction of signal outputs, use the SS bit. SS = 0, the data in the RAM address h00000 is output from S1. SS = 1, the data in the RAM address h00000 is output from S720. S1, S4, S7, display red (R), S2, S5, S8, ... display green (G), and S3, S6, S9, ... display blue (B) (SS = 0). Gate line output signals.
MDDI_GNDDUM
GND
S720~S1
LCD
G320~G1
LCD TFT common electrode Stabilizing capacitor Stabilizing capacitor GND or external resistor IOVcc
VGH: the level selecting gate lines VGL: the level not selecting gate lines A supply voltage to the common electrode of TFT panel. VCOM is AC voltage alternating signal between the VCOMH and VCOML levels. The high level of VCOM AC voltage. Connect to a stabilizing capacitor. Adjust the VCOML level with the VDV bits.
VCOM VCOMH VCOML
O O O
The low level of VCOM AC voltage. Connect to a stabilizing capacitor.
VGS LEDPWM
I O
Reference level for the grayscale voltage generating circuit. The VGS level can be changed by connecting to an external resistor. PWM signal output to control LED driver for LED brightness dimming. Charge-pump and Regulator Circuit
Pin Name VCI VCC I/O I I Type Power supply Power supply Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor Step-up capacitor Step-up capacitor 3.3V. A supply voltage to the digital circuit. 3.3V. An internal reference voltage for the step-up circuit1. VCI1 O Descriptions A supply voltage to the analog circuit.
ILI9331
Connect to an external power supply of 2.5 ~ Connect to an external power supply of 2.5 ~
The amplitude between VCI and GND is determined by the VC[2:0] bits. Make sure to set the VCI1 voltage so that the DDVDH, VGH and VGL voltages are set within the respective specification.
DDVDH VGH VGL
O O O
Power supply for the source driver and Vcom drive. Power supply for the gate driver. Power supply for the gate driver. VCOML driver power supply. VCL = 0.5 ~ VCI . Place a stabilizing capacitor between GND Capacitor connection pins for the step-up circuit 1.
VCL C11A, C11B C12A, C12B C13A, C13B C21A, C21B C22A, C22B
I/O
I/O
Capacitor connection pins for the step-up circuit 2. Output voltage generated from the reference voltage.
VREG1OUT
I/O
Stabilizing capacitor
The voltage level is set with the VRH bits. VREG1OUT is (1) a source driver grayscale reference voltage, (2) VcomH level reference voltage, and (3) Vcom amplitude reference voltage. Connect to a stabilizing capacitor. VREG1OUT = 3.0 ~ (DDVDH 0.5)V. Power Pads A supply voltage to the interface pins: IM[3:0], nRESET, nCS, nWR, nRD, RS, DB[17:0], VSYNC, HSYNC, DOTCLK, ENABLE, SCL, SDI, SDO. IOVcc = 1.65 ~ 3.3V. In case of COG, connect to Vcc on the FPC if IOVcc=Vcc, to prevent noise. A supply voltage to the MDDI interface pins: MDDI_STB_M, MDDI_STB_P, MDDI_DATA_P and MDDI_DATA_M IOVcc = 2.5 ~ 3.3V. In case of COG, connect to Vcc on the FPC if IOVcc=Vcc, to prevent noise. Digital circuit power pad. Connect these pins with the 1uF capacitor. DGND for the digital side: DGND = 0V. to prevent noise. AGND for the analog side: AGND = 0V. to prevent noise. Test pad. Leave these pins as open Connect unused gate lines to fix the level at VGL Test Pads In case of COG, connect to GND on the FPC In case of COG, connect to GND on the FPC
IOVCC
Power supply
VDD DGND AGND VGMMA1, 62 VGLDMY1~4
O I I O O
Power Power supply Power supply Unused gate lines
DUMMY3, 31.
5~27,30,
Dummy pad. Leave these pins as open Short circuited within the chip for COG contact resistance measurement. DUMMYR pins are short circuited as below: DUMMYR1 and DUMMYR29 DUMMYR2 and DUMMYR28 Connect unused interface and test pins to these pins on the glass to fix voltage
DUMMYR1,2, 28, 29.
IOVCCDUM
Pin Name AGNDDUM1~6 DGNDDUM1~7 TESTO1~16 TEST1, 2, 3 TS0~8 TSO TEST_EN I/O O O O I I O I Type Open IOGND OPEN OPEN OPEN Test pins. Leave them open. Test pins (internal pull low). Connect to GND or leave these pins as open. Test pins (internal pull low). Leave them open. Test pins. Leave it open or short to ground. Test pins. Leave it open or short to ground. Descriptions levels. Leave open when not used.
ILI9331
Liquid crystal power supply specifications Table 1

No. 1 2 3 4 TFT Source Driver TFT Gate Driver TFT Displays Capacitor Structure S1 ~ S720 Liquid Crystal Drive Output G1 ~ G320 VCOM 5 Input Voltage IOVcc VCI DDVDH VGH 6 Liquid Crystal Drive Voltages VGL VCL VGH - VGL VCI - VCL DDVDH 7 Internal Step-up Circuits VGH VGL VCL Item 720 pins (240 x RGB) 320 pins Cst structure only (Common VCOM) V0 ~ V63 grayscales VGH - VGL VCOMH - VCOML: Amplitude = electronic volumes 1.65 ~ 3.30V 2.50 ~ 3.30V 4.5V ~ 6.0V 10V ~ 20V -5V ~ -15V -1.9V ~ -3.0V Max. 30V Max. 6.0V VCI1 x2 VCI1 x4, x5, x6 VCI1 x-3, x-4, x-5 VCI1 x-1 Description
ILI9331
5. Pad Arrangement and Coordination
ILI9331
NO. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Pad Name VGS AGND AGND AGND AGND AGND AGND AGND AGND VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOM VCOM VCOM VCOM VCOM VCOM VCOML VCOML VCOML VCOML VCOML VCOML VCOML C11A C11A C11A C11A C11A C11B C11B C11B C11B C11B C12B C12B C12B C12B C12B C12A C12A C12A C12A C12A DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DUMMY10 VREG1OUT X -665 -595 -525 -455 -385 -315 -245 -175 -105 -35 35 105 175 245 315 385 455 525 595 665 735 805 875 945 1015 1085 1155 1225 1295 1365 1435 1505 1575 1645 1715 1785 1855 1925 1995 2065 2135 2205 2275 2345 2415 2485 2555 2625 2695 2765 2835 2905 2975 3045 3115 3185 3255 3325 3395 3465 Y -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Pad Name DGNDDUM1 DUMMYR1 DUMMYR2 TESTO[1] TESTO[2] TESTO[3] TESTO[4] TESTO[5] TESTO[6] TESTO[7] TESTO[8] LEDPWM LEDPWM TESTO[9] TESTO[10] TESTO[11] TESTO[12] DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND TESTO[13] TESTO[14] DGNDDUM2 IM0/ID IM1 IM2 IM3 IOVCCDUM TESTO[15] TESTO[16] TEST3 TEST2 TEST1 DGNDDUM3 FMARK VSYNC HSYNC DOTCLK ENABLE TEST_EN DB[17] DB[16] DB[15] TS[8] TS[7] DB[14] DB[13] DB[12] TS[6] TS[5] DB[11] DB[10] DB[9]
X -9065 -8995 -8925 -8855 -8785 -8715 -8645 -8575 -8505 -8435 -8365 -8295 -8225 -8155 -8085 -8015 -7945 -7875 -7805 -7735 -7665 -7595 -7525 -7455 -7385 -7315 -7245 -7175 -7105 -7035 -6965 -6895 -6825 -6755 -6685 -6615 -6545 -6475 -6405 -6335 -6265 -6195 -6125 -6055 -5985 -5915 -5845 -5775 -5705 -5635 -5565 -5495 -5425 -5355 -5285 -5215 -5145 -5075 -5005 -4935
Y -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281
NO. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Pad Name IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC DB[8] / MDDI_GNDDUM DB[7] / MDDI_DATA_P DB[6] / MDDI_GNDDUM TS[4] TS[3] DB[5] / MDDI_GNDDUM DB[4] / MDDI_DATA_M DB[3] / MDDI_GNDDUM TS[2] TS[1] DB[2] / MDDI_GNDDUM DB[1] / MDDI_STB_P DB[0] / MDDI_GNDDUM TS[0] TSO DGNDDUM5 nCS / MDDI_GNDDUM RS / MDDI_STB_M nWR/SCL / MDDI_GNDDUM nRD nRESET SDO SDI DGNDDUM6 DUMMY5 DUMMY6 DUMMY7 DUMMY8 DUMMY9 DGNDDUM7 VCC VCC VCC VCC VCC VCC VDD VDD VDD VDD VDD VDD VDD VDD DGND DGND DGND DGND DGND DGND DGND DGND
X -4865 -4795 -4725 -4655 -4585 -4515 -4445 -4375 -4305 -4235 -4165 -4095 -4025 -3955 -3885 -3815 -3745 -3675 -3605 -3535 -3465 -3395 -3325 -3255 -3185 -3115 -3045 -2975 -2905 -2835 -2765 -2695 -2625 -2555 -2485 -2415 -2345 -2275 -2205 -2135 -2065 -1995 -1925 -1855 -1785 -1715 -1645 -1575 -1505 -1435 -1365 -1295 -1225 -1155 -1085 -1015 -945 -875 -805 -735
Y -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281
NO. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Pad Name DUMMY11 DUMMY12 AGNDDUM1 AGNDDUM2 VCI1 VCI1 VCI1 VCI1 VCI1 VCI1 VCI1 VCI1 VCI VCI VCI VCI VCI VCI VCI VCI VCI AGNDDUM3 VGH VGH VGH VGH VGH VGH AGNDDUM4 VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL AGNDDUM5 VCL VCL VCL VCL C13B C13B C13B C13B C13A C13A C13A C13A AGND AGND AGND AGND AGND AGND AGND AGND X 3535 3605 3675 3745 3815 3885 3955 4025 4095 4165 4235 4305 4375 4445 4515 4585 4655 4725 4795 4865 4935 5005 5075 5145 5215 5285 5355 5425 5495 5565 5635 5705 5775 5845 5915 5985 6055 6125 6195 6265 6335 6405 6475 6545 6615 6685 6755 6825 6895 6965 7035 7105 7175 7245 7315 7385 7455 7525 7595 7665 Y -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 NO. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 Pad Name AGND AGND C21B C21B C21B C21A C21A C21A C22B C22B C22B C22A C22A C22A DUMMY13 DUMMY14 DUMMY15 DUMMY16 DUMMY17 AGNDDUM6 DUMMY18 DUMMY19 DUMMY20 DUMMY21 VGLDMY1 G[1] G[3] G[5] G[7] G[9] G[11] G[13] G[15] G[17] G[19] G[21] G[23] G[25] G[27] G[29] G[31] G[33] G[35] G[37] G[39] G[41] G[43] G[45] G[47] G[49] G[51] G[53] G[55] G[57] G[59] G[61] G[63] G[65] G[67] G[69] X 7735 7805 7875 7945 8015 8085 8155 8225 8295 8365 8435 8505 8575 8645 8715 8785 8855 8925 8995 9065 9216 9200 9184 9168 9152 9136 9120 9104 9088 9072 9056 9040 9024 9008 8992 8976 8960 8944 8928 8912 8896 8880 8864 8848 8832 8816 8800 8784 8768 8752 8736 8720 8704 8688 8672 8656 8640 8624 8608 8592 Y -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 -281 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 NO. 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 Pad Name G[71] G[73] G[75] G[77] G[79] G[81] G[83] G[85] G[87] G[89] G[91] G[93] G[95] G[97] G[99] G[101] G[103] G[105] G[107] G[109] G[111] G[113] G[115] G[117] G[119] G[121] G[123] G[125] G[127] G[129] G[131] G[133] G[135] G[137] G[139] G[141] G[143] G[145] G[147] G[149] G[151] G[153] G[155] G[157] G[159] G[161] G[163] G[165] G[167] G[169] G[171] G[173] G[175] G[177] G[179] G[181] G[183] G[185] G[187] G[189]
ILI9331
X 8576 8560 8544 8528 8512 8496 8480 8464 8448 8432 8416 8400 8384 8368 8352 8336 8320 8304 8288 8272 8256 8240 8224 8208 8192 8176 8160 8144 8128 8112 8096 8080 8064 8048 8032 8016 8000 7984 7968 7952 7936 7920 7904 7888 7872 7856 7840 7824 7808 7792 7776 7760 7744 7728 7712 7696 7680 7664 7648 7632 Y 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166
ILI9331
Pad Name S[669] S[668] S[667] S[666] S[665] S[664] S[663] S[662] S[661] S[660] S[659] S[658] S[657] S[656] S[655] S[654] S[653] S[652] S[651] S[650] S[649] S[648] S[647] S[646] S[645] S[644] S[643] S[642] S[641] S[640] S[639] S[638] S[637] S[636] S[635] S[634] S[633] S[632] S[631] S[630] S[629] S[628] S[627] S[626] S[625] S[624] S[623] S[622] S[621] S[620] S[619] S[618] S[617] S[616] S[615] S[614] S[613] S[612] S[611] S[610] X 5520 5504 5488 5472 5456 5440 5424 5408 5392 5376 5360 5344 5328 5312 5296 5280 5264 5248 5232 5216 5200 5184 5168 5152 5136 5120 5104 5088 5072 5056 5040 5024 5008 4992 4976 4960 4944 4928 4912 4896 4880 4864 4848 4832 4816 4800 4784 4768 4752 4736 4720 4704 4688 4672 4656 4640 4624 4608 4592 4576 Y 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279
NO. 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420
Pad Name G[191] G[193] G[195] G[197] G[199] G[201] G[203] G[205] G[207] G[209] G[211] G[213] G[215] G[217] G[219] G[221] G[223] G[225] G[227] G[229] G[231] G[233] G[235] G[237] G[239] G[241] G[243] G[245] G[247] G[249] G[251] G[253] G[255] G[257] G[259] G[261] G[263] G[265] G[267] G[269] G[271] G[273] G[275] G[277] G[279] G[281] G[283] G[285] G[287] G[289] G[291] G[293] G[295] G[297] G[299] G[301] G[303] G[305] G[307] G[309]
X 7616 7600 7584 7568 7552 7536 7520 7504 7488 7472 7456 7440 7424 7408 7392 7376 7360 7344 7328 7312 7296 7280 7264 7248 7232 7216 7200 7184 7168 7152 7136 7120 7104 7088 7072 7056 7040 7024 7008 6992 6976 6960 6944 6928 6912 6896 6880 6864 6848 6832 6816 6800 6784 6768 6752 6736 6720 6704 6688 6672
Y 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166
NO. 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480
Pad Name G[311] G[313] G[315] G[317] G[319] VGLDMY2 DUMMY22 DUMMY23 DUMMY24 S[720] S[719] S[718] S[717] S[716] S[715] S[714] S[713] S[712] S[711] S[710] S[709] S[708] S[707] S[706] S[705] S[704] S[703] S[702] S[701] S[700] S[699] S[698] S[697] S[696] S[695] S[694] S[693] S[692] S[691] S[690] S[689] S[688] S[687] S[686] S[685] S[684] S[683] S[682] S[681] S[680] S[679] S[678] S[677] S[676] S[675] S[674] S[673] S[672] S[671] S[670]
X 6656 6640 6624 6608 6592 6576 6560 6368 6352 6336 6320 6304 6288 6272 6256 6240 6224 6208 6192 6176 6160 6144 6128 6112 6096 6080 6064 6048 6032 6016 6000 5984 5968 5952 5936 5920 5904 5888 5872 5856 5840 5824 5808 5792 5776 5760 5744 5728 5712 5696 5680 5664 5648 5632 5616 5600 5584 5568 5552 5536
Y 279 166 279 166 279 166 279 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279
NO. 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540
ILI9331
Pad Name S[489] S[488] S[487] S[486] S[485] S[484] S[483] S[482] S[481] S[480] S[479] S[478] S[477] S[476] S[475] S[474] S[473] S[472] S[471] S[470] S[469] S[468] S[467] S[466] S[465] S[464] S[463] S[462] S[461] S[460] S[459] S[458] S[457] S[456] S[455] S[454] S[453] S[452] S[451] S[450] S[449] S[448] S[447] S[446] S[445] S[444] S[443] S[442] S[441] S[440] S[439] S[438] S[437] S[436] S[435] S[434] S[433] S[432] S[431] S[430] X 2640 2624 2608 2592 2576 2560 2544 2528 2512 2496 2480 2464 2448 2432 2416 2400 2384 2368 2352 2336 2320 2304 2288 2272 2256 2240 2224 2208 2192 2176 2160 2144 2128 2112 2096 2080 2064 2048 2032 2016 2000 1984 1968 1952 1936 1920 1904 1888 1872 1856 1840 1824 1808 1792 1776 1760 1744 1728 1712 1696 Y 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279
NO. 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600
Pad Name S[609] S[608] S[607] S[606] S[605] S[604] S[603] S[602] S[601] S[600] S[599] S[598] S[597] S[596] S[595] S[594] S[593] S[592] S[591] S[590] S[589] S[588] S[587] S[586] S[585] S[584] S[583] S[582] S[581] S[580] S[579] S[578] S[577] S[576] S[575] S[574] S[573] S[572] S[571] S[570] S[569] S[568] S[567] S[566] S[565] S[564] S[563] S[562] S[561] S[560] S[559] S[558] S[557] S[556] S[555] S[554] S[553] S[552] S[551] S[550]
X 4560 4544 4528 4512 4496 4480 4464 4448 4432 4416 4400 4384 4368 4352 4336 4320 4304 4288 4272 4256 4240 4224 4208 4192 4176 4160 4144 4128 4112 4096 4080 4064 4048 4032 4016 4000 3984 3968 3952 3936 3920 3904 3888 3872 3856 3840 3824 3808 3792 3776 3760 3744 3728 3712 3696 3680 3664 3648 3632 3616
Y 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279
NO. 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660
X 3600 3584 3568 3552 3536 3520 3504 3488 3472 3456 3440 3424 3408 3392 3376 3360 3344 3328 3312 3296 3280 3264 3248 3232 3216 3200 3184 3168 3152 3136 3120 3104 3088 3072 3056 3040 3024 3008 2992 2976 2960 2944 2928 2912 2896 2880 2864 2848 2832 2816 2800 2784 2768 2752 2736 2720 2704 2688 2672 2656
Y 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279
NO. 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720
NO. 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 Pad Name S[429] S[428] S[427] S[426] S[425] S[424] S[423] S[422] S[421] S[420] S[419] S[418] S[417] S[416] S[415] S[414] S[413] S[412] S[411] S[410] S[409] S[408] S[407] S[406] S[405] S[404] S[403] S[402] S[401] S[400] S[399] S[398] S[397] S[396] S[395] S[394] S[393] S[392] S[391] S[390] S[389] S[388] S[387] S[386] S[385] S[384] S[383] S[382] S[381] S[380] S[379] S[378] S[377] S[376] S[375] S[374] S[373] S[372] S[371] S[370] X 1680 1664 1648 1632 1616 1600 1584 1568 1552 1536 1520 1504 1488 1472 1456 1440 1424 1408 1392 1376 1360 1344 1328 1312 1296 1280 1264 1248 1232 1216 1200 1184 1168 1152 1136 1120 1104 1088 1072 1056 1040 1024 1008 992 976 960 944 928 912 896 880 864 848 832 816 800 784 768 752 736 Y 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 NO. 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 Pad Name S[369] S[368] S[367] S[366] S[365] S[364] S[363] S[362] S[361] VGMMA62 VGMMA1 S[360] S[359] S[358] S[357] S[356] S[355] S[354] S[353] S[352] S[351] S[350] S[349] S[348] S[347] S[346] S[345] S[344] S[343] S[342] S[341] S[340] S[339] S[338] S[337] S[336] S[335] S[334] S[333] S[332] S[331] S[330] S[329] S[328] S[327] S[326] S[325] S[324] S[323] S[322] S[321] S[320] S[319] S[318] S[317] S[316] S[315] S[314] S[313] S[312] X 720 704 688 672 656 640 624 608 592 576 -576 -592 -608 -624 -640 -656 -672 -688 -704 -720 -736 -752 -768 -784 -800 -816 -832 -848 -864 -880 -896 -912 -928 -944 -960 -976 -992 -1008 -1024 -1040 -1056 -1072 -1088 -1104 -1120 -1136 -1152 -1168 -1184 -1200 -1216 -1232 -1248 -1264 -1280 -1296 -1312 -1328 -1344 -1360 Y 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 NO. 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 Pad Name S[311] S[310] S[309] S[308] S[307] S[306] S[305] S[304] S[303] S[302] S[301] S[300] S[299] S[298] S[297] S[296] S[295] S[294] S[293] S[292] S[291] S[290] S[289] S[288] S[287] S[286] S[285] S[284] S[283] S[282] S[281] S[280] S[279] S[278] S[277] S[276] S[275] S[274] S[273] S[272] S[271] S[270] S[269] S[268] S[267] S[266] S[265] S[264] S[263] S[262] S[261] S[260] S[259] S[258] S[257] S[256] S[255] S[254] S[253] S[252]
ILI9331
X -1376 -1392 -1408 -1424 -1440 -1456 -1472 -1488 -1504 -1520 -1536 -1552 -1568 -1584 -1600 -1616 -1632 -1648 -1664 -1680 -1696 -1712 -1728 -1744 -1760 -1776 -1792 -1808 -1824 -1840 -1856 -1872 -1888 -1904 -1920 -1936 -1952 -1968 -1984 -2000 -2016 -2032 -2048 -2064 -2080 -2096 -2112 -2128 -2144 -2160 -2176 -2192 -2208 -2224 -2240 -2256 -2272 -2288 -2304 -2320 Y 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279
NO. 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 Pad Name S[251] S[250] S[249] S[248] S[247] S[246] S[245] S[244] S[243] S[242] S[241] S[240] S[239] S[238] S[237] S[236] S[235] S[234] S[233] S[232] S[231] S[230] S[229] S[228] S[227] S[226] S[225] S[224] S[223] S[222] S[221] S[220] S[219] S[218] S[217] S[216] S[215] S[214] S[213] S[212] S[211] S[210] S[209] S[208] S[207] S[206] S[205] S[204] S[203] S[202] S[201] S[200] S[199] S[198] S[197] S[196] S[195] S[194] S[193] S[192] X -2336 -2352 -2368 -2384 -2400 -2416 -2432 -2448 -2464 -2480 -2496 -2512 -2528 -2544 -2560 -2576 -2592 -2608 -2624 -2640 -2656 -2672 -2688 -2704 -2720 -2736 -2752 -2768 -2784 -2800 -2816 -2832 -2848 -2864 -2880 -2896 -2912 -2928 -2944 -2960 -2976 -2992 -3008 -3024 -3040 -3056 -3072 -3088 -3104 -3120 -3136 -3152 -3168 -3184 -3200 -3216 -3232 -3248 -3264 -3280 Y 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 NO. 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 Pad Name S[191] S[190] S[189] S[188] S[187] S[186] S[185] S[184] S[183] S[182] S[181] S[180] S[179] S[178] S[177] S[176] S[175] S[174] S[173] S[172] S[171] S[170] S[169] S[168] S[167] S[166] S[165] S[164] S[163] S[162] S[161] S[160] S[159] S[158] S[157] S[156] S[155] S[154] S[153] S[152] S[151] S[150] S[149] S[148] S[147] S[146] S[145] S[144] S[143] S[142] S[141] S[140] S[139] S[138] S[137] S[136] S[135] S[134] S[133] S[132] X -3296 -3312 -3328 -3344 -3360 -3376 -3392 -3408 -3424 -3440 -3456 -3472 -3488 -3504 -3520 -3536 -3552 -3568 -3584 -3600 -3616 -3632 -3648 -3664 -3680 -3696 -3712 -3728 -3744 -3760 -3776 -3792 -3808 -3824 -3840 -3856 -3872 -3888 -3904 -3920 -3936 -3952 -3968 -3984 -4000 -4016 -4032 -4048 -4064 -4080 -4096 -4112 -4128 -4144 -4160 -4176 -4192 -4208 -4224 -4240 Y 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 NO. 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 Pad Name S[131] S[130] S[129] S[128] S[127] S[126] S[125] S[124] S[123] S[122] S[121] S[120] S[119] S[118] S[117] S[116] S[115] S[114] S[113] S[112] S[111] S[110] S[109] S[108] S[107] S[106] S[105] S[104] S[103] S[102] S[101] S[100] S[99] S[98] S[97] S[96] S[95] S[94] S[93] S[92] S[91] S[90] S[89] S[88] S[87] S[86] S[85] S[84] S[83] S[82] S[81] S[80] S[79] S[78] S[77] S[76] S[75] S[74] S[73] S[72]
ILI9331
X -4256 -4272 -4288 -4304 -4320 -4336 -4352 -4368 -4384 -4400 -4416 -4432 -4448 -4464 -4480 -4496 -4512 -4528 -4544 -4560 -4576 -4592 -4608 -4624 -4640 -4656 -4672 -4688 -4704 -4720 -4736 -4752 -4768 -4784 -4800 -4816 -4832 -4848 -4864 -4880 -4896 -4912 -4928 -4944 -4960 -4976 -4992 -5008 -5024 -5040 -5056 -5072 -5088 -5104 -5120 -5136 -5152 -5168 -5184 -5200 Y 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279
ILI9331
Pad Name G[230] G[228] G[226] G[224] G[222] G[220] G[218] G[216] G[214] G[212] G[210] G[208] G[206] G[204] G[202] G[200] G[198] G[196] G[194] G[192] G[190] G[188] G[186] G[184] G[182] G[180] G[178] G[176] G[174] G[172] G[170] G[168] G[166] G[164] G[162] G[160] G[158] G[156] G[154] G[152] G[150] G[148] G[146] G[144] G[142] G[140] G[138] G[136] G[134] G[132] G[130] G[128] G[126] G[124] G[122] G[120] G[118] G[116] G[114] G[112] X -7312 -7328 -7344 -7360 -7376 -7392 -7408 -7424 -7440 -7456 -7472 -7488 -7504 -7520 -7536 -7552 -7568 -7584 -7600 -7616 -7632 -7648 -7664 -7680 -7696 -7712 -7728 -7744 -7760 -7776 -7792 -7808 -7824 -7840 -7856 -7872 -7888 -7904 -7920 -7936 -7952 -7968 -7984 -8000 -8016 -8032 -8048 -8064 -8080 -8096 -8112 -8128 -8144 -8160 -8176 -8192 -8208 -8224 -8240 -8256 Y 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279
NO. 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140
X -5216 -5232 -5248 -5264 -5280 -5296 -5312 -5328 -5344 -5360 -5376 -5392 -5408 -5424 -5440 -5456 -5472 -5488 -5504 -5520 -5536 -5552 -5568 -5584 -5600 -5616 -5632 -5648 -5664 -5680 -5696 -5712 -5728 -5744 -5760 -5776 -5792 -5808 -5824 -5840 -5856 -5872 -5888 -5904 -5920 -5936 -5952 -5968 -5984 -6000 -6016 -6032 -6048 -6064 -6080 -6096 -6112 -6128 -6144 -6160
Y 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279
NO. 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200
Pad Name S[11] S[10] S[9] S[8] S[7] S[6] S[5] S[4] S[3] S[2] S[1] DUMMY25 DUMMY26 DUMMY27 VGLDMY3 G[320] G[318] G[316] G[314] G[312] G[310] G[308] G[306] G[304] G[302] G[300] G[298] G[296] G[294] G[292] G[290] G[288] G[286] G[284] G[282] G[280] G[278] G[276] G[274] G[272] G[270] G[268] G[266] G[264] G[262] G[260] G[258] G[256] G[254] G[252] G[250] G[248] G[246] G[244] G[242] G[240] G[238] G[236] G[234] G[232]
X -6176 -6192 -6208 -6224 -6240 -6256 -6272 -6288 -6304 -6320 -6336 -6352 -6368 -6560 -6576 -6592 -6608 -6624 -6640 -6656 -6672 -6688 -6704 -6720 -6736 -6752 -6768 -6784 -6800 -6816 -6832 -6848 -6864 -6880 -6896 -6912 -6928 -6944 -6960 -6976 -6992 -7008 -7024 -7040 -7056 -7072 -7088 -7104 -7120 -7136 -7152 -7168 -7184 -7200 -7216 -7232 -7248 -7264 -7280 -7296
Y 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279
NO. 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260
ILI9331
Pad Name G[30] G[28] G[26] G[24] G[22] G[20] G[18] G[16] G[14] G[12] G[10] G[8] G[6] G[4] G[2] VGLDMY4 DUMMYR28 DUMMYR29 DUMMY30 DUMMY31 X -8912 -8928 -8944 -8960 -8976 -8992 -9008 -9024 -9040 -9056 -9072 -9088 -9104 -9120 -9136 -9152 -9168 -9184 -9200 -9216 Y 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279
NO. 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280
Pad Name G[110] G[108] G[106] G[104] G[102] G[100] G[98] G[96] G[94] G[92] G[90] G[88] G[86] G[84] G[82] G[80] G[78] G[76] G[74] G[72]
X -8272 -8288 -8304 -8320 -8336 -8352 -8368 -8384 -8400 -8416 -8432 -8448 -8464 -8480 -8496 -8512 -8528 -8544 -8560 -8576
Y 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279
NO. 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300
Pad Name G[70] G[68] G[66] G[64] G[62] G[60] G[58] G[56] G[54] G[52] G[50] G[48] G[46] G[44] G[42] G[40] G[38] G[36] G[34] G[32]
X -8592 -8608 -8624 -8640 -8656 -8672 -8688 -8704 -8720 -8736 -8752 -8768 -8784 -8800 -8816 -8832 -8848 -8864 -8880 -8896
Y 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279 166 279
NO. 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320
16
16
16
94
S1 ~ S720 G1 ~ G320 DUMMY18~31 VGMMA1, 62 VGLDMY1~4 94 Unit: um The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
19
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 50 20 50
ILI9331
Pad Pump
I/O Pads
Pad Pump
Min. 70
Alignment mark
80 Unit: um
30 20 30 30 30 30
30
20
Alignment mark 1 2
30 30 30 30
X -9266 9266
Y -251 -251
ILI9331
6. Block Description
MPU System Interface
ILI9331 supports three system high-speed interfaces: i80-system high-speed interfaces to 8-, 9-, 16-, 18-bit parallel ports and serial peripheral interface (SPI). The interface mode is selected by setting the IM[3:0] pins. ILI9331 has a 16-bit index register (IR), an 18-bit write-data register (WDR), and an 18-bit read-data register (RDR). The IR is the register to store index information from control registers and the internal GRAM. The WDR is the register to temporarily store data to be written to control registers and the internal GRAM. The RDR is the register to temporarily store data read from the GRAM. Data from the MPU to be written to the internal GRAM are first written to the WDR and then automatically written to the internal GRAM in internal operation. Data are read via the RDR from the internal GRAM. Therefore, invalid data are read out to the data bus when the ILI9331 read the first data from the internal GRAM. Valid data are read out after the ILI9331 performs the second read operation. Registers are written consecutively as the register execution time.
Registers selection by system interface (8-/9-/16-/18-bit bus width) Function Write an index to IR register Write to control registers or the internal GRAM by WDR register. Read from the internal GRAM by RDR register. RS 0 1 1 nWR 0 0 1
I80 nRD 1 1 0
Registers selection by the SPI system interface Function Write an index to IR register Write to control registers or the internal GRAM by WDR register. Read from the internal GRAM by RDR register. R/W 0 0 1 RS 0 1 1
Parallel RGB Interface

ILI9331 supports the RGB interface and the VSYNC interface as the external interface for displaying a moving picture. When the RGB interface is selected, display operations are synchronized with externally supplied signals, VSYNC, HSYNC, and DOTCLK. In RGB interface mode, data (DB17-0) are written in synchronization with these signals according to the polarity of enable signal (ENABLE) to prevent flicker on display while updating display data. In VSYNC interface mode, the display operation is synchronized with the internal clock except frame synchronization, where the operation is synchronized with the VSYNC signal. Display data are written to the internal GRAM via the system interface. In this case, there are constraints in speed and method in writing data to the internal RAM. For details, see the External Display Interface section. The ILI9331 allows for switching between the external display interface and the system interface by instruction so that the optimum interface is selected for the kind of picture to be displayed on the screen (still and/or moving picture(s)). The RGB interface, by writing all display data to the internal RAM, allows for transferring data only when updating the frames of a moving picture, contributing to low power requirement for moving picture display. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9331
Bit Operation
The ILI9331 supports a write data mask function for selectively writing data to the internal RAM in units of bits and a logical/compare operation to write data to the GRAM only when a condition is met as a result of comparing the data and the compare register bits. For details, see Graphics Operation Functions.
Address Counter (AC)

The address counter (AC) gives an address to the internal GRAM. When the index of the register for setting a RAM address in the AC is written to the IR, the address information is sent from the IR to the AC. As writing data to the internal GRAM, the address in the AC is automatically updated plus or minus 1. The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM.
Graphics RAM (GRAM)

GRAM is graphics RAM storing bit-pattern data of 172,800 (240 x 320x 18/8) bytes with 18 bits per pixel.
Grayscale Voltage Generating Circuit

The grayscale voltage generating circuit generates a liquid crystal drive voltage according to grayscale data set in the -correction register to display in 262,144 colors. For details, see the -Correction Register section.
Timing Controller
The timing generator generates a timing signal for operation of internal circuits such as the internal GRAM. The timing for the display operation such as RAM read operation and the timing for the internal operation such as access from the MPU are generated in the way not to interfere each other.
Oscillator (OSC)
ILI9331 generates RC oscillation with an internal oscillation resistor. The frame rate is adjusted by the register setting.
LCD Driver Circuit

The LCD driver circuit of ILI9331 consists of a 720-output source driver (S1 ~ S720) and a 320-output gate driver (G1~G320). Display pattern data are latched when the 720th bit data are input. The latched data control the source driver and generate a drive waveform. The gate driver for scanning gate lines outputs either VGH or VGL level. The shift direction of 720 source outputs from the source driver is set with the SS bit and the shift direction of gate outputs from the gate driver is set with the GS bit. The scan mode by the gate driver is set with the SM bit. These bits allow setting an appropriate scan method for an LCD module.
LCD Driver Power Supply Circuit

The LCD drive power supply circuit generates the voltage levels VREG1OUT, VGH, VGL and Vcom for driving an LCD The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9331
7. System Interface
7.1. Interface Specifications
ILI9331 has the system interface to read/write the control registers and display graphics memory (GRAM), and the RGB Input Interface for displaying a moving picture. User can select an optimum interface to display the moving or still picture with efficient data transfer. All display data are stored in the GRAM to reduce the data transfer efforts and only the updating data is necessary to be transferred. User can only update a sub-range of GRAM by using the window address function. ILI9331 also has the RGB interface and VSYNC interface to transfer the display data without flicker the moving picture on the screen. In RGB interface mode, the display data is written into the GRAM through the control signals of ENABLE, VSYNC, HSYNC, DOTCLK and data bus DB[17:0]. In VSYNC interface mode, the internal display timing is synchronized with the frame synchronization signal (VSYNC). The VSYNC interface mode enables to display the moving picture display through the system interface. In this case, there are some constraints of speed and method to write data to the internal RAM. ILI9331 operates in one of the following 4 modes. The display mode can be switched by the control register. When switching from one mode to another, refer to the sequences mentioned in the sections of RGB and VSYNC interfaces.
Operation Mode Internal operating clock only (Displaying still pictures) RGB interface (1) (Displaying moving pictures) RGB interface (2) (Rewriting still pictures while displaying moving pictures) VSYNC interface (Displaying moving pictures) (RM = 0)
RAM Access Setting System interface RGB interface (RM = 1) System interface (RM = 0) System interface (RM = 0)
(RM)
Display Operation Mode (DM[1:0]) Internal operating clock (DM[1:0] = 00) RGB interface (DM[1:0] = 01) RGB interface (DM[1:0] = 01) VSYNC interface (DM[1:0] = 01)
Note 1) Registers are set only via the system interface. Note 2) The RGB-I/F and the VSYNC-I/F are not available simultaneously.
ILI9331
System Interface
18/16/6
nCS RS nWR nRD DB[17:0]
System
ILI9331
ENABLE VSYNC HSYNC DOTCLK
RGB Interface
Figure1 System Interface and RGB Interface connection
7.2. Input Interfaces

The following are the system interfaces available with the ILI9331. The interface is selected by setting the IM[3:0] pins. The system interface is used for setting registers and GRAM access.
IM3 0 0 0 0 0 0 1 1 1 1 1
IM2 0 0 0 0 1 1 0 0 0 0 1
IM1 0 0 1 1 0 1 0 0 1 1 *
IM0/ID 0 1 0 1 ID * 0 1 0 1 *
Interface Mode Setting invalid Setting invalid i80-system 16-bit interface i80-system 8-bit interface Serial Peripheral Interface (SPI) Setting invalid MDDI Setting invalid i80-system18-bit interface i80-system 9-bit interface Setting invalid DB[17:0] DB[17:9]
DB Pin
DB[17:10], DB[8:1] DB[17:10] SDI, SDO (DB[1:0])
ILI9331
7.2.1. i80/18-bit System Interface

The i80/18-bit system interface is selected by setting the IM[3:0] as 1010 levels.
System
nCS A2 nWR nRD D[31:0]
18
18-bit S ys te m Inte rfa ce (262K colors ) TRI=0, DFM[1:0]=00

Input Da ta
DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0
Write Da ta Re gis te r
WD 17
WD 16
WD 15
WD 14
WD 13
WD 12
WD 11
WD 10
WD 9
WD 8
WD 7
WD 6
WD 5
WD 4
WD 3
WD 2
WD 1
WD 0
GRAM Da ta & RGB Ma pping
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure2 18-bit System Interface Data Format
ILI9331

The i80/16-bit system interface is selected by setting the IM[3:0] as 0010 levels. The 262K or 65K color can be display through the 16-bit MPU interface. When the 262K color is displayed, two transfers (1st transfer: 2 bits, 2nd transfer: 16 bits or 1st transfer: 16 bits, 2nd transfer: 2 bits) are necessary for the 16-bit CPU interface.
TRI
DFM
16-bit MP U S ys te m Inte rfa ce Da ta Forma t system 16-bit interface (1 transfers/pixel) 65,536 colors 1s t Tra ns fe r
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
80-system 16-bit interface (2 transfers/pixel) 262,144 colors 1s t Tra ns fe r 1 0

DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 2nd Tra ns fe r DB DB 17 16
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
80-system 16-bit interface (2 transfers/pixel) 262,144 colors

1s t Tra ns fe r DB DB 2 1
2nd Tra ns fe r
DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
ILI9331

The i80/9-bit system interface is selected by setting the IM[3:0] as 1011 and the DB17~DB9 pins are used to transfer the data. When writing the 16-bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first. The display data is also divided in upper byte (9 bits) and lower byte, and the upper byte is transferred first. The unused DB[8:0] pins must be tied to GND.
System
nCS A1 nWR nRD D[8:0]
9-bit S ys te m Inte rfa ce (262K colors ) TRI=0, DFM[1:0]=00

1 s t Tra ns fe r (Uppe r bits ) 2nd Tra ns fe r (Lowe r bits )
Input Da ta
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
WD 17
WD 16
WD 15
WD 14
WD 13
WD 12
WD 11
WD 10
WD 9
WD 8
WD 7
WD 6
WD 5
WD 4
WD 3
WD 2
WD 1
WD 0
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0

The i80/8-bit system interface is selected by setting the IM[3:0] as 0011 and the DB17~DB10 pins are used to transfer the data. When writing the 16-bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first. The display data is also divided in upper byte (8 bits) and lower byte, and the upper byte is transferred first. The written data is expanded into 18 bits internally (see the figure below) and then written into GRAM. The unused DB[9:0] pins must be tied to GND.
TRI DFM 8-bit MP U S ys te m Inte rfa ce Da ta Forma t system 8-bit interface (2 transfers/pixel) 65,536 colors 1s t Tra ns fe r 0 *
DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15
ILI9331
2nd Tra ns fe r
DB 14 DB 13 DB 12 DB 11 DB 10
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0

2nd Tra ns fe r
3rd Tra ns fe r
DB 14 DB 13 DB 12 DB 11 DB 10
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
80-system 8-bit interface (3 transfers/pixel) 262,144 colors 1s t Tra ns fe r 1 1

DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 17 DB 16
2nd Tra ns fe r
DB 15 DB 14 DB 13 DB 12 DB 17 DB 16
3rd Tra ns fe r
DB 15 DB 14 DB 13 DB 12
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
ILI9331
7.3. Serial Peripheral Interface (SPI)

The Serial Peripheral Interface (SPI) is selected by setting the IM[3:0] pins as 010x level. The chip select pin (nCS), the serial transfer clock pin (SCL), the serial data input pin (SDI) and the serial data output pin (SDO) are used in SPI mode. The ID pin sets the least significant bit of the identification code. The DB[17:0] pins, which are not used, must be tied to GND. The SPI interface operation enables from the falling edge of nCS and ends of data transfer on the rising edge of nCS. The start byte is transferred to start the SPI interface and the read/write operation and RS information are also included in the start byte. When the start byte is matched, the subsequent data is received by ILI9331. The seventh bit of start byte is RS bit. When RS = 0, either index write operation or status read operation is executed. When RS = 1, either register write operation or RAM read/write operation is executed. The eighth bit of the start byte is used to select either read or write operation (R/W bit). Data is written when the R/W bit is 0 and read back when the R/W bit is 1. After receiving the start byte, ILI9331 starts to transfer or receive the data in unit of byte and the data transfer starts from the MSB bit. All the registers of the ILI9331 are 16-bit format and receive the first and the second byte datat as the upper and the lower eight bits of the 16-bit register respectively. In SPI mode, 5 bytes dummy read is necessary and the valid data starts from 6th byte of read back data. Start Byte Format
Transferred bits Start byte format S Transfer start 0 1 1 2 3 1 4 1 5 0 6 ID 7 RS 1/0 8 R/W 1/0 Device ID code
Note: ID bit is selected by setting the IM0/ID pin. RS and R/W Bit Function
RS 0 0 1 1 R/W 0 1 0 1 Set an index register Read a status Write a register or GRAM data Read a register or GRAM data Function
ILI9331
S e ria l P e riphe ra l Inte rfa ce for re gis te r a cce s s

D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
S P I Input Da ta
Re gis te r Da ta
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
S e ria l P e riphe ra l Inte rfa ce 65K colors

Input Da ta
WD 17
WD 16
WD 15
WD 14
WD 13
WD 12
WD 11
WD 10
WD 9
WD 8
WD 7
WD 6
WD 5
WD 4
WD 3
WD 2
WD 1
WD 0
GRAM Da ta RGB m a pping
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure 6 Data Format of SPI Interface
ILI9331
End
(a) Basic data transmission through SPI

Start nCS (Input) 1 SCL (Input) SDI (Input) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
ID
RS RW D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Start Byte SDO (Output)
Index register, registers setting, and GRAM write D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Status, registers read and GRAM read
(b) Consecutive data transmission through SPI

Start nCS (Input) 1 SCL (Input) SDI (Input) Start Byte Register 1 upper eight bits Register 1 lower eight bits Register 2 upper eight bits Register 1 execution time Register 2 lower eight bits 8 9 16 17 24 25 32
Note: The first byte after the start byte is always the upper eight bits .
(c) GRAM data read transmission

Start nCS (Input)
End
SCL (Input) SDI (Input) SDO (Output) Start Byte RS=1, RW=1 Dummy read 1 Dummy read 2 Dummy read 3 Dummy read 4 Dummy read 5 RAM read upper byte RAM read lower byte
Note: Five bytes of invalid dummy data read after the start byte .
(d) Status/registers read transmission

Start nCS (Input) 1 SCL (Input) SDI (Input) SDO (Output) Start Byte Register 1 upper eight bits Register 1 lower eight bits 8 9 16 17 24
End
Note: One byte of invalid dummy data read after the start byte .
Figure7 Data transmission through serial peripheral interface (SPI)
ILI9331
End
(e) Basic data transmission through SPI

Start nCS (Input) 1 SCL (Input) SDI (Input) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ID
RS RW D23 D22 D21 D120 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 GRAM data write D23 D22 D21 D120 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 GRAM data read
D8
D7
D6
D5
D4
D3
D2
D1
D0
Start Byte SDO (Output)
D8
D7
D6
D5
D4
D3
D2
D1
D0
(f) GRAM data write transmission

Start nCS (Input)
End
SCL (Input) SDI (Input) SDO (Output) Note: Five bytes of invalid dummy data read after the start byte. Start Byte RAM data 1 1st transfer RAM data 1 2nd transfer RAM data 1 3rd transfer RAM data 2 1st transfer RAM data 2 2nd transfer RAM data 2 3rd transfer
GRAM Data (1) execution time
GRAM Data (2) execution time
(g) GRAM data read transmission

Start nCS (Input)
End
SCL (Input) SDI (Input) SDO (Output) Start Byte RS=1, RW=1 Dummy read 1 Dummy read 2 Dummy read 3 Dummy read 4 Dummy read 5 RAM read 1st byte RAM read 2nd byte RAM read 3rd byte
Note: Five bytes of invalid dummy data read after the start byte.
RAM data transfer in SPI mode when TRI=1 and DFM[1:0]=10.
Figure8 Data transmission through serial peripheral interface (SPI), TRI=1 and DFM=10)
ILI9331
7.4. VSYNC Interface

ILI9331 supports the VSYNC interface in synchronization with the frame-synchronizing signal VSYNC to display the moving picture with the i80 system interface. When the VSYNC interface is selected to display a moving picture, the minimum GRAM update speed is limited and the VSYNC interface is enabled by setting DM[1:0] = 10 and RM = 0.
VSYNC
MPU
nCS RS nWR DB[17:0]
Figure9 Data transmission through VSYNC interface) In the VSYNC mode, the display operation is synchronized with the internal clock and VSYNC input and the frame rate is determined by the pulse rate of VSYNC signal. All display data are stored in GRAM to minimize total data transfer required for moving picture display.
VSYNC Write data to RAM through system interface Display operation synchronized with internal clocks Rewriting screen data Rewriting screen data
Figure10 Moving picture data transmission through VSYNC interface
ILI9331
VSYNC
Back porch (14 lines)
RAM Write Display operation
Display (320 lines)
Front porch (2 lines) Black period
Figure11 Operation through VSYNC Interface The VSYNC interface has the minimum speed limitation of writing data to the internal GRAM via the system interface, which are calculated from the following formula. Internal clock frequency (fosc.) [Hz] = FrameFrequency x (DisplayLine (NL) + FrontPorch (FP) + BackPorch (BP)) x ClockCyclePerLines (RTN) x FrequencyFluctuation.
Minimum RAM write speed (HZ)
240 x DisplayLines (NL) [(BackPorch(BP)+DisplayLines(NL) - margins] x 16 (clocks) x 1/fosc
Note: When the RAM write operation does not start from the falling edge of VSYNC, the time from the falling edge of VSYNC until the start of RAM write operation must also be taken into account. An example of minimum GRAM writing speed and internal clock frequency in VSYNC interface mode is as below. [Example] Display size: 240 RGB 320 lines Lines: 320 lines (NL = 1000111) Back porch: 14 lines (BP = 1110) Front porch: 2 lines (FP = 0010) Frame frequency: 60 Hz Frequency fluctuation: 10% Internal oscillator clock (fosc.) [Hz] = 60 x [320+ 2 + 14] x 16 clocks x (1.1/0.9) 394KHz The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9331
When calculate the internal clock frequency, the oscillator variation is needed to be taken into consideration. In the above example, the calculated internal clock frequency with 10% margin variation is considered and ensures to complete the display operation within one VSYNC cycle. The causes of frequency variation come from fabrication process of LSI, room temperature, external resistors and VCI voltage variation. Minimum speed for RAM writing [Hz] > 240 x 320 x 394K / [ (14 + 320 2)lines x 16clocks] 5.7 MHz
The above theoretical value is calculated based on the premise that the ILI9331 starts to write data into the internal GRAM on the falling edge of VSYNC. There must at least be a margin of 2 lines between the physical display line and the GRAM line address where data writing operation is performed. The GRAM write speed of 5.7MHz or more will guarantee the completion of GRAM write operation before the ILI9331 starts to display the GRAM data on the screen and enable to rewrite the entire screen without flicker.
Notes in using the VSYNC interface 1. The minimum GRAM write speed must be satisfied and the frequency variation must be taken into consideration. 2. The display frame rate is determined by the VSYNC signal and the period of VSYNC must be longer than the scan period of an entire display. 3. When switching from the internal clock operation mode (DM[1:0] = 00) to the VSYNC interface mode or inversely, the switching starts from the next VSYNC cycle, i.e. after completing the display of the frame. 4. The partial display, vertical scroll, and interlaced scan functions are not available in VSYNC interface mode and set the AM bit to 0 to transfer display data.
ILI9331
System Interface Mode to VSYNC interface mode System Interface
VSYNC interface mode to System Interface Mode Opeartion through VSYNC interface
Set DM[1:0]=00, RM=0 for system interface mode
Set HWM=1, AM=0
Set GRAM Address
Display operation in synchronization with internal clocks

Wait more than 1 frame
Display operation in synchronization with VSYNC DM[1:0], RM become enable after completion of displaying 1 frame Display operation in synchronization with internal clocks
Set DM[1:0]=10, RM=0 for VSYNC interface mode
Set index register to R22h
DM[1:0], RM become enable after completion of displaying 1 frame
System Interface
Wait more than 1 frame
Note: input VSYNC for more than 1 frame period after setting the DM, RM register. Display operation in synchronization with VSYNC
Write data to GRAM through VSYNC interface
Opeartion through VSYNC interface
Figure12 Transition flow between VSYNC and internal clock operation modes
ILI9331
7.5. RGB Input Interface

The RGB Interface mode is available for ILI9331 and the interface is selected by setting the RIM[1:0] bits as following table.
RIM1 0 0 1 1
RIM0 0 1 0 1
RGB Interface 18-bit RGB Interface 16-bit RGB Interface 6-bit RGB Interface Setting prohibited DB[17:0]
DB pins DB[17:13], DB[11:1] DB[17:12]
18-bit RGB Inte rfa ce (262K colors )

Input Da ta
WD 17
WD 16
WD 15
WD 14
WD 13
WD 12
WD 11
WD 10
WD 9
WD 8
WD 7
WD 6
WD 5
WD 4
WD 3
WD 2
WD 1
WD 0
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
16-bit RGB Inte rfa ce (65K colors )

Input Da ta
WD 17
WD 16
WD 15
WD 14
WD 13
WD 11
WD 10
WD 9
WD 8
WD 7
WD 6
WD 5
WD 4
WD 3
WD 2
WD 1
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
6-bit RG B Inte rfa ce (262K colors )

1s t Tra ns fe r 2nd Tra ns fe r 3rd Tra ns fe r
Input Da ta
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
WD 17
WD 16
WD 15
WD 14
WD 13
WD 12
WD 11
WD 10
WD 9
WD 8
WD 7
WD 6
WD 5
WD 4
WD 3
WD 2
WD 1
WD 0
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure13 RGB Interface Data Format The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9331
7.5.1. RGB Interface

The display operation via the RGB interface is synchronized with the VSYNC, HSYNC, and DOTCLK signals. The RGB interface transfers the updated data to GRAM and the update area is defined by the window address function. The back porch and front porch are used to set the RGB interface timing.
VSYNC RAM data display area Moving picture display area HSYNC DOTCLK ENABLE DB[17:0]
Back porch period (BP[3:0])
Display period (NL[4:0]
Front porch period (FP[3:0]) Note 1: Front porch period continues until the next input of VSYNC. Note 2: Input DOTCLK throughout the operation. Note 3: Supply the VSYNC, HSYNC and DOTCLK with frequency that can meet the resolution requirement of panel.
Figure14 GRAM Access Area by RGB Interface
ILI9331
7.5.2. RGB Interface Timing

The timing chart of 18-/16-bit RGB interface mode is shown as follows.
1 frame Back porch VSYNC VLW >= 1H Front porch
HSYNC
DOTCLK
ENABLE DB[17:0]
HLW >= 3 DOTCLK HSYNC
// 1H
// DOTCLK DTST >= HLW ENABLE //
DB[17:0] Valid data VLW: VSYNC low period HLW: HSYNC low period DTST: data transfer startup time N t 1 U th hi h d it d (HWM 1) t it d t th h th RGB i t f
Figure15 Timing Chart of Signals in 18-/16-bit RGB Interface Mode
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color The timing chart of 6-bit RGB interface mode is shown as follows.
1 frame Back porch VSYNC VLW >= 1H Front porch
ILI9331
HSYNC
DOTCLK
ENABLE DB[17:12]
HLW >= 3 DOTCLK HSYNC
// 1H
// DOTCLK DTST >= HLW ENABLE // R G B R G B DB[17:12] Valid data VLW: VSYNC low period HLW: HSYNC low period DTST: data transfer startup time
Note 1) In 6-bit RGB interface mode, each dot of one pixel (R, G and B) is transferred in synchronization with DOTCLKs. Note 2) In 6-bit RGB interface mode, set the cycles of VSYNC, HSYNC and ENABLE to 3 multiples of DOTCLKs.
//
B R G B
Figure16 Timing chart of signals in 6-bit RGB interface mode
ILI9331
7.5.3. Moving Picture Mode

ILI9331 has the RGB interface to display moving picture and incorporates GRAM to store display data, which has following merits in displaying a moving picture. The window address function defined the update area of GRAM. Only the moving picture area of GRAM is updated. When display the moving picture in RGB interface mode, the DB[17:0] can be switched as system interface to update still picture area and registers, such as icons. RAM access via a system interface in RGB-I/F mode ILI9331 allows GRAM access via the system interface in RGB interface mode. In RGB interface mode, data are written to the internal GRAM in synchronization with DOTCLK and ENABLE signals. When write data to the internal GRAM by the system interface, set ENABLE to terminate the RGB interface and switch to the system interface to update the registers (RM = 0) and the still picture of GRAM. When restart RAM access in RGB interface mode, wait one read/write cycle and then set RM = 1 and the index register to R22h to start accessing RAM via the RGB interface. If RAM accesses via two interfaces conflicts, there is no guarantee that data are written to the internal GRAM. The following figure illustrates the operation of the ILI9331 when displaying a moving picture via the RGB interface and rewriting the still picture RAM area via the system interface.
Still Picture Area Moving Picture Area Update a frame
Update a frame
VSYNC
ENABLE
DOTCLK
DB[17:0] Update moving picture area Update moving picture area
Set IR to R22h
Set RM=0
Set AD[15:0]
Set IR to R22h
Update display data in other than the moving picture area
Set AD[15:0]
Set RM=1
Set IR to R22h
Figure17 Example of update the still and moving picture
ILI9331
7.5.4. 6-bit RGB Interface

The 6-bit RGB interface is selected by setting the RIM[1:0] bits to 10. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transferred to the internal GRAM in synchronization with the display operation via 6-bit RGB data bus (DB[17:12]) according to the data enable signal (ENABLE). Unused pins (DB[11:0]) must be fixed at GND level. Registers can be set by the system interface (i80/SPI).
R G B in te rfa c e with 6 -b it d a ta b u s
1st Transfer Input Da ta
2nd Transfer
DB 15 DB 14 DB 13 DB 12 DB 17 DB 16
3rd Transfer
DB 15 DB 14 DB 13 DB 12
RGB As s ignm e nt
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Data transfer synchronization in 6-bit RGB interface mode ILI9331 has data transfer counters to count the first, second, third data transfers in 6-bit RGB interface mode. The transfer counter is always reset to the state of first data transfer on the falling edge of VSYNC. If a mismatch arises in the number of each data transfer, the counter is reset to the state of first data transfer at the start of the frame (i.e. on the falling edge of VSYNC) to restart data transfer in the correct order from the next frame. This function is expedient for moving picture display, which requires consecutive data transfer in light of minimizing effects from failed data transfer and enabling the system to return to a normal state. Note that internal display operation is performed in units of pixels (RGB: taking 3 inputs of DOTCLK). Accordingly, the number of DOTCLK inputs in one frame period must be a multiple of 3 to complete data transfer correctly. Otherwise it will affect the display of that frame as well as the next frame.
HS YNC
ENABLE
DOTCLK DB[17:12]
st nd rd 1 s t 2 nd 3 rd 1 s t 2 nd 3 rd 1 2 3 1 s t 2 nd 3 rd
Tra ns fe r s ynchroniza tion
ILI9331

The 16-bit RGB interface is selected by setting the RIM[1:0] bits to 01. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transferred to the internal RAM in synchronization with the display operation via 16-bit RGB data bus (DB17-13, DB11-1) according to the data enable signal (ENABLE). Registers are set only via the system interface.
16-bit RG B Inte rfa ce (65K colors )

Input Da ta
WD 17
WD 16
WD 15
WD 14
WD 13
WD 11
WD 10
WD 9
WD 8
WD 7
WD 6
WD 5
WD 4
WD 3
WD 2
WD 1
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0

The 18-bit RGB interface is selected by setting the RIM[1:0] bits to 00. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transferred to the internal RAM in synchronization with the display operation via 18-bit RGB data bus (DB[17:0]) according to the data enable signal (ENABLE). Registers are set only via the system interface.
R G B inte rfa c e with 18 -bit d a ta b us

Input Da ta
RGB As s ignm e nt
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Notes in using the RGB Input Interface 1. The following are the functions not available in RGB Input Interface mode.
Function Partial display Scroll function Interlaced scan Graphics operation function
RGB interface Not available Not available Not available Not available
I80 system interface Available Available Available Available
2. VSYNC, HSYNC, and DOTCLK signals must be supplied throughout a display operation period. 3. The periods set with the NO[1:0] bits (gate output non-overlap period), STD[1:0] bits (source output delay period) and EQ[1:0] bits (equalization period) are not based on the internal clock but based on DOTCLK in The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color RGB interface mode.
ILI9331
4. In 6-bit RGB interface mode, each of RGB dots is transferred in synchronization with a DOTCLK input. In other words, it takes 3 DOTCLK inputs to transfer one pixel. Be sure to complete data transfer in units of 3 DOTCLK inputs in 6-bit RGB interface mode. 5. In 6-bit RGB interface mode, data of one pixel, which consists of RGB dots, are transferred in units of 3 DOTCLK. Accordingly, set the cycle of each signal in 6-bit interface mode (VSYNC, HSYNC, ENABLE, DB[17:0]) to contain DOTCLK inputs of a multiple of 3 to complete data transfer in units of pixels. 6. When switching from the internal operation mode to the RGB Input Interface mode, or the other way around, follow the sequence below. 7. In RGB interface mode, the front porch period continues until the next VSYNC input is detected after drawing one frame. 8. In RGB interface mode, a RAM address (AD[15:0]) is set in the address counter every frame on the falling edge of VSYNC.
In te rn a l c loc k o pe ra tion to R G B I/F
RGB I/F to Inte rna l clock ope ra tion RGB Inte rfa ce (Dis pla y ope ra tion in s ynchroniza tion with VS YNC , HS YNC, DOTCLK) * DM[1:0] a nd RM be com e e na ble a fte r com ple tion of dis pla y 1 fra m e
In te rn a l c loc k o pe ra tion HWM = 1, AM=0 Inte rna l clock ope ra tion * S P I inte rfa ce ca n be us e d to s e t the re gis te rs a nd da ta
R G B In te rfa c e O pe ra tio n S e t Inte rna l Clock Ope ra tion mode DM[1:0]=00 a nd R M=0
S e t AD[15:0]
Wa it for m ore tha n 1 fra m e S e t RGB Inte rfa ce mode DM[1:0]=01 a nd RM=1
Note
* DM[1:0] a nd RM be com e e na ble a fte r com ple tion of dis pla y 1 fra m e
Inte rn a l c lo c k op e ra tio n
S e t IR to R22h (GRAM da ta write )
Dis pla y ope ra tion in s ynchroniza tion with inte rna l clock
Wa it for m ore tha n 1 fra m e RGB Inte rfa ce (Dis pla y ope ra tion in s ynchroniza tion with VS YNC, HS YNC, DOTCLK)
Write da ta through RGB I/F
R G B Inte rfa c e O p e ra tion

Note : Input RG B Inte rfa ce s igna ls (VS YNC, HS YNC, DO TCLK) be fore s e tting DM[1;0] a nd RM to the RGB inte rfa ce mode
Figure18 Internal clock operation/RGB interface mode switching The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9331
Write da ta throu gh R G B in te rfa c e to write da ta th roug h s ys te m inte rfa ce R G B Inte rfa ce o pe ra tion S e t DM[1:0]=01, RM=0 with RGB inte rfa ce m ode
Write da ta th rou gh s ys te m in te rfa c e to write da ta thro u g h R G B in te rfa c e S ys te m Inte rfa ce o pe ra tion Write da ta to GRAM through s ys te m inte rfa ce
HWM=1/0
HWM=1/0
S e t AD[15;0]
S e t AD[15;0]
S e t DM[1:0]=01, RM=1 with RG B inte rfa ce m ode
Write da ta to GRAM through s ys te m inte rfa ce
R G B Inte rfa ce o pe ra tion S ys te m In te rfa c e op e ra tio n
Figure19 GRAM access between system interface and RGB interface
ILI9331
7.6. MDDI (Mobile Display Digital Interface)

MDDI (Mobile display digital interface) is a differential small amplitude serial interface for high-speed data transfer via following 4 lines: Stb+/(MDDI_STB_P, MDDI_STB_M), Data+/(MDDI_DATA_P, MDDI_DATA_M). The specifications of MDDI supported by the ILI9331 are compatible to the MDDI specifications disclosed by VESA, Video Electronics Standards Association. The following are the specifications particular to the ILI9331s MDDI.
7.6.1. ILI9331 MDDI Specifications

MDDI Type-I High-speed, differential, small-amplitude data transfer via Stb+/-, Data+/- lines MDDI client: the ILI9331 enables direct connection to the base band (BB) chip without bridge chip Cost-performance optimized interface for mobile display systems 1. Only internal mode (one client) and Forward Link are supported 2. Hibernation mode to save power consumption 3. Tearing-free moving picture display via FMARK/VSYNC interface 4. Moving picture display with low power consumption, realized by the features 2 ~ 3 5. Shutdown mode for saving power consumption in the standby state Incorporates an output port for sub-display interface or peripheral control Providing single-chip solution for MDDI mobile display systems ILI9331 MDDI_Data0+ MDDI_Data0MDDI_Stb+ MDDI Host nRESET GPIO MDDI_StbStb+/See Note 1
Data+/See Note 1
RCOG 100
See Note 2
MDDI_Data_P MDDI_Data_M MDDI_Stb_P MDDI_Stb_M nRESET nCS
RCOG RCOG
100
See Note 2
RCOG
(IRQ)
FMARK VSYNC Figure20 MDDI architecture
Notes: 1. An external end resistor of 100 ohm is necessary between Data+ and Data- lines 2. Make the COG wiring resistances of Data+/-, Stb+/- lines as small as possible (RCOG < 60 ohm).
ILI9331
7.6.2. MDDI Link Protocol (Packets Supported by the ILI9331)

The MDDI Link Protocol of the ILI9331 is in line with the MDDI specifications disclosed by VESA. See the MDDI specifications by VESA for details on the MDDI Link Protocol. The MDDI packets supported by the ILI9331 are as follows. Do not send packets not supported by the ILI9331 in the system incorporating the ILI9331.
Sub-Frame Header Packet

0 1 2 3 4 5 6 7 8 9 1 2 3 (0x0014) Packet Type (0x3bFF) Unique Word (0x005A) Reserved 1 (0x0000) Sub-Frame Length 4 5 6 7 Packet Length
Bytes
10 11 12 13 14 15 16 17 18 19 20 21 22 CRC (0x0000) Media-frame Count (0x0014) Protocol Version (0x0000) Sub-frame Count
ILI9331
Video Stream Packet

The ILI9331 writes image data to RAM via Video Stream Packet. The window and RAM addresses are set via Register Access Packet.
Packet Length 2 Bytes Packet Type = 16 2 Bytes bClient ID 2 Bytes Video Data format Descriptor 2 Bytes Pixel Data Attributes 2 Bytes X Left Edge 2 Bytes Y Top Edge 2 Bytes X Right Edge 2 Bytes Y Bottom Edge 2 Bytes
X Start 2 Bytes
Y Start 2 Bytes
Pixel Count 2 Bytes
Parameter CRC 2 Bytes
Pixel Data Packet Length - 26Bytes
Pixel Data CRC 2 Bytes
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Bit0 Bit1
Packet Length Packet Type (0x0010) bClient ID (0x0000) Video Data Format Descriptor Pixel Data Attributes X Left Edge Y Top Edge X Right Edge Y Bottom Edge X Start Y Start Pixel Count Parameter CRC
Pixel Data (Packet Length - 26 bytes) CRC
Note: The parameters colored in gray are not supported by the ILI9331.
ILI9331
Video Data Format Descriptor: sets the pixel data format. The ILI9331 supports only the following format. Set the same pixel format (bpp) as selected by DSS[1:0] in Video Data Format Descriptor.
[15:13] 010 010 [12] 1 1 [11:8] 0x5 0x6 Others [7:4] 0x6 0x6 [3:0] 0x5 0x6
Packed 16bpp RGB format (R:G:B=5:6:5) Packed 18bpp RGB format (R:G:B=6:6:6) Setting disabled
Packet 16bpp Packet 18bpp
0 0 0
MDDI Bytes n 1 2 3 4 5 1 2 3 4 0 Pixel 1 Blue 1 2 3 4 5 Pixel 2 Blue
6 1
MDDI Bytes (n+1) 7 0 1 2 3 4 5 6 7 0 2 3 4 5 0 1 2 3 4 0 Pixel 1 Green Pixel 1 Red 0 1 2 3 4 5 0 1 2 3 4 Pixel 2 Green Pixel 2 Red
MDDI Bytes (n+2) 1 2 3 4 5 6 7 1 2 3 4 0 1 2 Pixel 2 Blue Pixel 2 5 0 1 2 3 4 5 Pixel 2 Blue
Pixel Data Attributes: the image data sent vial Video Stream Packet is recognized as either the data for the main-panel or for the sub-panel according to the setting in [1:0] bits in this field.
Pixel Data Attributes 0x0000 0x0001 0x0002 0x0003 Others
Bits[1:0] 00 01 10 11 ILI9331 doesnt support the sub-panel display. Setting disabled
Description
The Video Stream Packet data is recognized as the data written in the ILI9331. The Video Stream Packet data is written in the ILI9331 and not outputted via sub-display interface.
Register Access Packet Register Access Packet is used when setting instruction to the ILI9331. Do not use this packet for RAM access.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pixel Data (Packet Length - 14 bytes) Register Dara CRC Note: The parameters colored in gray are not supported by the ILI9331. Parameter CRC Register Address Packet Type (0x0092) bClient ID (0x0000) Read/Write Info. 1 2 3 4 5 6 7 Packet Length
ILI9331
Read/Write Info: Read or Write information in register access. The ILI9331 supports only the following access setting
Bits[15:14] 00 00 Others
Bits[13:0] 0x0001 0xn
Function Single Access mode, in which one instruction is set via one register access packet In multi random access mode, the number of Register Data (index+instruction) is set. Setting disabled.
Register Address The index of the register to be accessed is set in Register Address area. Also, the register access mode, i.e. single or multi random access mode, and whether the Register Address Packet is directed to the ILI9331 or the sub display are determined by the setting in Register Address area.
Bits[31] 0
Description Single Access mode. The index of the register to be accessed (ID[11:0]) is set in bits[11:0] in Register Address. The instruction set (IB[15:0]) to be written in the register is stored in the Register Data area in Register Access Packet. Multi Random Access mode. The index of the register to be accessed (ID[11:0]) is stored in the upper 2 bytes in the Register Data area in Register Access Packet. The instruction set (IB[15:0]) to be written in the register is stored in the
lower 2 bytes in the Register Data area in Register Access Packet. In Multi Random Access mode, both index and instruction set are stored in the Register Data area and instruction set can be transferred consecutively without setting the index in Register Address in each time transferring instruction.
Bits[30:12] 19h00000 19h00001 19h00002 ~ 19h7FFFF
Description The Register Access Packet is directed to the ILI9331 via main-display interface. The Register Access Packet is directed to the sub display via sub-display interface. Setting disabled
Bits[11:0] Single Access Multi Random Access
Description Bits [11:0] are used as index [11:0]. In Multi Random Access mode, bits [11:0] are not used. Set 0 to all bits.
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Register Data
ILI9331
The data for register access is written in Register Data. Four bytes are allocated for one instruction.
Bits[31:16] All 0 Bits[15:0] Instruction IB[15:0] 4h0 + IndexID[11:0] Instruction consecutive instruction setting without setting the index in Register Address in each time transferring IB[15:0] instruction. Description In Single access mode, the instruction set written in bits[15:0] is set in the register, which is specified in the bits[11:0] in Register Address. In Multi Random Access mode, both index and instruction set are stored in Register Data to allow
Example of Register Access Packet in Single Access mode (e.g. write to the ILI9331)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Note: The parameters colored in gray are not supported by the ILI9331. Parameter CRC Register Data List (lower instruction IB[7:0]) (Upper instruction IB[15:8]) (0x00) (0x00) Parameter CRC Register Address Read/Write Info. bClient ID Packet Type 1 2 3 4 5 (0x12) (0x00) (0x92) (0x00) (0x00) (0x00) (0x01) (0x00) (index ID[7:0]) (0x0, upper index ID[11:8]) (0x00) (0x00) 6 7 Packet Length
ILI9331
6 7
Example of Register Access Packet in Multi Random Access mode (e.g. write 4 instructions to the ILI9331)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Note: The parameters colored in gray are not supported by the ILI9331. Parameter CRC Register Data List 4 index + instruction
th
5 (0x1E) (0x00) (0x92) (0x00) (0x00) (0x00) (0x04) (0x00) (0x00) (0x00) (0x00) (0x80)
Packet Length Packet Type bClient ID Read/Write Info. Register Address
Parameter CRC Register Data List 1 index + instruction

st
(Lower instruction IB1[7:0]) (Upper instruction IB1[15:8) (Lower Index ID1[7:0]) (Upper indexID1[15:8)
Register Data List 2 index + instruction
nd
(Lower instruction IB2[7:0]) (Upper instruction IB2[15:8) (Lower Index ID2 [7:0]) (Upper indexID2 [15:8)
Register Data List
3 index + instruction
rd
(Lower instruction IB3[7:0]) (Upper instruction IB3[15:8) (Lower Index ID3 [7:0]) (Upper indexID3[15:8) (Lower instruction IB4[7:0]) (Upper instruction IB4[15:8) (Lower Index ID4[7:0]) (Upper indexID4[15:8)
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Register Access Packet Restrictions
ILI9331
The ILI9331s internal RAM is accessible via Video Stream Packet. RAM access data is not included in Register Access Packet. Link Shutdown Packet This packet is used to bring Link to the Hibernation state.
0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 Packet Length (0X0014) Packet Type (0x0045) Parameter CRC
All Zeros (Type-I: 16 bytes) 22 Note: The parameters colored in gray are not supported by the ILI9331.
Filler Packet
0 1 2 3 4 Packet Type (0x0000) Filler bytes (all zeros) (Packet Length: 4 bytes) CRC 1 2 3 4 5 6 7 Packet Length
ILI9331
7.6.3. MDDI Instruction Setting

Instruction Setting in Single Access Mode In Single Access mode, one instruction set is transferred in one Register Access Packet. When transferring multiple numbers of instruction sets, they must be transferred in the same number of Register Access Packets.
Register Access Packet Parameter Read/Write Info[15:0] Register Address[31:0] Register Data[31:0] 0x0001
Register Setting 20h0000000+ID[11:0] 16h0000+IB[15:0]
MDDI Packet sRAP(x,y) = Single Register Access Packet (ID[15:0], IB[15:0])
sRAP (ID1, IB1) sRAP (ID2, IB2) sRAP (ID3, IB3) sRAP (ID4, IB4) sRAP (ID5, IB5)
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Instruction Setting via Multi Random Access Mode
ILI9331
In Multi Random Register Access operation, both index and instruction set are stored in one field of Register Data List in the Register Access Packet to allow random instruction setting. In this mode, a multiple number of instruction sets can be transferred in one Register Access Packet.
Register Access Packet Parameter Read/Write Info [15:0] Register Address [31:0] Register Data List [31:0] 32h8000_0000
Register Setting 0 x n (n: Number of Register List) ID[15:0]+IB[15:0]
MDDI Packet sRAP(x,y) = Multi-random Register Access Packet (ID[15:0], IB[15:0])
mRAP( ID1, IB1, ID2, IB2, ID3, IB3, ID3, IB4, ID3, IB5, IDn, IBn)
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color RAM Access Setting Example
ILI9331
The following are examples of RAM access via Video Stream Packet and register access via Register Access Packet in Single and Multi Random Access modes. Example: 240RGB x 320 panel, full screen rewrite, 18bpp data MDDI Packet: Single Access Mode sRAP (x, y) = Register Access Packet (ID[15:0], IB[15:0]) in Single Access Mode VSP (p, n) = Video Stream Packet (pixel data)
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color MDDI Packet: Multi Random Access Mode
ILI9331
mRAP (x, y) = Register Access Packet (ID[15:0], IB[15:0]) in Multi Random Access mode. VSP (p, n) = Video Stream Packet (pixel data)
Entry-mode Window-Address Address set
mRAP ( 32'h0003_1280, 32'h0210_0000, 32'h0211_00EF, 32'h0212_0000, 32'h0213_018F, 32'h0210_0000, 32'h0201_0000, )
RAM-Access
VSP (18'hxx_xxxx X n)
240RGB x 320 = 76,800 pixels
RAM-Access
VSP (18'hxx_xxxx X n)
Video Stream Access Packet Restriction AM Data write transfer to RAM RAM start address RAM window address 0 (Horizontal write) Transfer data for each line at a time within the window address area. Set them via register access packet
Register Packet Restriction RAM access The ILI9331s internal RAM is accessible via Video Stream Packet. RAM access data is not included in Register Access Packet.
Hibernation Setting The ILI9331s Client MDDI supports Hibernation setting. There are two ways to cancel the Hibernation setting, which can be selected according to the condition of use.
Hibernation Cancellation Host-initiated wake up FMARK-initiated wake up In power-saving mode such as standby Save power consumption in transferring moving picture data Host-initiated wake up triggered by the output from FMARK.
ILI9331
The Hibernation setting and cancellation sequence must be compatible with the VESA-MDDI specifications.
ILI9331
7.7. Interface Timing

The following are diagrams of interfacing timing with LCD panel control signals in internal operation and RGB interface modes.
// VS YNC // HS YNC
DOTCLK // ENABLE // // DB[17:0] 1 2 3 4 5 318 319 320 1 2 3 4
FLM
G1 G2
G 320 // S [720:1] 1 2 3 4 5 318 319 320
VCOM
..
Figure21 Relationship between RGB I/F signals and LCD Driving Signals for Panel
ILI9331
7.8. CABC (Content Adaptive Brightness Control)

ILI9331 provide a dynamic backlight control function as CABC (Content adaptive brightness control) to reduce the power consumption of the luminance source. ILI9331 will refer the gray scale content of display image to output a PWM waveform to LED driver for backlight brightness control. Content adaptation means that the content of gray sale can be increased while simultaneously lowering brightness of the backlight to achieve the same perceived brightness. The adjusted gray level scale and thus the power consumption reduction depend on the content of the image. LIL9331 can calculate the backlight brightness level and send a PWM pulse to LED driver via LEDPWM pin for backlight brightness control purpose. The figure in the following is the basic timing diagram which is applied ILI9331 to control LED driver.
Tperiod
LED PWM
Ton
Toff
The period Tperiod of PWM pulse can be changed by the PWM_DIV[7:0] bits of the command PWM_DIV (F2h).The LED-on time Ton and the LED-off time Toff are decided by the backlight brightness level which is calculated with CABC in ILI9331. If CABC is off, then LEDPWM will forced to H level. The PWM period value will be calculated via the equation as below.
f PWM_OUT =
5.8MHz (PWM_DIV[7 : 0] + 1) 255
ILI9331
8. Register Descriptions
8.1. Registers Access
ILI9331 adopts 18-bit bus interface architecture for high-performance microprocessor. All the functional blocks of ILI9331 starts to work after receiving the correct instruction from the external microprocessor by the 18-, 16-, 9-, 8-bit interface. The index register (IR) stores the register address to which the instructions and display data will be written. The register selection signal (RS), the read/write signals (nRD/nWR) and data bus D17-0 are used to read/write the instructions and data of ILI9331. The registers of the ILI9331 are categorized into the following groups. 1. Specify the index of register (IR) 2. Read a status 3. Display control 4. Power management Control 5. Graphics data processing 6. Set internal GRAM address (AC) 7. Transfer data to/from the internal GRAM (R22) 8. Internal grayscale -correction (R30 ~ R39) Normally, the display data (GRAM) is most often updated, and in order since the ILI9331 can update internal GRAM address automatically as it writes data to the internal GRAM and minimize data transfer by using the window address function, there are fewer loads on the program in the microprocessor. As the following figure shows, the way of assigning data to the 16 register bits (D[15:0]) varies for each interface. Send registers in accordance with the following data transfer format.
S e ria l P e rip h e ra l In te rfa c e fo r re g is te r a c c e s s

S P I Input Da ta
Re gis te r Da ta
D 15
D 14
D 13
D 12
D 11
D 10
D 9
D 8
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
Figure22 Register Setting with Serial Peripheral Interface (SPI)
ILI9331
i80/M68 s ys te m 18-bit da ta bus inte rfa ce

Da ta Bus (DB[17:0])
Re gis te r Bit (D[15:0])
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

Da ta Bus (DB[17:10]), (DB[8:1])
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

1 s t Tra ns fe r DB DB DB 14 13 12 2 nd Tra ns fe r DB DB DB 14 13 12
DB 17
DB 16
DB 15
DB 11
DB 10
DB 9
DB 17
DB 16
DB 15
DB 11
DB 10
DB 9
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
i80/M68 s ys te m 8-bit da ta bus inte rfa ce /S e ria l pe riphe ra l inte rfa ce (2/3 tra ns m is s ion)
1 s t Tra ns fe r DB DB 14 13 2 nd Tra ns fe r DB DB 14 13
DB 17
DB 16
DB 15
DB 12
DB 11
DB 10
DB 17
DB 16
DB 15
DB 12
DB 11
DB 10
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure23 Register setting with i80 System Interface
ILI9331
i80 18-/16-bit S ys te m Bus Inte rfa ce Tim ing
(a ) Write to re gis te r
nC S RS nR D nWR DB[17:0]
Write re gis te r x inde Write re gis te r ta da
(b) Re a d from re gis te r

Write re gis te r x inde R e a d re gis te r ta da
i80 9-/8-bit S ys te m Bus Inte rfa ce Tim ing
(a ) Write to re gis te r
h 00 Write re gis te r x inde Write re gis te r high byte da ta Write re gis te r byte da ta low
(b) Re a d from re gis te r

h 00 Write re gis te r x inde R e a d re gis te r byte da ta high Re a d re gis te r byte da ta low
Figure 24 Register Read/Write Timing of i80 System Interface The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9331
D10 0 SM 0 0 0 FP2 PTS2 0 0 0 0 BT2 DC12 0 VDV2 0 0 D9 1 0 B/C 0 0 FP1 PTS1 0 0 0 0 BT1 DC11 0 VDV1 0 0 D8 1 SS 0 0 BASEE FP0 PTS0 0 RM FMP8 0 BT0 DC10 0 VDV0 0 AD16 D7 ID7 0 0 0 ORG 0 0 0 0 0 FMP7 0 APE 0 VCIRE 0 AD7 AD15 D6 ID6 0 0 0 0 0 0 0 0 0 FMP6 0 AP2 DC02 0 0 AD6 AD14 D5 ID5 1 0 0 I/D1 GON 0 PTG1 0 DM1 FMP5 0 AP1 DC01 0 0 AD5 AD13 D4 ID4 1 0 0 I/D0 DTE 0 PTG0 0 DM0 FMP4 VSPL AP0 DC00 0 0 AD4 AD12 D3 ID3 0 0 0 AM CL BP3 ISC3 FMARKOE 0 FMP3 HSPL 0 0 VRH3 0 AD3 AD11 D2 ID2 0 0 0 0 0 BP2 ISC2 FMI2 0 FMP2 0 0 VC2 VRH2 0 AD2 AD10 D1 ID1 0 0 0 0 D1 BP1 ISC1 FMI1 RIM1 FMP1 EPL SLP VC1 VRH1 0 AD1 AD9 D0 ID0 1 0 0 0 D0 BP0 ISC0 FMI0 RIM0 FMP0 DPL STB VC0 VRH0 0 AD0 AD8
8.2. Instruction Descriptions

No. IR 00h 01h 02h 03h 07h 08h 09h Registers Name Index Register Driver Code Read Driver Output Control 1 LCD Driving Control Entry Mode Display Control 1 Display Control 2 Display Control 3 R/W RS W RO W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D15 1 0 0 TRI 0 0 0 0 0 0 0 0 0 0 0 0 0 D14 0 0 0 DFM 0 0 0 0 ENC2 0 0 0 0 0 0 0 0 D13 0 0 0 0 PTDE1 0 0 0 ENC1 0 0 0 0 0 0 0 0 D12 1 0 0 BGR PTDE0 0 0 0 ENC0 0 0 SAP 0 0 VDV4 0 0 D11 0 0 0 0 0 FP3 0 0 0 0 0 0 0 0 VDV3 0 0
0Ah Display Control 4 0Ch RGB Display Interface Control 1 0Dh Frame Maker Position 0Fh 10h 11h 12h 13h 20h 21h 22h 29h 30h 31h 32h 35h 36h 37h 38h 39h RGB Display Interface Control 2 Power Control 1 Power Control 2 Power Control 3 Power Control 4 Horizontal GRAM Address Set Vertical GRAM Address Set Write Data to GRAM Power Control 7 Gamma Control 1 Gamma Control 2 Gamma Control 3 Gamma Control 4 Gamma Control 5 Gamma Control 6 Gamma Control 7 Gamma Control 8
RAM write data (WD17-0) / read data (RD17-0) bits are transferred via different data bus lines according to the selected interfaces. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VRP1[4] 0 0 0 0 VRN1[4] 0 0 0 0 0 0 0 VRP1[3] 0 0 0 0 VRN1[3] 0 0 0 KP1[2] KP3[2] KP5[2] RP1[2] KN1[2] KN3[2] KN5[2] RN1[2] 0 0 KP1[1] KP3[1] KP5[1] RP1[1] KN1[1] KN3[1] KN5[1] RN1[1] 0 0 KP1[0] KP3[0] KP5[0] RP1[0] KN1[0] KN3[0] KN5[0] RN1[0] 0 0 0 0 0 0 0 0 0 0 0 0 HSA7 0 0 0 0 0 0 0 0 0 0 0 0 HSA6 VCM5 0 0 0 0 0 0 0 0 0 0 0 HSA5 VCM4 0 0 0 0 0 0 0 0 0 0 0 HSA4 VCM3 FRS[3] 0 0 0 0 VRP0[3] 0 0 0 0 VRN0[3] HSA3 VCM2 FRS[2] KP0[2] KP2[2] KP4[2] RP0[2] KN0[2] KN2[2] KN4[2] RN0[2] VCM1 FRS[1] KP0[1] KP2[1] KP4[1] RP0[1] KN0[1] KN2[1] KN4[1] RN0[1] VCM0 FRS[0] KP0[0] KP2[0] KP4[0] RP0[0] KN0[0] KN2[0] KN4[0] RN0[0]
2Bh Frame Rate and Color Control
VRP1[2] VRP1[1] VRP1[0]
VRP0[2] VRP0[1] VRP0[0]
3Ch Gamma Control 9 3Dh Gamma Control 10 50h Horizontal Address Start Position
VRN1[2] VRN1[1] VRN1[0] 0 0 0
VRN0[2] VRN0[1] VRN0[0] HSA2 HSA1 HSA0
No. 51h 52h 53h 60h 61h 80h 81h 82h 83h 84h 85h 90h 92h 95h 97h Registers Name Horizontal Address End Position Vertical Address Start Position Vertical Address End Position Driver Output Control 2 Base Image Display Control Partial Image 1 Display Position Partial Image 1 Area (Start Line) Partial Image 1 Area (End Line) Partial Image 2 Display Position Partial Image 2 Area (Start Line) Partial Image 2 Area (End Line) Panel Interface Control 1 Panel Interface Control 2 Panel Interface Control 4 Panel Interface Control 5 R/W RS W W W W W W W W W W W W W W W W W W W W R W R W R W R W W W 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D15 0 0 0 GS 0 0 0 0 0 0 0 0 0 0 0 0 0 PGM_ CNT1 KEY 15 X X X X X X X X X X X D14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGM_ CNT0 KEY 14 X X X X X X X X X X X D13 0 0 0 NL5 0 0 0 0 0 0 0 0 0 0 0 0 0 VCM_ D5 KEY 13 X X X X X X X X X X X D12 0 0 0 NL4 0 0 0 0 0 0 0 0 0 0 0 0 0 VCM_ D4 KEY 12 X X X X X X X X X X X D11 0 0 0 NL3 0 0 0 0 0 0 0 0 0 0 0 NOWE3 OTP_ PGM_EN VCM_ D3 KEY 11 X X X X X X X X X X X D10 0 0 0 NL2 0 0 0 0 0 0 0 0 0 NOWI2 0 0 VCM_ D2 KEY 10 X X X X X X X X X X X
ILI9331
D9 0 0 0 NL1 0 0 0 0 0 0 0 0 DIVI1 NOWI1 DIVE1 0 VCM_ D1 KEY 9 X X X X X X X X X X X D8 0 VSA8 VEA8 NL0 0 VL8 D7 HEA7 VSA7 VEA7 0 0 VL7 D6 HEA6 VSA6 VEA6 0 0 VL6 D5 HEA5 VSA5 VEA5 SCN5 0 VL5 D4 HEA4 VSA4 VEA4 SCN4 0 VL4 PTDP04 PTSA04 PTEA04 PTDP14 PTSA14 PTEA14 RTNI4 0 0 0 VCM_ OTP4 0 KEY 4 DBV4 DBV4 X X X X D3 HEA3 VSA3 VEA3 SCN3 0 VL3 PTDP03 PTSA03 PTEA03 PTDP13 PTSA13 PTEA13 RTNI3 0 0 0 VCM_ OTP3 0 KEY 3 DBV3 DBV3 DD DD X X CMB[7:0] CMB[7:0] PWM_DIV[7:0] THRES_MOV[3:0] 0 0 0 0 THRES_STILL[3:0] THRES_UI[3:0] D2 HEA2 VSA2 VEA2 SCN2 NDL VL2 D1 HEA1 VSA1 VEA1 SCN1 VLE VL1 D0 HEA0 VSA0 VEA0 SCN0 REV VL0
6Ah Vertical Scroll Control
PTDP08 PTDP07 PTDP06 PTDP05 PTSA08 PTSA07 PTSA06 PTSA05 PTEA08 PTEA07 PTEA06 PTEA05 PTDP18 PTDP17 PTDP16 PTDP15 PTSA18 PTSA17 PTSA16 PTSA15 PTEA18 PTEA17 PTEA16 PTEA15 DIVI00 NOWI0 DIVE0 0 VCM_ D0 KEY 8 X X X X X X X X X X X 0 0 0 0 0 0 KEY 7 DBV7 DBV7 X X X X 0 0 0 0 0 0 KEY 6 DBV6 DBV6 X X X X 0 0 0 0 VCM_ OTP5 0 KEY 5 DBV5 DBV5 BCTRL BCTRL X X
PTDP02 PTDP01 PTDP00 PTSA02 PTSA01 PTSA00 PTEA02 PTEA01 PTEA00 PTDP12 PTDP11 PTDP10 PTSA12 PTSA11 PTSA10 PTEA12 PTEA11 PTEA10 RTNI2 0 0 0 VCM_ OTP2 0 KEY 2 DBV2 DBV2 BL BL X X RTNI1 0 0 0 VCM_ OTP1 0 KEY 1 DBV1 DBV1 X X C[1:0] C[1:0] RTNI0 0 0 0 VCM_ OTP0 VCM_ EN KEY 0 DBV0 DBV0 X X
NOWE2 NOWE1 NOWE0
A1h OTP VCM Programming Control A2h OTP VCM Status and Enable A5h OTP Programming ID Key B1h Write Display Brightness B2h Read Display Brightness B3h Write CTRL Display value B4h Read CTRL Display value B5h Write Content Adaptive Brightness Control value B6h Read Content Adaptive Brightness Control value BEh Write CABC Minimum Brightness BFh Read CABC Minimum Brightness C8h CABC Control 1 C9h CABC Control 2 CAh CABC Control 3
No. Registers Name R/W RS W W W W 1 1 1 1 D15 X X X X D14 X X X X D13 X X X X D12 X X X X D11 X X X X D10 X X X X
ILI9331
D9 X X X X D8 X X X D7 0 D6 D5 DTH_MOV[3:0] 0 0 DIM_OPT2[3:0] SCD_VLINE[8:0] D4 0 0 D3 D2 D1 DTH_STILL[3:0] DTH_UI[3:0] DIM_OPT1[2:0] D0
CBh CABC Control 4 CCh CABC Control 5 CDh CABC Control 6 CEh CABC Control 7
ILI9331
D4 ID4 D3 ID3 D2 ID2 D1 ID1 D0 ID0
8.2.1. Index (IR)

R/W W RS 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 ID7 D6 ID6 D5 ID5
The index register specifies the address of register (R00h ~ RFFh) or RAM which will be accessed.
8.2.2. ID code (R00h)

R/W RO RS 1 D15 1 D14 0 D13 0 D12 1 D11 0 D10 0 D9 1 D8 1 D7 0 D6 0 D5 1 D4 1 D3 0 D2 0 D1 0 D0 1
The device code 9331h is read out when read this register.
8.2.3. Driver Output Control (R01h)

R/W RS W 1 Default D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 0 0 D10 SM 0 D9 0 0 D8 SS 0 D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0
SS: Select the shift direction of outputs from the source driver. When SS = 0, the shift direction of outputs is from S1 to S720 When SS = 1, the shift direction of outputs is from S720 to S1. In addition to the shift direction, the settings for both SS and BGR bits are required to change the assignment of R, G, B dots to the source driver pins. To assign R, G, B dots to the source driver pins from S1 to S720, set SS = 0. To assign R, G, B dots to the source driver pins from S720 to S1, set SS = 1. When changing SS or BGR bits, RAM data must be rewritten. SM: Sets the gate driver pin arrangement in combination with the GS bit (R60h) to select the optimal scan mode for the module.
ILI9331
SM
GS
Scan Direction
G319 G317 Odd-number TFT Panel G320 G318 Even-number
Gate Output Sequence
0
G3 G1 ILI9331 G4 G2
G1, G2, G3, G4, ,G316 G317, G318, G319, G320
G319 G317 Odd-number TFT Panel
G320 G318 Even-number
1
G3 G1 ILI9331 G4 G2
G320, G319, G318, , G6, G5, G4, G3, G2, G1
G1, G3, G5, G7, ,G311 G313, G315, G317, G319

G2 to G320
0
G1 to G319
G2, G4, G6, G8, ,G312 G314, G316, G318, G320
G320, G318, G316, , G10, G8, G6, G4, G2

G2 to G320
1
G1 to G319
G319, G317, G315, , G9, G78, G5, G3, G1
ILI9331
D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0
8.2.4. LCD Driving Wave Control (R02h)

R/W RS W 1 Default D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 0 0 D10 0 0 D9 B/C 0 D8 0 0 D7 0 0 D6 0 0 D5 0 0
.B/C 0 : Frame/Field inversion 1 : Line inversion
8.2.5. Entry Mode (R03h)

R/W RS W 1 Default D15 TRI 0 D14 DFM 0 D13 0 0 D12 BGR 0 D11 0 0 D10 0 0 D9 0 0 D8 0 0 D7 ORG 0 D6 0 0 D5 I/D1 1 D4 I/D0 1 D3 AM 0 D2 0 0 D1 0 0 D0 0 0
AM Control the GRAM update direction. When AM = 0, the address is updated in horizontal writing direction. When AM = 1, the address is updated in vertical writing direction. When a window area is set by registers R50h ~R53h, only the addressed GRAM area is updated based on I/D[1:0] and AM bits setting. I/D[1:0] Control the address counter (AC) to automatically increase or decrease by 1 when update one pixel display data. Refer to the following figure for the details.
I/D[1:0] = 00 Horizonta l : de cre m e nt Ve rtica l : de cre me nt
I/D[1:0] = 01 Horizonta l : incre me nt Ve rtica l : de cre me nt
I/D[1:0] = 10 Horizonta l : de cre me nt Ve rtica l : incre me nt
I/D[1:0] = 11 Horizonta l : incre me nt Ve rtica l : incre me nt
AM = 0 Horizonta l
B B E E
AM = 1 Ve rtica l
B B E E
Figure25 GRAM Access Direction Setting ORG Moves the origin address according to the ID setting when a window address area is made. This function is enabled when writing data with the window address area using high-speed RAM write. ORG = 0: The origin address is not moved. In this case, specify the address to start write operation according to the GRAM address map within the window address area. ORG = 1: The original address 00000h moves according to the I/D[1:0] setting. Notes: 1. When ORG=1, only the origin address address00000h can be set in the RAM address set registers R20h, and R21h. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 2. In RAM read operation, make sure to set ORG=0. BGR Swap the R and B order of written data. BGR=0: Follow the RGB order to write the pixel data. BGR=1: Swap the RGB data to BGR in writing into GRAM.
ILI9331
TRI When TRI = 1, data are transferred to the internal RAM in 8-bit x 3 transfers mode via the 8-bit interface. It is also possible to send data via the 16-bit interface or SPI in the transfer mode that realizes display in 262k colors in combination with DFM bits. When not using these interface modes, be sure to set TRI = 0. DFM Set the mode of transferring data to the internal RAM when TRI = 1. See the following figures for details.
TRI DFM 16-bit MP U S ys te m Inte rfa ce Da ta Forma t
system 16-bit interface (1 transfers/pixel) 65,536 colors
1s t Tra ns fe r 0 *
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
1s t Tra ns fe r 1 0
2nd Tra ns fe r DB DB 17 16
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0

2nd Tra ns fe r
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure26 16-bit MPU System Interface Data Format
TRI DFM 8-bit MP U S ys te m Inte rfa ce Da ta Forma t
system 8-bit interface (2 transfers/pixel) 65,536 colors
ILI9331
1s t Tra ns fe r 0 *
2nd Tra ns fe r
DB 14 DB 13 DB 12 DB 11 DB 10
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0

2nd Tra ns fe r
3rd Tra ns fe r
DB 14 DB 13 DB 12 DB 11 DB 10
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
1s t Tra ns fe r 1 1
2nd Tra ns fe r
DB 15 DB 14 DB 13 DB 12 DB 17 DB 16
3rd Tra ns fe r
DB 15 DB 14 DB 13 DB 12
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure27 8-bit MPU System Interface Data Format
8.2.6. Display Control 1 (R07h)

R/W RS W 1 Default D15 0 0 D14 0 0 D13 PTDE1 0 D12 PTDE0 0 D11 0 0 D10 0 0 D9 0 0 D8 BASEE 0 D7 0 0 D6 0 0 D5 GON 0 D4 DTE 0 D3 CL 0 D2 0 0 D1 D1 0 D0 D0 0
D[1:0] Set D[1:0]=11 to turn on the display panel, and D[1:0]=00 to turn off the display panel. A graphics display is turned on the panel when writing D1 = 1, and is turned off when writing D1 = 0. When writing D1 = 0, the graphics display data is retained in the internal GRAM and the ILI9331 displays the data when writing D1 = 1. When D1 = 0, i.e. while no display is shown on the panel, all source outputs becomes the GND level to reduce charging/discharging current, which is generated within the LCD while driving liquid crystal with AC voltage. When the display is turned off by setting D[1:0] = 01, the ILI9331 continues internal display operation. When the display is turned off by setting D[1:0] = 00, the ILI9331 internal display operation is halted completely. In combination with the GON, DTE setting, the D[1:0] setting controls display ON/OFF.
D1 0 0 1 1 1 D0 0 1 0 1 1 BASEE 0 1 0 0 1 GND GND Non-lit display Non-lit display Base image display Source, VCOM Output ILI9331 internal operation Halt Operate Operate Operate Operate
Note: 1. data write operation from the microcontroller is performed irrespective of the setting of D[1:0] bits. 2. The D[1:0] setting is valid on both 1st and 2nd displays. 3. The non-lit display level from the source output pins is determined by instruction (PTS).
ILI9331
CL When CL = 1, the 8-color display mode is selected.

CL 0 1 262,144 8 Colors
GON and DTE Set the output level of gate driver G1 ~ G320 as follows
GON 0 0 1 1
DTE 0 1 0 1 VGH VGH VGL
G1 ~G320 Gate Output
Normal Display
BASEE Base image display enable bit. When BASEE = 0, no base image is displayed. The ILI9331 drives liquid crystal at non-lit display level or displays only partial images. When BASEE = 1, the base image is displayed. The D[1:0] setting has higher priority over the BASEE setting. PTDE[1:0] Partial image 2 and Partial image 1 enable bits PTDE1/0 = 0: turns off partial image. Only base image is displayed. PTDE1/0 = 1: turns on partial image. Set the base image display enable bit to 0 (BASEE = 0).

R/W RS W 1 Default D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 FP3 1 D10 FP2 0 D9 FP1 0 D8 FP0 0 D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 BP3 1 D2 BP2 0 D1 BP1 0 D0 BP0 0
FP[3:0]/BP[3:0] The FP[3:0] and BP[3:0] bits specify the line number of front and back porch periods respectively. When setting the FP[3:0] and BP[3:0] value, the following conditions shall be met: BP + FP 16 lines FP 2 lines BP 2 lines
Set the BP[3:0] and FP[3:0] bits as below for each operation modes
Operation Mode I80 System Interface Operation Mode RGB interface Operation VSYNC interface Operation BP BP 2 lines BP 2 lines BP 2 lines FP FP 2 lines FP 2 lines FP 2 lines BP+FP FP +BP 16 lines FP +BP 16 lines FP +BP = 16 lines
ILI9331
FP[3:0] BP[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Number of lines for Front Porch Number of lines for Back Porch Setting Prohibited Setting Prohibited 2 lines 3 lines 5 lines 6 lines 7 lines 8 lines 9 lines 10 lines 11 lines 12 lines 13 lines 14 lines Setting Prohibited
Front Porch VSYNC Back Porch
4 lines
Display Area
Note: The output timing to the LCD is delayed by 2 lines period from the input of synchronizing signal.

R/W RS W 1 Default D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 0 0 D10 PTS2 0 D9 PTS1 0 D8 PTS0 0 D7 0 0 D6 0 0 D5 PTG1 0 D4 PTG0 0 D3 ISC3 0 D2 ISC2 0 D1 ISC1 0 D0 ISC0 0
ISC[3:0]: Specify the scan cycle interval of gate driver in non-display area when PTG[1:0]=10 to select interval scan. Then scan cycle is set as odd number from 0~29 frame periods. The polarity is inverted every scan cycle.
ISC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ISC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ISC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ISC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Scan Cycle 0 frame 0 frame 3 frame 5 frame 7 frame 9 frame 11 frame 13 frame 15 frame 17 frame 19 frame 21 frame 23 frame 25 frame 27 frame 29 frame fFLM=60 Hz 50ms 84ms 117ms 150ms 184ms 217ms 251ms 284ms 317ms 351ms 384ms 418ms 451ms 484ms
PTG[1:0] Set the scan mode in non-display area.

PTG1 0 0 1 1 PTG0 0 1 0 1 Gate outputs in non-display area Normal scan Setting Prohibited Interval scan Setting Prohibited Source outputs in non-display area Set with the PTS[2:0] bits Set with the PTS[2:0] bits Vcom output VcomH/VcomL VcomH/VcomL -
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color PTS[2:0]
ILI9331
Set the source output level in non-display area drive period (front/back porch period and blank area between partial displays). When PTS[2] = 1, the operation of amplifiers which generates the grayscales other than V0 and V63 are halted.
PTS[2:0] 000 001 010 011 100 101 110 111
Source output level Positive polarity V63 Setting Prohibited GND Hi-Z V63 Setting Prohibited GND Hi-Z Negative polarity V0 Setting Prohibited GND Hi-Z V0 Setting Prohibited GND Hi-Z
Grayscale amplifier in operation V63 to V0 V63 to V0 V63 to V0 V63 and V0 V63 and V0 V63 and V0
Notes: 1. The power efficiency can be improved by halting grayscale amplifiers only in non-display drive period. 2. The gate output level in non-lit display area drive period is determined by PTG[1:0].
8.2.9. Display Control 4 (R0Ah)

R/W RS W 1 Default D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 0 0 D10 0 0 D9 0 0 D8 0 0 D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 FMARKOE 0 D2 FMI2 0 D1 FMI1 0 D0 FMI0 0
FMI[2:0] Set the output interval of FMARK signal according to the display data rewrite cycle and data transfer rate. FMARKOE When FMARKOE=1, ILI9331 starts to output FMARK signal in the output interval set by FMI[2:0] bits.
FMI[2:0] 000 001 011 101 Others Output Interval 1 frame 2 frame 4 frame 6 frame Setting disabled
8.2.10. RGB Display Interface Control 1 (R0Ch)

R/W RS W 1 Default D15 0 0 D14 ENC2 0 D13 ENC1 0 D12 ENC0 0 D11 0 0 D10 0 0 D9 0 0 D8 RM 0 D7 0 0 D6 0 0 D5 DM1 0 D4 DM0 0 D3 0 0 D2 0 0 D1 RIM1 0 D0 RIM0 0
RIM[1:0] Select the RGB interface data width.
RIM1 0 0 1 1
RIM0 0 1 0 1
RGB Interface Mode 18-bit RGB interface (1 transfer/pixel), DB[17:0] 16-bit RGB interface (1 transfer/pixel), DB[17:13] and DB[11:1] 6-bit RGB interface (3 transfers/pixel), DB[17:12] Setting disabled
Note1: Registers are set only by the system interface. Note2: Be sure that one pixel (3 dots) data transfer finished when interface switch.
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color DM[1:0] Select the display operation mode.
DM1 0 0 1 1 DM0 0 1 0 1 Display Interface Internal system clock RGB interface VSYNC interface Setting disabled
ILI9331
The DM[1:0] setting allows switching between internal clock operation mode and external display interface operation mode. However, switching between the RGB interface operation mode and the VSYNC interface operation mode is prohibited. RM Select the interface to access the GRAM. Set RM to 1 when writing display data by the RGB interface.
RM 0 1 Interface for RAM Access System interface/VSYNC interface RGB interface
Display State Still pictures Moving pictures
Operation Mode Internal clock operation RGB interface (1)
RAM Access (RM) System interface (RM = 0) RGB interface (RM = 1) System interface (RM = 0) System interface (RM = 0)
Display Operation Mode (DM[1:0] Internal clock operation (DM[1:0] = 00) RGB interface (DM[1:0] = 01) RGB interface (DM[1:0] = 01) VSYNC interface (DM[1:0] = 10)
Rewrite still picture area while RGB interface Displaying moving pictures. Moving pictures VSYNC interface
Note 1: Registers are set only via the system interface or SPI interface. Note 2: Refer to the flowcharts of RGB Input Interface section for the mode switch.
ENC[2:0] Set the GRAM write cycle through the RGB interface
ENC[2:0] 000 001 010 011 100 101 110 111 GRAM Write Cycle (Frame periods) 1 Frame 2 Frames 3 Frames 4 Frames 5 Frames 6 Frames 7 Frames 8 Frames
8.2.11. Frame Marker Position (R0Dh)

R/W RS W 1 Default D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 0 0 D10 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 FMP8 FMP7 FMP6 FMP5 FMP4 FMP3 FMP2 FMP1 FMP0 0 0 0 0 0 0 0 0 0 0
EMP[8:0] Sets the output position of frame cycle (frame marker). When FMP[8:0]=0, a high-active pulse FMARK is output at the start of back porch period for one display line period (1H). Make sure the 9h000 FMP BP+NL+FP The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9331
FMP[8:0] 9h000 9h001 9h002 9h003 . . . 9h175 9h176 9h177
FMARK Output Position 0 line 1 line 2 line 3 line . . . 373 line 374 line 375 line
th th rd rd nd st th
8.2.12. RGB Display Interface Control 2 (R0Fh)

R/W RS W 1 Default D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 0 0 D10 0 0 D9 0 0 D8 0 0 D7 0 0 D6 0 0 D5 0 0 D4 VSPL 0 D3 HSPL 0 D2 0 0 D1 EPL 0 D0 DPL 0
DPL: Sets the signal polarity of the DOTCLK pin. DPL = 0 The data is input on the rising edge of DOTCLK DPL = 1 The data is input on the falling edge of DOTCLK EPL: Sets the signal polarity of the ENABLE pin. EPL = 0 The data DB17-0 is written when ENABLE = 0. Disable data write operation when ENABLE = 1. EPL = 1 The data DB17-0 is written when ENABLE = 1. Disable data write operation when ENABLE = 0. HSPL: Sets the signal polarity of the HSYNC pin. HSPL = 0 Low active HSPL = 1 High active VSPL: Sets the signal polarity of the VSYNC pin. VSPL = 0 Low active VSPL = 1 High active
8.2.13. Power Control 1 (R10h)

R/W RS W 1 Default D15 0 0 D14 0 0 D13 0 0 D12 SAP 0 D11 0 0 D10 BT2 0 D9 BT1 0 D8 BT0 0 D7 APE 0 D6 AP2 0 D5 AP1 0 D4 AP0 0 D3 0 0 D2 0 0 D1 SLP 0 D0 STB 0
SLP: When SLP = 1, ILI9331 enters the sleep mode and the display operation stops except the RC oscillator to reduce the power consumption. In the sleep mode, the GRAM data and instructions cannot be updated except the following instruction. a. Exit sleep mode (SLP = 0) STB: When STB = 1, ILI9331 enters the standby mode and the display operation stops except the GRAM power supply to reduce the power consumption. In the STB mode, the GRAM data and instructions cannot be updated except the following instruction. a. Exit standby mode (STB = 0) The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9331
AP[2:0]: Adjusts the constant current in the operational amplifier circuit in the LCD power supply circuit. The larger constant current enhances the drivability of the LCD, but it also increases the current consumption. Adjust the constant current taking the trade-off into account between the display quality and the current consumption. In no-display period, set AP[2:0] = 000 to halt the operational amplifier circuits and the step-up circuits to reduce current consumption.
AP[2:0] 000 001 010 011 100 101 110 111
Gamma driver amplifiers Halt 1.00 1.00 1.00 0.75 0.75 0.75 0.50
Source driver amplifiers Halt 1.00 0.75 0.50 1.00 0.75 0.50 0.50
SAP: Source Driver output control SAP=0, Source driver is disabled. SAP=1, Source driver is enabled. When starting the charge-pump of LCD in the Power ON stage, make sure that SAP=0, and set the SAP=1, after starting up the LCD power supply circuit. APE: Power supply enable bit. Set APE = 1 to start the generation of power supply according to the power supply startup sequence. BT[3:0]: Sets the factor used in the step-up circuits. Select the optimal step-up factor for the operating voltage. To reduce power consumption, set a smaller factor.
BT[2:0] 3h0 3h1 3h2 3h3 3h4 3h5 3h6 3h7 VCI1 x 2 - VCI1 VCI1 x 4 VCI1 x 2 - VCI1 VCI1 x 5 DDVDH VCI1 x 2 VCI1 x 2 VCL - VCI1 - VCI1 VCI1 x 6 VGH VGL - VCI1 x 5 - VCI1 x 4 - VCI1 x 3 - VCI1 x 5 - VCI1 x 4 - VCI1 x 3 - VCI1 x 4 - VCI1 x 3
Notes: 1. Connect capacitors to the capacitor connection pins when generating DDVDH, VGH, VGL and VCL levels. 2. Make sure DDVDH = 6.0V (max.),
ILI9331
D4 DC00 1 D3 0 0 D2 VC2 0 D1 VC1 0 D0 VC0 0

R/W RS W 1 Default D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 0 0 D10 DC12 1 D9 DC11 1 D8 DC10 1 D7 0 0 D6 DC02 1 D5 DC01 1
VC[2:0] Sets the ratio factor of VCI to generate the reference voltages VCI1.
VC2 0 0 0 0 1 1 1 1 VC1 0 0 1 1 0 0 1 1 VC0 0 1 0 1 0 1 0 1 VCI1 voltage 0.95 x VCI 0.90 x VCI 0.85 x VCI 0.80 x VCI 0.75 x VCI 0.70 x VCI Disabled 1.0 x VCI
DC0[2:0]: Selects the operating frequency of the step-up circuit 1. The higher step-up operating frequency enhances the drivability of the step-up circuit and the quality of display but increases the current consumption. Adjust the frequency taking the trade-off between the display quality and the current consumption into account. DC1[2:0]: Selects the operating frequency of the step-up circuit 2. The higher step-up operating frequency enhances the drivability of the step-up circuit and the quality of display but increases the current consumption. Adjust the frequency taking the trade-off between the display quality and the current consumption into account.
DC02 0 0 0 0 1 1 1 1
DC01 0 0 1 1 0 0 1 1
DC00 0 1 0 1 0 1 0 1
Step-up circuit1 step-up frequency (fDCDC1) Fosc Fosc / 2 Fosc / 4 Fosc / 8 Fosc / 16 Fosc / 32 Fosc / 64 Halt step-up circuit 1
DC12 0 0 0 0 1 1 1 1
DC11 0 0 1 1 0 0 1 1
DC10 0 1 0 1 0 1 0 1
Step-up circuit2 step-up frequency (fDCDC2) Fosc / 4 Fosc / 8 Fosc / 16 Fosc / 32 Fosc / 64 Fosc / 128 Fosc / 256 Halt step-up circuit 2
Note: Be sure fDCDC1fDCDC2 when setting DC0[2:0] and DC1[2:0].

R/W RS W 1 Default D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 0 0 D10 0 0 D9 0 0 D8 0 0 D7 VCIRE 0 D6 0 0 D5 0 0 D4 0 0 D3 VRH3 0 D2 VRH2 0 D1 VRH1 0 D0 VRH0 0
VRH[3:0] Set the amplifying rate (1.6 ~ 1.9) of VCI applied to output the VREG1OUT level, which is a reference level for the VCOM level and the grayscale voltage level. VCIRE: Select the external reference voltage VCI or internal reference voltage VCIR.
VCIRE=0 VCIRE =1 External reference voltage VCI (default) Internal reference voltage 2.5V
ILI9331
VREG1OUT Halt 2.5V x 2.00 = 5.000V 2.5V x 2.05 = 5.125V 2.5V x 2.10 = 5.250V 2.5V x 2.20 = 5.500V 2.5V x 2.30 = 5.750V 2.5V x 2.40 = 6.000V 2.5V x 2.40 = 6.000V 2.5V x 1.60 = 4.000V 2.5V x 1.65 = 4.125V 2.5V x 1.70 = 4.250V 2.5V x 1.75 = 4.375V 2.5V x 1.80 = 4.500V 2.5V x 1.85 = 4.625V 2.5V x 1.90 = 4.750V 2.5V x 1.95 = 4.875V
VCIRE =0 VRH3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VRH2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VRH1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VRH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VREG1OUT Halt VCI x 2.00 VCI x 2.05 VCI x 2.10 VCI x 2.20 VCI x 2.30 VCI x 2.40 VCI x 2.40 VCI x 1.60 VCI x 1.65 VCI x 1.70 VCI x 1.75 VCI x 1.80 VCI x 1.85 VCI x 1.90 VCI x 1.95 VRH3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VRH2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
VCIRE =1 VRH1 VRH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
When VCI<2.5V, Internal reference voltage will be same as VCI. Make sure that VC and VRH setting restriction: VREG1OUT (DDVDH - 0.2)V.

R/W RS W 1 Default D15 0 0 D14 0 0 D13 0 0 D12 D11 VDV4 VDV3 0 0 D10 VDV2 0 D9 VDV1 0 D8 VDV0 0 D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0
VDV[4:0] Select the factor of VREG1OUT to set the amplitude of Vcom alternating voltage from 0.70 to 1.24 x VREG1OUT .
VDV4 VDV3 VDV2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 VDV1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VDV0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCOM amplitude VREG1OUT x 0.70 VREG1OUT x 0.72 VREG1OUT x 0.74 VREG1OUT x 0.76 VREG1OUT x 0.78 VREG1OUT x 0.80 VREG1OUT x 0.82 VREG1OUT x 0.84 VREG1OUT x 0.86 VREG1OUT x 0.88 VREG1OUT x 0.90 VREG1OUT x 0.92 VREG1OUT x 0.94 VREG1OUT x 0.96 VREG1OUT x 0.98 VREG1OUT x 1.00 VDV4 VDV3 VDV2 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 VDV1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VDV0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCOM amplitude VREG1OUT x 0.94 VREG1OUT x 0.96 VREG1OUT x 0.98 VREG1OUT x 1.00 VREG1OUT x 1.02 VREG1OUT x 1.04 VREG1OUT x 1.06 VREG1OUT x 1.08 VREG1OUT x 1.10 VREG1OUT x 1.12 VREG1OUT x 1.14 VREG1OUT x 1.16 VREG1OUT x 1.18 VREG1OUT x 1.20 VREG1OUT x 1.22 VREG1OUT x 1.24
Set VDV[4:0] to let Vcom amplitude less than 6V.
ILI9331
D4 AD4 AD12 0 0 D3 AD3 AD11 0 0 D2 AD2 AD10 0 0 D1 AD1 AD9 0 0 D0 AD0 AD8 0 0
8.2.17. GRAM Horizontal/Vertical Address Set (R20h, R21h)

R/W W W RS 1 1 D15 0 0 0 0 D14 0 0 0 0 D13 0 0 0 0 D12 0 0 0 0 D11 0 0 0 0 D10 0 0 0 0 D9 0 0 0 0 D8 0 AD16 0 0 D7 AD7 AD15 0 0 D6 AD6 AD14 0 0 D5 AD5 AD13 0 0
Default
AD[16:0] Set the initial value of address counter (AC). The address counter (AC) is automatically updated in accordance to the setting of the AM, I/D bits as data is written to the internal GRAM. The address counter is not automatically updated when read data from the internal GRAM.
AD[16:0] 17h00000 ~ 17h000EF 17h00100 ~ 17h001EF 17h00200 ~ 17h002EF 17h00300 ~ 17h003EF 17h13D00 ~ 17 h13DEF 17h13E00 ~ 17 h13EEF 17h13F00 ~ 17h13FEF
GRAM Data Map 1 line GRAM Data 2 line GRAM Data 3 line GRAM Data 4 line GRAM Data 318 line GRAM Data 319 line GRAM Data 320 line GRAM Data
th th th th rd nd st
Note1: When the RGB interface is selected (RM = 1), the address AD[16:0] is set to the address counter every frame on the falling edge of VSYNC. .
8.2.18. Write Data to GRAM (R22h)

R/W W RS 1 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 RAM write data (WD[17:0], the DB[17:0] pin assignment differs for each interface. D1 D0
This register is the GRAM access port. When update the display data through this register, the address counter (AC) is increased/decreased automatically.
8.2.19. Read Data from GRAM (R22h)

R/W R RS 1 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 RAM Read Data (RD[17:0], the DB[17:0] pin assignment differs for each interface. D1 D0
RD[17:0] Read 18-bit data from GRAM through the read data register (RDR).
ILI9331
1 8 -bit S ys te m In te rfa c e
G RAM Da ta & RGB Ma pping
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RD 17
RD 16
RD 15
RD 14
RD 13
RD 12
RD 11
RD 10
RD 9
RD 8
RD 7
RD 6
RD 5
RD 4
RD 3
RD 2
RD 1
RD 0
O utput Da ta
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
DB 0
1 6 -bit S ys te m In te rfa c e
RD 17
RD 16
RD 15
RD 14
RD 13
RD 12
RD 11
RD 10
RD 9
RD 8
RD 7
RD 6
RD 5
RD 4
RD 3
RD 2
RD 1
RD 0
O utput Da ta
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
9 -b it S ys te m In te rfa ce
RD 17
RD 16
RD 15
RD 14
RD 13
RD 12
RD 11
RD 10
RD 9
RD 8
RD 7
RD 6
RD 5
RD 4
RD 3
RD 2
RD 1
RD 0
O utput Da ta
DB 17
DB 16
DB 15
DB 14
DB 13
1s t Tra ns fe r
DB 12
DB 11
DB 10
DB 9
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
2nd Tra ns fe r
8 -b it S ys te m In te rfa ce / S e ria l Da ta Tra n s fe r In te rfa c e

RD 17
RD 16
RD 15
RD 14
RD 13
RD 12
RD 11
RD 10
RD 9
RD 8
RD 7
RD 6
RD 5
RD 4
RD 3
RD 2
RD 1
RD 0
O utput Da ta
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
1s t Tra ns fe r
2nd Tra ns fe r
Figure 28 Data Read from GRAM through Read Data Register in 18-/16-/9-/8-bit Interface Mode
ILI9331
S e t I/D AM, HAS /HEA, VS A/VEA
S e t a ddre s s M
Dum m y re a d (inva lid da ta ) G RAM -> R e a d da ta la tch
Re a d O utput (da ta of a ddre s s M) Re a d da ta la tch -> DB[17:0]
R e a d O utput (da ta of a ddre s s M+1) Re a d da ta la tch -> DB[17:0]
S e t a ddre s s N
Dum m y re a d (inva lid da ta ) G RAM -> R e a d da ta la tch
Re a d O utput (da ta of a ddre s s N) Re a d da ta la tch -> DB[17:0]
Figure 29 GRAM Data Read Back Flow Chart
ILI9331

R/W RS W 1 Default D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 0 0 D10 0 0 D9 0 0 D8 0 0 D7 0 0 D6 0 0 D5 D4 D3 D2 D1 D0 VCM5 VCM4 VCM3 VCM2 VCM1 VCM0 0 0 0 0 0 0
VCM[5:0] Set the internal VcomH voltage.

VCM5 VCM4 VCM3 VCM2 VCM1 VCM0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCOMH VREG1OUT x 0.685 VREG1OUT x 0.690 VREG1OUT x 0.695 VREG1OUT x 0.700 VREG1OUT x 0.705 VREG1OUT x 0.710 VREG1OUT x 0.715 VREG1OUT x 0.720 VREG1OUT x 0.725 VREG1OUT x 0.730 VREG1OUT x 0.735 VREG1OUT x 0.740 VREG1OUT x 0.745 VREG1OUT x 0.750 VREG1OUT x 0.755 VREG1OUT x 0.760 VREG1OUT x 0.765 VREG1OUT x 0.770 VREG1OUT x 0.775 VREG1OUT x 0.780 VREG1OUT x 0.785 VREG1OUT x 0.790 VREG1OUT x 0.795 VREG1OUT x 0.800 VREG1OUT x 0.805 VREG1OUT x 0.810 VREG1OUT x 0.815 VREG1OUT x 0.820 VREG1OUT x 0.825 VREG1OUT x 0.830 VREG1OUT x 0.835 VREG1OUT x 0.840 VCM5 VCM4 VCM3 VCM2 VCM1 VCM0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCOMH VREG1OUT x 0.845 VREG1OUT x 0.850 VREG1OUT x 0.855 VREG1OUT x 0.860 VREG1OUT x 0.865 VREG1OUT x 0.870 VREG1OUT x 0.875 VREG1OUT x 0.880 VREG1OUT x 0.885 VREG1OUT x 0.890 VREG1OUT x 0.895 VREG1OUT x 0.900 VREG1OUT x 0.905 VREG1OUT x 0.910 VREG1OUT x 0.915 VREG1OUT x 0.920 VREG1OUT x 0.925 VREG1OUT x 0.930 VREG1OUT x 0.935 VREG1OUT x 0.940 VREG1OUT x 0.945 VREG1OUT x 0.950 VREG1OUT x 0.955 VREG1OUT x 0.960 VREG1OUT x 0.965 VREG1OUT x 0.970 VREG1OUT x 0.975 VREG1OUT x 0.980 VREG1OUT x 0.985 VREG1OUT x 0.990 VREG1OUT x 0.995 VREG1OUT x 1.000
8.2.21. Frame Rate and Color Control (R2Bh)

R/W RS W 1 Default D15 0 0 D14 0 0 D13 0 0 D12 D11 0 0 0 0 D10 0 0 D9 0 0 D8 0 0 D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 D2 D1 D0 FRS3 FRS2 FRS1 FRS0 1 0 1 1
FRS[4:0] Set the frame rate when the internal resistor is used for oscillator circuit.
FRS[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 FRS[3:0] 4h0 4h1 4h2 4h3 4h4 4h5 4h6 4h7 4h8 4h9 4hA 4hB 4hC 4hD 4hE 4hF Frame Rate 30 31 33 35 38 40 43 47 51 56 62 70 80 93 Setting Prohibited Setting Prohibited
ILI9331
8.2.22. Gamma Control (R30h ~ R3Dh)

R/W W W W W W W W W W W RS 1 1 1 1 1 1 1 1 1 1 D15 D14 D13 D12 D11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VRP1[4] VRP1[3] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VRN1[4] VRN1[3] D10 KP1[2] KP3[2] KP5[2] RP1[2] VRP1[2] KN1[2] KN3[2] KN5[2] RN1[2] VRN1[2] D9 KP1[1] KP3[1] KP5[1] RP1[1] VRP1[1] KN1[1] KN3[1] KN5[1] RN1[1] VRN1[1] D8 KP1[0] KP3[0] KP5[0] RP1[0] VRP1[0] KN1[0] KN3[0] KN5[0] RN1[0] VRN1[0] D7 D6 D5 D4 D3 D2 D1 0 0 0 0 0 KP0[2] KP0[1] 0 0 0 0 0 KP2[2] KP2[1] 0 0 0 0 0 KP4[2] KP4[1] 0 0 0 0 0 RP0[2] RP0[1] 0 0 0 0 VRP0[3] VRP0[2] VRP0[1] 0 0 0 0 0 KN0[2] KN0[1] 0 0 0 0 0 KN2[2] KN2[1] 0 0 0 0 0 KN4[2] KN4[1] 0 0 0 0 0 RN0[2] RN0[1] 0 0 0 0 VRN0[3] VRN0[2] VRN0[1] D0 KP0[0] KP2[0] KP4[0] RP0[0] VRP0[0] KN0[0] KN2[0] KN4[0] RN0[0] VRN0[0]
R30h R31h R32h R35h R36h R37h R38h R39h R3Ch R3Dh
KP5-0[2:0] : fine adjustment register for positive polarity RP1-0[2:0] : gradient adjustment register for positive polarity VRP1-0[4:0] : amplitude adjustment register for positive polarity KN5-0[2:0] : fine adjustment register for negative polarity RN1-0[2:0] : gradient adjustment register for negative polarity VRN1-0[4:0] : amplitude adjustment register for negative polarity For details -Correction Function section.
8.2.23. Horizontal and Vertical RAM Address Position (R50h, R51h, R52h, R53h)
R50h R51h R52h R53h R50h R51h R52h R53h R/W W W W W RS 1 1 1 1 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSA8 0 0 0 0 0 0 0 VEA8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D7 HSA7 HEA7 VSA7 VEA7 0 1 0 0 D6 HSA6 HEA6 VSA6 VEA6 0 1 0 0 D5 HSA5 HEA5 VSA5 VEA5 0 1 0 1 D4 HSA4 HEA4 VSA4 VEA4 0 0 0 1 D3 HSA3 HEA3 VSA3 VEA3 0 1 0 1 D2 HSA2 HEA2 VSA2 VEA2 0 1 0 1 D1 HSA1 HEA1 VSA1 VEA1 0 1 0 1 D0 HSA0 HEA0 VSA0 VEA0 0 1 0 1
Default
HSA[7:0]/HEA[7:0] HSA[7:0] and HEA[7:0] represent the respective addresses at the start and end of the window address area in horizontal direction. By setting HSA and HEA bits, it is possible to limit the area on the GRAM horizontally for writing data. The HSA and HEA bits must be set before starting RAM write operation. In setting these bits, be sure 00h HSA[7:0]< HEA[7:0] EFh. and 04hHEA-HAS.
VSA[8:0]/VEA[8:0] VSA[8:0] and VEA[8:0] represent the respective addresses at the start and end of the window address area in vertical direction. By setting VSA and VEA bits, it is possible to limit the area on the GRAM vertically for writing data. The VSA and VEA bits must be set before starting RAM write operation. In setting, be sure 000h VSA[8:0]< VEA[8:0] 13Fh.
ILI9331
HS A
0000h
HEA
VS A Window Addre s s Are a VEA GRAM Addre s s Are a

13FEFh
Figure 30 GRAM Access Range Configuration
00h HSA[7:0] HEA[7:0] EFh 00h VSA[8:0] VEA[8:0] 13Fh

Note1. The window address range must be within the GRAM address space. Note2. Data are written to GRAM in four-words when operating in high speed mode, the dummy write operations should be inserted depending on the window address area. For details, see the High-Speed RAM Write Function section.
ILI9331
8.2.24. Gate Scan Control (R60h, R61h, R6Ah)

R60h R61h R6Ah R60h R61h R6Ah R/W W W W RS 1 1 1 D15 GS 0 0 0 0 0 D14 0 0 0 0 0 0 D13 NL5 0 0 1 0 0 D12 NL4 0 0 0 0 0 D11 NL3 0 0 0 0 0 D10 NL2 0 0 1 0 0 D9 NL1 0 0 1 0 0 D8 NL0 0 VL8 1 0 0 D7 0 0 VL7 0 0 0 D6 D5 D4 D3 D2 D1 D0 0 SCN5 SCN4 SCN3 SCN2 SCN1 SCN0 0 0 0 0 NDL VLE REV VL6 VL5 VL4 VL3 VL2 VL1 VL0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Default
SCN[5:0] The ILI9331 allows to specify the gate line from which the gate driver starts to scan by setting the SCN[5:0] bits.
Scanning Start Position SCN[5:0] GS=0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h ~ 3Fh G1 G9 G17 G25 G33 G41 G49 G57 G65 G73 G81 G89 G97 G105 G113 G121 G129 G137 G145 G153 G161 G169 G177 G185 G193 G201 G209 G217 G225 G233 G241 G249 G257 G265 G273 G281 G289 G297 G305 G313 Setting disabled SM=0 GS=1 G320 G312 G304 G296 G288 G280 G272 G264 G256 G248 G240 G232 G224 G216 G208 G200 G192 G184 G176 G168 G160 G152 G144 G136 G128 G120 G112 G104 G96 G88 G80 G72 G64 G56 G48 G40 G32 G24 G16 G8 Setting disabled GS=0 G1 G17 G33 G49 G65 G81 G97 G113 G129 G145 G161 G177 G193 G209 G2 G18 G34 G50 G66 G82 G98 G114 G130 G146 G162 G178 G194 G114 G130 G146 G162 G178 G194 G210 G226 G242 G258 G274 G290 G306 Setting disabled SM=1 GS=1 G320 G304 G288 G272 G256 G240 G224 G208 G192 G176 G160 G144 G128 G112 G96 G80 G64 G48 G32 G16 G319 G303 G287 G271 G255 G239 G223 G207 G191 G175 G159 G143 G127 G111 G95 G79 G63 G47 G31 G15 Setting disabled
Note: When SM=1, it is a interlacing scanning. Please reference page 72!
ILI9331
NL[5:0]: Sets the number of lines to drive the LCD at an interval of 8 lines. The GRAM address mapping is not affected by the number of lines set by NL[5:0]. The number of lines must be the same or more than the number of lines necessary for the size of the liquid crystal panel.
NL[5:0] 6h00 6h01 6h02 6h1D 6h1E 6h1F 6h20 6h21 6h22 6h23 6h24 6h25 6h26 6h27 Others
LCD Drive Line 8 lines 16 lines 24lines 240 lines 248 lines 256 lines 264 lines 272 lines 280 lines 288 lines 296 lines 304 lines 312 line 320 line Setting inhibited
NDL: Sets the source driver output level in the non-display area.
NDL 0 1 Non-Display Area Positive Polarity V63 V0 Negative Polarity V0 V63
GS: Sets the direction of scan by the gate driver in the range determined by SCN[4:0] and NL[4:0]. The scan direction determined by GS = 0 can be reversed by setting GS = 1. When GS = 0, the scan direction is from G1 to G320. When GS = 1, the scan direction is from G320 to G1 REV: Enables the grayscale inversion of the image by setting REV=1.
Source Output in Display Area Positive polarity negative polarity V0 V63 . . . . . . V63 V0 V63 V0 . . . . . . V0 V63
REV
GRAM Data 18h00000 . . . 18h3FFFF 18h00000 . . . 18h3FFFF
VLE: Vertical scroll display enable bit. When VLE = 1, the ILI9331 starts displaying the base image from the line (of the physical display) determined by VL[8:0] bits. VL[8:0] sets the amount of scrolling, which is the The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9331
number of lines to shift the start line of the display from the first line of the physical display. Note that the partial image display position is not affected by the base image scrolling. The vertical scrolling is not available in external display interface operation. In this case, make sure to set VLE = 0.
VLE 0 1 Base Image Display Fixed Enable Scrolling
VL[8:0]: Sets the scrolling amount of base image. The base image is scrolled in vertical direction and displayed from the line determined by VL[8:0]. Make sure that VL[8:0] 320.
8.2.25. Partial Image 1 Display Position (R80h)

R/W W Default RS 1 D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 0 0 D10 0 0 D9 0 0 D8 PTD P0[8] 0 D7 PTD P0[7] 0 D6 PTD P0[6] 0 D5 PTD P0[5] 0 D4 PTD P0[4] 0 D3 PTD P0[3] 0 D2 PTD P0[2] 0 D1 PTD P0[1] 0 D0 PTD P0[0] 0
PTDP0[8:0]: Sets the display start position of partial image 1. The display areas of the partial images 1 and 2 must not overlap each another.
8.2.26. Partial Image 1 RAM Start/End Address (R81h, R82h)

R/W W W Default RS 1 1 D15 0 0 0 0 D14 0 0 0 0 D13 0 0 0 0 D12 0 0 0 0 D11 0 0 0 0 D10 0 0 0 0 D9 0 0 0 0 D8 PTS A0[8] PTE A0[8] 0 0 D7 PTS A0[7] PTE A0[7] 0 0 D6 PTS A0[6] PTE A0[6] 0 0 D5 PTS A0[5] PTE A0[5] 0 0 D4 PTS A0[4] PTE A0[4] 0 0 D3 PTS A0[3] PTE A0[3] 0 0 D2 PTS A0[2] PTE A0[2] 0 0 D1 PTS A0[1] PTE A0[1] 0 0 D0 PTS A0[0] PTE A0[0] 0 0
PTSA0[8:0] PTEA0[8:0]: Sets the start line address and the end line address of the RAM area storing the data of partial image 1. Make sure PTSA0[8:0] PTEA0[8:0].
8.2.27. Partial Image 2 Display Position (R83h)

R/W W Default RS 1 D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 0 0 D10 0 0 D9 0 0 D8 D7 PTD PTD P1[8] P1[7] 0 0 D6 PTD P1[6] 0 D5 PTD P1[5] 0 D4 PTD P1[4] 0 D3 PTD P1[3] 0 D2 PTD P1[2] 0 D1 PTD P1[1] 0 D0 PTD P1[0] 0
PTDP1[8:0]: Sets the display start position of partial image 2 The display areas of the partial images 1 and 2 must not overlap each another.
8.2.28. Partial Image 2 RAM Start/End Address (R84h, R85h)

R/W W W Default RS 1 1 D15 0 0 0 0 D14 0 0 0 0 D13 0 0 0 0 D12 0 0 0 0 D11 0 0 0 0 D10 0 0 0 0 D9 0 0 0 0 D8 PTS A1[8] PTE A1[8] 0 0 D7 PTS A1[7] PTE A1[7] 0 0 D6 PTS A1[6] PTE A1[6] 0 0 D5 PTS A1[5] PTE A1[5] 0 0 D4 PTS A1[4] PTE A1[4] 0 0 D3 PTS A1[3] PTE A1[3] 0 0 D2 PTS A1[2] PTE A1[2] 0 0 D1 PTS A1[1] PTE A1[1] 0 0 D0 PTS A1[0] PTE A1[0] 0 0
PTSA1[8:0] PTEA1[8:0]: Sets the start line address and the end line address of the RAM area storing the data of partial image 2 Make sure PTSA1[8:0] PTEA1[8:0]. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9331
D3 RTNI3 0 D2 RTNI2 0 D1 RTNI1 0 D0 RTNI0 0
8.2.29. Panel Interface Control 1 (R90h)

R/W RS W 1 Default D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 0 0 D10 0 0 D9 DIVI1 0 D8 DIVI0 0 D7 0 0 D6 0 0 D5 0 0 D4 RTNI4 1
RTNI[4:0]: Sets 1H (line) clock number of internal clock operating mode. In this mode, ILI9331 display operation is synchronized with internal clock signal.
RTNI[4:0] 00000~01111 10000 10001 10010 10011 10100 10101 10110 10111 Clocks/Line Setting Disabled 16 clocks 17 clocks 18 clocks 19 clocks 20 clocks 21 clocks 22 clocks 23 clocks RTNI[4:0] 11000 11001 11010 11011 11100 11101 11110 11111 Clocks/Line 24 clocks 25 clocks 26 clocks 27 clocks 28 clocks 29 clocks 30 clocks 31 clocks
DIVI[1:0]: Sets the division ratio of internal clock frequency.

DIVI1 0 0 1 1 DIVI0 0 1 0 1 Division Ratio 1 2 4 8 Internal Operation Clock Frequency fosc / 1 fosc / 2 fosc / 4 fosc / 8

R/W RS W 1 Default D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 0 0 D10 D9 D8 NOWI[2] NOWI[1] NOWI[0] 1 1 0 D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0
NOWI[2:0]: Sets the gate output non-overlap period when ILI9331 display operation is synchronized with internal clock signal.
NOWI[2:0] 000 001 010 011 100 101 110 111 Gate Non-overlap Period 0 clocks 1 clocks 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks
Note: The gate output non-overlap period is defined by the number of frequency-divided internal clocks, the frequency of which is determined by instruction (DIVI), from the reference point.

R/W RS W 1 Default D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 0 0 D10 0 0 D9 D8 DIVE1 DIVE0 1 0 D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0
DIVE[1:0]: Sets the division ratio of DOTCLK when ILI9331 display operation is synchronized with RGB interface signals.
DIVE[1:0] 00 01 10 11 Division Ratio Setting Prohibited 1/4 1/8 1/16 18/16-bit RGB Interface Setting Prohibited 4 8 16 DOTCLKS DOTCLKS DOTCLKS DOTCLK=5MHz 0.8 s 1.6 s 3.2 s 6-bit x 3 Transfers RGB Interface Setting Prohibited 12 24 48 DOTCLKS DOTCLKS DOTCLKS
ILI9331
DOTCLK=5MHz 0.8 s 1.6 s 3.2 s

R/W RS W 1 Default D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 D10 D9 D8 NOWE3 NOWE2 NOWE1 NOWE0 1 1 0 0 D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0
NOWE[3:0]: Sets the gate output non-overlap period when the ILI9331 display operation is synchronized with RGB interface signals.
NOWE[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 Gate Non-overlap Period 0 clocks 1 clocks 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks NOWE[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 Gate Non-overlap Period 8 clocks 9 clocks 10 clocks 11 clocks 12 clocks 13 clocks 14 clocks 15 clocks
Note: 1 clock = (number of data transfer/pixel) x DIVE (division ratio) [DOTCLK]
8.2.33. OTP VCM Programming Control (RA1h)

R/W W RS 1 D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 OTP_ PGM_EN 0 D10 0 0 D9 0 0 D8 0 0 D7 0 0 D6 0 0 D5 VCM_ OTP5 0 D4 VCM_ OTP4 0 D3 VCM_ OTP3 0 D2 VCM_ OTP2 0 D1 VCM_ OTP1 0 D0 VCM_ OTP0 0
Default
OTP_PGM_EN: OTP programming enable. When program OTP, must set this bit. OTP data can be programmed 3 times. VCM_OTP[5:0]: OTP programming data for VCOMH voltage, the voltage refer to VCM[5:0] value.
8.2.34. OTP VCM Status and Enable (RA2h)

R/W W RS 1 D15 PGM_ CNT1 0 D14 PGM_ CNT0 0 D13 VCM_ D5 0 D12 VCM_ D4 0 D11 VCM_ D3 0 D10 VCM_ D2 0 D9 VCM_ D1 0 D8 VCM_ D0 0 D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 VCM_ EN 0
Default
PGM_CNT[1:0]: OTP programmed record. These bits are read only.

OTP_PGM_CNT[1:0] 00 01 10 11 Description OTP clean OTP programmed 1 time OTP programmed 2 times OTP programmed 3 times
VCM_D[5:0]: OTP VCM data read value. These bits are read only. VCM_EN: OTP VCM data enable. 1: Set this bit to enable OTP VCM data to replace R29h VCM value. 0: Default value, use R29h VCM value.
ILI9331
D4 KEY 4 0 D3 KEY 3 0 D2 KEY 2 0 D1 KEY 1 0 D0 KEY 0 0
8.2.35. OTP Programming ID Key (RA5h)

R/W W RS 1 D15 KEY 15 0 D14 KEY 14 0 D13 KEY 13 0 D12 KEY 12 0 D11 KEY 11 0 D10 KEY 10 0 D9 KEY 9 0 D8 KEY 8 0 D7 KEY 7 0 D6 KEY 6 0 D5 KEY 5 0
Default
KEY[15:0]: OTP Programming ID key protection. Before writing OTP programming data RA1h, it must write RA5h with 0xAA55 value first to make OTP programming successfully. If RA5h is not written with 0xAA55, OTP programming will be fail. See OTP Programming flow.
8.2.36. Write Display Brightness Value (RB1h)

R/W W RS 1 D15 X D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 DBV7 D6 DBV6 D5 DBV5 D4 DBV4 D3 DBV3 D2 DBV2 D1 DBV1 D0 DBV0
Description This command is used to adjust the brightness value of the display. DBV[7:0]: 8 bit, for display brightness of manual brightness setting and CABC in ILI9331. There is a PWM output signal, LEDPWM pin, to control the LED driver IC in order to control display brightness.
8.2.37. Read Display Brightness Value (RB2h)

R/W R RS 1 D15 X D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 DBV7 D6 DBV6 D5 DBV5 D4 DBV4 D3 DBV3 D2 DBV2 D1 DBV1 D0 DBV0
Description This command is used to return the brightness value of the display. DBV[7:0] is reset when display is in sleep-in mode. DBV[7:0] is 0 when bit BCTRL of Write CTRL Display (B3h) command is 0. DBV[7:0] is manual set brightness specified with Write CTRL Display (B3h) command when BCTRL bit is 1. When bit BCTRL of Write CTRL Display (B3h) command is 1 and C1/C0 bit of Write Content Adaptive Brightness Control (B5h) command are 0, DBV[7:0] output is the brightness value specified with Write Display Brightness (B1h) command. Restriction ILI9331 is sending 2nd parameter value on the data lines if the MCU wants to read more than one parameter (= more than 2 RDX cycle) on parallel MCU interface. Only 2nd parameter is sent on DSI (The 1st parameter is not sent).
8.2.38. Write CTRL Display Value (RB3h)

R/W w RS 1 D15 X D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 X D6 X D5 BCTRL D4 X D3 DD D2 BL D1 X D0 X
Description This command is used to control display brightness. BCTRL: Brightness Control Block On/Off, This bit is always used to switch brightness for display.
BCTRL 0 1 Description Brightness Control Block OFF (DBV[7:0]=00h) Brightness Control Block ON (DBV[7:0] is active)
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color DD: Display Dimming Control. This function is only for manual brightness setting.
DD 0 1 Description Display Dimming OFF Display Dimming ON
ILI9331
BL: Backlight Control On/Off

BL 0 1 Description Backlight Control OFF Backlight Control ON
Dimming function is adapted to the brightness registers for display when bit BCTRL is changed at DD=1, e.g. BCTRL: 0 -> 1 or 1-> 0. When BL bit change from On to Off, backlight is turned off without gradual dimming, even if dimming-on (DD=1) are selected X: dont care
8.2.39. Read CTRL Display Value (RB4h)

R/W R RS 1 D15 X D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 X D6 X D5 BCTRL D4 X D3 DD D2 BL D1 X D0 X
Description This command is used to control display brightness. BCTRL: Brightness Control Block On/Off, This bit is always used to switch brightness for display.
BCTRL 0 1 Description Brightness Control Block OFF (DBV[7:0]=00h) Brightness Control Block ON (DBV[7:0] is active)
DD: Display Dimming Control. This function is only for manual brightness setting.
DD 0 1 Description Display Dimming OFF Display Dimming ON
BL: Backlight Control On/Off

BL 0 1 Description Backlight Control OFF Backlight Control ON
X = Dont care
8.2.40. Write Content Adaptive Brightness Control Value (RB5h)

R/W W RS 1 D15 X D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 X D6 X D5 X D4 X D3 X D2 X D1 D0 C[1:0]
Description This command is used to set parameters for image content based adaptive brightness control functionality. There is possible to use 4 different modes for content adaptive image functionality, which are defined on a table below.
C[1:0] 0 0 1 1 0 1 0 1 CABC OFF User Interface Image Still Picture Moving Image Description
X = Dont care The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9331
D4 X D3 X D2 X D1 D0 C[1:0]
8.2.41. Read Content Adaptive Brightness Control Value (RB6h)

R/W R RS 1 D15 X D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 X D6 X D5 X
Description This command is used to set parameters for image content based adaptive brightness control functionality. There is possible to use 4 different modes for content adaptive image functionality, which are defined on a table below.
C[1:0] 0 0 1 1 0 1 0 1 CABC OFF User Interface Image Still Picture Moving Image Description
X = Dont care
8.2.42. Write CABC Minimum Brightness (RBEh)

R/W W RS 1 D15 X D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 D6 D5 D4 D3 CMB[7:0] D2 D1 D0
Description This command is used to set the minimum brightness value of the display for CABC function. CMB[7:0]: CABC minimum brightness control, this parameter is used to avoid too much brightness reduction. When CABC is active, CABC can not reduce the display brightness to less than CABC minimum brightness setting. Image processing function is worked as normal, even if the brightness can not be changed. This function does not affect to the other function, manual brightness setting. Manual brightness can be set the display brightness to less than CABC minimum brightness. Smooth transition and dimming function can be worked as normal. When display brightness is turned off (BCTRL=0 of Write CTRL Display (B3h)), CABC minimum brightness setting is ignored. In principle relationship is that 00h value means the lowest brightness for CABC and FFh value means the highest brightness for CABC.
ILI9331
D4 D3 CMB[7:0] D2 D1 D0
8.2.43. Read CABC Minimum Brightness (RBFh)

R/W R RS 1 D15 X D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 D6 D5
Description This command is used to set the minimum brightness value of the display for CABC function. CMB[7:0]: CABC minimum brightness control, this parameter is used to avoid too much brightness reduction. When CABC is active, CABC can not reduce the display brightness to less than CABC minimum brightness setting. Image processing function is worked as normal, even if the brightness can not be changed. This function does not affect to the other function, manual brightness setting. Manual brightness can be set the display brightness to less than CABC minimum brightness. Smooth transition and dimming function can be worked as normal. When display brightness is turned off (BCTRL=0 of Write CTRL Display (B3h)), CABC minimum brightness setting is ignored. In principle relationship is that 00h value means the lowest brightness for CABC and FFh value means the highest brightness for CABC. Restriction ILI9331 is sending 2nd parameter value on the data lines if the MCU wants to read more than one parameter (= more than 2 RDX cycle) on parallel MCU interface. Only 2nd parameter is sent on DSI (The 1st parameter is not sent).
8.2.44. CABC Control 1 (RC8h)

R/W W RS 1 D15 X D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 D6 D5 D4 D3 D2 PWM_DIV[7:0] D1 D0
Description PWM_DIV[7:0]: PWM_OUT output period control. This command is used to adjust the PWM waveform period of PWM_OUT. The PWM period can be calculated using the equation in the following.
f PWM_OUT =
5.8MHz (PWM_DIV[7 : 0] + 1) 255
PWM_DIV[7:0] D7 0 0 0 0 0 D6 0 0 0 0 0 D5 0 0 0 0 0 D4 0 0 0 0 0 : : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 D3 0 0 0 0 0 D2 0 0 0 0 1 D1 0 0 1 1 0 D0 0 1 0 1 0 fPWM_OUT 22.74 KHz 11.37 KHz 7.58KHz 5.68 KHz 4.54 KHz : : 90.26 Hz 89.9Hz 89.53Hz 89.17 Hz 88.81 Hz
ILI9331
Note : The output frequency tolerance of internal frequency divider in CABC is 10% Restriction EXTC should be high to enable this command
ILI9331
D4 D3 D2 D1 D0 THRES_STILL[3:0]
8.2.45. CABC Control 2 (RC9h)

R/W W RS 1 D15 X D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 D6 D5 THRES_MOV[3:0]
Description THRES_MOV[3:0]: This parameter is used to set the ratio (percentage) of the maximum number of pixels that makes display image white (data=63) to the total of pixels by image process in MOVING image mode. After this parameter sets the number of pixels that makes display image white, threshold grayscale value (DTH) that makes display image white is set so that the number of the pixels set by this parameter does not change.
THRES_MOV[3:0] D3 0 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Description 99 % 98 % 96 % 94 % 92 % 90 % 88 % 86 % THRES_MOV[3:0] D3 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Description 84 % 82 % 80 % 78 % 76 % 74 % 72 % 70 %
THRES_STILL[3:0]: This parameter is used to set the ratio (percentage) of the maximum number of pixels that makes display image white (data=63) to the total of pixels by image process in STILL mode. After this parameter sets the number of pixels that makes display image white, threshold grayscale value (DTH) that makes display image white is set so that the number of the pixels set by this parameter does not change.
THRES_STILLI[3:0] D3 0 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Description 99 % 98 % 96 % 94 % 92 % 90 % 88 % 86 % THRES_STILL[3:0] D3 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Description 84 % 82 % 80 % 78 % 76 % 74 % 72 % 70 %
Restriction EXTC should be high to enable this command The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9331
D4 0 D3 D2 D1 D0 THRES_UI[3:0]
8.2.46. CABC Control 3 (RCAh)

R/W W RS 1 D15 X D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 0 D6 0 D5 0
Description THRES_UI[3:0]: This parameter is used to set the ratio (percentage) of the maximum number of pixels that makes display image white (data=63) to the total of pixels by image process in USER INTERFACE mode. After this parameter sets the number of pixels that makes display image white, threshold grayscale value (DTH) that makes display image white is set so that the number of the pixels set by this parameter does not change.
THRES_UI[3:0] D3 0 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Description 99 % 98 % 96 % 94 % 92 % 90 % 88 % 86 % THRES_UI[3:0] D3 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Description 84 % 82 % 80 % 78 % 76 % 74 % 72 % 70 %
Restriction EXTC should be high to enable this command
ILI9331
D3 D2 D1 D0 DTH_STILL[3:0]
8.2.47. CABC Control 4 (RCBh)

R/W W RS 1 D15 X D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 D6 D5 D4 DTH_MOV[3:0]
Description DTH_MOV[3:0]: This parameter is used set the minimum limitation of grayscale threshold value in MOVING image mode.
DTH_MOV[3:0] D3 0 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Description 224 220 216 212 208 204 200 196 DTH_MOV[3:0] D3 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Description 192 188 184 180 176 172 168 164
DTH_STILL[3:0]: This parameter is used to set the minimum limitation of grayscale threshold value in STILL image mode.
DTH_STILLI[3:0] D3 0 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Description 224 220 216 212 208 204 200 196 DTH_STILL[3:0] D3 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Description 192 188 184 180 176 172 168 164
ILI9331
D4 0 D3 D2 D1 DTH_UI[3:0] D0
8.2.48. CABC Control 5 (RCCh)

R/W W RS 1 D15 X D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 0 D6 0 D5 0
Description DTH_UI[3:0]: This parameter is used set the minimum limitation of grayscale threshold value in USER INTERFACE mode.
DTH_UI[3:0] D3 0 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Description 252 248 244 240 236 232 228 224 DTH_UI[3:0] D3 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Description 220 216 212 208 2-4 200 196 192
ILI9331
D3 0 D2 D1 D0 DIM_OPT1[2:0]
8.2.49. CABC Control 6 (RCDh)

R/W W RS 1 D15 X D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 D6 D5 D4 DIM_OPT2[3:0]
Description DIM_OPT1[2:0]: This parameter is used set the transition time of brightness level change to avoid the sharp brightness change on vision.
DIM_OPT1[2:0] D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Description 1 frame 1 frame 2 frames 4 frames 8 frames 16 frames 32 frames 64 frames
DIM_OPT2[3:0]: This parameter is used to set the imitation of minimum brightness change. If this parameter is large than the difference between target brightness and current brightness, then the brightness will not change. Restriction EXTC should be high to enable this command
ILI9331
D0 SCD_VLINE[8]
8.2.50. CABC Control 7 (RCEh)

R/W W W RS 1 1 D15 X X D14 X X D13 X X D12 X X D11 X X D10 X X D9 X X D8 X X D7 X D6 X D5 X D4 D3 D2 D1 SCD_VLINE[7:0] X X X X
Description SCD_VLINE[8:0]: This parameter is used set the display line per frame while partial mode ON.
SCD_VLINE[8:0] D8 0 0 0 0 0 D7 0 0 0 0 0 D6 0 0 0 0 0 D5 0 0 0 0 0 D4 0 0 0 0 0 : : 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 0 Others 1 1 1 0 1 1 1 0 0 1 1 0 1 0 1 0 D3 0 0 0 0 0 D2 0 0 0 0 1 D1 0 0 1 1 0 D0 0 1 0 1 0 Display line 0 line 1 line 2 lines 3 lines 4 lines : : 317 lines 318 lines 319lines 320 lines Setting prohibited
ILI9331
9. OTP Programming Flow
ILI9331
10. GRAM Address Map & Read/Write

ILI9331 has an internal graphics RAM (GRAM) of 172,800 bytes to store the display data and one pixel is constructed of 18 bits. The GRAM can be accessed through the i80 system, SPI and RGB interfaces.
i80 18-/16-bit S ys te m Bus Inte rfa ce Timing
(a ) Write to G R AM
Write 0022 h to inde x re gis te r Write G RAM ta da Nth pixe l Write G R AM ta da (N+1 )th pixe l Write G R AM ta da (N+2 )th pixe l Write GR AM ta da (N+3)th pixe l
(b) R e a d from G R AM
Write 0022 h to inde x re gis te r Du m m y Re a d 1s t R e a d ta da Nth pixe l 2 nd R e a d ta da (N+1)th pixe l 3rd R e a d ta da (N+2 )th pixe l
i80 9-/8-bit S ys te m Bus Inte rfa ce Timing
(a ) Write to G R AM
00h 22h 1s t write high byte 1s t write low byte 2nd write high byte 2nd write low byte 3 rd write high byte 3 rd write low byte
Nth pixe l
(N+1)th pixe l
(N+2)th pixe l
(b) R e a d from G R AM
00h 22h Dum m y Re a d 1 Du m m y Re a d 2 1 s t re a d high byte 1s t re a d low byte 2nd re a d high byte 2nd re a d low byte
Nth pixe l
(N+1)th pixe l
Figure31 GRAM Read/Write Timing of i80-System Interface The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color GRAM address map table of SS=0, BGR=0
SS=0, BGR=0 GS=0 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 . . . G311 G312 G313 G314 G315 G316 G317 G318 G319 G320 GS=1 G320 G319 G318 G317 G316 G315 G314 G313 G312 G311 . . . G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 S1S3 DB170 00000h 00100h 00200h 00300h 00400h 00500h 00600h 00700h 00800h 00900h . . . 13600h 13700h 13800h 13900h 13A00h 13B00h 13C00h 13D00h 13E00h 13F00h S4S6 DB170 00001h 00101h 00201h 00301h 00401h 00501h 00601h 00701h 00801h 00901h . . . 13601h 13701h 13801h 13901h 13A01h 13B01h 13C01h 13D01h 13E01h 13F01h S7S9 DB170 00002h 00102h 00202h 00302h 00402h 00502h 00602h 00702h 00802h 00902h . . . 13602h 13702h 13802h 13902h 13A02h 13B02h 13C02h 13D02h 13E02h 13F02h S10S12 DB170 00003h 00103h 00203h 00303h 00403h 00503h 00603h 00703h 00803h 00903h . . . 13603h 13703h 13803h 13903h 13A03h 13B03h 13C03h 13D03h 13E03h 13F03h S517S519 DB170 000ECh 001ECh 002ECh 003ECh 004ECh 005ECh 006ECh 007ECh 008ECh 009ECh . . . 136ECh 137ECh 138ECh 139ECh 13AECh 13BECh 13CECh 13DECh 13EECh 13FECh S520S522 DB170 000EDh 001EDh 002EDh 003EDh 004EDh 005EDh 006EDh 007EDh 008EDh 009EDh . . . 136EDh 137EDh 138EDh 139EDh 13AEDh 13BEDh 13CEDh 13DEDh 13EEDh 13FEDh
ILI9331
S523S525 DB170 000EEh 001EEh 002EEh 003EEh 004EEh 005EEh 006EEh 007EEh 008EEh 009EEh . . . 136EEh 137EEh 138EEh 139EEh 13AEEh 13BEEh 13CEEh 13DEEh 13EEEh 13FEEh S526S720 DB170 000EFh 001EFh 002EFh 003EFh 004EFh 005EFh 006EFh 007EFh 008EFh 009EFh . . . 136EFh 137EFh 138EFh 139EFh 13AEFh 13BEFh 13CEFh 13DEFh 13EEFh 13FEFh
ILI9331
GRAM Data
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
DB 0
RGB Assignment Source Output Pin
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (3n+1)
S (3n+2)
S (3n+3)
N=0 to 239
GRAM Data
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (3n+1)
S (3n+2)
S (3n+3)
N=0 to 239
1st Transfer GRAM Data

DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 17 DB 16 DB 15
2nd Transfer
DB 14 DB 13 DB 12 DB 11 DB 10 DB 9
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (3n+1)
S (3n+2)
S (3n+3)
N=0 to 239
GRAM Data and display data of 18-/16-/9-bit system interface (SS=0", BGR=0")
Figure32 i80-System Interface with 18-/16-/9-bit Data Bus (SS=0, BGR=0)
ILI9331
Figure33 i80-System Interface with 8-bit Data Bus (SS=0, BGR=0)
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color GRAM address map table of SS=1, BGR=1
SS=1, BGR=1 GS=0 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 . . . G311 G312 G313 G314 G315 G316 G317 G318 G319 G320 GS=1 G320 G319 G318 G317 G316 G315 G314 G313 G312 G311 . . . G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 S720S718 DB170 00000h 00100h 00200h 00300h 00400h 00500h 00600h 00700h 00800h 00900h . . . 13600h 13700h 13800h 13900h 13A00h 13B00h 13C00h 13D00h 13E00h 13F00h S717S715 DB170 00001h 00101h 00201h 00301h 00401h 00501h 00601h 00701h 00801h 00901h . . . 13601h 13701h 13801h 13901h 13A01h 13B01h 13C01h 13D01h 13E01h 13F01h S714S712 DB170 00002h 00102h 00202h 00302h 00402h 00502h 00602h 00702h 00802h 00902h . . . 13602h 13702h 13802h 13902h 13A02h 13B02h 13C02h 13D02h 13E02h 13F02h S711S709 DB170 00003h 00103h 00203h 00303h 00403h 00503h 00603h 00703h 00803h 00903h . . . 13603h 13703h 13803h 13903h 13A03h 13B03h 13C03h 13D03h 13E03h 13F03h S12S10 DB170 000ECh 001ECh 002ECh 003ECh 004ECh 005ECh 006ECh 007ECh 008ECh 009ECh . . . 136ECh 137ECh 138ECh 139ECh 13AECh 13BECh 13CECh 13DECh 13EECh 13FECh S9S7 DB170 000EDh 001EDh 002EDh 003EDh 004EDh 005EDh 006EDh 007EDh 008EDh 009EDh . . . 136EDh 137EDh 138EDh 139EDh 13AEDh 13BEDh 13CEDh 13DEDh 13EEDh 13FEDh
ILI9331
S6S4 DB170 000EEh 001EEh 002EEh 003EEh 004EEh 005EEh 006EEh 007EEh 008EEh 009EEh . . . 136EEh 137EEh 138EEh 139EEh 13AEEh 13BEEh 13CEEh 13DEEh 13EEEh 13FEEh S3S1 DB170 000EFh 001EFh 002EFh 003EFh 004EFh 005EFh 006EFh 007EFh 008EFh 009EFh . . . 136EFh 137EFh 138EFh 139EFh 13AEFh 13BEFh 13CEFh 13DEFh 13EEFh 13FEFh
Figure 34 i80-System Interface with 18-/9-bit Data Bus (SS=1, BGR=1)
ILI9331
11. Window Address Function

The window address function enables writing display data consecutively in a rectangular area (a window address area) made on the internal RAM. The window address area is made by setting the horizontal address register (start: HSA[7:0], end: HEA[7:0] bits) and the vertical address register (start: VSA[8:0], end: VEA[8:0] bits). The AM bit sets the transition direction of RAM address (either increment or decrement). These bits enable the ILI9331 to write data including image data consecutively not taking data wrap positions into account. The window address area must be made within the GRAM address map area. Also, the GRAM address bits (RAM address set register) must be an address within the window address area. [Window address setting area] (Horizontal direction) 00H HSA[7:0] HEA[7:0] EFH (Vertical direction) 00H VSA[8:0] VEA[8:0] 13FH [RAM address, AD (an address within a window address area)]] (RAM address) HSA[7:0] AD[7:0] HEA[7:0] VSA[8:0] AD[15:8] VEA[8:0]
Figure 35 GRAM Access Window Map
ILI9331
12. Gamma Correction

ILI9331 incorporates the -correction function to display 262,144 colors for the LCD panel. The -correction is performed with 3 groups of registers determining eight reference grayscale levels, which are gradient adjustment, amplitude adjustment and fine-adjustment registers for positive and negative polarities, to make ILI9331 available with liquid crystal panels of various characteristics.
Gra die nt Adjus tme nt Re gis te r

VREG1OUT
P R P /N0 P RP /N1
Fine Adjus tm e nt Re gis te rs (6 x 3 bits )

P KP /N5 P KP /N4 P KP /N3 P KP /N2 P KP /N1 P KP /N0
Am plitude Adjus tme nt Re gis te r

VRP /N0 VRP /N1
VgP 0/VgN0
V0
8 to 1 s e le ction
VgP 1/VgN1
V1 V2 ...
8 to 1 s e le ction
VgP 8/VgN8 ... VgP 20/VgN20 ... VgP 43/VgN43 ... VgP 55/VgN55
V7 V8
8 to 1 s e le ction
V20
8 to 1 s e le ction
V43
8 to 1 s e le ction
V55 V56 ...
8 to 1 s e le ction
VgP 62/VgN62
V61 V62
VgP 63/VgN63
V63
VGS
Figure 36 Grayscale Voltage Generation
VREG1OUT
VROP0 0 ~ 30R 5R
RP0 RP1 RP2 RP3 RP4 RP5 RP6 RP7
ILI9331
VgN0 VRN0[3:0] KN0[2:0] VN1 VN2 VN3 VN4 VN5 VN6 VN7 VN8 PRN0[2:0]
VgP0 VRP0[3:0] KP0[2:0] VP1 VP2 VP3 VP4 VP5 VP6 VP7 VP8 PRP0[2:0]
RP8 RP9 RP10 RP11 RP12 RP13 RP14 RP15
1uF/10V
VRON0 0 ~ 30R 5R
RN0 RN1 RN2 RN3 RN4 RN5 RN6 RN7
8 to 1 Selection
4Rx7=28R
VgP1
8 to 1 Selection
4Rx7=28R
VgN1
VRCP0 0 ~ 28R
KP1[2:0]
VRCP0 0 ~ 28R
RN8 RN9 RN10 RN11 RN12 RN13 RN14 RN15
KN1[2:0]
Rx7=7R
VP9 VP10 VP11 VP12 VP13 VP14 VP15 VP16
VgP8
Rx7=7R
VN9 VN10 VN11 VN12 VN13 VN14 VN15 VN16
8 to 1 Selection
8 to 1 Selection
VgN8
KP2[2:0] VP17 VP18 VP19 VP20 VP21 VP22 VP23 VP24
KN2[2:0] VN17 VN18 VN19 VN20 VN21 VN22 VN23 VN24
8 to 1 Selection
Rx7=7R
VgP20
Rx7=7R
8 to 1 Selection
RP16 RP17 RP18 RP19 RP20 RP21 RP22 RP23 RP24 RP25 RP26 RP27 RP28 RP29 RP30 RP31
RN16 RN17 RN18 RN19 RN20 RN21 RN22 RN23 RN24 RN25 RN26 RN27 RN28 RN29 RN30 RN31
VgN20
KP3[2:0] VP25 VP26 VP27 VP28 VP29 VP30 VP31 VP32
KN3[2:0] VN25 VN26 VN27 VN28 VN29 VN30 VN31 VN32
8 to 1 Selection
Rx7=7R
VgP43
8 to 1 Selection
Rx7=7R
VgN43
KP4[2:0] VP33 VP34 VP35 VP36 VP37 VP38 VP39 VP40 PRP1[2:0]
KN4[2:0] VN33 VN34 VN35 VN36 VN37 VN38 VN39 VN40 PRN1[2:0]
8 to 1 Selection
Rx7=7R
VgP55
Rx7=7R
8 to 1 Selection
RP32 RP33 RP34 RP35 RP36 RP37 RP38
RN32 RN33 RN34 RN35 RN36 RN37 RN38
VgN55
VRCP1 0 ~ 28R
RP39 RP40 RP41 RP42 RP43 RP44 RP45
KP5[2:0]
VRCN1 0 ~ 28R
RN39 RN40 RN41 RN42 RN43 RN44 RN45
KN5[2:0]
4Rx7=28R
VP41 VP42 VP43 VP44 VP45 VP46 VP47 VP48
VgP62
4Rx7=28R
VN41 VN42 VN43 VN44 VN45 VN46 VN47 VN48
8 to 1 Selection
8 to 1 Selection
VgN62
5R VROP1 0 ~ 31R 8R
RP46
VP49
5R VgP63 VRON1 0 ~ 31R 8R
RN46
VN49
VgN63
VRP1[4:0]
RP47
VRN1[4:0]
RN47
VGS
Figure 37 Grayscale Voltage Adjustment
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 1. Gradient adjustment registers
ILI9331
The gradient adjustment registers are used to adjust the gradient of the curve representing the relationship between the grayscale and the grayscale reference voltage level. To adjust the gradient, the resistance values of variable resistors in the middle of the ladder resistor are adjusted by registers PRP0[2:0]/PRN0[2:0], PRP1[2:0]/PRN1[2:0]. The registers consist of positive and negative polarity registers, allowing asymmetric drive. 2. Amplitude adjustment registers The amplitude adjustment registers, VRP0[3:0]/VRN0[3:0], VRP1[4:0]/VRN1[4:0], are used to adjust the amplitude of grayscale voltages. To adjust the amplitude, the resistance values of variable resistors at the top and bottom of the ladder resistor are adjusted. Same as the gradient registers, the amplitude adjustment registers consist of positive and negative polarity registers. 3. Fine adjustment registers The fine adjustment registers are used to fine-adjust grayscale voltage levels. To fine-adjust grayscale voltage levels, fine adjustment registers adjust the reference voltage levels, 8 levels for each register generated from the ladder resistor, in respective 8-to-1 selectors. Same with other registers, the fine adjustment registers consist of positive and negative polarity registers.
G ra ys ca le vo lta ge
G ra ys ca le volta g e
G ra die nt a djus tme nt
Amplitude a djus tm e nt
G ra ys ca le volta g e
Fine a djus tm e nt
Figure 38 Gamma Curve Adjustment
Register Groups Gradient adjustment Amplitude adjustment
Positive Polarity PRP0 [2:0] PRP1 [2:0] VRP0 [3:0] VRP1 [4:0] KP0 [2:0] KP1 [2:0] KP2 [2:0] KP3 [2:0] KP4 [2:0] KP5 [2:0]
Negative Polarity PRN0 [2:0] PRN1 [2:0] VRN0 [3:0] VRN1 [4:0] KN0 [2:0] KN1 [2:0] KN2 [2:0] KN3 [2:0] KN4 [2:0] KN5 [2:0]
Description Variable resistor VRCP0, VRCN0 Variable resistor VRCP1, VRCN1 Variable resistor VROP0, VRON0 Variable resistor VROP1, VRON1 8-to-1 selector (voltage level of grayscale 1) 8-to-1 selector (voltage level of grayscale 8) 8-to-1 selector (voltage level of grayscale 20) 8-to-1 selector (voltage level of grayscale 43) 8-to-1 selector (voltage level of grayscale 55) 8-to-1 selector (voltage level of grayscale 62)
Fine adjustment
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Ladder resistors and 8-to-1 selector Block configuration
ILI9331
The reference voltage generating block consists of two ladder resistor units including variable resistors and 8-to-1 selectors. Each 8-to-1 selector selects one of the 8 voltage levels generated from the ladder resistor unit to output as a grayscale reference voltage. Both variable resistors and 8-to-1 selectors are controlled according to the -correction registers. This unit has pins to connect a volume resistor externally to compensate differences in various characteristics of panels. Variable resistors ILI9331 uses variable resistors of the following three purposes: gradient adjustment (VRCP(N)0/VRCP(N)1); amplitude adjustment (1) (VROP(N)0); and the amplitude adjustment (2) (VROP(N)1). The resistance values of these variable resistors are set by gradient adjustment registers and amplitude adjustment registers as follows.
Gradient adjustment PRP(N)0/1[2:0] Register 000 001 010 011 100 101 110 111 VRCP(N)0/1 Resistance 0R 4R 8R 12R 16R 20R 24R 28R
Amplitude adjustment (1) VRP(N)0[3:0] Register 0000 0001 0010 : : 1101 1111 1111 VROP(N)0 Resistance 0R 2R 4R : : 26R 28R 30R
Amplitude adjustment (2) VRP(N)1[4:0] Register 00000 00001 00010 : : 11101 11110 11111 VROP(N)1 Resistance 0R 1R 2R : : 29R 30R 31R
8-to-1 selectors The 8-to-1 selector selects one of eight voltage levels generated from the ladder resistor unit according to the fine adjustment register and output the selected voltage level as a reference grayscale voltage (VgP(N)1~6). The table below shows the setting in the fine adjustment register and the selected voltage levels for respective reference grayscale voltages.
Fine adjustment registers and selected voltage Register KP(N)[2:0] 000 001 010 011 100 101 110 111 VgP(N)1 VP(N)1 VP(N)2 VP(N)3 VP(N)4 VP(N)5 VP(N)6 VP(N)7 VP(N)8 VgP(N)8 VP(N)9 VP(N)10 VP(N)11 VP(N)12 VP(N)13 VP(N)14 VP(N)15 VP(N)16 Selected Voltage VgP(N)20 VP(N)17 VP(N)18 VP(N)19 VP(N)20 VP(N)21 VP(N)22 VP(N)23 VP(N)24 VgP(N)43 VP(N)25 VP(N)26 VP(N)27 VP(N)28 VP(N)29 VP(N)30 VP(N)31 VP(N)32 VgP(N)55 VP(N)33 VP(N)34 VP(N)35 VP(N)36 VP(N)37 VP(N)38 VP(N)39 VP(N)40 VgP(N)62 VP(N)41 VP(N)42 VP(N)43 VP(N)44 VP(N)45 VP(N)46 VP(N)47 VP(N)48
Fine adjustment registers and selected resistor Register KP(N)[2:0] 000 001 010 011 100 101 110 111 RMP(N)0 0R 4R 8R 12R 16R 20R 24R 28R RMP(N)1 0R 1R 2R 3R 4R 5R 6R 7R 0R 1R 2R 3R 4R 5R 6R 7R Selected Resistor RMP(N)2 RMP(N)3 0R 1R 2R 3R 4R 5R 6R 7R RMP(N)4 0R 1R 2R 3R 4R 5R 6R 7R
ILI9331
RMP(N)5 0R 4R 8R 12R 16R 20R 24R 28R
Figure 39 Example of RMP(N)0~5 definition
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Gamma correction resister ratio
ILI9331
Data 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh VP0 VP1 VP2 VP3 VP4 VP5 VP6 VP7 VP8 VP9 VP10 VP11 VP12 VP13 VP14 VP15 VP16 VP17 VP18 VP19 VP20 VP21 VP22 VP23 VP24 VP25 VP26 VP27 VP28 VP29 VP30 VP31
Positive polarity output voltage (VgP0) (VgP1) (VP8+(VP1-VP8)*(30/48)) (VP8+(VP1-VP8)*(23/48)) (VP8+(VP1-VP8)*(16/48)) (VP8+(VP1-VP8)*(12/48)) (VP8+(VP1-VP8)*(8/48)) (VP8+(VP1-VP8)*(4/48)) (VgP8) VP20+(VP8-VP20)*(22/24) VP20+(VP8-VP20)*(20/24) VP20+(VP8-VP20)*(18/24) VP20+(VP8-VP20)*(16/24) VP20+(VP8-VP20)*(14/24) VP20+(VP8-VP20)*(12/24) VP20+(VP8-VP20)*(10/24) VP20+(VP8-VP20)*(8/24) VP20+(VP8-VP20)*(6/24) VP20+(VP8-VP20)*(4/24) VP20+(VP8-VP20)*(2/24) (VgP20) (VP43+(VP20-VP43)*(22/23)) (VP43+(VP20-VP43)*(21/23)) (VP43+(VP20-VP43)*(20/23)) (VP43+(VP20-VP43)*(19/23)) (VP43+(VP20-VP43)*(18/23)) (VP43+(VP20-VP43)*(17/23)) (VP43+(VP20-VP43)*(16/23)) (VP43+(VP20-VP43)*(15/23)) (VP43+(VP20-VP43)*(14/23)) (VP43+(VP20-VP43)*(13/23)) (VP43+(VP20-VP43)*(12/23)) VN0 VN1 VN2 VN3 VN4 VN5 VN6 VN7 VN8 VN9 VN10 VN11 VN12 VN13 VN14 VN15 VN16 VN17 VN18 VN19 VN20 VN21 VN22 VN23 VN24 VN25 VN26 VN27 VN28 VN29 VN30 VN31
Negative polarity output voltage (VgN0) (VgN1) (VN8+(VN1-VN8)*(30/48)) (VN8+(VN1-VN8)*(23/48)) (VN8+(VN1-VN8)*(16/48)) (VN8+(VN1-VN8)*(12/48)) (VN8+(VN1-VN8)*(8/48)) (VN8+(VN1-VN8)*(4/48)) (VgN8) VN20+(VN8-VN20)*(22/24) VN20+(VN8-VN20)*(20/24) VN20+(VN8-VN20)*(18/24) VN20+(VN8-VN20)*(16/24) VN20+(VN8-VN20)*(14/24) VN20+(VN8-VN20)*(12/24) VN20+(VN8-VN20)*(10/24) VN20+(VN8-VN20)*(8/24) VN20+(VN8-VN20)*(6/24) VN20+(VN8-VN20)*(4/24) VN20+(VN8-VN20)*(2/24) (VgN20) (VN43+(VN20-VN43)*(22/23)) (VN43+(VN20-VN43)*(21/23)) (VN43+(VN20-VN43)*(20/23)) (VN43+(VN20-VN43)*(19/23)) (VN43+(VN20-VN43)*(18/23)) (VN43+(VN20-VN43)*(17/23)) (VN43+(VN20-VN43)*(16/23)) (VN43+(VN20-VN43)*(15/23)) (VN43+(VN20-VN43)*(14/23)) (VN43+(VN20-VN43)*(13/23)) (VN43+(VN20-VN43)*(12/23))
Data 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh VP32 VP33 VP34 VP35 VP36 VP37 VP38 VP39 VP40 VP41 VP42 VP43 VP44 VP45 VP46 VP47 VP48 VP49 VP50 VP51 VP52 VP53 VP54 VP55 VP56 VP57 VP58 VP59 VP60 VP61 VP62 VP63 Positive polarity output voltage (VP43+(VP20-VP43)*(11/23)) (VP43+(VP20-VP43)*(10/23)) (VP43+(VP20-VP43)*(9/23)) (VP43+(VP20-VP43)*(8/23)) (VP43+(VP20-VP43)*(7/23)) (VP43+(VP20-VP43)*(6/23)) (VP43+(VP20-VP43)*(5/23)) (VP43+(VP20-VP43)*(4/23)) (VP43+(VP20-VP43)*(3/23)) (VP43+(VP20-VP43)*(2/23)) (VP43+(VP20-VP43)*(1/23)) (VgP43) (VP55+(VP43-VP55)*(22/24)) (VP55+(VP43-VP55)*(20/24)) (VP55+(VP43-VP55)*(18/24)) (VP55+(VP43-VP55)*(16/24)) (VP55+(VP43-VP55)*(14/24)) (VP55+(VP43-VP55)*(12/24)) (VP55+(VP43-VP55)*(10/24)) (VP55+(VP43-VP55)*(8/24)) (VP55+(VP43-VP55)*(6/24)) (VP55+(VP43-VP55)*(4/24)) (VP55+(VP43-VP55)*(2/24)) (VgP55) (VP62+(VP55-VP62)*(44/48)) (VP62+(VP55-VP62)*(40/48)) (VP62+(VP55-VP62)*(36/48)) (VP62+(VP55-VP62)*(32/48)) (VP62+(VP55-VP62)*(25/48)) (VP62+(VP55-VP62)*(18/48)) (VgP62) (VgP63) VN32 VN33 VN34 VN35 VN36 VN37 VN38 VN39 VN40 VN41 VN42 VN43 VN44 VN45 VN46 VN47 VN48 VN49 VN50 VN51 VN52 VN53 VN54 VN55 VN56 VN57 VN58 VN59 VN60 VN61 VN62 VN63
ILI9331
Negative polarity output voltage (VN43+(VN20-VN43)*(11/23)) (VN43+(VN20-VN43)*(10/23)) (VN43+(VN20-VN43)*(9/23)) (VN43+(VN20-VN43)*(8/23)) (VN43+(VN20-VN43)*(7/23)) (VN43+(VN20-VN43)*(6/23)) (VN43+(VN20-VN43)*(5/23)) (VN43+(VN20-VN43)*(4/23)) (VN43+(VN20-VN43)*(3/23)) (VN43+(VN20-VN43)*(2/23)) (VN43+(VN20-VN43)*(1/23)) (VgN43) (VN55+(VN43-VN55)*(22/24)) (VN55+(VN43-VN55)*(20/24)) (VN55+(VN43-VN55)*(18/24)) (VN55+(VN43-VN55)*(16/24)) (VN55+(VN43-VN55)*(14/24)) (VN55+(VN43-VN55)*(12/24)) (VN55+(VN43-VN55)*(10/24)) (VN55+(VN43-VN55)*(8/24)) (VN55+(VN43-VN55)*(6/24)) (VN55+(VN43-VN55)*(4/24)) (VN55+(VN43-VN55)*(2/24)) (VgN55) (VN62+(VN55-VN62)*(44/48)) (VN62+(VN55-VN62)*(40/48)) (VN62+(VN55-VN62)*(36/48)) (VN62+(VN55-VN62)*(32/48)) (VN62+(VN55-VN62)*(25/48)) (VN62+(VN55-VN62)*(18/48)) (VgN62) (VgN63)
ILI9331
Figure 40 Relationship between Source Output and VCOM
V0
N e g a tiv e P o la rity S o u rce O u tp u t Le ve ls
P o s itiv e P o la rity
V6 3 000000 G R AM D a ta 111111
Figure 41 Relationship between GRAM Data and Output Level
ILI9331
13. Application
13.1. Configuration of Power Supply Circuit
Figure 42 Power Supply Circuit Block
The following table shows specifications of external elements connected to the ILI9331s power supply circuit.
Items Capacity 1 F (B characteristics) Recommended Specification 6.3V 10V 25V VF<0.4V/20mA at 25C, VR (Recommended diode: HSC226) 30V Pin connection VREG1OUT, VCI1, VDD, VCL, VCOMH, VCOML, C11A/B, C12 A/B, C13 A/B, DDVDH, C21 A/B, C22 A/B VGH, VGL (VCL VGL), (DDVDH VGH), (VCI DDVDH)
Schottky diode
13.2. Display ON/OFF Sequence
ILI9331
Figure 43 Display On/Off Register Setting Sequence
ILI9331
13.3. Standby and Sleep Mode
Standby
Display Off Sequence
Sleep
Display Off Sequence
Set Standby (STB = 1)
Set Sleep (SLP = 1)
Release from Standby (STB = 0)
Release from standby
Release from Sleep (SLP = 0)
Release from Sleep
R10 0190h
80ms or more Stabilizing time 80ms or more Stabilizing time
R10 0190h
Display On Sequence
Display On Sequence
Figure 44 Standby/Sleep Mode Register Setting Sequence
ILI9331
13.4. Power Supply Configuration

When supplying and cutting off power, follow the sequence below. The setting time for step-up circuits and operational amplifiers depends on external resistance and capacitance.
Power Supply ON (VCC, VCI, IOVCC) VCI IOVCC GND VCI IOVCC or VCI, IOVCC Simultaneously Display OFF Setting Power On Reset and Display OFF
DTE = 0 D[1:0] = 00 GON = 0 PON = 0
Display ON Setting
Normal Display
DTE=1 D[1:0]=11 GON=1
Display OFF Sequence
Display OFF
LCD Power Supply ON Sequence 50ms or more Stabilizing time
Registers setting before power supply startup
Power supply initial setting

Set VC[2:0], VRH[3:0], VCM[5;0], VDV[5:0], PON=0,BT[2:0] = 000
Power Supply Halt Setting
SAP=0 AP[2:0] = 000 PON = 0
Power Supply OFF (VCC, VCI, IOVCC) IOVCC Registers setting for power supply startup Power supply operation setting
Set BT[2:0],PON = 1, Set AP[2:0],APE=1, Set DC1[2:0], DC0[2:0]
VCI GND VCI
IOVCC
80ms or more Step-up circuit stabilizing time
Or IOVCC, VCI Simultaneously
Operational Amplifier stabilizing time
Set the other registers
Display ON Sequence
Set SAP=1
Display ON
DTE=1 D[1:0]=11 GON=1
Figure 45 Power Supply ON/OFF Sequence
ILI9331
13.5. Voltage Generation

The pattern diagram for setting the voltages and the waveforms of the voltages of the ILI9331 are as follows.
BT VGH
VG H (+9 ~ 16.5V)
DDVDH VRH VCM VDV
VLCD (4.5 ~ 5.5V) VG AM1O UT (3.0 ~ (VLCD-0.5)V ) VCO MH (3.0 ~ (VLCD-0.5)V )
Vci
(2.5 ~ 3.3V)
VC[2:0]
VCI1
VCO ML (VCL+0.5) ~ -1V )

VCOMG VCL
VCL (0 ~ -3.3V) VG L (-4.0 ~ -16.5V)
BT
VGL
Figure 46 Voltage Configuration Diagram Note: The DDVDH, VGH, VGL, and VCL output voltage levels are lower than their theoretical levels (ideal voltage levels) due to current consumption at respective outputs. The voltage levels in the following relationships (DDVDH VREG1OUT ) > 0.2V and (VCOML VCL) > 0.5V are the actual voltage levels. When the alternating cycles of VCOM are set high (e.g. the polarity inverts every line cycle), current consumption is large. In this case, check the voltage before use.
ILI9331
13.6. Applied Voltage to the TFT panel
VG H G a te O utput VCO M S ource output
VG L
Figure 47 Voltage Output to TFT LCD Panel
13.7. Partial Display Function

The ILI9331 allows selectively driving two partial images on the screen at arbitrary positions set in the screen drive position registers. The following example shows the setting for partial display function:
Base Image Display Setting 0 6h27 Partial Image 1 Display Setting 1 9h000 9h00F 9h080 Partial Image 2 Display Setting 1 9h020 9h02F 9h0C0
BASEE NL[5:0] PTDE0 PTSA0[8:0] PTEA0[8:0] PTDP0[8:0] PTDE1 PTSA1[8:0] PTEA1[8:0] PTDP1[8:0]
ILI9331
GRAM MAP
PTSA0=9'h000 Partial Image 1 GRAM Area PTEA0=9'h00F
LCD Panel
0 (1st line) 1 (2nd line) 2 (3rd line)
PTSA1=9'h020 Partial Image 2 GRAM Area PTEA1=9'h02F Partial Image 1 Display Area
PTDP0=9'h080
PTDP1=9'h0C0 Partial Image 2 Display Area
319 (320th line)
Figure 48 Partial Display Example
ILI9331
14. Electrical Characteristics

14.1. Absolute Maximum Ratings
The absolute maximum rating is listed on following table. When ILI9331 is used out of the absolute maximum ratings, the ILI9331 may be permanently damaged. To use the ILI9331 within the following electrical characteristics limit is strongly recommended for normal operation. If these electrical characteristic conditions are exceeded during normal operation, the ILI9331 will malfunction and cause poor reliability.
Item Power supply voltage (1) Power supply voltage (1) Power supply voltage (1) Power supply voltage (1) Power supply voltage (1) Power supply voltage (1) Input voltage Operating temperature Storage temperature Notes: 1. GND must be maintained
Symbol IOVCC VCI GND DDVDH GND GND VCL DDVDH VCL VGH VGL Vt Topr Tstg
Unit V V V V V V V C C
Value -0.3 ~ + 4.6 -0.3 ~ + 4.6 -0.3 ~ + 6.0 -0.3 ~ + 4.6 -0.3 ~ + 9.0 0.3 ~ + 30 -0.3 ~ VCC+ 0.3 -40 ~ + 85 -55 ~ + 110
Note 1, 2 1, 4 1, 4 1 1, 5 1, 5 1 8, 9 8, 9
2. (High) (VCC = VCC) GND (Low), (High) IOVCC GND (Low). 3. Make sure (High) VCI GND (Low). 4. Make sure (High) DDVDH GND (Low). 5. Make sure (High) DDVDH VCL (Low). 6. Make sure (High) VGH GND (Low). 7. Make sure (High) GND VGL (Low). 8. For die and wafer products, specified up to 85C. 9. This temperature specifications apply to the TCP package
ILI9331
Typ. 100 (VCC) Max. IOVCC 0.2*IOVCC 0.2*IOVCC 0.1 Note -
14.2. DC Characteristics
(VCC = VCI=2.40 ~ 3.0V, IOVCC = 1.65 ~ 3.30V, Ta= -40 ~ 85 C)
Item Input high voltage Input low voltage Output high voltage(1) ( DB0-17 Pins) Output low voltage ( DB0-17 Pins) I/O leakage current Current consumption during normal operation (VCC GND ) Current consumption during standby mode (VCC GND ) VCI=2.8V , VREG1OUT =4.8V LCD Drive Power Supply Current ( DDVDH-GND ) LCD Driving Voltage ( DDVDH-GND ) Output deviation voltage Output offset voltage ILCD mA DDVDH=5.2V , Frame Rate: 70Hz, line-inversion, Ta=25 C, GRAM data = 0000h, DDVDH VDEV VOFFSET V mV mV Note1 4.5 6 20 35 5.5 IST A VCI=2.8V , Ta=25 C 30 50 IOP A Symbol VIH VIL VOH1 VOL1 ILI Unit V V V V A Test Condition IOVCC= 1.8 ~ 3.3V IOVCC= 1.8 ~ 3.3V IOH = -0.1 mA IOVCC=1.65~3.3V Vin = 0 ~ VCC VCC=2.8V , Ta=25C , fOSC = 512KHz ( Line) GRAM data = 0000h Min. 0.8*IOV CC -0.3 0.8*IOV CC -0.1 -
Note1: The Max. value is between with measure point and Gamma setting value.
14.3. Reset Timing Characteristics

Reset Timing Characteristics (IOVCC = 1.65 ~ 3.3 V)
Item Reset low-level width Reset rise time Reset high-level width Symbol tRES_L trRES tRES_H Unit ms s ms Min. 1 50 Typ. Max. 10 -
ILI9331
14.4. AC Characteristics
14.4.1. i80-System Interface Timing Characteristics
Normal Write Mode (IOVCC = 1.65~3.3V)
Item Bus cycle time Write low-level pulse width Write high-level pulse width Read low-level pulse width Read high-level pulse width Write / Read rise / fall time Setup time Address hold time Write data set up time Write data hold time Read data delay time Read data hold time Write ( RS to nCS, E/nWR ) Read ( RS to nCS, RW/nRD ) Write Read Symbol tCYCW tCYCR PWLW PWHW PWLR PWHR tWRr/tWRf tAS tAH tDSW tH tDDR tDHR Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Min. TBD 300 TBD TBD 150 150 10 5 5 10 15 5 Typ. 500 25 100 Max. Test Condition -
RS
VIH VIL
tAS tcs
tAH
VIH VIL
tchw
nCS nWR
tcYcw
PWLW
t w Rf
DB[17:0] (Write)
tDSW
twRr
PWHW
tH tAH
Valid data
tAS
tCYCR
PWLR
nRD
twRf
tDDR
twRr
PWHR
tDHR
DB[17:0] (Read)
Valid data Figure 49 i80-System Bus Timing
ILI9331
Max. 5 100 Test Condition
14.4.2. Serial Data Transfer Interface Timing Characteristics

(IOVCC= 1.65 ~ 3.3V)
Item Serial clock cycle time Serial clock high level pulse width Serial clock low level pulse width Serial clock rise / fall time Chip select set up time Chip select hold time Serial input data set up time Serial input data hold time Serial output data set up time Serial output data hold time Write ( received ) Read ( transmitted ) Write ( received ) Read ( transmitted ) Write ( received ) Read ( transmitted ) Symbol tSCYC tSCYC tSCH tSCH tSCL tSCL tSCr, tSCf tCSU tCH tSISU tSIH tSOD tSOH Unit s s ns ns ns ns ns ns ns ns ns ns ns Min. TBD 200 40 100 40 100 10 50 20 20 5 Typ. -
nCS
VIL tC S U tS CH tS Cr tS Cf VIH VIL tS IS U tS IH Input Da ta VIH VIL Input Da ta VIH VIL tS CYC tS CL VIH VIL tC H
VIH
S CL
VIH VIL
S DI tS O D S DO
VIH VIL
VO H VO L
Output Da ta
VO H VO L
O utput Da ta
VO H VO L
Figure 50 SPI System Bus Timing
14.4.3. RGB Interface Timing Characteristics

18/16-bit Bus RGB Interface Mode (IOVCC = 1.65 ~ 3.3V)
Item VSYNC/HSYNC setup time ENABLE setup time ENABLE hold time PD Data setup time PD Data hold time DOTCLK high-level pulse width DOTCLK low-level pulse width DOTCLK cycle time DOTCLK, VSYNC, HSYNC, rise/fall time Symbol tSYNCS tENS tENH tPDS tPDH PWDH PWDL tCYCD trghr, trghf Unit ns ns ns ns ns ns ns ns ns Min. 0 10 10 10 40 40 40 TBD Typ. Max. 25 Test Condition -
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 6-bit Bus RGB Interface Mode (IOVCC = 1.65 ~ 3.3V)
Item VSYNC/HSYNC setup time ENABLE setup time ENABLE hold time PD Data setup time PD Data hold time DOTCLK high-level pulse width DOTCLK low-level pulse width DOTCLK cycle time DOTCLK, VSYNC, HSYNC, rise/fall time Symbol tSYNCS tENS tENH tPDS tPDH PWDH PWDL tCYCD trghr, trghf Unit ns ns ns ns ns ns ns ns ns Min. 0 10 10 10 30 30 30 80 Typ. Max. 25
ILI9331
Test Condition -
trgb f trgb r HS YNC VS YNC VIH VIL tAS E
tS YNC S
tENS HS YNC VS YNC trgbf VIH VIL tP DS VIH VIL VIH VIL P WDL trgbr VIH
tENH VIH VIL P WDH VIH
VIL
tC YC D tP DH Write Da ta VIH VIL
Figure51 RGB Interface Timing
ILI9331
15. Revision History

Version No. V0.00 V0.01 Date 2008/03/25 2008/04/16 Page all 42/ 43/ 44 13 / 15/ 16 117 14/15 76 84 13,14,15 71, 85, 86 13 98~116 121 81 72/96/97 71/76 64/65 75 73 78 50 109 1 14 15 117,118 83 106 114 32 68, 71 81 127 90 71~95 87 8 26 68 69 77 89 102 106 109,110,111 112 114 Description new built P42, remove high speed write. P43, remove note 1. P44, remove note 1 Change pin name : DUMMY4 TSO. (P13, 15, 16) Change SCD_VLINE format Pad swapped. C11A and C11B R02h, D10 data, 1 0 Remove b. Start Oscillation in stand by and sleep mode Change pad name from DGNDDUM4 TEST_EN Remove PON function. R12h, D4 change from PON 0 TSO Change I/O type from I O Remove description (Register availability, default, and flow chart) of CABC related register! VRP0[4:0], VRN0[4:0] VRP0[3:0], VRN0[3:0] Delete PTS[2] half frequency at non display area! Delete RTNE[5:0] Delete EOR Remove shutdown mode setting Exchange drawing of even and old number of gate output Modify drawing at SM=1 Modify ISC[3:0]=[0,0,0,1] scan cycle setting External resistance 60 100 VPP1 DDVDH, VPP3 DGND. And the flow modified Company address Coordinate center change Pad 149, C11BA C11A Add formula for gamma voltage! VREG1OUT (DDVDH 0.5)V VREG1OUT (DDVDH 0.2)V. Add destruction rate VRCP0 VRCN0 Delete Data transfer synchronization in 8/9-bit bus interface mode function R00h ID code change Delete VGH = 15.0V (max.), VGL = 12.5V (max) and VCL= -3.0V (max.) Modify VGH-VGL rating Add one note Add initial code default setting FRS[3:0]=1110 setting prohibited CABC (Brightness Adaptive Brightness Control) CABC (Content Adaptive Brightness Control) 172,820 172800 02h, BC0 B/C. 0Fh EPL DPL. DPL EPL 90h, add RTNI4 ISC3/ISC3/ISC3/ISC3 ISC3/ISC2/ISC1/ISC0 00h VSA[7:0] VEA[7:0] 13Fh 00h VSA[8:0] VEA[8:0] 13Fh DTH_OPT[2:0] DTH_STILL[3:0] 87120 bytes 172800 bytes N=0 to 175 N=0 to 239 HAS[7:0]=3Fh HEA[7:0]=3Fh, VSA[8:0]=4Fh VEA[8:0]=4Fh PKP(N)0[2:0] KP(N)0[2:0], PKP(N)1[2:0] KP(N)1[2:0], PKP(N)2[2:0] KP(N)2[2:0], PKP(N)3[2:0] KP(N)3[2:0], PKP(N)4[2:0] KP(N)4[2:0], PKP(N)5[2:0] KP(N)5[2:0], Modify resistor description Add one table to describe RMP(N)0~5 Add one figure to describe RMP(N)0~5
V0.02
2008/05/06
2008/05/19
V0.03 V0.04 V0.05 V0.06
2008/06/03 2008/06/04 2008/06/09 2008/06/27 2008/07/01 2008/07/03 2008/07/12
V0.07
2008/07/18
V0.08
2008/08/04
V0.09
2008/08/05
117 117

A-Si TFT LCD Single Chip Driver 240Rgbx320 Resolution and 262K Color Datasheet

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ILI9331

Version: V0.09 Document No.: ILI9331DS_V0.09.pdf

ILI TECHNOLOGY CORP.

MDDI (Mobile Display Digital Interface) ........................................................................................... 5 7.6.1. 7.6.2. 7.6.3.

7.7. 7.8. 8.1. 8.2.

8. Register Descriptions .................................................................................................................................... 5

Control Register (CR)

Address Counter (AC)

LCD Source Driver

Grayscale Reference Voltage

Charge-pump Power Circuit

VCOM VCOMH VCOML

The low level of VCOM AC voltage. Connect to a stabilizing capacitor.

DDVDH VGH VGL

VDD DGND AGND VGMMA1, 62 VGLDMY1~4

Power Power supply Power supply Unused gate lines

DUMMYR1,2, 28, 29.

Liquid crystal power supply specifications Table 1

5. Pad Arrangement and Coordination

Parallel RGB Interface

Address Counter (AC)

Graphics RAM (GRAM)

Grayscale Voltage Generating Circuit

LCD Driver Circuit

LCD Driver Power Supply Circuit

nCS RS nWR nRD DB[17:0]

Figure1 System Interface and RGB Interface connection

7.2. Input Interfaces

DB[17:10], DB[8:1] DB[17:10] SDI, SDO (DB[1:0])

7.2.1. i80/18-bit System Interface

nCS A2 nWR nRD D[31:0]

nCS RS nWR nRD DB[17:0]

18-bit S ys te m Inte rfa ce (262K colors ) TRI=0, DFM[1:0]=00

GRAM Da ta & RGB Ma pping

Figure2 18-bit System Interface Data Format

7.2.2. i80/16-bit System Interface

80-system 16-bit interface (2 transfers/pixel) 262,144 colors 1s t Tra ns fe r 1 0

80-system 16-bit interface (2 transfers/pixel) 262,144 colors

Figure3 16-bit System Interface Data Format

7.2.3. i80/9-bit System Interface

nCS A1 nWR nRD D[8:0]

nCS RS nWR nRD DB[17:9]

9-bit S ys te m Inte rfa ce (262K colors ) TRI=0, DFM[1:0]=00

GRAM Da ta & RGB Ma pping

Figure4 9-bit System Interface Data Format

7.2.4. i80/8-bit System Interface

80-system 8-bit interface (3 transfers/pixel) 262,144 colors

80-system 8-bit interface (3 transfers/pixel) 262,144 colors 1s t Tra ns fe r 1 1

Figure5 8-bit System Interface Data Format

7.3. Serial Peripheral Interface (SPI)

S e ria l P e riphe ra l Inte rfa ce for re gis te r a cce s s

S e ria l P e riphe ra l Inte rfa ce 65K colors

GRAM Da ta RGB m a pping

Figure 6 Data Format of SPI Interface

(a) Basic data transmission through SPI

RS RW D15 D14 D13 D12 D11 D10 D9

Start Byte SDO (Output)

Status, registers read and GRAM read

(b) Consecutive data transmission through SPI

(c) GRAM data read transmission

(d) Status/registers read transmission

Figure7 Data transmission through serial peripheral interface (SPI)

(e) Basic data transmission through SPI