Concept of Noise Margins

At point VIL the NMOS is biased in the saturation region and PMOS is biased in the nonsaturation region

Noise Margins equations

(1)

Taking derivative with respect to VI yields (2) At VIL (3) (4) Assume CMOS is symmetrical i. e. KN=KP
VI

Substituting (5) into (1)

(5)

NML=VIL-VOL (noise margin for low input) NMH=VOH-VIH (noise margin for high input)

NML=VIL-VOLU (noise margin for low input) NMH=VOHU - VIH (noise margin for high input)

(6)

At point VIH the NMOS is biased in the nonsaturation region and PMOS is biased in the saturation region

(6) Taking derivative with respect to VI yields

Noise Margins equations (cont.)

Summary of the noise margin of a symmetrical CMOS inverter

NML = VIL - VOLU (noise margin for low input)

(7)

NMH = VOHU - VIH (noise margin for high input)

(8)

(9) Assume CMOS is symmetrical i. e. KN=KP (10) Substituting (10) into (6)

Summary of the noise margin of asymmetrical CMOS inverter

NML = VIL - VOLU (noise margin for low input) NMH = VOHU - VIH (noise margin for high input)

CMOS Logic Circuits

Large scale integrated CMOS logic circuits such as watched, calculators, and microprocessors are constructed by using basic CMOS NOR and NAND gates. Therefore, understanding of these basic gates is very important for the designing of very large scale integrated (VLSI) logic circuits.

CMOS NOR gate

CMOS NOR gate can be constructed by using two parallel NMOS devices and two series PMOS transistors as shown in the figure. In the CMOS NOR gate the output is at logic 1 when all inputs are low. For all other possible inputs, output is low or at logic 0.

CMOS NAND gate

How can we design CMOS NOR symmetrical gate?

In order to obtained symmetrical switching times for the high-to-low and low-to-high output transitions, the effective conduction (design) parameters of the composite PMOS and composite NMOS device must be equal. For the CMOS NOR gate we can write as, KCN=KCP

In CMOS NAND gate the output is at logic 0 when all inputs are high. For all other possible inputs, output is high or at logic 1.

For asymmetrical case switching time is longer

By recalling effective channel width and effective channel length concept, the effective conduction parameter for NMOS and PMOS for a CMOS NOR can be written as, Since Kn~2Kp

K W K n 2W p = 2 L N 2 2L p

W 2W 2 = L N 2L p

or

W W = 8 L P L N

This implies that in order to get the symmetrical switching properties , the width to length ratio of PMOS transistor must be approximately eight times that of the NMOS device.

Concept of effective width to length ratios

Parallel combination Series combination

Fan-In and Fan-Out

The Fan-in of a gate is the number of its inputs. Thus a four input NOR gate has a fan-In of 4. Similarly, Fan-Out is the maximum number of similar gates that a gate can drive while remaining within guaranteed specifications.

Propagation Delay Definitions

The propagation delay tp of a gate defines how quickly it responds to a change at its input(s).

Vin

Vout

Switching Time and Propagation Delay Time

The dynamic performance of a logic circuit family is characterized by propagation delay of its basic inverter. The propagation delay time is define as the average of low-to-high

Vin
Propagation delay input waveform
50%

tp = (tpHL + tpLH)/2 t
90% 50% 10%

tpHL Vout
output waveform

tpLH

signal slopes

tf

tr

The propagation delay time is directly proportional to the switching time and increases as the Fan-out increases. Therefore, the maximum Fan-out is limited by the maximum acceptable propagation delay time.
Each additional load gate increases the load capacitance their must be charge and discharge as the driver gate changes state. This place a practical limit on the maximum allowable number of load gates.

propagation delay time and the high-to-low propagation delay time.

Inverter Transient Response (input step pulse)

3 2.5 2

Vin

Vout (V)

1.5 1 0.5 0

VDD=2.5V 0.25m W/Ln = 1.5 W/Lp = 4.5 Reqn= 13 k ( 1.5) Reqp= 31 k ( 4.5) tpLH tr tpHL = 36 psec tpLH = 29 psec so tp = 32.5 psec

Propagation Delay Estimate

tpHL

tf

-0.5 0 0.5 1 1.5 2 2.5

t (sec) From simulation: tpHL = 39.9 psec and

x 10-10

tpLH = 31.7 psec

The two modes of capacitive charging/discharging that contribute to propagation delay

Switch-level model
Delay estimation using switchlevel model (for general RC circuit):
I =C I= V R dV dt
V1

Switch-level model
For fall delay tphl, V0=Vcc, V1=Vcc/2

R
n

CL

dt = RC dV V

dt =

C dV I

RC dV V

V 1V t p = RC ln 1 = RC ln 2 CC V V 0 CC t p = RC ln(0.5) t phl = 0.69RnCL t plh = 0.69R pCL

Standard RC-delay equations

t1 t0 = t p =

V0

V t p = RC[ln(V1 ) ln(V0 )] = RC ln 1 V 0