PROJECT REPORT ON

“DIGITAL SIGNAL GENERATOR”

BY

AGOLA KEWAL V. (EC-02)

BAROT KASHYAP J. (EC-09)

UNDER SUPERVISION OF

Mr. VASIM A. VHORA

DEPARTMENT OF
ELECTRONICS & COMMUNICATION
FACULTY OF TECHNOLOGY
D.D.UNIVERSITY, NADIAD

1
 CERTIFICATE

This is to certify that the project titled DIGITAL SIGNAL GENERATOR done
by AGOLA KEWAL (EC-02) & BAROT KASHYAP (EC-09) is a bonafide work
carried out by him under my guidance and supervision.

Mr. Vasim A. Vhora Dr. N. J. Kothari

Project Supervisor Head of the
Department
Department of Electronics & Comm. Department of Electronics &
Comm.
DDU, Nadiad DDU,
Nadiad

2
 ACKNOWLEDGMENT

Our first experience of project has been successful, thanks

to the support staff of many friends & colleagues with gratitude.
We wish to acknowledge all of them. However, we wish to make
special mention of the following.

First of all we are thankful to our project guide Mr. Vasim A.

Vhora sir under whose guideline we were able to complete our
project. We are wholeheartedly thankful to him for giving us his
value able time & attention & for providing us a systematic way
for completing our project in time.

We would thank to our H.O.D. Dr. N. J. Kothari sir & all lab
maintenance staff for providing us assistance in various hardware
& software problem encountered during course of our project.

We are also very thankful to the dean Mr. D. G. Panchal sir

who gave us an opportunity to present this project.

Agola Kewal V.

3
 Barot Kashyap J.

INTRODUCTION

Starting from older times the compactness and efficiency of the devices have attracted
people. In recent times the development the digital device technologies has made the digital
devices more compact and more efficient. The portability of the devices like mobiles and laptops
has proved really handy.
The same way Digital Signal Generator is designed to aim that portability and efficiency.
The device being a battery operated device eliminates the need of external ac power supply. This
makes this device appropriate for portable use.
In order to interface the signal generators with other devices, the digital form of the device
is one of the most appropriate forms available. For future use also this device can be connected to
the microcontrollers with some modification.

FEATURES OF DIGITAL SIGNAL GENERATOR:

• As compared to the bulky conventional signal generators these digital generators are less
bulky and easy to use devices.
• The change in the speed of accessing the data in the memory can be varied and thus the
signal can be generated of various frequency ranges.
• Same way the signal can be generated in various magnitude values.
• The maximum frequency of the signal that can be generated is limited by the access time of
the memory.
• And the maximum magnitude of the signal that can be generated is limited by the power
supply used.

4
 CONTENTS
Sr. No. TITLE Page No.
1. BLOCK DIAGRAM………………………………………………

2. CLOCK GENERATING CIRCUIT………………………………

2.1 555 Pin Description…………………………………………...
2.2 Astable Mode operation of 555……………………………….

2.3 Importance in the Project……………………………………...

3. DIGITAL DATA ACCESSING CIRCUIT………………………

3.1 Counter………………………………………………………..

3.1.1 74191 Pin Description…………………………………..

3.1.2 Cascaded operation of counter………………………….
3.1.3 Importance in the project……………………………….
3.2 EEPROM………………………………………………………
3.2.1 Internal working of EEPROM………………………….
3.2.2 Method to program the EEPROM………………………
3.2.3 Hardware support for programming…………………….
3.2.4 Software support for programming……………………..
3.2.5 Intel Hex file……………………………………………
3.2.6 Pin Description of 28C64B…………………………….
3.2.7 Operation of EEPROM…………………………………
3.2.8 Look up table stored……………………………………
3.2.9 Importance in the project……………………………….
4. THE ANALOG SIGNAL CREATING CIRCUIT……………….

4.1 DAC 0808 pin description……………………………………

5
 4.2 Operation of DAC 0808………………………………………
5. OVERALL CIRCIUT WORKING…………………………………

LIST OF FIGURES

Sr. No. Name of figure Page no.

1. Block diagram……..………………………………………………
2. 555 timer IC pin diagram………………………………………….
3. Astable mode of operation………………………………………...
4. 74191 counter IC pin diagram…………………………………….
5. Cascaded operation of counters…………………………………...
6. Waveform for clock input and LSB frequency…………………...
7. EEPROM internal memory element………………………………
8. Quantum tunneling………………………………………………..
9. Normal operation of the memory element………………………...
10. EEPROM 28C64B IC pin diagram………………………………
11. Operation of EEPROM…………………………………………..
12. Digital to Analog Converter 0808 pin diagram………………….
13. Application of digital to analog converter.………………………
14. Circuit for Regulated Signal Generation………………………...
15. Overall Circuit Diagram...……………………………………….
16. Final Signal Waveform………………………………………….

6
 BLOCK DIAGRAM

Figure1. Block Diagram of Digital Signal Generator

Block Diagram Description:

1. Clock Generator:
The clock generator applies the clock pulses essential for synchronizing the
sequential components used. Here in the project a 555 timer circuit is used as clock
generator. The clock is initially applied to the counters.

7
 2. Counter:
Counters are applied with the clock generated by the clock generator. And in order
to create six addressing lines, two 74LS191 counters are used in the cascaded mode. The
address lines generated is given to the memory having digital data.

3. Memory Element:
The memory element used here is the EEPROM (Atmel – 28C64B). The address
lines of the memory are provided with the output of the counters. According to the address
present on the address line memory puts the data on data bus, which is then given to the
digital to analog converter.
4. Digital to Analog Converter:
The data put on the data bus by memory element is given to the digital to analog
converter. This block converts the digital input signal to the analog output signal.

The project consists of three parts.

1. The clock generating circuit.

2. The digital data accessing circuit.
3. The analog signal creating circuit.

8
 The Clock Generating Circuit

Here the 555 timer is used to generate the clock pulses. Normally 555 timer gives output
pulse of 5Vp to 18Vp. Here in order to match the output of 555 to the TTL counter input the
voltage level has been maintained at 5V. So as to generate the clock pulses continuously here the
555 timer is used in astable mode. We have a provision to get a variable clock frequency up to 330
KHz.

Pin Description:

Figure2. Pin Description of 555 Timer IC

• 555 timer is an 8 pin IC package.

• Trigger to the circuit is applied through the pin 2.
• Output of the 555 circuit in terms of the square wave is taken out from the pin 3.
• Pin 5 is the control input where the capacitor is joined to avoid the high frequency noise
influencing the circuit operation.
• The voltage level to be kept as a reference voltage is given on pin 6.
• And the mechanism to discharge the capacitor and get the output to fall pin 7 is used.
• GND is on pin 1 and Vcc is on pin 8.

9
Astable Mode Operation of 555:

Figure3. Circuit Diagram for Astable Mode Operation of 555

In astable mode, the 555 timer puts out a continuous stream of rectangular pulses having a
specified frequency. Resistor R1 is connected between VCC and the discharge pin (pin 7) and
another resistor (R2) is connected between the discharge pin (pin 7), and the trigger (pin 2) and
threshold (pin 6) pins that share a common node. Hence the capacitor is charged through R1 and
R2, and discharged only through R2, since pin 7 has low impedance to ground during output low
intervals of the cycle, therefore discharging the capacitor.

In the astable mode, the frequency of the pulse stream depends on the values of R 1, R2 and
C:

F=1/ (ln (2)*C*(R1 + 2R 2 ))

10
Here C=0.01uF, R1=10K, R2=1K – 501K (Variable to vary the frequency)

This gives maximum of 330 KHz.

The high time from each pulse is given by

High = ln (2)*(R1 + R2)*C

And the low time from each pulse is given by

Low = ln (2)*R2*C

Where R1 and R2 are the values of the resistors in ohms and C is the value of the

Because of the requirement of variable frequency of the final wave the clock frequency
must be variable as well. So, to change the clock frequency capacitor and resistors are selected as
per need. Selection of capacitor in turn selects the range of the frequency and variable capacitor
changes the frequency in that range.

Here the generated clock pulses are given to the counter and the output of the counter
provides incrementing addressing of the EEPROM.

11
 Digital Data Accessing Circuit

The digital data accessing circuit consist of two parts.

1. Counter
2. EEPROM

1. Counter:

In order to get different digital values of analog output signal which are stored at sequential
ROM location the counters are used. In the project 2 numbers of 74LS191 4-bit binary counters are
used. Each counter can provide four address lines. But in this project one counter provides 4 LSB
addressing lines where as the second counter provides other 2 MSB addressing lines to the
EEPROM.

Pin Description:

12
 Figure4. Pin Diagram of 74LS191

• The DATA A, B, C, D pins are the input pins which loads the initial value to be loaded in the
counter.
• OA, OB, OC, OD are the output pins.
• ENABLE’ pin is the active low pin which must be grounded in order to work the counter work
properly.
• DOWN/UP’ selects the mode of the counter whether it will count up or count down.
• The LOAD’ pin when grounded the data present at the data pins of the counter will be loaded into
the counter.
• Pin 14 is the clock pin where the clock signal is applied.

Operation of the Counter:

13
 Figure5. Cascaded Operation of counter

Initially the values of both the counters are 0000 & 0000. Here the counters are used in
count up mode. So, as the counter receives the clock pulse it starts counting up.
Now as shown in the figure both the counter are used in cascaded mode to get 6 address
lines. To use the two counters in cascaded mode MSB data pin of the counter 0 is given to the
clock input of the counter 1.

Figure6. Relative frequency of clock and LSB of counter

The input of the clock and the LSB state’s waveforms are shown in the figure. Here the
frequency of the LSB signal is half of the frequency of the clock input. The same relation applies
to all the bits of the counter. And the MSB of the counter has a frequency 16 th of the applied clock
frequency.

14
 So, in order to cascade the counters the output of MSB should be given to the counter 2 as
clock input. And again the frequency relation states that both of the counters would work as
cascaded.

Value of Counter 1 Value of Counter2

0000 0000
. .
. .
1111 0000
0000 0001
. .
. .
1111 0001
0000 0010
. .
. .
1111 0010
0000 0011
. .
. .
1111 0011
0000 0000

As shown in here the values of the clock keeps on rotating like this and continuously keeps
on accessing the data stored in the EEPROM.
The counters are used in the project to address the EEPROM. The six output lines of the
counters are given to the six address lines of the EEPROM. It is important to continuously get the
data from the EEPROM.

2. EEPROM:

EEPROM stands for Electrically Erasable Programmable Read-Only Memory and is a

type of non-volatile memory used in computers and other electronic devices to store small amounts
of data that must be saved when power is removed, e.g., calibration tables or device configuration.

When larger amounts of static data are to be stored (such as in USB flash drives) a specific
type of EEPROM such as flash memory is more economical than traditional EEPROM devices.
EEPROMs are realized as arrays of floating-gate transistors.

15
 EEPROM is user-modifiable read-only memory (ROM) that can be erased and
reprogrammed (written to) repeatedly through the application of higher than normal electrical
voltage generated externally or internally in the case of modern EEPROMs. EPROM usually must
be removed from the device for erasing and programming, whereas EEPROMs can be
programmed and erased in circuit. Originally, EEPROMs were limited to single byte operations
which made them slower, but modern EEPROMs allow multi-byte page operations. It also has a
limited life - that is, the number of times it could be reprogrammed was limited to tens or hundreds
of thousands of times. That limitation has been extended to a million write operations in modern
EEPROMs. In an EEPROM that is frequently reprogrammed while the computer is in use, the life
of the EEPROM can be an important design consideration. It is for this reason that EEPROMs
were used for configuration information, rather than random access memory. Nowadays instead of
EEPROM the flash memory is more in trend because the EEPROM can be erased byte by byte and
it takes time to manually erase the UV-EPROM and the EEPROM is erased byte by byte which
still takes a lot of time to erase the ROM in faster systems, where as the flash memory can be
erased block by block, and so the memory can be erased very fast.

Normally EEPROMs are available in either serial or parallel data output. The biggest
advantage of the EEPROM is that it can be erased as well as re-written while it is in the system,
and no need to remove and re-write it like UV-EPROM.

Internal Working of the EEPROM:

EEPROM has several units of the FET with an isolated gate as shown in the figure.

16
 Figure7. EEPROM Internal Memory Element

Programming:

While programming the electrons gets trapped in the isolated gate due to the tunneling
effect. And these electrons can not skip from this gate even after the power supply is turned off.

And so the data is stored in the EEPROM.

Tunneling:

Tunneling is a concept developed from the quantum mechanics which states that for
very tiny particles like electrons, the conventional physics laws do not hold sufficient and it works
on the probability.

17
 Figure8. Explanation of Quantum Tunneling

As the classical physics says that electron not having sufficient energy to get through the
barrier can not get across it. But as we know that the quantum physics works on the probability. It
states that the electron wave on one side of the potential barrier have some probability of going on
the other side of the barrier.

Erase:

And at the time of erasing the high voltage at the control gate will help electrons skip from
the isolated gate and the memory gets erased.

Normal Operation:

18
 While using the ROM in normal mode 5V dc is applied to the gate. And the gate having
electrons stored in it does not allow the channel to conduct. But the gate without electrons trapped
in it conducts at 5V.

Figure9. Operation of the Memory Element

Method to Program the EEPROM:

• Insert the ROM into the programmer.
• Open the software for the programmer and select the
chip from the given list that you want to program.
• Load the hex file into the software.
• And select the program option.
• After programming read the file if it is correctly
programmed, and if not then try to reprogram it.
• After programming safely remove the ROM from the
programmer.

Hardware Support for programming the EEPROM:

The EEPROM can be programmed using several programmers. But the one we used to
program the EEPROM was ADVANTECH LAB TOOL – 48 UXP UNIVERSAL
PROGRAMMER.

Features:

19
 • The programmer can be used to program almost all of the normally used controllers and
memories.
• The programming is just a matter of seconds.
• And it is easy to use the programmer along with its software support.

Software Support for programming the EEPROM:

The universal programmers are provided with software setup wizard CDs. LT48-
UXP_83203 is the software compatible with this programmer. The file to be loaded in the
EEPROM should be in INTEL HEX format.

Introduction to Intel Hex file:

Example:
:100000007590FF75A0C6758901112D3090FB309158
:100010000530920A8010C2A7112DD2A780EDC2A28E
:10002000112DD2A280E575A0A5112D80E1758CC39C
:10003000758A50C28DD28C7828D8FE308DF9C28C4A
:01004000229D
:00000001FF

The format is a text file, with each line containing hexadecimal values encoding a sequence
of data and their starting offset or absolute address.

There are three types of Intel HEX: 8-bit, 16-bit, and 32-bit. They are distinguished by their
byte order.

Each line of Intel HEX file consists of six parts:

1. Start code: one character, an ASCII colon ':'.

2. Byte count: two hex digits, a number of bytes (hex digit pairs) in the data field. 16 (0x10)
or 32 (0x20) bytes of data are the usual compromise values between line length and address
overhead.

20
 3. Address: four hex digits, a 16-bit address of the beginning of the memory position for the
data. Limited to 64 kilobytes, the limit is worked around by specifying higher bits via
additional record types.
4. Record type: two hex digits, 00 to 05, defining the type of the data field.
5. Data: a sequence of n bytes of the data themselves, represented by 2n hex digits.
6. Checksum: two hex digits - the least significant byte of the two's complement of the sum of
the values of all fields except fields 1 and 6 (Start code ":" byte and two hex digits of the
Checksum). It is calculated by adding together the hex-encoded bytes (hex digit pairs), then
leaving only the least significant byte of the result and making a 2's complement. If you are
not working with 8-bit variables, you must suppress the overflow by AND-ing the result
with 0xFF. The overflow may occur since both 0x100-0 and (0x00 XOR 0xFF)+1 equal
0x100. If the checksum is correctly calculated, adding all the bytes (the Byte count, both
bytes in Address, the Record type, each Data byte and the Checksum) together will always
result in a value wherein the least significant byte is zero. Here in the project the EEPROM
supports 8-bit wide data. So to program the ROM 8-bit HEX file is used.

EEPROM Pin Description:

Figure10. Pin Diagram of EEPROM 28C64B

• WE’ is the write enable pin which is held at ground potential while programming and Vcc other
wise.
• CE’ is chip enable pin which is active low and should be held at ground potential in order to enable
the chip.

21
• OE’ is output enable pin which is held at ground potential to read the data from the ROM.
• Pins A0 to A12 are the address lines.
• Pins I/O0 to I/O7 are the data bus.

Operation of EEPROM:

Figure11. Operation of EEPROM

The input of the EEPROM is given from the output of the counter. Six address lines are
used. And the data that is stored in the ROM is accessed via applying the address on the address
bus. According to the address given to the EEPROM the data is given to the data bus in turn giving
it to the DAC 0808.
Look up Table stored in the EEPROM:

22
 The EEPROM is the inevitable part of the project. As all the data of the signals are stored
in the ROM. To make the Digital Signal Generator a portable device ROM is must needed.

The analog signal creating circuit

The data stored in the EEPROM now comes out of the data lines. Here we have used six
address lines and six data lines. Now in order to convert the digital data into the analog signal we

23
have used 8 pin Digital to Analog converter (DAC-0808). It can provide the output up to 10 V. But
here in the project we have designed the circuit that gives the output voltage from 0 to 2.5V.
Because only 6 address lines are used and remaining 2 MSB lines are grounded.

Pin Description:

Figure12. Pin Diagram of DAC 0808

• Pin No. 1 is not connected, so it is kept open.

• Pin No. 2 is the ground pin. So all the supply grounds are connected to it.
• Pin No. 3 is the Vee supply pin. Normally -9 to -15 V are applied to this pin for the op-
amps in the chip.
• Pin No. 4 is the output pin, which gives the output in the current form. So a current to
voltage converter is used to get the output in form of voltages.
• Pin No. 5 – 12 are the input data pins of DAC. Digital input is given to these pins. Pin No.
5 is the MSB and Pin No. 12 is the LSB.
• Pin No. 13 is the Vcc supply voltage pin. A supply of 5V with respect to ground is given
to these pins.
• Pin No. 14 is the Iref input pin. Generally an input current of 2mA is given to this pin. Iref
= V14 / R. In this way the Vref (+) and R are set.
• Pin No. 15 is Vref (-) pin. Generally a 5k resistor is connected to Vcc through this pin.

24
 • Pin No. 16 is compensation pin. This pin is connected to Pin No. 3 via a capacitor of
0.1uF.

Typical Operation:

Figure13. Operation of Digital to Analog Converter

Here 2.2K resistor is used to setup the Iref.

The capacitor is used for compensation, and the 4.7 K resistor is used to regulate the Iref
current using 2.2 K resistor.

Now, Iref = Vref / Rref

= 5V / 2.2 K
= 2.27 mA

Output analog current,

So, the output analog voltage is given by,

25
 Vout = Iout * RL

Now in order to get variable peak to peak output voltage of the wave we are using variable
resistor which in turn varies the load voltage on pin no. 4.

Circuit for Properly Regulating the output voltage:

Figure14. Circuit Diagram for Regulated Signal Generation

Here in place of 5 K resistor we can connect our variable resistor there and the load resistor
to the Vo and ground. So that now the output voltage only depends on the variable resister and not
on the load resister which gives a better regulation of voltage.

OVERALL CIRCUIT WORKING

Circuit Diagram:

26
 Figure15. Overall Circuit Diagram

As shown in the figure the first IC 555 generates the clock pulse of variable frequency
which is varied by the potentiometer. The clock is given to the cascaded connection of the counter.
Cascaded connection of the counters generates 6 address lines for the EEPROM. And the data
stored in the memory is sequentially put on the data bus of the memory. The data output of the
EEPROM is given to the DAC. DAC converts digital data to the analog signal. And the output
wave can be utilized from the output pin.

Final Output Wave Form:

Figure16. Final Sinusoidal Waveform

Conclusion:

27
 By completing this project we came to know that ideally analog signals are made up of
infinite number of voltage stages. But using a finite number of voltage stages the signal can be
generated with some distortion. Thus any analog signals can also be generated using digital
systems. Any digital memory can work as a source of the analog signal. Computers use the same
concept to generate music or video for the speaker or monitor attached to it.

Applications:
1. Digital Signal Generator can be used as a portable solution for signal generation.
2. This generator is the basis of the computer interfacing with the analog devices.
3. Any number of analog signals can be generated by this device provided once the digital
data of the signal is stored in the memory. So, it can be used in any of the voice or image
processing devices.

Reference:

28
 1. “Fundamentals of digital electronics” by Anand Kumar
2. “The 8051 Microcontroller and Embedded Systems” By Muhammad Ali Mazidi
3. www.google.com
4. www.wikipedia.org
5. www.atmel.com
6. www.alldatasheets.com

Datasheets:
1. NE 555 TIMER
2. 4 BIT UP-DOWN 74LS191 COUNTER
3. 28C64B EEPROM
4. DAC 0808

29