PULSE

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Issue 50 June 12, 2012

EEWeb.com

Jim Sealock
Boeing
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TA B L E O F C O N T E N T S
Jim Sealock
BOEING
Interview with Jim Sealock - Technical Lead for EMARSS Program

4 8 10 16

TABLE OF CONTENTS

Featured Products Making Wireless Truly Wireless

BY DAVE BAARMAN WITH FULTON INNOVATION
The need to develop a standard that will allow consumers around the world to power their devices under a single, interoperable standard.

How to Specify an ADC for a Digital Communication Receiver

BY ELETTRA VENOSA WITH IQ-ANALOG
How noise budget, linearity requirements and timing jitter impact the specification process.

RTZ - Return to Zero Comic

22

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JimSealock
Boeing
Jim Sealock - Technical Lead for EMARSS Program

INTERVIEW

FEATURED INTERVIEW

Can you tell us about your work experience before becoming the technical lead at Boeing? My work has been quite varied since I earned by bachelors degree in physics from James Madison University. I designed transponders for missiles and aircraft, monopulse radar receivers and HF/VHF/UHF miniaturized receivers.

After five years of designing receivers, I wanted to get more involved in the development of systems that used those components so I went back to school and earned my masters in systems engineering from George Mason University. While working on that degree, I participated in the design, integration and field testing of unmanned aerial vehicle (UAV) tracking and control systems, as well as communications intelligence (COMINT) systems for installation on various aircraft and surface ships. What have been some of your influences that have helped you get to where you are today? I would certainly say that continuing education in aspects of my field that interested me or in which new technology is emerging has played a significant role in the opportunities Ive had.

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Do you have any noteworthy engineering experiences? Prior to joining Boeing, I would say my favorite project was working on the original design for the Global Hawk System. My manager at the time asked if I would like to work on a project that would take my experience in data links, receivers and ground systems, and apply it to the next-generation ISR bird. How could I turn down an opportunity like that?! So from September 1994 until September 2000, I worked the end-to-end systems engineering design of the Global Hawk System. I was both the ground segment IPT lead and co-IPT of the systems engineering IPT for the Global Hawk team. That team was later honored with the 2000 National Aeronautical Associations Collier Award. Do you have any experiential stories you would like to share? As the lead systems engineer on an Army Joint Task Force QRC, I was sent down to Roosevelt Roads to meet a ship that was towing a 30-meter aerostat that had one of the COMINT sensors onboard supporting the missions. When I arrived, I determined that the tail reference antenna had a broken connector on the cable. We had to wait until three in the morning for the winds to die down so we could access the tail of the aerostat. I went up to the tail in a bucket truck and leaned out over the pier about 45 feet above the water, with only an SMA wrench and a 15 Watt batteryoperated soldering iron. (Thats all I was allowed to bring in the bucket!) To reach the connector, I had to hang out of the bucket while one of my team members held onto my belt so I wouldnt fall into the water. After three attempts, we finally got the antenna fixed, and the ship sailed on time to get back out on its mission. The moral of the story is that as a systems engineer supporting the customer, you have to be able to improvise and get the task completed any way that you can! Do you continue to take an active role in product development? If so, how? As a systems engineer, I push hard to be part of initial concept been proven time and again that if you do not do the upfront systems engineering tasks of requirements, concept of employment and interface definition, the best products will be thrown to the side because they cannot be easily integrated into the final system. What are you currently working on? The Enhanced Medium Altitude Reconnaissance Surveillance System (EMARSS) is an extremely fast-moving program providing an ISR platform to the U.S. Army on an 18-month schedule. One of the greatest assets to the program is the team environment being fostered by the U.S. Army customer with the Boeing-led team. Our goal is to deliver a quality system capable of meeting both todays immediate needs and the needs of battlefield commanders in the future. The aircraft is the Hawker Beechcraft King Air 350 ER platform. It includes two DCGS-A enabled operator workstations, payloads supporting MX-15HDi and broadspectrum COMINT, and line-ofsight and beyond-line-of-sight communication and data links. What are your main roles and responsibilities with this project? As the technical lead for the EMARSS program, I report to the chief engineer and support the overall system design and integration efforts where Im needed. I support all of the design engineers in their efforts to apply the practical fieldproven lessons learned, along with new model-based design techniques to reduce the amount of

FEATURED INTERVIEW

As a systems developer and systems integrator, well need to become more efficient in the selection and integration of the sensors into the existing platforms.
development for whatever our next product development effort is. Its

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INTERVIEW
design change through our recently completed System Design Review in December 2011. I have now been given the responsibility to lead the integration efforts of the PME in the U.S. Army Joint Test and Integration Facility (JTIF) in Aberdeen Proving Grounds, Maryland. This is the most exciting part of any program -- getting to see the paper design come to fruition. Its like putting a jigsaw puzzle together and then being able to frame it for everyone else to see. When will this technology be employed and where do you hope to see it implemented? The initial system design for EMARSS is currently on schedule to deploy four aircraft by the end of 2012. As mentioned above, this is a fast moving program with a hard delivery date. Battlefield commanders need more ISR assets capable of being tasked to meet the immediate needs of warfighters in the field. Weve also been addressing capabilities that the system could provide in the future and will begin to demonstrate those capabilities through the JTIF Systems Integration Laboratory and onboard the Boeingowned Hawker B350. What is the work culture like at Boeing? I came to work at Boeing through its acquisition of Argon ST in August 2010. Argon had grown from 125 employees when I joined in January 2001 to 1,000 employees when Boeing acquired us. The integration into Boeing has been interesting. Ive learned new engineering processes, new business processes and discovered the working relationships forged by a company of more than 160,000 employees. I can say definitively that all the people Ive met at Boeing are focused on a singular goal: making quality products. What direction do you see your business heading in the next few years? The defense industry is working in a budget-constrained environment. The ISR industry will stay busy, but the development of new capabilities could be slowed due to constrained development budgets. The Army has already begun to slim down their budgets and the current approach is to use the best-of-breed sensors that are available now vice what can be developed. What challenges do you foresee in our industry? As a systems developer and systems integrator, well need to become more efficient in the selection and integration of the sensors into the existing platforms. What are some of your hobbies outside of work and design? Im heavily invested in the Boy Scouts of America. I earned my Eagle in 1974 and have had the honor of working with boys in both Cub Scouts and Boy Scouts since 1997. I served as a scoutmaster for six years and am now the assistant scoutmaster for the same troop working with the new scouts as they join the troop. I also enjoy playing softball and golf whenever I can get the chance. Is there anything that you have not accomplished yet, that you have your sights on accomplishing in the near future? Im becoming more involved in both the International Council of Systems Engineering (INCOSE) and the Boeing Systems Engineering process teams. I am in the middle of INCOSE certification as a Certified Systems Engineering Professional (CSEP) and will be working on my Expert Systems Engineering Professional certification after completing the CSEP .

FEATURED INTERVIEW

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Low-Voltage Bluetooth Low-Energy Controller

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TECHNICAL ARTICLE

Making Wireless Truly Wireless:

Need For Universal Wireless Power Solution

TECHNICAL ARTICLE

Dave Baarman
Director Of Advanced Technologies

ABSTRACT Wireless power is not a new technology. Different embodiments have been in development for over 180 years with differing degrees of success. However, with the recent invention of the microprocessor, wireless power has not been a viable solution for the challenges facing wired technologies due to inefficiencies and lack of control, causing safety and other issues. Several companies and higher education institutions have recently presented solutions to the challenges delaying the introduction of efficient wireless power for mass adoptionbut this positive development has brought with it a new set of challenges, including the problem of proprietary solutions versus the creation of an interoperable global standard. Consumer research suggests that a universal standard is the preferred solution, so it is now up to the companies interested in developing and manufacturing these solutions to develop a standard that will allow consumers around the world to power their devices across a broad range of brands and power needs under a

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TECHNICAL ARTICLE
single, interoperable standard. This solution willlike the Wi-Fi Alliance did for wireless networkingcreate a new protocol for how people interact with power. EXECUTIVE SUMMARY Since the concept was first introduced by notables including Hans Christian rsted, Michael Faraday, Nikola Tesla and Guglielmo Marconi, wireless power has been a technology steeped in possibilities and promises of increased levels of convenience and freedom for consumers around the world. As wireless power has developed over the years, an increasing number of companies have been pushing towards proprietary solutions using several technologies, including inductive coupling, conductive coupling and radio frequency (RF). Unfortunately, the proprietary approach to bringing wireless power to the market is creating a potential challenge that mirrors one of greatest issues in the industry: that of offering consumers a single, globally accepted solution for powering different devices with different power needs across a wide range of brands. The solution is to follow the example of organizations like the Wi-Fi Alliance; to publish a single global standard through a cooperative organization of international developers, manufacturers and distributors, which will serve as the blueprint for utilizing wireless power implementation worldwide. By approaching mass integration of wireless power through this method, many questions, including supply chain considerations, price point, device and infrastructure integration, efficiency, safety and range of power needs can all be addressed collectively. This will finally bring wireless power out of the ether of science fiction and into the world of a viable real world solution, cutting the last cord. INTRODUCTION THE STAGE IS SET We live in a world that is rapidly progressing toward newer and greater levels of convenience, connectivity and freedom. This is the age of the wireless power and communications revolution, where everything from handheld consumer electronics to home appliances to transportation is incorporating wireless technologies to create new levels of convenience and interaction. While tremendous progress has been made because of technologies like Bluetooth, Wi-Fi, radio frequency (RF), Ultra Wide Band (UWB) and global positioning systems (GPS), one last tether has kept consumers from making the leap to a completely wireless lifestyle the power cord. In research conducted by the Alliance for Universal Power Supplies, consumer demand for simplicity, a better charging experience and convenience, along with manufacturing, usability, waste and environmental concerns surrounding the billions of power adapters that are produced and shipped each year globally, have created a surge of interest in wireless power solutions. In association with Chicago market researcher Synovate, Green Plug (http://www. greenplug.us), an organization committed to creating a single plug solution for electronics, asked 1,000 online consumers about their attitude toward purchasing consumer electronics devices, which typically come with external power supplies that dont work with any other product. According to the survey, conducted in April, 2008, 31 percent of respondents said they regard incompatible power supplies as wasteful and have many unused adaptors just lying around, while 30 percent described the situation as frustrating agreeing that forgetting to bring the right charger when leaving the house can prevent the use of an important device such as a laptop, cell phone, camera or music player. Another 18 percent said that they never thought about the situation before, while 13 percent said it doesnt really bother them and 8 percent said it is costly and that they have had to purchase replacements when forgetting to bring the required charger to the office, school or on a trip. Consumer demand, coupled with the formation of several companies offering viable wireless power solutions, has generated an accelerated race to market for wireless power solutions ranging from proprietary pad and adaptive solutions to integrated near-field and broadcast technologies pursuing international standards all of them promising the right answer. THE CHALLENGE THE EMERGENCE OF WIRELESS POWER AS AN INDUSTRY As consumer demand and multiple solutions converged on the emerging wireless power

TECHNICAL ARTICLE

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TECHNICAL ARTICLE
industry, questions at the consumer and developmental levels began to develop. Is wireless power safe? What is the additional cost? How will this technology come to market? Is it efficient? Is there a universal, interoperablesolution? How much power is the technology able to handle? In addition to the developing questions, a challenge already facing wired technologies also began to emerge: the companies beginning to answer the questions and developing the solutions started on a fast-track focused on developing proprietary applications and being first to market rather than on pursuing a global standard, which addresses these issues. This approach has segmented the wireless power industry and, as a result, the media conversations are seeing conflicting answers from multiple points of view (depending on the embodiment being implemented), which is creating confusion about the technologies in the marketplace and potentially delaying the implementation of useful new wireless power embodiments. THE SOLUTION COLLABORATION IN CREATING A WIRELESS POWER STANDARD Wireless power is a lifestyle technology. Like Bluetooth and Wi-Fi, it radically changes the way people are able to live their lives offering new levels of mobility, convenience and safety. It has the ability to add value and create greater flexibility in the development and use of products across a wide range of power needs and industries. As such, it is imperative that a standard application of the technology be introduced to create the greatest opportunity for mass adoption and integration into consumers lifestyles. Questions on the possibility of a universal standard for power adapters are at the front of the wireless power conversations happening around the world, and without a universal standard, this will continue to be a challenge. In addition to the challenges connected with individual organizations developing proprietary solutions, the number of market segments represented across the various power levels is another significant factor that must be considered. It is clear that technology is needed to bridge a broader range than each individual manufacturer would normally expect. The idea that a 60-watt power supply could power anything under that wattage and supply the proper device requirements used to be considered costly. With the advent of advanced, low-cost power supply technology, this possibility is becoming reality. The adoption of this philosophy needs to align with consumers expectations. If pursuit of a universal standard is not made the highest priority, it could certainly limit the widespread adoption of wireless power technology. In addition to addressing questions on the feasibility of a universal solution, the cooperative development of a standard also addresses other key issues that could threaten widespread adoption of wireless power technology. The most prominent of these is the Chicken or the Egg issue, which poses the challenge to manufacturers on when to invest in wireless power technology. Device manufacturers want infrastructure in place before they commit to mass production of their products, and infrastructure manufacturers want devices to use with their products before they commit to mass production. Both are valid concerns. By working independently on proprietary solutions, this question creates a potential stalemate that could delay implementation of the technology for years. Through cooperative efforts both device and infrastructure manufacturers will reach solutions to achieve their mutual needs. Additionally, by coordinating development and production activities, manufacturers will be better positioned to respond to the actual consumer demand for an integrated, interoperable solution. Taking these thoughts into consideration, in the end it seems obvious that devices need to be manufactured to enable infrastructure. However, consumer pull based on acceptance will ultimately determine the magnitude of industry adoption and timing of entry into the market space. In addition to the Chicken or the Egg challenge, there are other equally important considerations that can be addressed by the cooperative efforts of a unified wireless power industry in pursuit of a global standard. Supply chain development and production costs are significant factors that can have a potentially negative effect on integration of the technology. Only when key contributors bring their collective capabilities and solutions to bear will wireless power be

TECHNICAL ARTICLE

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TECHNICAL ARTICLE
Devices
Phones Laptops Headsets Cameras Computer Media Players Camcorders

10% of annual income

120,000,000 15,000,000 26,000,000 12,500,000 20,000,000 21,100,000 2,000,000

Charge Power Watts

4 45 1 4 2 3 8

Standby Power Watts

0.5 0.5 0.5 0.5 0.5 0.5 0.5

Charge Hours/Wk
7 14 5 4 7 9 10

Standby Hours/Wk
161 154 163 164 161 159 158

Charge Power Standby Power Potential Savings KW-Hr/Year KW-Hr/Year in KW-Hr@10%

1.456 32.76 0.26 0.832 0.728 1.404 4.16 4.186 4.004 4.238 4.264 4.186 4.134 4.108 502,320,000 60,060,000 110,188,000 53,300,000 83,720,000 87,227,400 8,216,000 905,031,400 $72,402,512

TECHNICAL ARTICLE

Total Annual KW-Hr @ 10% Total Dollars at 0.08/KW-Hr

Note: Volume and usage data are provided as an example. The 10% is an estimated volume that could have 100% time plugged in.

Figure 1: Example Impact of standby power in devices.

able to realize its immediate potential. By working with chip set manufacturers and developing design solutions collectively, issues like cost of implementation, safety, efficiency and environmental effects can all be mitigated and create an environment in which wireless power can flourish. THE ECOUPLEDTM SOLUTION Like the model established by the Wi-Fi Alliance, Fulton Innovation (Fulton) has been working closely with a wide range of partners, including the Wireless Power Consortium, to create and drive a global standard for wireless power. A standard has been established for low-power applications (5 watts and less) and a medium standard is currently being developed. Already, Fulton has medium and high power solutions, creating new opportunities for companies to develop advanced applications, opening up the possibility of developing interoperable wireless power solutions across a broad spectrum of power needs and brands. Fulton holds over 700 granted,

published, or pending patents worldwide on wireless power development and applications, holding key technology in many areas, including medium and highpower applications, as well as in lower power delivery. On that point, device standby power is a critical concern in the manufacturing of power adapters and energy conservation and promises to be a key attribute in the development of wireless power solutions (see Table 1). Fulton uses a method called ultra-low standby power combined with efficiency comparable to wired systems to minimize the power footprint of wireless power systems. By understanding the user habits of the charge cycles and powering of devices, Fulton has designed a system that looks at the total power used as well as the convenience of charging. This equates to looking at total power used. In some cases, the standby power is actually a larger power concern than the power consumption during use. Up to seven times the consumption can be used in standby versus normal operation. Research has shown that consumers do not want the

inconvenience of disconnecting the power when power usage by the portable device has been completed. Ultra-low standby power automates this process. Systems working together to minimize power usage while providing a universal wireless power source are just part of what intelligent wireless power must accomplish. The chart below provides an example of how standby power can impact overall efficiency. It should also be noted that the efficiency of wireless power is usually considered in the context of a basic wire configuration. In some cases this would be true, but typically, elements of the wall or source power supply, the connection and the device power supplies, chargers and power management will all play a factor in this comparison. This is why wireless power can be considered comparable to wired solutions. With ultra-low standby power, it can provide even more latitude for wireless power in this comparison. Additionally, according to a 1394 Trade Association Technical brief, the wall warts, also called energy vampires, provided with so many electronic devices are

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TECHNICAL ARTICLE
Product
Cell Phone DECT Phone Digital Camera Set Top Box Personal Care Std. Battery Charger Power Tool Charger Printer Laptop Other

PJ4
21 5 2 5 1 3 4 4 2 10

Metric Tons of CO2

4,200,000 1,000,000 400,000 1,000,000 200,000 600,000 800,000 800,000 400,000 2,000,000

#1000MW Power Plant

0.7 0.2 0.1 0.2 0.0 0.1 0.1 0.1 0.1 0.3

Figure 2: Total Energy for Production, Distribution, End of life CO2 Generated by Coal

often linear power supplies, which are approximately 30-40 percent efficient. That means that they waste up to 70 percent of the power being used by the device they are connected to. Unfortunately, when the device is turned off, it continues to consume power. The effect of this wasted energy can be felt not only in the inefficiency of the wall warts, but also in the environmental impact of disposing of them. In 2008 alone, 3.2 billion external power supplies were manufactured worldwide, with 737 million external power supplies shipped to the U.S. Moreover, 434 million external power supplies will be retired in the U.S. alone and only 12.6 percent of them will be recycled, leaving 379 million external power supplies going into landfills (see Table 2). These devices dont just go away either. According to the EPA these power supplies are made with toxic materials and dont have a lot of salvageable components making them unattractive to recyclers. In addition to the development of

key IP across low, medium and high-power applications, Fulton has developed relationships with market leaders in the areas of chip set development, innovative product process and materials development, supply chain and distribution channel management and, with the Wireless Power Consortium, collaboration on wireless power standards. Fultons commitment to creating the best possible solution for mass adoption by consumers worldwide is an open invitation to all electronics manufacturers, wireless power developers, institutions of higher learning, governing bodies and any other interested parties to join in the development and dialog needed to drive integration of wireless power across the myriad applications of power delivery across the planet. CONCLUSION Wireless power is an exciting new frontier, opening up new possibilities for manufacturers and consumers around the world. This new frontier

will have a major impact on many significant market segments and product design; in addition, it will provide environmental savings, simplify human interface with infrastructure and create new ways to interact with design of both devices and complementary products. As this technology reaches its tipping point and realizes mass adoption with consumers, it is imperative that engineering and design teams, wireless power solution providers, manufacturers and governing bodies collaborate closely to ensure that a universal, interoperable solution that meets consumer needs. Only by doing so will universal power delivery reach its potential and make wireless truly wireless. About the Author David Baarman is the Director of Advanced Technologies at Fulton Innovation and the lead inventor of eCoupled intelligent wireless power technology. Mr. Baarman is responsible for the technical supervision and development of eCoupled technology and other Fulton Innovation technologies. Mr. Baarman joined Amway in 1997, where he first pioneered the use of intelligent inductive coupling in the eSpring Water Purifier. With over 20 years of leadership experience in the development of consumer and industrial products, Mr. Baarman took the technology behind eSpring and developed it to power everyday technologies, including consumer electronics, with a diverse range of power needs. Mr. Baarman has more than 700 U.S. and foreign patents that are granted or pending.

TECHNICAL ARTICLE

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Get the Datasheet and Order Samples

http://www.intersil.com

4-Channel LED Driver with Independent Channel Control for Dynamic Dimming
ISL97686
The ISL97686 is a PWM controlled LED driver that supports 4 channels of LED current, for Monitor and TV LCD backlight applications. It is capable of driving 160mA per channel from a 9V to 32V input supply, with current sources rated up to 75V absolute maximum. The ISL97686s current sources achieve typical current matching to 1%, while dynamically maintaining the minimum required VOUT necessary for regulation. This adaptive scheme compensates for the non-uniformity of forward voltage variance in the LED strings. The ISL97686 dimming can be controlled by a high speed SPI interface for independent channel control for dynamic dimming function synthesized on chip at 10-bit resolution. The ISL97686 has an advanced dynamic headroom control function, which monitors the highest LED forward voltage string, and regulates the output to the correct level to minimize power loss. This proprietary regulation scheme also allows for extremely linear PWM dimming from 0.02% to 100%. The LED current can also be switched between two current levels, giving support for 3D applications. The ISL97686 incorporates extensive protections of string open and short circuit detections, OVP, and OTP

Features
4 x 160mA, 75V Rated Channels with Integrated Channel Regulation FETs Channels can be Ganged for High Current - 2 x 350mA - 1 x 700mA 9V~32V Input Voltage Dimming Modes: - Independent Channel Dimming Control with SPI - PWM Dimming with Adjustable Output Frequency - 10-bit Dimming Resolution - VSYNC Mode 2 Selectable Current Levels for 3D Applications Current Matching of 1% Integrated Fault Protection Features such as String Open Circuit Protection, String Short Circuit Protection, Overvoltage Protection, and Over-Temperature Protection 28 Ld 5x5mm TQFN and 28 Ld 300mil SOIC Packages Available

Applications
Monitor/TV LED Backlighting General/Industrial/Automotive Lighting

Related Literature
See Application note for ISL97686IBZ_EVALZ for SOIC Application

VIN: 9V~32V

Fuse D1 VIN VDC VLOGIC EN CLK SDI SDO /CS EN_VSYNC CSEL ISET1 ISET2 OSC PWM_SET/PLL CH1 CH2 CH3 CH4 OVP SLEW GD CS Q1 RSENSE
160mA MAX PER STRING

110 100 CHANNEL CURRENT (mA) 90 80 70 60 50 40 30 20 10 0 0 20 40 60 80 100 I_CH2 I_CH3 I_CH1 I_CH4

PGND COMP

DIMMING DUTY CYCLE (%)

FIGURE 1. ISL97686 APPLICATION DIAGRAM

FIGURE 2. PWM DIMMING LINEARITY

April 23, 2012 FN7953.0

Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2012 All Rights Reserved. All other trademarks mentioned are the property of their respective owners.

How to Specify an ADC for a Digital Communications Receiver

TECHNICAL ARTICLE
ABSTRACT The goal of this paper is to provide methods and directions for specifying an analog-to-digital converter (ADC) when it has to be placed in a digital communication receiver. In this case the specification process requires particular attention because of the nature of the signals involved. The presence of channel noise and interference contribute to complicate the task. In this paper, the most important issues, such as noise budget, linearity requirements, timing jitter and phase noise are all considered. In order to simplify the understanding process of the reader, numerical examples are provided for each given specification. NOISE BUDGET A modern digital receiver has to perform the first tier tasks of filtering, spectral translation and analog-to-digital conversion. The receiver must also perform a number of second-tier tasks needed for estimating unknown parameters of the received signal such as amplitude, frequency and timing alignment. Figure 1 shows the

TECHNICAL ARTICLE

Dr. Elettra Venosa EE PHD

Co-Authors: Dr. Mikko Waltari Dr. fred harris Mike Kappes

block diagram of the first and second tier processing in a typical digital receiver. The analog-to-digital converter samples the output of the analog intermediate frequency (IF) filter which is down converted to base-band by a digital down converter (DDC). The base-band signal is then down sampled by a decimating filter and finally processed in the matched filter to maximize the signalto-noise ratio (SNR) of the samples presented to the detector. The digital signal processing (DSP) portion of this receiver includes carrier alignment, timing recovery, channel equalization, automatic gain control, SNR estimation, signal detection and interference suppression blocks. Because the receiver contains analog hardware components, it also incorporates a number of third tier DSP blocks to suppress the undesired artifacts formed by the imperfect analog blocks. The performance of such a receiver is usually considered by looking at the bit-error-rate (BER) at the output. The BER depends of the SNR of the incoming signal. The noise power which is superimposed on the signal has two main sources: the channel and the hardware devices.

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TECHNICAL ARTICLE
The ADC is one of the key components of the receiver. It samples the analog input signals and delivers the samples to the DSP-based part of the receiver which handles tasks like base-band shifting, demodulation and channel equalization. When a signal is received, due to the attenuation caused by the channel, its signal-to-noise (SNR) is very low; usually it is close to the limits set by the background noise. The goal of the front-end of the receiver (including the ADC) is to capture this weak signal and pass it to the digital portion of the receiver adding minimal - 0.2 - 10log (10 - SNRbecause - 10 degradation (implementation loss). However, 10 some degradation is inevitable, the system designer creates a system line-up where a certain noise budget is allocated for each block of the receiver. The designer knows the maximum amount of noise that can be added to the incoming signal by the hardware devices and based on the characteristics of the incoming spectrum and technological limitations, decides how to distribute the noise between the different processing blocks operating in the digital receiver.
i n

Assuming, for example, that the input signal has an SNR of 14dB and the minimum SNR required for the receiver is 12dB. The system can then degrade the signal by maximum 2dB, which has to be split between the different blocks. Assuming that the noise allocation for the ADC has been selected to be maximum 0.2dB (which means that the ADC can degrade the SNR by 0.2dB while all the other devices of the receiver can degrade the signal by the remaining 1.8dB), the SNR of the ADC has to be

TECHNICAL ARTICLE

- 10log (10 SNRi n 10

SNRi - 0.2 n 10

- 10 -

SNRi n 10

- 0.2 ) = - 10log (10 - 1410 - 10 - 14 10

- 0.2 ) = - 10log (10 - 1410 - 10 - 14 ) = 27.3dB 10

(1)

Where SNRin is the signal-to-noise ratio of the received signal. Note that the total SNR, in dB, allocated for the ADC is the combination of all its impairments (noise, harmonic distortion, and clock phase noise). The designer decides to split the ADC allocation equally between these three, making the individual specifications

Note that the input signal is most susceptible to additional noise at the very front of the receiver and it becomes less sensitive as it gets amplified. For this reason the majority of the receiver noise budget is allocated for the front-end blocks such as the low noise amplifier (LNA), and the back-end blocks such as the ADC or the digital blocks following usually receive a smaller noise allocation.

27.3 + 10 * log (3) - 32dB

(2)

The ADC signal-to-noise ratio should be specified for a single sine wave whose amplitude matches the full scale of the device which is affected by the ADC thermal and quantization noise across the whole Nyquist bandwidth. In a communication scenario we never receive pure sine waves, we have modulated sine waves that carry

Clock

Gain Control LNA VGA

Carrier Waveform X IF Stage ADC

Digital Back-End

Bits

Oscillator

RF Carrier

Figure 1: Block Diagram of a Digital Communication Receiver.

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TECHNICAL ARTICLE
the information we desire to transmit. For this reason the spectrum of the received signal is very different from the spectrum of a sine wave. Our goal is to understand how the ADC SNR allocation for a specified band-limited signal spectrum and the ADC SNR for a full-scale sine wave are related and how we can achieve the second one from the first one. In the following example, we consider a typical worstcase scenario for an ADC input signal which is composed of four equal-amplitude band limited channels and one weak band-limited channel which is the one we would like to detect. An example of this scenario is shown in Figure 3. The power of the strong channels places an upper bound on the dynamic range of the ADC while the noise and distortion from different sources limits it on the lower side. For calculating the ADC SNR allocation we need to know: Relative power of the ADC input channels Peak-to-average ratio (PAR) of the ADC input signal Bandwidth of the desired channel (bw) ADC sampling rate (fs) Composite (total) power of the ADC input signal The ADC is a hard limiter. If the input signal level exceeds the ADC code range either on the positive or negative side, the ADC output code is saturated to its maximum or minimum value. Once this clipping happens, the output signal value has a large error with major impact on the signal SNR. It is important to make sure that the input signal level is proper so that clipping doesnt happen too often. In order to avoid clipping the user needs to know the PAR of the input signal. This number is used as a back-off in the gain control loop which monitors the average signal level. For making sure that the input signal level is suitable for the ADC in most cases one or more variable gain amplifiers are embedded in the receiver before the ADC. The first important thing to do for specifying the ADC, in the sine waves case, is to compare the ADC full scale to the received signal level. Remember that we are assuming the input signal composed of five, equal bandwidth (bw=5MHz) channels; four of them having high power level and the desired channel having a power level which is 25dB below the others. We are also assuming that the PAR for this signal is 12dB while, as calculated before (see Eq.(2)), the ADC SNR allocation for the weak channel is 32dB and its sampling rate is fs=100MHz. The first step is to relate the amplitude level of the weak channel to the ADC full scale. The reasoning proceeds in this way: the signal composite power is 12dB below the ADC full scale (PAR), the power of each strong channel is 6dB below that (10log(4)=6) while the power of the weak channel is 25dB below that. In conclusion, the power of the weak power is 43dB below the ADC full scale (12+6+25). At this point we need to calculate the oversampling gain which takes care of the fact that in the case of a single sine wave the white noise that is spread over the entire Nyquist zone needs to be considered while in the real signal case only the noise falling in the signal bandwidth degrades its SNR. This is true because we assume that, in the digital domain, after the ADC, there is a filter that removes the noise outside the signal bandwidth.
0 -10 -20

TECHNICAL ARTICLE

Log Magnitude (dB)

-30 -40 -50 -60 -70 -80

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Frequency (Hz)
Figure 2: You should see something like this

The oversampling gain can be calculated by using the following formula:

10log (2bw/fs) = 10dB

(3)

By knowing the ADC SNR allocation (32dB), the amplitude of the weak signal relative to the full scale (- ( 43dB)), the oversampling gain (- 10dB) and the adjustment factor for PAR of a sinusoid (- 3dB) we can calculate the ADC SNR for a full scale sine wave: (32+43-10-3)dB=62dB. Usually RF designers work with noise figure (NF) instead of SNR, hence it is important to relate the just calculated

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signal-to-noise ratio to the noise figure. The noise figure is defined as the ratio of the total effective input noise power of the ADC to the amount of noise power caused by the source impedance alone, expressed in dB (see Equation (4)). most important unwanted harmonic components are the second and third order distortion components (generally referred as to IM2 and IM3). Typically the ADC linearity is specified using total-harmonic-distortion (THD) or using the levels of individual harmonics (HD2 and HD3, for instance). The ADC designer can simulate or measure these parameters with a single tone sinusoidal input signal test. A two-tone test is also commonly used and gives IM2 and IM3 specifications. However, the real world signals are different from sine waves; their PAR is much higher and for this reason those tests are not really accurate. Instead of IM2 and IM3, RF designers prefer to consider the second order intercept point (IIP2) and the third order intercept point (IIP3) whose relation with IM2 and IM3 is illustrated in Figure 3. The worst case scenario is most often the reception of a weak signal along with high power signals. In this case, we can set up the two-tone test by modeling the strong signals with two sine waves while the IM product lands on the weak desired signal channel; the fundamental question here is whether the peak of the sine wave should match the peak of the modulated signals or if it should match the rms. None of these two options is the correct one because the first one over-specifies the linearity requirements of the ADC while the second one gives a number that is not adequate for the real modulated signal. In most of the cases, a simulation is the best way for solving the issue. Sometimes the noise-power-ratio (NPR) test or the missing tone-power-ratio (MTPR) test are also performed which are more closely resembling many real world usage scenarios. However, the NPR test cannot be performed with commonly available sinusoidal signal sources and is often avoided for that reason. More details along with practical examples on this topic can
P[dB]
IIP2 IIP3

TECHNICAL ARTICLE

NF = 10log (1 + ( n n ) 2)
ADC

() 4

where nADC is the ADC noise which can be calculated by using Equation (5)

n ADC =

VADC 2 210 SnR 20

ADC

() 5

where VADC is the differential ADC full-scale and SNRADC is the ADC noise allocation for a single sine wave whose peak-to-peak amplitude fills exactly the ADC input range. The value of SNR ADC is usually shown on the data sheets for various input frequencies, then we have to make sure to use the value corresponding to the IF input frequency of interest. Also, we have to make sure that the harmonics of the fundamental signal are not included in the SNR number. The parameter n, in Equation (4) is the noise of the source impedance alone

n = kTBR

(6)

where k is the Boltzmanns constant, T is the temperature expresses in Kelvin, B=fs/2 and R is the impedance. Note that Equation (4) assumes that the input to the ADC is band-limited to fs/2 with a filter having a noise bandwidth equal to fs/2. Of course, it is possible to further band-limit the input signal which results in oversampling and process gain. LINEARITY SPECIFICATIONS Analog circuits generally have many different performance criteria so that the overall system performance meets the desired specifications. For analog-to-digital converters linearity is a very important issue to be taken care of. It strongly affects system performance. It is well known that if a sinusoidal waveform is applied to a linear time-varying system, the output will also be a sinusoidal waveform at the same frequency, but most likely with different magnitude and phase. However if the same input signal is applied to a non-linear system, the output signal will have frequency components at harmonics of the input waveform including the fundamental frequency. The

P[dB]

x x Pin 2x

x x

x 3x

IM2

Pin[dB]

Pin

IM3

Pin[dB]

Figure 3: Graphical Illustration for IIP2, IM2, IIP3 and IM3.

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CLOCK PHASE NOISE AND TIMING JITTER The displacements of the sampling clock edges from the ideal locations are called clock (or timing) jitter. The clock jitter can be random, originating from the noise of the clock generation circuit and the clock distribution network, or it can be systematic as a result of another signal coupling to the clock. However, it does not describe the spectral distribution of the clock error. For this reason it is sometimes preferable to use phase noise instead. When time jitter is considered, instead of phase noise, the noise is

TECHNICAL ARTICLE

Vn = Tjitter A (2r f) 1/2

The corresponding SNR is

(10) (11)

SNR = - 20 * log (2r fTjitter)

The phase noise can be defined as a spectral plot or as an integral of noise power spectral density over a specific frequency range around the carrier. Often the ADC sampling clock is generated using a phase-lockedloop (PLL). PLLs characteristic phase noise profile has a region of elevated noise floor around the carrier, where a majority of the noise power is concentrated. In many cases it makes sense to have separate specifications for the close-in phase noise and the noise outside this region. The phase noise power or power spectral density is usually expressed relative to the power of the carrier - 38dBc - 20 * log (1GHz/100MHz) + 3dB = - 55dBc in dBc. This way the unit of phase noise can be thought - 38dBcthe clock period. - 20 * log (1GHz/100MHz) + 3dB = - 55dBc (12) to be radians, and thus dependent on Phase noise is always specified at a certain carrier where -38dBc is the integrated single-side-band phase frequency, often at the output frequency of the PLL, and noise for the PLL. its value changes if the clock is divided down to a lower The ADC noise is frequency. The phase noise of a divided clock is:

In the following figure, we present a numerical example of ADC SNR when the input signal is a pure sine wave centered on 20MHz and the noise source considered is only the phase noise. The integrated single-side-band phase noise for the PLL is set to -38dBc at 1GHz. The ADC sampling clock (100MHz) is generated from this signal by dividing it by 10. In such a case, the phase noise profile of the clock appears around the sampled signal and its amplitude is (20*log(fsig/fclk)). This factor,when other noise sources are present, has to be scaled from the total ADC SNR. By applying Equation (7) with the numbers we selected for the numerical example we find that the DSB phase noise at ADC clock frequency is

(12

- 55dbc - 20 * log (100MHz / 20MHz)= - 69dBc (i.e. SNR - 55dbc - 20 * log (100MHz / 20MHz)= - 69dBc (i.e. SNR - 69dB) (13) Pdiv = PPLL + 20 * log (fdiv /fPLL) (7)
Note that this calculation can be done in one step skipping the intermediate passages:

The jitter is measured in seconds and the time being absolute, its jitter doesnt change when the clock - 38dBc - 20 * log (1GHz/20MHz) + 3dB = - 69dBc frequency is divided. Note that clock jitter and phase - 38dBc - the same noise are two different ways of describing 20 * log (1GHz/20MHz) + 3dB = - 69dBc (14) phenomena. Of course the same calculation can be done using the Integrated phase noise is specified either as single-sideband (SSB) or double-side-band (DSB). Generally phase noise is symmetric about the carrier and thus timing jitter instead of phase noise:

Tjitter = 10 -(38 - 3)/20 /6.28 * 1GHz = 3.8ps

(15) (16)

PDSB = PSSB + 3dB

The relation between integrated phase noise and clock jitter is expressed by Equation (9)

(8) SNR = 20log (2 * r * 20MHz * 3.8ps) = 69dB SNR = 20log (2 * r * 20MHz * 3.8ps) = 69dB (16)
The final result for both the phase noise and the timing jitter is the same as it should be. Note that when we consider a sine wave as an input signal, the noise power is considered to be spread over the whole Nyquist band.

Tjitter =

PDSB 1 * 2r fclk

(9)

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In practical situations, the received signal has a limited bandwidth, and only the noise fraction which is spread over this band needs to be considered. If the noise is spectrally white (which is usually the assumption with jitter) the over-sampling ratio (calculated in the previous section) can be used for obtaining the SNR. When the noise cannot be considered white (close-in phase noise of a PLL) this method cannot be used. This situation usually happens when the desired signal is close to a strong interferer or if it is bracket between more stronger interference signals. However, the sine waves are still very important in the designing process. In fact, if we have, at the input to the ADC, two signals, one much weaker than the other one, both 5MHz wide with 5MHz spacing and with the center frequency of the stronger channel being 25MHz. The SNR requirement for the weaker channel is 32dB, the stronger channel is 25dB higher in amplitude than the weaker one. The PLL driving the clock has an output frequency of 1GHz. In such a situation, by modeling the stronger channel with a sine wave at the center of its frequency range, as shown in Figure 4, we achieve an approximate phase noise specification which leads to the following requirement: the SSB phase noise integrated from 2.5MHz to 7.5MHz has to be less than 57dB (25+32) at 25MHz. The same calculation, specified at the 1GHz PLL frequency, leads to 57dB- 20*log(1000/25)=25dBc. However a more accurate jitter specification can be obtained only with a system simulation.
0
Ch0 - 5MHz Ch1 - 5MHz

TECHNICAL ARTICLE

-20

Log Magnitude (dB)

-40

-60

-80

-100

-120 0 5 10 15 20 25 30 35 40 45 50

Frequency (MHz)

Figure 4: Signal Modeled with Sine Waves.

REFERENCES [1] David A. Johns, Ken Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc. New York. [2] Mikko Waltari, How to Specify an ADC for a Digital Communication Receiver, Available on http://www. iqanalog.com/company/index.html [3] Mikko Waltari and Kari Halonen, Circuit Techniques for Low-Voltage and High-Speed A/D Converters, Kluwer Academic Publishers, 2002. About the Author

Elettra Venosa received the Laurea (BS/MS) degree (summa cum laude) in electrical engineering in January For the case of a weak desired signal bracket between 2007 from Seconda Universit degli Studi di Napoli, multiple stronger interference channels, we can consider Italy. In November 2010, she received her Ph.D. in the following numerical example: the interfering channels Telecommunication/DSP from Seconda Universit degli are 5MHz wide, the weak one centered at 15MHz and Studi di Napoli, Italy. From June 2008 to September others at 20, 25, 30, and 35MHz. The stronger channels 2008, she worked as a project manager for Kiranet are 25dB higher in amplitude than the weaker one. The s.r.l.- ICT Research Centre to develop an advanced ADC sampling rate is 100MHz and the SNR required at radio identification system for avionics, in collaboration the weak channel 32dB. The phase noise is assumed with the Italian Center for Aerospace Research (CIRA). white. In this case we model the channel with a single Currently, she is working as a system engineer in IQsine wave centered at the mean of the channel center Analog Corp., a semiconductor company located frequencies having power equal to the total power of the in San Diego, CA. Currently, she is also working as a four channels. Calculating again the jitter requirement postdoctoral researcher on multirate signal processing techniques for software defined radio design in the for this imaginary signal we obtain: department of Electrical and Computer Engineering at SNR = 32dB + 25dB + 10 * log (4) - 10 * log (5MHz/50MHz) = 53dB San Diego, CA. She is author San Diego State University, (17) 0 * log (4) - 10 * log (5MHz/50MHz) = 53dB (17) of the book, Software Radio Sampling Rate Selection, Design and Synchronization. -SNR -2.6

Tjitter =

10 20 10 = = 12ps 2r f 6.28 * 28.75MHz

5

(18)

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