SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY, KARACHI

Department of Computer Science 3rd Semester, Batch 2011 Spring Semester - Final Examination 2012

Logic Design & Switching Theory

Instructions: Attempt any Five Questions. Time Allowed: 3 Hrs. Question No. 8 is compulsory. Max. Marks: 60 All Questions carry equal marks. Draw neat & clean diagrams where necessary. Q1. (a) How many bits are required to represent the following decimal numbers? (i) 68 (ii) 81 (iii) 205 (b) Perform the following binary arithmetic. (i) 1101 + 1011 (ii) 1100 1001 (iii) 1001 X 110 (iv) 1100 100 (c) Convert the following decimal numbers to hexadecimal numbers. (i) 840 (ii) 95 Q2. (a) Switches arranged in the following figure, act like what type of logic gate?

(b) Given several two-input NAND and OR gates, draw how you would produce a four-input NAND gate? (c) Given an AND gate and inverters, draw how you would produce a NOR function? Q3. (a) Draw the logic circuit represented by each of the following expressions. (i) AB + CD (ii) (AB) + C (iii) A+B[C+D (B+C)] (b) Design the 8-input NAND gate using 2-input NAND gates and NOT gates. (c) Design the 8-input NAND gate using 2-input NAND gates, 2-input NOR gates, and NOT gates only if needed. Q4. (a) Demonstrate by means of truth tables the validity of the following identities: (i) De Morgans theorem for three variables: XYZ = X + Y + Z (ii) The second distributive law: X + YZ = (X + Y)(X + Z) (iii) XY + YZ + XZ = XY + YZ + XZ (b) Given that A B = 0 AND A + B = 1, use algebraic manipulation to prove that (A + C) (A + B) (B + C) = B C (c) Using De Morgans theorem, express the function F = ABC + BC + AB With only OR and complement operations. With only AND and complement operations.

(i) (ii)

Q5. (a) Using Boolean algebra, simplify the following expressions as much as possible.

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(i) (ii)

ABC + (A + B + C) + ABCD BD + B(D + E) + D(D + F) (b) Implement the expression X = (A + B +C) DE by using NAND logic. (c) Implement the expression X = ABC + (D + E) with NOR logic. Q6. (a) Convert the following Boolean expression into standard SOP form (i) AB + ABC + AC (ii) WXY + XYZ + WXY (b) Convert the following Boolean expression into standard POS form. (A + B + C) (B + C + D) (A + B + C + D) (X + Y) (Y + Z) (c) Convert the following POS expression into equivalent SOP expression (W+X+Y+Z)(W+X+Y+Z)(W+X+Y+Z)(W+X+Y+Z)(W+X+Y+Z) Q7. (a) Define an active-LOW input S-R latch; draw its diagram and a truth table. (b) Determine the Q output waveform, if the inputs shown in the following figure are applied to a Gated S-R latch, which initially RESET.

(c)Draw the circuit diagram of a half-adder and write down the equations for sum-bit and a carry-bit. Q8. (a) From the following truth table do the following (i) Write the un-simplified SOP expression. (ii) Write the un-simplified POS expression. C 0 0 0 0 1 1 1 1 Input B 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 Output X 1 1 0 1 1 1 0 0

(b) Use a Karnaughs map to simplify the SOP expression from part (a)(i) (c) Implement the following operations using NOR gates. Draw the neat and clean circuit diagrams. Also mention the output expression on each stage of the circuit: (i) OR (ii) AND (iii) NOR (iv) Negative-OR (v) XOR 31/05/2012 Page 2 of 2 Page 2/