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Achieving Timing Closure in FPGA Designs

Lattice Semiconductor Corporation 5555 NE Moore Court Hillsboro, OR 97124 (503) 268-8000 November 2008

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Copyright 2008 Lattice Semiconductor Corporation. This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machinereadable form without prior written consent from Lattice Semiconductor Corporation.

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Achieving Timing Closure in FPGA Designs

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Contents

Achieving Timing Closure in FPGA Designs

Introduction 1 Learning Objectives 1 Time to Complete this Tutorial 2 System Requirements 2 Windows and Linux/UNIX, Command Line Conventions 2 About the Tutorial Design 2 The Lattice Timing Closure Methodology 3 The Tutorial Process Flow 3 Preparing the Command-line Environment 5 Task 1: Perform Logic Synthesis 6 Logic Synthesis with Synplify 6 Task 2: Translate the Design 11 Create the Output Directories 11 Create a Logical Design Database File (.ngd) Command-line Summary 13

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Task 3: Create Timing and Location Constraints 14 Create a Logical Preference File (.lpf) 14 Run the Design Planner Spreadsheet View 14 Assign a Block Preference 15 Assign Clock Preferences 17 Assign I/O Timing Preferences 19 Create Location Preferences 22 Create a Physical Design Database File (.ncd) 23 Estimate Baseline Performance Timing 24 Command-line Summary 26 Task 4: Establish Baseline Performance 26 PAR Session 1: Run Initial Place and Route Command-line Summary 31 26

Task 5: Increase Place and Route Effort 33 PAR Session 2: Run PAR with a Higher fMAX Objective

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Achieving Timing Closure in FPGA Designs

Contents

PAR Session 3: Run PAR in Multi-Placement Mode 35 PAR Session 4: Run PAR with Multiple Routing Passes 38 Command-line Summary 39 Task 6: Floorplan for Performance 40 Prepare to Run the Design Planner from the Command Line Examine Critical Paths 41 Use Design Planning and Grouping 42 Summary Glossary 52 53 57 64 54 Recommended References 41

Appendix A: Logic Synthesis with Precision RTL

Appendix B: Command Line Interface Quick Reference

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Achieving Timing Closure in FPGA Designs

Introduction
This tutorial demonstrates techniques for optimizing your Lattice FPGA design to meet timing performance objectives. In the tasks of this tutorial, you will use the ispLEVER software to implement an HDL design and see the influence of map and place-and-route preferences, increased placement and routing effort, and floorplanning. You will analyze the primary clock domain of the design and establish a performance baseline. You will then push the system to meet a faster timing objective until it fails, after which you will apply techniques to try to meet timing closure if technically possible. This tutorial uses the command line interface, which gives you more flexibility for viewing and analyzing tutorial files and allows you to issue custom command sequences. Some of these features are not available from the ispLEVER Project Navigator GUI.

Learning Objectives
When you have completed this tutorial, you should be able to: Use the recommended methodology to meet timing objectives of your design specification Use utilization and timing reports to understand device implementations Influence map, place, and route to increase performance or minimize area utilization Examine critical paths Use scripts or batch files to process your design from the command line

Achieving Timing Closure in FPGA Designs

Achieving Timing Closure in FPGA Designs

Introduction

Use the Design Planner graphical point tool to define timing constraints and floorplan the design

Time to Complete this Tutorial


The time to complete this tutorial is about five hours.

System Requirements
The following software is required to complete the tutorial: ispLEVER software The following systems were used to implement the tutorial design and measure program run times. System: Microsoft Windows XP Version 2002, Service Pack 3 Computer: Intel Pentium processor, 3.4 GHz, 2.0 GB of RAM

Windows and Linux/UNIX, Command Line Conventions


Command line sequences in the tutorial use the Windows backslash (\) convention to indicate directory paths and delimiters. For Linux or UNIX platforms, substitute forward slashes (/).

About the Tutorial Design


The tutorial design is a small system-on-chip implementation that utilizes a RISC processor, a 2048x32 on-chip RAM, an SDR SDRAM memory controller, a development interface, and a traffic cop module. The module serves as an arbiter of the Wishbone on-chip bus that connects the components. Figure 1 shows a high-level block diagram of the system. The OpenRISC 1200 processor and Wishbone on-chip bus are both fully documented ASIC or FPGA IP cores that are available for free from the OpenCores organization. While the tutorial does not explore the functionality

Achieving Timing Closure in FPGA Designs

Achieving Timing Closure in FPGA Designs

Introduction

Figure 1: Tutorial Design

of the design, it does demonstrate the timing closure and optimization techniques that can be effectively used within the design. Note
The OpenRISC 1200 processor and the Wishbone interface are both active Open Source projects available from www.opencores.org and are covered by the GNU Lesser General Public License. They are freely available, freely usable and re-usable open source hardware. The SDR SDRAM Memory Controller is based on Lattice Reference Design 1010 and is covered by the permissions explained in the header section of the source files.

The Lattice Timing Closure Methodology


The tutorial follows the methods recommended by Lattice for achieving timing requirements. Figure 2 illustrates the sequence of steps used in this method.

The Tutorial Process Flow


The tutorial tasks examine a few key techniques used by Lattice Applications Engineering to meet timing objectives with ispLEVER programs. The techniques can provide (though not always) improved results. They are presented in an order that provides the quickest implementation with the largest performance benefit. Figure 6 on page 32 illustrates the process flow that establishes the designs baseline performance. In this flow you will translate the EDIF netlist, produced by logic synthesis, into the databases that the ispLEVER design tools require for map, place, route, and timing analysis.

Achieving Timing Closure in FPGA Designs

Achieving Timing Closure in FPGA Designs

Introduction

Figure 2: Lattice Timing Closure Methodology

The following overview describes each processor: edif2ngd A netlist reader tool that converts an EDIF 2 0 0 format netlist into a binary .ngo file. This file describes the design in terms of components and hierarchy. ngdbuild A build utility that combines one or more .ngo files and binds each design component of the design to a Lattice FPGA library primitive. This produces an .ngd logical design database. map A design mapper program that converts the logical components of the .ngd into device-specific physical components. This produces an .ncd physical design database. par A place and route (PAR) program that assigns the locations of physical components and adds routing to connect them. This produces a placed and routed .ncd file.

Achieving Timing Closure in FPGA Designs

Achieving Timing Closure in FPGA Designs

Introduction

trce A static timing analysis tool that you can run on an .ncd physical design with associated timing preferences to produce a timing report. Design Planner A design planning tool with a graphical user interface that helps you visualize design placement, routing, critical paths, and programming.

Preparing the Command-line Environment


This section shows how to set up the Windows or UNIX OS environment to run ispLEVER command line executables. To set Windows OS environment variables: 1. From the Start Menu, choose Settings > Control Panel > System. 2. Click the Advanced tab, and then click Environment Variables. 3. Select the variable PATH from the User variables for your system or from the System variables, and then click Edit. 4. Add the following path nodes to the Variable Value string: <drive>\<install_dir>; <drive>\<install_dir>\ispcpld\bin; <drive>\<install_dir>\ispfpga\bin\nt; where <drive> is the volume in which ispLEVER is installed and <install_dir> is the ispLEVER installation directory. For example, given a default installation of ispLEVER v7.2, add the path nodes as follows:
c:\ispTOOLS7_2;c:\ispTOOLS7_2\ispcpld\bin;c:\ispTOOLS7_2\isp FPGA\bin\nt;

5. Click OK to close the Edit System Variable dialog box. 6. Click OK to close the Environment Variables dialog box. 7. Clock OK to close the System Properties dialog box. Note
If your system includes an installation of Xilinx ISE software, you should ensure that the ispLEVER-related path nodes occur before the Xilinx-related path nodes. Both software systems use similarly named program executables such as ngdbuild, map, par, etc.

Achieving Timing Closure in FPGA Designs

Achieving Timing Closure in FPGA Designs

Task 1: Perform Logic Synthesis

Task 1: Perform Logic Synthesis


This tutorial gives you three options for synthesis: Create a netlist using Synplicity Synplify. If you prefer to use Synplify, proceed with the Task 1 instructions that follow. Create a netlist using Mentor Graphics Precision RTL Synthesis. If you prefer to use Precision, use the instructions provided in Appendix A: Logic Synthesis with Precision RTL on page 57, and then proceed to Task 2. Use the EDIF 2 0 0 netlist that is already provided in the timing_closure_tutor folder. If you prefer to use this netlist, skip to Task 2: Translate the Design on page 11.

Logic Synthesis with Synplify


Synplify synthesis produces a netlist file that uses .edn for the file name extension. To create a Synplify project and add the source files: 1. Create a new folder, Synplify, inside the timing closure tutorial directory, as follows: <drive>\<install_dir>\examples\Tutorial\timing_closure_tutor\Synplify 2. From the Start menu, choose Programs > Lattice Semiconductor > Accessories > Synplify Pro for Lattice. The Synplicity Synplify Pro for Lattice interface opens.

3. Choose File > New, and in the dialog box, select Project File (Project).

Achieving Timing Closure in FPGA Designs

Achieving Timing Closure in FPGA Designs

Task 1: Perform Logic Synthesis

4. Under File Location, click the browse button. 5. Click the down arrow at the top, next to Look In, and navigate to \<install_path>\examples\Tutorial\timing_closure_tutor. 6. Select the Synplify folder and click Choose to return to the New dialog box. 7. In the File Names text box, type ec_fpga_top and click OK. 8. Click the Add File button to open the Select Files to Add to Project dialog box. 9. Click the down arrow in the Look In box at the top and navigate to \<install_path>\examples\Tutorial\timing_closure_tutor\ dbg_interface Select all Verilog HDL (.v) files except dbg_defines.v and timescale.v. Click Add.

10. Navigate to the ..\timing_closure_tutor\onchip_ram folder. Select the two Verilog HDL (.v) files. Click Add. 11. Navigate to the ..\timing_closure_tutor\or1200 folder. Select all Verilog HDL (.v) files except or1200_defines.v. Click Add. 12. Navigate to the ..\timing_closure_tutor\sdr_sdram folder. Select all Verilog HDL (.v) files except sdr_par.v. Click Add. 13. Navigate to the ..\timing_closure_tutor\uart16550 folder. Select all Verilog HDL (.v) files except uart_defines.v and timescale.v. Click Add.

Achieving Timing Closure in FPGA Designs

Achieving Timing Closure in FPGA Designs

Task 1: Perform Logic Synthesis

14. Navigate to the ..\timing_closure_tutor folder. Select the ec_fpga_top.v and tc_top.v files. Click Add 15. Click OK. Note
If you want to preserve the original tutorial design files, copy the timing_closure_tutor directory to another location before proceeding.

To save the project: 1. In the Synplify main window, expand the Verilog folder. 2. Make sure that the ec_fpga_top.v file is listed last. If it is not, select it and drag it to the bottom of the list. 3. Choose File > Save. To select the settings: 1. Click the Implementation Options button on the left. 2. Click the Device tab and select the following settings: Technology: Lattice-ECP Part: LFECP10E Package: Q208C Speed: -4 3. Select the Constraints tab. Select the first option under Frequency (MHz) and type 66 in the text box. 4. Select the Implementation Results tab and verify that ec_fpga_top.edn is listed in the Results File Name box and that ..\Synplify\rev_1 is displayed as the Results directory. 5. Click OK. 6. Right-click the ec_fpga_top project in the main window and choose Compile Only. The Synplify software compiles the design based on the source files, targeted device, and settings you specified. To create a new SCOPE file: 1. Choose File > New. 2. Select Constraint File (Scope), and then type ec_fpga_top in the File Names box. 3. Under File Location, verify that the path name is correct for the Synplify folder and click OK.

Achieving Timing Closure in FPGA Designs

Achieving Timing Closure in FPGA Designs

Task 1: Perform Logic Synthesis

4. Click OK to accept the defaults in the Create a New Top-Level SCOPE File dialog box and open the SCOPE editor.

5. In the SCOPE editor, select the Clocks tab on the bottom left. 6. Enable the constraints for clk and jtag_tck by selecting these options in the Enable column. Specify the following in row 1: Clock: jtag_tck Frequency (MHz): 10 7. Specify the following in row 2: Clock: clk Frequency (MHz): 66 8. Select the Inputs/Outputs tab. 9. Select the options in the Enable column for rows 1 and 2. Specify the following in row 1: Port: <input default> Type: input delay Clock Edge: clk:r Value: 10 10. Specify the following in row 2: Port: <output default> Type: output delay Clock Edge: clk:r Value: 10 11. Choose File > Save and save the file as ec_fpga_top_1.sdc. Click Yes to add the file to the project. 12. Close the SCOPE Editor.

Achieving Timing Closure in FPGA Designs

Achieving Timing Closure in FPGA Designs

Task 1: Perform Logic Synthesis

To create the netlist and view the performance summary: 1. In the Synplify main window, click Run. Synplify creates an output EDIF netlist, ec_fpga_top.edn, for the implementation. When the process has completed, the name of the netlist appears in the rev_1 pane to the right. Note
This process might take several minutes to complete.

2. In the rev_1 pane, double-click ec_fpga_top.edn to open the netlist in a new tab. 3. Return to the ec_fpga_top.prj tab, and then double-click ec_fpga_top.srr to open the log file in a new tab. 4. Locate the Performance Summary section and notice the Estimated Frequency for clk.
Performance Summary ******************* Worst slack in design: -7.790 Requested Estimated Starting Clock Frequency Frequency ---------------------------------------------clk 66.0 MHz 32.2 MHz jtag_tck 10.0 MHz 41.1 MHz ==============================================

5. Choose File > Exit, and in the dialog box, click Yes to save your changes to the project. 6. Copy the ec_fpga_top.edn file from the Synplify\rev_1 folder and paste it in the \timing_closure_tutor folder.

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Achieving Timing Closure in FPGA Designs

Task 2: Translate the Design

Task 2: Translate the Design


In this task, you will create the output directories for the tutorial and you will translate the EDIF netlist produced by logic synthesis into a logical design database (.ngd).

Create the Output Directories


To prepare for these tasks, you will set up directories for map, and par. These directories will store the map and timing analysis information for numerous iterations. To make the needed directories using Windows OS: 1. From the Windows desktop, choose Start > Programs > Accessories > Command Prompt to open the Command Prompt window. Note
The exact location of the Command Prompt shortcut might vary from system to system. The following Command Prompt window properties are recommended for a Screen Area of 1280 by 1024: Font: Lucinda Console Font Size: 14 Layout Screen Buffer Size: Width 800, Height 600 Layout Window Size: Width 116, Height 53

2. Type the following command to change the directory to the tutorial design folder:
cd \<install_path>\examples\Tutorial\timing_closure_tutor

3. Type the following commands to make new directories in the tutorial design folder:
md md md md md map1\par1 map1\par2 map1\par3 map1\par4 map2

To make the needed directories using X-Windows: 1. Open a terminal. 2. Type the following command to change the directory to the tutorial design folder:
cd <install_path>/examples/Tutorial/timing_closure_tutor

3. Type the following commands to make the map directories:


mkdir map1 map2

4. Type the following commands to make the map1/par directories:


mkdir map1/par1 mkdir map1/par2

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Achieving Timing Closure in FPGA Designs

Task 2: Translate the Design

mkdir map1/par3 mkdir map1/par4

Create a Logical Design Database File (.ngd)


This procedure implements the two-part process of building the logical design database: the edif2ngd process converts the netlist file to an binary database file (.ngo), and the ngdbuild converts the .ngo to a logical design database (.ngd) file that can be used as input to mapping. To create an .ngd Logical Design Database File: 1. Type the following command at the command prompt:
edif2ngd

The netlist reader runs and reports copyright information and the basic usage information.
edif2ngd: version ispLever_v72_PROD_Build (35) Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. MachXO LatticeXP2 LatticeXP LatticeSCM LatticeSC LatticeECP2S LatticeECP2MS LatticeECP2M LatticeECP2 LatticeECP LatticeEC

2. Type the following command to convert the tutorial EDIF netlist into an NGO object file:
edif2ngd l LatticeECP ec_fpga_top.edf ec_fpga_top.ngo

Note
If you used Synplify for logic synthesis, the EDIF netlist is named ec_fpga_top.edn.

The netlist reader runs and creates an NGO object file in the local folder. 3. Type the following command to build an .ngd file:
ngdbuild -a LatticeECP p .\timing_closure_tutor ec_fpga_top.ngo ec_fpga_top.ngd > ngdbuild.log

The build tool runs and creates an .ngd file in the local folder.

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Achieving Timing Closure in FPGA Designs

Task 2: Translate the Design

4. Type the following command to run the ispLEVER Text Editor and open the log file:
synedit ngdbuild.log.

The log file opens in the Text Editor. The many warnings that appear are normal; most of them reflect loadless nets that result from unused carryout outputs of counters or the unused portions of memory arrays. It is good practice to examine these warnings since the nets and associated logic will be optimized away later. 5. In the Text Editor, choose File > Close to close the log file, but keep the Text Editor open.

Command-line Summary
The following ispLEVER command lines were issued in this task to process the tutorial design. To quickly create a batch or script file for the tutorial, copy the commands to a text file.
rem rem rem rem rem *********************************************************** ispLEVER Tutorial: Timing Closure of FPGA Designs Task 2: Translate the Design *********************************************************** rem Create an .ngd Logical Database File edif2ngd -l LatticeECP ec_fpga_top.edf ec_fpga_top.ngo ngdbuild -a LatticeECP -p .\timing_closure_tutor ec_fpga_top.ngo ec_fpga_top.ngd > ngdbuild.log

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Achieving Timing Closure in FPGA Designs

Task 3: Create Timing and Location Constraints

Task 3: Create Timing and Location Constraints


In this task, you will use the Spreadsheet View of the ispLEVER Design Planner to assign timing constraints that are considered essential for good placement and routing results and that will produce a complete static timing analysis. You will define constraints such as frequency, false paths, and I/O timing.You will then use the design mapper to produce a physical design database (.ncd), and you will run an early static timing analysis to estimate the maximum operating frequency and timing constraints.

Create a Logical Preference File (.lpf)


The logical preference file contains all the design constraints that are created after the build database process. Because you are using the command-line interface, you will need to create this file manually. To create the logical preference file (.lpf): 1. In the Text Editor, choose File > New to create a blank document. 2. Choose File > Save As and make sure that the timing_closure_tutor folder is shown as the targeted directory. 3. In the File Name box, type ec_fpga_top.lpf and click OK. 4. Choose File > Close but keep the Text Editor open. Logical preferences can be created and modified before and after mapping and after placement and routing. Saving logical preference changes to the .lpf file will ensure that they persist through repeated modifications and PAR iterations.

Run the Design Planner Spreadsheet View


The Pre-Map Design Planner provides a convenient spreadsheet view of preferences. The small Design Planner Control window that accompanies the Spreadsheet View allows you to hide and display this view. You should keep this Control window open throughout this task. To run the Design Planner Spreadsheet View: 1. Type the following command:
flmainappw

The Design Planner Control window opens. 2. Choose File > Open Design and browse to the following directory:
<install_path>\examples\Tutorial\timing_closure_tutor

3. Select ec_fpga_top.ngd, and click Open. The Device Selector dialog box appears. 4. Select the following options: Device: LFECP10E Speed Grade: -4

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Achieving Timing Closure in FPGA Designs

Task 3: Create Timing and Location Constraints

Package Type: PQFP208 Operation Conditions: Commercial 5. Click OK. Design Planner loads the logical design database (.ngd) of the tutorial design in Spreadsheet View and Package View. Keep the small Design Planner Control window open while you use Design Planner.

Assign a Block Preference


In this procedure, you will assign a BLOCK preference to the global reset of the system, rstn. When given a BLOCK preference, the ispLEVER system timing analysis skips the nets, paths, buses, and component pins that are not relevant to the synchronous timing of the design. To block asynchronous, false paths: 1. Maximize Spreadsheet View, and then choose Preference > Block Preference to open the dialog box. 2. In the Filter text box, type rst* and click Go.

3. Select rstn_c and click Add. Note


If you used Precision RTL for logic synthesis, the reset net is named rstn_int.

4. Click OK.

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Achieving Timing Closure in FPGA Designs

Task 3: Create Timing and Location Constraints

A BLOCK preference is defined for global Reset rstn_c and added to the list on the Block sheet in Spreadsheet View.

5. Select the Global tab. 6. Under Preference Value, double-click the box for Block Asynchpaths and choose ON from the menu. 7. Repeat Step 6 for Block Resetpaths and Block InterClock Domain Paths.

8. Choose File > Save to save the BLOCK preferences to the .lpf file. A BLOCK preference is set for all other potential asynchronous paths such as primary inputs and set/reset signals.

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Achieving Timing Closure in FPGA Designs

Task 3: Create Timing and Location Constraints

Assign Clock Preferences


In this procedure, you will assign frequency preferences to the primary clocks of the system, clk and jtag_tck. When given a frequency preference, the ispLEVER system infers a 50% dutycycle and a 1/FREQUENCY period clock. With these objectives, the place-and-route program (PAR) will attempt to optimize the levels and routing of logic between registers to achieve a period that is less than or equal to 1/FREQUENCY. Figure 3 illustrates the principle. Figure 3: Levels of Logic And Routing Between Registers

The bubble between REG1 and REG2 represents the logic and routing delay that will be optimized to meet the timing constraint. Later in this tutorial you will apply the technique of over-constraining clock frequency by 20% while pushing the effort of place and route. To create frequency preferences: 1. In Spreadsheet View, choose Preference > Period/Frequency to open the dialog box. 2. Select the following options: Type: FREQUENCY Second Type: Clock Port

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Achieving Timing Closure in FPGA Designs

Task 3: Create Timing and Location Constraints

The Available Clock Ports display is updated.

3. Select clock port clk. Specify 25 in the Frequency box and select MHz. Note
The target frequency is based on the estimate reported by logic synthesis.

4. Click Add. 5. Select clock port jtag_tck. Specify 10 in the Frequency box and select MHz. 6. Click Add, and then click OK. A FREQUENCY preference is defined for clock port clk and jtag_tck and added to the list on the Period/Frequency sheet. The 25 MHz objective for clk is a very conservative goal for the system based on the estimates reported by logic synthesis in Task 1 of the tutorial.

7. Choose File > Save to save the clock preferences to the .lpf.

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Achieving Timing Closure in FPGA Designs

Task 3: Create Timing and Location Constraints

Assign I/O Timing Preferences


In this procedure, you will assign I/O timing preferences to the primary I/Os of the system, an SDR SDRAM memory interface. Figure 4 illustrates the input setup principle, which is the amount of time required for the system interface bus, sdr_DQ, to be stable before the arrival of the clock edge. If you do not define this for PAR, the system will assume that the time is the same as the period of the clock. This might be far too pessimistic or optimistic, depending on the PCB trace delays that are involved. In this example, setup time (tSU) is defined as 10 ns, which accounts for both the combinational logic and the external delays of the device. Figure 4: I/O Timing Input Setup Example

The clock-to-output (tCO) delay is another recommended I/O timing preference. It defines the requirement for output signal validity after the arrival of the clock. If you do not specify this for PAR and static timing analysis, it will be completely unconstrained. In the tutorial design, sdr_DQ tCO is set to 10 ns, as shown in Figure 5. To group I/Os: 1. In the Spreadsheet View, choose Preference > Grouping Assignment to open the dialog box. 2. In the Group Name text box, type sdr_DQ. 3. In the Filter box under Available Ports, type sdr_DQ* and click GO. 4. Under Available Ports, select sdr_DQ_0 through sdr_DQ_3. Use the Shift key to select all four. 5. Click the > button to add these ports to the Selected Ports list. 6. Click the Add button to create the new group and add it to the Available Group List.

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Achieving Timing Closure in FPGA Designs

Task 3: Create Timing and Location Constraints

Figure 5: I/O Timing Clock-to-Output Example

7. Click OK. The sdr_DQ group is added to the Group Name list in the bottom left pane of the Spreadsheet View.

8. Choose File > Save to save the timing preferences to the .lpf. Creating group preferences is a convenient way to refer to collections of objects. In the next procedure, you will define tSU and tCO constraints relative to these groups of ports.

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Achieving Timing Closure in FPGA Designs

Task 3: Create Timing and Location Constraints

To create I/O timing preferences: 1. Choose Preference > Input_Setup/Clock_To_Out to open the dialog box.

2. Select the following options: Type: INPUT_SETUP Second Type: Group Time: 10 (ns) The Available Input Groups and Available Clock Ports/Nets lists are updated. 3. Select sdr_DQ from the Available Input Groups list. 4. Select clk from the Available Clock Ports/Nets list. 5. Click Add. The Existing Preference List is updated. 6. Select the following options: Type: CLOCK_TO_OUT Second Type: Group Time: 10 (ns) The Available Output Groups and Available Clock Ports/Nets lists are updated. 7. Select sdr_DQ from the Available Output Groups list. 8. Select clk from the Available Clock Ports/Nets list. 9. Click Add, and then click OK.

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Achieving Timing Closure in FPGA Designs

Task 3: Create Timing and Location Constraints

Key INPUT_SETUP and CLOCK_TO_OUT preferences are defined for the tutorial design and added to the list on the In/Out Clock sheet. 10. Choose File > Save to save the I/O timing preferences to the .lpf file.

Create Location Preferences


In this procedure, you will establish a set of I/O locations to reflect the typical scenario of a predefined PC board layout. To create location preferences: 1. In Spreadsheet View, choose the Port Attributes tab. 2. Click the Name column header to sort the pins alphabetically. 3. In the Name column, select sdr_A_0. 4. Press and hold the Shift key, scroll down, and click uart_stx to select a range of ports. 5. Right-click any selected cell and choose Assign Pins from the pop-up menu to open the dialog box.

The Assign Pins dialog box enables you to assign one or more ports to a selection of pin locations based on a set of filters. The right side of the dialog box controls the types of pins that are available based on the criteria you define, such as type, polarity, and order. 6. In the Pin Types panel, clear all pin types except I/O Only. 7. Under And polarity is, select Dont Care. 8. Select Auto Sort. Select Pin Number and Ascending in the Sort by panel and clear any other selections. 9. On the bottom left, select every from the Assign Pin drop-down menu.

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Achieving Timing Closure in FPGA Designs

Task 3: Create Timing and Location Constraints

The list of pins is adjusted based on the filters, and the pins to be assigned appear in bold type. The result is a selection of pins beginning with pin 7 and ascending to pin 58. 10. Click Check Pins to confirm that basic assignment rules are met, and then click OK to close the Information dialog box. 11. Click Assign Pins. Spreadsheet View is updated with the pin assignments and related banks. 12. Choose File > Save. 13. In the Design Planner Control window, choose File > Exit to close all windows of the Design Planner.

Create a Physical Design Database File (.ncd)


The map program uses the .ngd and .lpf files to create the physical database file, a network of device-specific component. It writes any new or modified preferences to the physical preference file (.prf). To create the .ncd physical database file: 1. Type the following command to run the design mapper on the .ngd and .lpf files:
map -a LatticeECP p LFECP10E t PQFP208 s 4 -m ec_fpga_top.ngd -o map1\map1.ncd ec_fpga_top.lpf > map1\map1.log

The options for MAP are summarized below:


-a <pmname> -p <device> -t -s -m Map to the LatticeECP architecture. Map to the specified device. Map to the specified package. Use the speed indicated. Create an .ncd even if the design exceeds the available resources. Output to the specified .ncd file name and directory.

-o

The design mapper converts the logical .ngd into a physical .ncd file and reports the results in the log file. 2. From the Text Editor, choose File Open and from the Files of type list, choose All Files. 3. Navigate to the map1\map1.log file, and click Open. The Text Editor loads the log file. The Design Summary, shown below, provides a preview of the relative amount of device resources required to accommodate the tutorial design.
Design Summary: Number of registers: 1802 PFU registers: 1781 PIO registers: 21

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Achieving Timing Closure in FPGA Designs

Task 3: Create Timing and Location Constraints

Number of SLICEs: 3391 out of 5120 (66%) SLICEs(logic/ROM): 3375 out of 3840 (88%) SLICEs(logic/ROM/RAM): 16 out of 1280 (1%) As RAM: 16 As Logic/ROM: 0 Number of logic LUT4s: 5035 Number of distributed RAM: 16 (32 LUT4s) Number of ripple logic: 218 (436 LUT4s) Number of shift registers: 0 Total number of LUT4s: 5503 Number of PIO sites used: 35 out of 147 (24%) Number of PIO FIXEDDELAY: 0 Number of 3-state buffers: 0 Number of DQSDLLs: 0 out of 2 (0%) Number of PLLs: 0 out of 4 (0%) Number of block RAMs: 12 out of 30 (40%) Number of GSRs: 1 out of 1 (100%) JTAG used : No Readback used : No Oscillator used : No Startup used : No

4. In the Text Editor, choose File > Close to close the log file, but keep the Text Editor open. Note
Each time you modify preferences in the .lpf file, you must remap the design to write the changes to the physical preference file (.prf).

Estimate Baseline Performance Timing


In this procedure, you will run the static timing analysis tool, TRACE, on the pre-route version of the design. This will enable you to determine the worstcase path that will influence the designs maximum operating frequency. In general, the results from pre-route static timing analysis will be approximately twice as fast as the routed version of the design. To estimate baseline performance timing: 1. Type the following command to run the static timing analysis tool on the pre-route .ncd file.
trce -c -o map1\map1.twr map1\map1.ncd -v 10 ec_fpga_top.prf

The options for TRACE are summarized below:


Report unconstrained connections. Report the ten worst-case paths per preference in a full (verbose) timing report. Specify the output file name.

-c -v 10

-o

For more details on command line options, see Appendix B: Command Line Interface Quick Reference on page 64.

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Achieving Timing Closure in FPGA Designs

Task 3: Create Timing and Location Constraints

TRACE runs, using the timing constraints you specified earlier, and reports the worst-case paths in the log file, map1.twr. 2. In the Text Editor, choose File > Open. In Files of Type, select All Files, navigate to the map1\map1.twr file, and click Open. 3. Use the Edit > Find command to locate each of the following major sections in the TRACE report: Preference: FREQUENCY PORT clk 25.000000 MHz ; Notice that the ten critical paths are presented in terms of both Logical and Physical details. In general, the longest paths related to clk are between the or1200_operandmuxes module and or1200_top. This review will provide a first hint of how to potentially floorplan the design for performance. Report Summary The Report Summary provides an estimate of the pre-route device timing. It shows the constraint defined by the preferences you set earlier in this task and the estimate generated by static timing analysis. Running TRACE immediately after the translation and design mapping phase gives you an early estimate of the designs timing characteristics and of what your baseline performance preferences should be. Routing accounts for approximately 70% of the delay in a heavily interconnected design, such as the one in this tutorial. TRACE reports ~ 134 MHz here; therefore, a good first objective is .3(130 MHz) = 40 MHz. Note The results above are based on the EDIF file (ec_fpga_top.edf) supplied with the tutorial. Your results might differ. Connections not covered by the preferences This section often illustrates unconstrained nets that can, when constrained, result in a more complete and accurate analysis by TRACE. Note
With no timing preferences defined, TRACE performs a default enumeration of the worst-case path.

One design mapping optimization that might improve design performance is register retiming. In the next step, you will enable this map option to see if the design can be adjusted. 4. In the Text Editor, choose File > Close to close the TRACE report, but keep the Text Editor open. 5. At the command prompt, type the following command to run the design mapper with the retime option on the .ngd file:
map -a LatticeECP -p LFECP10E -t PQFP208 -s 4 -m ec_fpga_top.ngd -o map2\map2.ncd ec_fpga_top.lpf -retime > map2\map2.log

The design mapper converts the logical .ngd file into a physical .ncd file and reports the results in the log file.

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Achieving Timing Closure in FPGA Designs

Task 4: Establish Baseline Performance

6. In the Text Editor, choose File > Open. In Files of Type, select Project Log Files, and navigate to the map2\map2.log file. 7. Notice the message regarding retiming near the top. The tutorial design might exhibit changes or it might not. If retiming occurs, a Retiming Report will summarize any adjustments made by the design mapper. You can confirm any performance benefit by running place and route and static timing analysis on the map2.ncd file. Notice that running TRACE on the pre-route design will not show any benefit from the netlist rebalancing performed by the retiming algorithm. 8. Choose File > Close and leave the Text Editor open.

Command-line Summary
The following ispLEVER command lines were issued in this task to process the tutorial design. To quickly create a batch or script file for the tutorial, copy the command to a text file.
rem rem rem rem rem ******************************************************** ispLEVER Tutorial: Timing Closure of FPGA Designs Task 3: Create Timing and Location Constraints ******************************************************** rem Create an .ncd Physical Database File map -a LatticeECP -p LFECP10E -t PQFP208 -s 4 -retime -m ec_fpga_top.ngd -o map2\map2.ncd ec_fpga_top.lpf > map2\map2.log rem Estimate Baseline Performance Timing trce -c -o map1\map1.twr map1\map1.ncd -v 10 ec_fpga_top.prf trce -c -o map2\map2.twr map2\map2.ncd -v 10 ec_fpga_top.prf

Task 4: Establish Baseline Performance


In this task, you will use the ispLEVER Place & Route program and the static timing analysis program TRACE to establish the tutorial designs baseline performance. You will compare the timing preferences defined earlier against the implementation results and determine which objectives were met or not met.

PAR Session 1: Run Initial Place and Route


In this session you will run place and route with a frequency goal of 25 MHz for the system clock, and then you will run static timing analysis with the current speed grade (-4). To run place and route and static timing analysis: 1. At the command prompt, type the following command to run PAR:
par -d 1 -i 6 -l 5 -n 1 -w map1\map1.ncd map1\par1\par1.ncd ec_fpga_top.prf

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Achieving Timing Closure in FPGA Designs

Task 4: Establish Baseline Performance

The following list summarizes the options for this PAR session:
-d 1 -i 6 -l 5 -n 1 -w Run one delay-based cleanup pass of the router. Run six iterations of the router. Run the placer at the maximum effort level. Run one iteration of the placer. Overwrite any existing files.

For more details on command-line options, see Appendix B: Command Line Interface Quick Reference on page 64. PAR uses the location and timing constraints you specified earlier and creates a placed and routed version of the tutorial .ncd file at map1\par1\par1.ncd. Note
This process might take 10-20 minutes.

2. From the Text Editor, choose File > Open. In Files of Type, select All Files, navigate to the map1\par1\par1.par file, and click Open. Near the beginning, the PAR report describes the physical resources, signals, and unique connections required to accommodate the tutorial design.
Device utilization summary: GSR IOLOGIC PIO (prelim) EBR MULT36 SLICE 1/1 21/288 35/288 35/147 12/30 1/5 3391/5120 100% 7% 12% 23% 40% 20% 66% used used used bonded used used used

Number of Signals: 7279 Number of Connections: 23442

Note The utilization summary above is based on the EDIF netlist supplied with the tutorial (ec_fpga_top.edf). Your results might differ. 3. Page down further in the PAR report and notice the routing assignments made by PAR for high fan-out signals such as clocks (clk load), set/ resets (sr load), and clock enables (ce load).

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Achieving Timing Closure in FPGA Designs

Task 4: Establish Baseline Performance

The primary and secondary clocking resources of the LatticeECP/EC architecture are used in these cases to provide the best performance.
Global Clock CLK_PIN PLL DCS Resources: : 3 out of 4 (75%) : 0 out of 4 (0%) : 0 out of 8 (0%)

Quadrants All (TL, TR, BL, BR) - Global Clocks: PRIMARY "clk_c" from comp "clk" on CLK_PIN site "180 (PT25A)", clk load = 964 PRIMARY "jtag_tck_c" from comp "jtag_tck" on CLK_PIN site "81 (PB25A)", clk load = 125 SECONDARY "or1200_top/or1200_cpu/N_660_i" from F0 on comp "or1200_top/or1200_cpu/SLICE_1892" on site "R29C27C", clk load = 0, ce load = 37, sr load = 0 SECONDARY "or1200_top/or1200_cpu/wb_freeze_i" from F1 on comp "or1200_top/or1200_cpu/SLICE_1928" on site "R11C26B", clk load = 0, ce load = 97, sr load = 0 SECONDARY "or1200_top/or1200_cpu/or1200_if/ un1_flushpipe_2_iZ0Z_0" from F0 on comp "or1200_top/ or1200_cpu/or1200_if/SLICE_2326" on site "R29C25A", clk load = 0, ce load = 34, sr load = 0 SECONDARY "jtag_trst_c" from comp "jtag_trst" on CLK_PIN site "139 (PR18A)", clk load = 0, ce load = 0, sr load = 121 PRIMARY : 2 out of 4 (50%) DCS : 0 out of 2 (0%) SECONDARY: 4 out of 4 (100%)

Note
If you used Precision for logic synthesis in Task 1, internal signals such as clk will appear as clk_int instead of clk_c.

4. Choose File > Close and leave the Text Editor open. 5. At the command prompt, type the following command to run TRACE:
trce -v 1 -o map1\par1\par1.twr map1\par1\par1.ncd ec_fpga_top.prf

The static timing analysis program runs using the timing constraints that you specified earlier. It creates a timing report file at map1\par1\par1.twr. 6. From the Text Editor, choose File > Open. In Files of Type, select All Files and navigate to the map1\par1\par1.twr file.

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Achieving Timing Closure in FPGA Designs

Task 4: Establish Baseline Performance

The Report Summary provides a report of the post-route device timing. Given the worst-case path between registers, the maximum operating frequency is ~28 MHz.

Report Summary ----------------------------------------------------------------------------------------Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------| | | FREQUENCY PORT "clk" 25.000000 MHz ; | 25.000 MHz| 28.406 MHz| 9 | | | FREQUENCY PORT "jtag_tck" 10.000000 MHz | | | ; | 10.000 MHz| 33.740 MHz| 8 | | | INPUT_SETUP GROUP "sdr_DQ" 10.000000 ns | | | CLKPORT "clk" ; | 10.000 ns| 3.313 ns| 1 | | | CLOCK_TO_OUT GROUP "sdr_DQ" 10.000000 | | | ns CLKPORT "clk" ; | 10.000 ns| 7.621 ns| 2 | | | ----------------------------------------------------------------------------

7. Locate the timing details for the FREQUENCY PORT clk preference and notice the following details about the report: The Logical Details section describes the worst case critical path that is limiting the speed of signal clk. The originating synchronous component in the example below is the onchip_ram_top, and the destination synchronous component is at the or1200_except module of the or1200 RISC processor. This information illustrates a path that crosses hierarchical boundaries, which can guide possible floorplanning of the design for better performance. The Physical Path Details section describes the same path in terms of LatticeECP/EC slice/PFU or IOLOGIC details. Each site along the path is described using the syntax:
R<row#>C<col#>.<pin_name> to R<row#>C<col#>.<pin_name>

The type of delay contributed by each element along the path appears in the list. Careful examination of the PAR and TRACE reports will help you decide how to improve performance with the least amount of time and effort. Did PAR apply primary and secondary routing resources to high-fan out signals? If not and the resources are available, then additional preferences such as USE PRIMARY might help. How does routing relative to logic contribute to the total delay? If routing accounts for more than 80%, then the design could benefit from additional placement and routing iterations. It might also benefit from careful manual floorplanning. Is a low number of critical paths limiting fMAX? If so, selective grouping of slices might lower routing distances.

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Achieving Timing Closure in FPGA Designs

Task 4: Establish Baseline Performance

================================================================================ Preference: FREQUENCY PORT "clk" 25.000000 MHz ; 4096 items scored, 0 timing errors detected. -------------------------------------------------------------------------------Passed: The following path meets requirements by 2.398ns Cell type Pin type Q Data in Cell/ASIC name (clock net +/-)

Logical Details:

Source: FF Destination: FF eearZ0Z_29 (to clk_c +) Delay: Constraint Details:

onchip_ram_top/ack_weZ0 (from clk_c -) or1200_top/or1200_cpu/or1200_except/

17.462ns

(16.0% logic, 84.0% route), 9 logic levels.

17.462ns physical path delay onchip_ram_top/SLICE_391 to or1200_top/or1200_cpu/ or1200_except/SLICE_487 meets 20.000ns delay constraint less 0.000ns skew and 0.140ns DIN_SET requirement (totaling 19.860ns) by 2.398ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --0.476 R23C35B.CLK to R23C35B.Q0 onchip_ram_top/SLICE_391 (from clk_c) ROUTE 6 1.137 R23C35B.Q0 to R18C35D.D0 onchip_ram_top_ack_we CTOF_DEL --0.289 R18C35D.D0 to R18C35D.F0 tc_top/t18_ch_upper/ SLICE_1440 ROUTE 11 1.820 R18C35D.F0 to R23C32B.A0 tc_top_t18_ch_upper_i4_out_0_0_0_1 CTOF_DEL --0.289 R23C32B.A0 to R23C32B.F0 or1200_top/SLICE_1875 ROUTE 15 1.028 R23C32B.F0 to R24C33B.C1 or1200_top/dcpu_ack_o_0x CTOF_DEL --0.289 R24C33B.C1 to R24C33B.F1 or1200_top/or1200_dc_top/ SLICE_1866 ROUTE 8 1.705 R24C33B.F1 to R14C34B.D1 or1200_top/dcpu_ack_dc CTOF_DEL --0.289 R14C34B.D1 to R14C34B.F1 or1200_top/or1200_cpu/ or1200_freeze/SLICE_1940 ROUTE 1 1.549 R14C34B.F1 to R11C26B.C1 or1200_top/or1200_cpu/ or1200_freeze/wb_freezeZ0Z_1 CTOF_DEL --0.289 R11C26B.C1 to R11C26B.F1 or1200_top/or1200_cpu/ SLICE_1928 ROUTE 139 5.149 R11C26B.F1 to R13C28A.D0 or1200_top/or1200_cpu/ wb_freeze_i CTOF_DEL --0.289 R13C28A.D0 to R13C28A.F0 or1200_top/or1200_cpu/ or1200_except/SLICE_1935 ROUTE 2 1.631 R13C28A.F0 to R13C28A.C1 or1200_top/or1200_cpu/ or1200_except/N_528 CTOF_DEL --0.289 R13C28A.C1 to R13C28A.F1 or1200_top/or1200_cpu/ or1200_except/SLICE_1935 ROUTE 1 0.655 R13C28A.F1 to R15C28A.C1 or1200_top/or1200_cpu/ or1200_except/N_640_0Z0Z_1 CTOF_DEL --0.289 R15C28A.C1 to R15C28A.F1 or1200_top/or1200_cpu/ or1200_except/SLICE_487 ROUTE 1 0.000 R15C28A.F1 to R15C28A.DI1 or1200_top/or1200_cpu/ or1200_except/N_803_iZ0 (to clk_c) -------17.462 (16.0% logic, 84.0% route), 9 logic levels. Achieving Timing Closure in FPGA Designs 30

Achieving Timing Closure in FPGA Designs

Task 4: Establish Baseline Performance

8. Choose File > Close and leave the Text Editor open. Note
Your results might vary.

Figure 6 illustrates the data files produced and processes that you have executed so far to implement the tutorial design. In the next task, you will perform the timing closure steps shown in Figure 2 on page 4 in an attempt to maximize the performance of the clock port clk.

Command-line Summary
The following ispLEVER commands were issued in this task to process the tutorial design. To quickly create a batch or script file for the tutorial, copy the commands to a text file.
rem rem rem rem rem *********************************************************** ispLEVER Tutorial: Timing Closure of FPGA Designs Task 4: Establish Baseline Performance *********************************************************** rem PAR Session 1: Initial PAR par -d 1 -i 6 -l 5 -n 1 -w map1\map1.ncd map1\par1\par1.ncd ec_fpga_top.prf trce -v 1 -o map1\par1\par1.twr map1\par1\par1.ncd ec_fpga_top.prf

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Achieving Timing Closure in FPGA Designs

Task 4: Establish Baseline Performance

Figure 6: Tutorial Process Flow Establishing Baseline Performance

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Achieving Timing Closure in FPGA Designs

Task 5: Increase Place and Route Effort

Task 5: Increase Place and Route Effort


In this task, you will use the command-line interface to run the place and route program PAR and the static timing analysis program TRACE. In a series of three PAR sessions, you will attempt to maximize fMAX of input clock clk using the following key techniques: Increase the frequency preference Apply five different seeds with the PAR placer algorithm Run ten routing passes on the best result of the multi-placement technique It is important to remember that although the tutorial design might not exhibit significant benefit from these procedures, your own design can significantly improve. These PAR techniques are the ones most commonly used by Lattice Applications Engineering, and they will result in the most benefit in the least amount of time.

PAR Session 2: Run PAR with a Higher fMAX Objective


In this PAR session, you will rerun place and route with a higher FREQUENCY preference objective (40 MHz), which will push PAR harder to exceed the baseline found at 25 MHz. The processes are shown in Figure 7. An increase of 20% or more in target frequency is often an effective technique to use with PAR. The session will also demonstrate how to examine the performance of the fastest (-5) speed grade LFECP10 device. Figure 7: Tutorial Process Flow Changing Target Clock Frequency and Speed Grade

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Achieving Timing Closure in FPGA Designs

Task 5: Increase Place and Route Effort

To run place and route with the higher fMAX: 1. From the Text Editor, choose File > Open. In Files of Type, select Logic Preference File (.lpf). 2. Navigate to the timing_closure_tutor folder, select ec_fpga_top.lpf, and click Open. 3. Modify the FREQUENCY PORT clk preference. Add the PAR_ADJ parameter as shown below.
FREQUENCY PORT CLK 25.000000 MHz PAR_ADJ 15;

The preference keyword PAR_ADJ uses the simple addition formula of 25 + 15 = 40 MHz to direct PAR while running TRACE on the 25MHz objective. 4. Choose File > Save, and then choose File > Close and keep the Text Editor open. 5. At the command prompt, type the following command to remap the design and apply the modified preference to the physical preference file:
map -a LatticeECP -p LFECP10E -t PQFP208 -s 4 -m ec_fpga_top.ngd -o map1\map1.ncd ec_fpga_top.lpf

6. Type the following command to run PAR:


par -d 1 -i 6 -l 5 -n 1 -w map1\map1.ncd map1\par2\par2.ncd ec_fpga_top.prf

The place and route program reruns the design with the higher target frequency and creates a placed and routed version of the tutorial .ncd at map1\par2\par2.ncd. Note
This process might take 10-20 minutes.

To run static timing analysis: 1. Type the following command to run TRACE:
trce -v 1 -o map1\par2\par2.twr map1\par2\par2.ncd ec_fpga_top.prf

The static timing analysis program runs, using the timing constraints you specified earlier, and creates a report file at map1\par2\par2.twr. 2. Type the following command to run TRACE using the -sp (speed grade) option:
trce -sp 5 -v 1 -o map1\par2\par2sp5.twr map1\par2\par2.ncd ec_fpga_top.prf

The static timing analysis program runs, using the fastest (-5) speed grade, and creates a report file at map1\par2\par2sp5.twr. 3. From the Text Editor, choose File > Open. In Files of Type, select All Files and navigate to the map1\par2 directory. 4. Select the par2.twr and par2sp5.twr files and click Open.

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Achieving Timing Closure in FPGA Designs

Task 5: Increase Place and Route Effort

5. Choose Window > Tile Horizontal to compare the reports, and examine the Report Summary section in each of these timing report files. The table below illustrates the differences between the last three static timing analysis results and the relative gains in fMAX.
F (max) par1.twr par2.twr par2sp5.twr clk=28.41 MHz clk=40.24 MHz clk=48.08 MHz % Gain Baseline 41.64% 69.24%

Note
Your results might vary from the tutorial. As an exercise, calculate the % gain, if any, between PAR sessions.

6. Choose File > Close All and keep the Text Editor open.

PAR Session 3: Run PAR in Multi-Placement Mode


The majority of delays associated with timing paths in FPGA designs are routing delays. In this PAR session, you will apply a technique for discovering a placement of components in the device floorplan that minimizes routing distances. The multi-placement mode of PAR allows up to 99 unique placement seeds that can be attempted for each run. In this session, you will rerun place and route in the multi-placement mode. You will then run static timing analysis with the five resultant .ncd output files, as shown in Figure 8. Figure 8: Tutorial Process Flow Multiple Placement Cost Tables

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Achieving Timing Closure in FPGA Designs

Task 5: Increase Place and Route Effort

Note
This session will take about one hour to complete using a 1.6 GHz PC with 500 MB of RAM. If the session is taking longer than you wish, use Ctrl+C in the command window. After a moment, PAR will be interrupted and you will be given the following options:

Continue processing and ignore the interrupt. Exit the program normally at the next check point. This will result in saving the best results so far after concluding the current processing. Exit the program immediately.
During a long multi-placement run, you might want to use the second option, which will allow you to save the immediate results for analysis.

To run PAR and TRACE: 1. Type the following command to run PAR:
par -d 1 -i 3 -l 5 -n 5 -s 5 -t 2 -w map1\map1.ncd map1\par3\par3.dir ec_fpga_top.prf

The options for this PAR session are summarized below:


Run one delay-based cleanup pass of the router. Run three iterations of the router. Run the placer at the maximum effort level. Run five iterations of the placer. Save five of the results from the run. Start at the second placer cost table entry. Overwrite any existing files.

-d 1 -i 3 -l 5 -n 5 -s 5 -t 2 -w

The additional controls produce five routed .ncd file results instead of the default of one. Each result uses a different cost table entryseed 2 through 6to guide the placer algorithm. Since the earlier runs of PAR used seed 1, the -t switch sets the new starting point at seed 2. The place and route program runs, using the location and timing constraints you specified earlier. It creates a placed and routed version of the tutorial .ncd at map1\par3\par3.dir. Notice the naming convention of the result files created by PAR: 5_2.ncd through 5_6.ncd. The number 5 indicates placer effort, and 2 through 6 indicates each seed. Since routing delay is the major cause of delay in most FPGA designs, a useful PAR strategy is to discover a placement of components in the device floorplan that minimizes routing distances. The multi-placement mode of PAR allows up to 99 unique placement seeds that can be attempted for each run. Notice the low number of routing passes (-i 3) applied for this run. This speeds the overall PAR runtime in this mode.

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Achieving Timing Closure in FPGA Designs

Task 5: Increase Place and Route Effort

2. Type the following command to run TRACE on each result of the multiplacement mode:
for /L %n in (2,1,6) do trce -v 1 -o map1\par3\par3.dir\5_%n.twr map1\par3\par3.dir\5_%n.ncd ec_fpga_top.prf

The static timing analysis program runs, using the timing constraints you specified earlier, and creates report files 5_2.twr through 5_6.twr at map1\par3\par3.dir. Note
For more information on the for command, see Windows online Help. Equivalent commands are available from the UNIX command line. Use the %% variable to carry out the for command within a batch program.

3. Type the following command to quickly examine the TRACE report files and determine the best result:
find MHz map1\par3\par3.dir\*.twr

Note
For more information on the find command, see Windows online Help. Equivalent commands are available from the UNIX command line.

Though multi-placement can be the most time-consuming mode for running PAR, it can also be the most effective in improving results. The following table illustrates the differences between the baseline performance and PAR Session 3.
F (max) par1.twr 5_2.twr 5_3.twr 5_4.twr 5_5.twr 5_6.twr clk=28.41 MHz clk=37.21 MHz clk=38.38 MHz clk=36.59 MHz clk=38.41 MHz clk=37.06 MHz % Gain Baseline +30.98% +35.09% +28.79% +35.20% +30.45%

The results are less than those from PAR Session 2 (40.24 MHz). The tutorial uses the best result of the multi-placement session to demonstrate the design flow. In practice, you might need to run more multi-placement seeds to find a better result. As an exercise, try additional PAR runs using the placer table flag (-t) to specify a starting point. Note
Your results might differ from those shown in the tutorial. As an exercise, calculate the % gain, if any, between placements.

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Achieving Timing Closure in FPGA Designs

Task 5: Increase Place and Route Effort

PAR Session 4: Run PAR with Multiple Routing Passes


In this PAR session, you will rerun the place and route program using the route-only mode. You will run ten routing iterations and five clean-up passes in an effort to improve the timing results using the -4 speed grade, as shown in Figure 9 The route-only (or reentrant) mode of PAR is also often useful on tough routing jobs where a lower number of passes has not resulted in a fully routed design. . Figure 9: Tutorial Process Flow PAR with Multiple Routing Passes

To run PAR and TRACE: 1. Type the following command to run place and route:
par -c 0 -d 5 -i 10 -k -p -w map1\par3\par3.dir\5_5.ncd map1\par4\par4.ncd ec_fpga_top.prf

The options for this PAR session are summarized below:


-c 0 -d 5 -i 10 -k -p Run no cost-based cleanup passes of the router. Run five delay-based cleanup passes of the router. Run ten iterations of the router Skip placement and begin routing, leaving the existing routing in place. Overwrite any existing files.

-w

The place and route process runs, using the location and timing constraints you specified earlier, and creates a placed and routed version of the tutorial .ncd at map1\par4\par4.ncd. Note
This process might take 10-15 minutes.

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Achieving Timing Closure in FPGA Designs

Task 5: Increase Place and Route Effort

2. Type the following commands to run TRACE:


trce -v 1 -o map1\par4\par4.twr map1\par4\par4.ncd ec_fpga_top.prf

The static timing analysis program runs, using the timing constraints you specified earlier, and creates a report file at map1\par4\par4.twr. 3. From the Text Editor, choose File > Open and navigate to the map1\par4\par4.twr file. 4. Examine the Report Summary section. The following table illustrates the differences between the baseline performance and PAR Session 4.
F (max) par1.twr par4.twr clk=28.41 MHz clk=38.41 MHz % Gain Baseline +35.20%

Note
Your results might differ from those shown in the tutorial. As an exercise, calculate the% gain, if any, between PAR sessions.

5. Choose File > Close and keep the Text Editor open.

Command-line Summary
The following ispLEVER command lines were issued in this task to process the tutorial design. To quickly create a batch or script file for the tutorial, copy the commands to a text file.
rem rem rem rem ********************************************************** ispLEVER Tutorial: Timing Closure of FPGA Designs Task 5: Increasing Place and Route Effort *********************************************************** rem PAR Session 2: Running PAR with a higher Fmax objective par -d 1 -i 6 -l 5 -n 1 -w map1\map1.ncd map1\par2\par2.ncd ec_fpga_top.prf trce -v 1 -o map1\par2\par2.twr map1\par2\par2.ncd ec_fpga_top.prf trce -sp 5 -v 1 -o map1\par2\par2sp5.twr map1\par2\par2.ncd ec_fpga_top.prf rem PAR Session 3: Running PAR in multi-placement mode par -d 1 -i 3 -l 5 -n 5 -s 5 -t 2 -w map1\map1.ncd map1\par3\par3.dir ec_fpga_top.prf for /L %%n in (2,1,6) do trce -v 1 -o map1\par3\par3.dir\5_%%n.twr map1\par3\par3.dir\5_%%n.ncd ec_fpga_top.prf rem PAR Session 4: Running PAR with multiple routing passes par -c 0 -d 5 -i 10 -k -p -w map1\par3\par3.dir\5_5.ncd map1\par4\par4.ncd ec_fpga_top.prf trce -v 1 -o map1\par4\par4.twr map1\par4\par4.ncd ec_fpga_top.prf

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Achieving Timing Closure in FPGA Designs

Task 6: Floorplan for Performance

Task 6: Floorplan for Performance


The performance of some FPGA designs can be improved with careful floorplanning. Floorplanning constraints override the automatic placement algorithms of the place and route program, PAR. The ispLEVER software provides flexible floorplanning constraints that support the placement of individual logic blocks to device sites as well as the grouping of logic blocks to minimize interconnect length. The ispLEVER universal group (UGROUP) preference enables you to group Slices and embedded blocks, such as sysMEM EBR and sysDSP, and constrain them to a particular area of the device floorplan. Slice-only groups can optionally float and be anchored by PAR automatically. Group constraints can be captured in two ways in the ispLEVER software: as preferences or HDL attributes. In this task you will use the Design Planner user interface to organize major modules of the tutorial design and produce a UGROUP of Slices. Lattice recommends the following technique for developing floorplan constraints: 1. Examine the TRACE report and look for obvious candidates for improving timing. If a few (< 5) critical paths are limiting fMAX, consider grouping the blocks along those paths using the universal group (UGROUP) preference. An important consideration is whether the critical path is really a true path or just a physical connection. If you can determine that the path is false, you can then safely treat it as a timing exception and block it using a preference. Use the Path Tracer utility of the Design Planner to quickly create a UGROUP of blocks along a critical path. 2. If it appears that the design can benefit from design planning on a moduleby-module basis, create dedicated areas of the device floorplan. Consider using REGION and UGROUP preferences, as well as bounding box (BBox), with the Design Planner. Rerun PAR and TRACE to confirm performance gains. 3. If the design benefits from floorplanning, create an HDL-based grouping attribute. Rewrite UGROUP preferences in terms of a UGROUP or HGROUP HDL attribute so that future HDL revisions will infer UGROUP preferences automatically. 4. Consider higher level floorplanning through logic synthesis. Note Before you attempt any floorplanning strategy, you should be aware of the stability of preferences that you define. The logic blocks that a preference refers to could easily be made obsolete from revision to revision of the designs HDL source code or EDIF netlist.

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Achieving Timing Closure in FPGA Designs

Task 6: Floorplan for Performance

The stability of group preferences are illustrated in the following table.

Stability Most More Least

Type Universal Group (UGROUP) or Hierarchical group (HGROUP) HDL attributes Universal Groups (UGROUPs) written in terms of premap (logical) blocks Placement Groups (PGROUPs) written in terms of postmap (physical) elements

Source HDL .lpf .prf

Prepare to Run the Design Planner from the Command Line


The Design Planner requires a common prefix name between the .ngd, .ncd, and .prf files. Use the following commands to create this organization from the files generated earlier in the tutorial:
md fp cd fp copy ..\ec_fpga_top.ngd copy ..\ec_fpga_top.lpf copy ..\ec_fpga_top.prf copy ..\map1\par4\par4.ncd ec_fpga_top.ncd

Examine Critical Paths


To report more critical paths: 1. Type the following command to produce a timing report of the 25 most critical paths.
trce -v 25 -o ec_fpga_top.twr ec_fpga_top.ncd ec_fpga_top.prf

2. Type the following command to quickly examine the TRACE report and determine the best results:
find Delay: *.twr

3. Scroll through the list of Delay values from the TRACE report. The first 25 are related to the clock port clk, and all are greater than 12 ns. This indicates that there is no clear candidate for floorplanning. 4. From the Text Editor, choose File Open. In Files of Type, select All Files, navigate to the fp directory, and select ec_fpga_top.twr. 5. Scroll through the critical paths reported. In this implementation from Synplify, a couple of different submodules emerge along the critical path: or1200_freeze and or1200_except.

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Achieving Timing Closure in FPGA Designs

Task 6: Floorplan for Performance

A portion of the ec_fpga_top.twr is reproduced below.


REG_DEL --0.476 R14C10C.CLK to (from clk_c) ROUTE 6 0.626 R14C10C.Q0 to CTOF_DEL --0.289 R14C9B.D0 to ROUTE 2 0.366 R14C9B.F0 to CTOF_DEL --0.289 R14C9B.C1 to ROUTE 2 0.366 R14C9B.F1 to dcpu_ack_o_0_LZ0Z5 CTOF_DEL --0.289 R14C9C.C0 to ROUTE 15 1.394 R14C9C.F0 to CTOF_DEL --0.289 R11C10D.C1 to SLICE_1866 ROUTE 8 0.602 R11C10D.F1 to CTOF_DEL --0.289 R11C11A.D1 to or1200_except/SLICE_2502 ROUTE 1 1.064 R11C11A.F1 to or1200_except/ex_pc_6_i_o2_2_m5_i_m7_i_LZ0Z6 CTOF_DEL --0.289 R14C12B.C1 to or1200_except/SLICE_1887 ROUTE 23 1.657 R14C12B.F1 to or1200_except/ex_pc_6_i_o2_2_m5_i_m7_i_LZ0Z10 CTOF_DEL --0.289 R11C17B.C1 to or1200_except/SLICE_548 ROUTE 8 1.116 R11C17B.F1 to flushpipe_r21 CTOF_DEL --0.289 R11C22B.C0 to SLICE_1892 ROUTE 37 2.847 R11C22B.F0 to N_660_i (to clk_c) R14C10C.Q0 onchip_ram_top/SLICE_391 R14C9B.D0 R14C9B.F0 R14C9B.C1 R14C9B.F1 R14C9C.C0 onchip_ram_top_ack_we SLICE_1726 tc_top_xi4_wb_ack_o SLICE_1726 or1200_top/or1200_dc_top/

R14C9C.F0 or1200_top/SLICE_1876 R11C10D.C1 or1200_top/dcpu_ack_o_0x_0 R11C10D.F1 or1200_top/or1200_dc_top/ R11C11A.D1 or1200_top/dcpu_ack_dc R11C11A.F1 or1200_top/or1200_cpu/ R14C12B.C1 or1200_top/or1200_cpu/ R14C12B.F1 or1200_top/or1200_cpu/ R11C17B.C1 or1200_top/or1200_cpu/ R11C17B.F1 or1200_top/or1200_cpu/ R11C22B.C0 or1200_top/or1200_cpu/ R11C22B.F0 or1200_top/or1200_cpu/ R12C13D.CE or1200_top/or1200_cpu/

Notice the ROUTE names that begin with or1200_top/or1200_cpu. This is a branch of the Verilog module for the OpenRISC 1200 portion of the tutorial design, as shown in Figure 1 on page 3. 6. Choose File > Close and keep the Text Editor open.

Use Design Planning and Grouping


Design planning and grouping can in some cases improve a designs performance. This strategy tends to work best with datapath style logic. In this next procedure, you will attempt to guide placement based on a portion of the or1200_top module. You will examine branches of the design hierarchy and critical paths using the Design Planner GUI.

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Achieving Timing Closure in FPGA Designs

Task 6: Floorplan for Performance

To examine a critical path: 1. Type the following command to run the ispLEVER post-map Design Planner:
flmainappw -inp ec_fpga_top.ncd -dir <install>\examples\Tutorial\timing_closure_tutor\fp -prj ec_fpga_top -lpf ec_fpga_top.lpf -prf ec_fpga_top.prf

Tip
The post-map Design Planner command line requires a drive specification with the -dir switch. For example, -dir c:\ispTOOLS7_2\examples\tutorial\timing_closure_tutor\fp As an alternative, you can simply type the flmainappw command and open the ec_fpga_top.ncd file directly from the Design Planner GUI. You can then open the different views from the View menu.

The Design Planner application opens, showing the Design Planner Control. It then opens the Floorplan View, Post-Mapped View, Package View, and Pre-Mapped View. Note
If any of the views do not open, choose View > Default Window Layout from the Design Planner Control window.

2. Maximize the Floorplan View window. Press F6 to fit the floorplan layout in the maximized window, and then choose Tools > Path Tracer. 3. From the Path Tracer, click Query.

4. In the Timing Query dialog box, select FREQUENCY PORT clk 25.000000 MHz0 PAR_ADJ 15 from the list and click Query.

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Achieving Timing Closure in FPGA Designs

Task 6: Floorplan for Performance

The Path Tracer displays a list of combinatorial paths.

5. Click the highlight color of the topmost row to open the Change Display Color dialog box. 6. Select the white color, which will provide the best contrast, and click OK.

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Achieving Timing Closure in FPGA Designs

Task 6: Floorplan for Performance

7. With the top row still selected, click Locate, and then select the Floorplan View window if it is not visible.

The related slices along the path are highlighted with the color white in the Floorplan View, and a flywire indicates the logical connection. Note
The appearance of the Floorplan View layout on your computer might vary from the one shown.

8. From Floorplan View, click the Physical View

button on the toolbar.

The Physical View opens and displays the related path and the physical routes related to the connection.

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Achieving Timing Closure in FPGA Designs

Task 6: Floorplan for Performance

To better view the delay path, choose Layer, and turn off Routes.

Note
If the related path is not displayed, choose Layer and make sure that Delay Path is selected. The appearance of the Physical View on your computer might vary from the one shown.

9. Return to Floorplan View and click the Show Delay Path button turn off the path display.

to

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Achieving Timing Closure in FPGA Designs

Task 6: Floorplan for Performance

To examine the design hierarchy: 1. From the Design Planner Control choose View > Pre-Mapped View.

2. Expand the Instances folder, and then scroll down to the or1200_top (LOGIC: 2293) folder and expand it. Notice the LOGIC: 2293 summary of the Slice utilization within this branch. 3. Expand the Instances folder within the or1200_top (LOGIC: 2293) folder. 4. Locate the or1200_cpu (LOGIC: 2018) folder and expand the Instances folder within it. 5. Locate the or1200_except (LOGIC: 308) folder, right-click it, and choose Locate > Floorplan View.

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Achieving Timing Closure in FPGA Designs

Task 6: Floorplan for Performance

The selected elements are highlighted in Floorplan View.

6. From Floorplan View choose View > Highlight > Light Blue. The physical elements related to the or1200_except submodule of the design are highlighted in light blue. 7. In Pre-Mapped View, right-click the or1200_freeze (LOGIC: 29) folder and choose Locate > Floorplan View. The selected elements are highlighted in Floorplan View. 8. From Floorplan View choose View > Highlight > Green. The physical elements related to the or1200_freeze submodule of the design are highlighted in green. With this view, you can now determine where your original logic has been placed, the relative amount of logic required for each branch, and where the critical path is relative to these resources. In the next procedure, you will create a user group (UGROUP) in an effort to improve the performance of the modules. The best organization comes from careful analysis of your HDL design. Many times the RTL views provided by your synthesis tool will help you visualize datapaths and modules that are good candidates for grouping. To create a logical group (UGROUP): 1. In Pre-Mapped View, use Ctrl+Click to select the following modules from the or1200_cpu (LOGIC: 2018) folder: or1200_except (LOGIC: 308)

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Achieving Timing Closure in FPGA Designs

Task 6: Floorplan for Performance

or1200_freeze (LOGIC: 29) 2. Right-click the selected modules and choose new UGROUP. 3. In the New UGROUP dialog box select the BBox option.

4. Specify 10 for Height and 15 for Width and click OK. Expand Ugroup in the Group/Module/Region pane of Pre-Mapped View and you will see the newly created Group_0. Group_0 instructs PAR to place all the logic from the selected modules into a 15 x 10 area (150 PFUs = 600 slices) of the floorplan. One or more logic components will be assigned to a slice by the design mapper (map). The 600 slices should be more than enough to accommodate the 337 logic components reported in the Pre-Mapped Logical Netlist View (or1200_except (LOGIC: 308) + or1200_freeze (LOGIC: 29). Lattice recommends that you add a bounding box (BBox) attribute with 20% additional area beyond the minimum required to accommodate the logic. You can estimate the necessary resources based on the notation (LOGIC: n) next to each module. With no BBox attribute defined, PAR will pack the group into the smallest square boundary (height=width) required to accommodate the physical resources. If embedded memory is part of a group, you should ensure that the group is anchored and overlaps enough sysMEM blocks of the device. Tip A quick way to help you visualize and calculate the size and height/width ratio for a UGROUP BBox is to create a group in Floorplan View. Right-click an empty space in Floorplan View and choose Create GROUP from the pop-up menu. Draw the area by dragging your mouse. Right-click the new group and choose Group Property. Review the GROUP definition. The size and number of resources encompassed by the BBox are reported. Edit the BBox as needed, and optionally, the anchor point. The new group is listed in Pre-Mapped View. In Pre-Mapped View, drag the modules from the design tree over to the new UGROUP.

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Achieving Timing Closure in FPGA Designs

Task 6: Floorplan for Performance

5. In Pre-Mapped View, choose File > Save. The Design Planner saves the new UGROUP to the logical preference file, ec_fpga_top.lpf. It will be written to the physical preference file with the next mapping process. When you issue the Save command in any Design Planner window, the Save icon is dimmed in all windows, including the Design Planner Control. 6. From the Design Planner Control, choose File > Exit. The Design Planner Control closes all windows. To rerun map and place & route with the new module group: 1. At the command prompt, type the following command to run the design mapper on the .ngd file:
map -a LatticeECP p LFECP10E t PQFP208 s 4 m ec_fpga_top.ngd -o fp.ncd ec_fpga_top.lpf

The mapper runs the design and applies the changes. 2. From the Text Editor choose File > Open. In the Files of type box, choose Preference Language File (.prf), select the ec_fpga_top.prf file, and click Open. 3. Notice the group_0 placement group (PGROUP) produced by the design mapper based on the UGROUP you created:
PGROUP COMP COMP COMP : "Group_0" BBOX 10 15 DEVSIZE "or1200_top/or1200_cpu/SLICE_405" "or1200_top/or1200_cpu/or1200_except/SLICE_473" "or1200_top/or1200_cpu/or1200_except/SLICE_474"

4. Close the Text Editor. 5. At the command prompt, type the following command to run PAR:
par -d 1 -i 6 -l 5 -n 1 -w fp.ncd ec_fpga_top.ncd ec_fpga_top.prf

The place and route program runs, using the location and timing constraints you specified earlier, and creates a placed and routed version of the tutorial .ncd at ec_fpga_top.ncd. Note
This process might take 15-20 minutes.

6. Type the following command to produce a timing report of the 25 most critical paths:
trce -v 25 -o ec_fpga_top_fp.twr ec_fpga_top.ncd ec_fpga_top.prf

7. Type the following command to quickly examine the TRACE report and determine the best result:
find Delay: *.twr

8. Scroll through the list of Delay values from the TRACE report.

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Achieving Timing Closure in FPGA Designs

Task 6: Floorplan for Performance

A new set of critical paths appears, and many paths are over 12 ns. In this case, the grouping constraint has not improved performance. Additional grouping and anchoring might be required in this design to arrive at a floorplan that is superior to what the automatic placement tools can produce. If you wish, experiment with the Group_0 BBox boundary. Set an anchor point for Group_0 to see how position and shape might influence timing. You can use the Design Planner to make changes to the UGROUP (logical). When you adjust a UGROUP, remember to rerun MAP and PAR. If you are able to discover a better result, you might wish to migrate the UGROUP into your HDL source code. A portion of the Verilog source for the or1200_cpu module (or1200_cpu.v) is shown below for your reference. Precision RTL syntax appears as a comment following the module instance (/ /pragma); Synplify syntax appears before the ending semicolon of the module instance (/* synthesis*).
// // Instantiation of load/store unit // or1200_lsu or1200_lsu( .addrbase(operand_a), .addrofs(lsu_addrofs), .lsu_op(lsu_op), .lsu_datain(operand_b), .lsu_dataout(lsu_dataout), .lsu_stall(lsu_stall), .lsu_unstall(lsu_unstall), .du_stall(du_stall), .except_align(except_align), .except_dtlbmiss(except_dtlbmiss), .except_dmmufault(except_dmmufault), .except_dbuserr(except_dbuserr), .dcpu_adr_o(dcpu_adr_o), .dcpu_cycstb_o(dcpu_cycstb_o), .dcpu_we_o(dcpu_we_o), .dcpu_sel_o(dcpu_sel_o), .dcpu_tag_o(dcpu_tag_o), .dcpu_dat_o(dcpu_dat_o), .dcpu_dat_i(dcpu_dat_i), .dcpu_ack_i(dcpu_ack_i), .dcpu_rty_i(dcpu_rty_i), .dcpu_err_i(dcpu_err_i), .dcpu_tag_i(dcpu_tag_i) ) /* synthesis UGroup=group_0 PBBox=10,15 */; //pragma attribute or1200_lsu UGroup group_0 //pragma attribute or1200_lsu PBBox 10,15

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Achieving Timing Closure in FPGA Designs

Summary

Summary
In this tutorial you have learned how to do the following: Use the methodology recommended by Lattice to meet the timing objectives of your design specification. Review and understand device implementations reports such as logic utilization and static timing results. Use a combination of preferences and controls to influence map, place, and route to increase performance. Examine critical paths and logic utilization from the perspective of the device floorplan. Use scripts or batch files to process your design from the command line. Use the ispLEVER Design Planner graphical point tool to define timing constraints and floorplan the design. Use both logical and physical preferences to establish timing and location constraints.

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Achieving Timing Closure in FPGA Designs

Recommended References

Recommended References
You will find more useful information about timing closure in the ispLEVER online Help and the Lattice FPGA Design Guide. The following recommended references are available with the ispLEVER software. Lattice FPGA Design Guide HDL Synthesis Coding Guidelines Strategies for Timing Closure ispLEVER Online Help > FPGA and Crossover Design Running FPGA Tools from the Command Line Design Implementation Design Verification LatticeECP/EC sysIO Usage Guide. LatticeSC PURESPEED I/O Usage Guide. Design Planner Online Help

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Achieving Timing Closure in FPGA Designs

Glossary

Glossary
The following are the terms and concepts that you should understand in order to use this tutorial most effectively. bank An organization of LatticeECP/EC/XP sysIO buffers arranged around the periphery of the device. clock tree or clock spine A clock distribution network in the LatticeECP/ EC/XP device architecture used for high-fanout signals. clock-to-out delay (tCO) The time it takes for a signal to go from the primary input pin through the clock of the flip-flops or gate of latches to the primary output pin. critical path The path through a circuit that determines the maximum speed at which the circuit can operate. The critical path is a signal in a section of combinatorial logic that limits the speed of the logic. Storage elements begin and end a critical path, which might include I/O pads. edif2ngd The ispLEVER translation program that converts EDIF 2 0 0 format netlists into the Lattice NGO object format. embedded block RAM (EBR) A large dedicated fast memory block in the LatticeECP/EC/XP device architecture. fMAX The symbol for the maximum operating frequency expressed in hertz units. Clock frequency is the number of complete clock cycles that occur per unit of time. For example, a 50- MHz clock signal will cycle 50 million times per second. The maximum frequency is a function of the longest combinatorial delay between registered elements. HGROUP An attribute in the HDL code that groups blocks of logic or library components in an FPGA design. HGROUP attributes are expanded into UGROUPs in the Build Database process and can be viewed in the Design Planner. When modified by the Design Planner, they are written to the logical preference file. These groups are then translated by the design mapper into PGROUP preferences in terms of physical components (slices) for the placement and routing process. The design mapper includes a hierarchy identifier for each PGROUP preference, which enforces strict hierarchical control. IOLOGIC A representation of PIO logic within a PIC block that is generated by the ispLEVER Design Planner tool. Look-up table (LUT) An architectural element within a LatticeECP/EC/XP PFU for implementing combinational logic or memory. Manhattan routing A representation of the physical routing interconnect among slices in which the routing is rectilinear. MAP The ispLEVER design mapper program.

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Achieving Timing Closure in FPGA Designs

Glossary

.ncd file A binary format FPGA post-map physical design database file generated by the map program or Map Design process of the Project Navigator. The .ncd file includes mapped and potentially placement and route information. .ngd file A binary format FPGA pre-map logical design database file generated by the EDIF2.NGD/NGDBuild programs or by the Build Database process in the Project Navigator. The .ngd file represents the logical design information of the ASCII EDIF netlist. ngdbuild The ispLEVER program that merges NGO object files into a single logical database (.ngd). PAR The ispLEVER place and route program.

PGROUP (Placement Group) A preference that establishes a partition of physical components. It is typically used to guide the placer algorithm of PAR. programmable function without RAM/ROM (PFF) contain a RAM. A PFU that does not

programmable function unit (PFU) A block within the LatticeECP/EC device that implements combinational logic, memory, and registers. The core of the architecture consists of PFU blocks that can be programmed to perform logic, arithmetic, distributed RAM, and distributed ROM functions. programmable I/O cell (PIO) An architectural element within an FPGA that handles actual input-output functions. It includes the I/O registers, tristate registers, and control multiplexers of a PIC. programmable interface cell (PIC) A cell within a LatticeECP/EC device architecture that contains a group of two PIOs. The edges of the architecture consist of PIC blocks that contain two PIOs connected to sysIO buffers. PICs provide high-speed I/O registers and buffering to support a variety of signal interface standards. slice An architectural element within an FPGA consisting of two LUT4 lookup tables that feed two registers (programmed to be in FF or latch mode), and some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. It also includes control logic to perform set/reset functions (programmable as synchronous/ asynchronous), clock select, chip-select and wider RAM/ROM functions. The registers in the slice can be configured for positive or negative and edge or level clocks. There are four interconnected slices per PFU block. Each slice in a PFU is capable of four modes of operation: logic, ripple, RAM, and ROM. Each slice in the PFF is capable of all modes except RAM. TRACE (trce) The ispLEVER static timing analysis program.

UGROUP (Universal Group) An attribute that establishes a partition of logical components within the EDIF netlist. The UGROUP attribute is used for grouping blocks of logic or library components in different hierarchies or no hierarchy. UGROUPs are converted into PGROUPs (placement groups) by

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Achieving Timing Closure in FPGA Designs

Glossary

the mapping process (map) and are typically used to guide the placer algorithm of PAR.

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Achieving Timing Closure in FPGA Designs

Appendix A: Logic Synthesis with Precision RTL

Appendix A: Logic Synthesis with Precision RTL


Use the following procedure to synthesize the design using Precision RTL synthesis. To create a Precision RTL project: 1. From the Start menu, choose Programs > Lattice Semiconductor > Accessories > Precision RTL Synthesis. The Mentor Graphics Precision Transcript Window opens.

2. Choose File > New Project. 3. In the New Project dialog box, specify ec_fpga_top as the project name. 4. Click the browse button and navigate to <drive>\<install_dir>\examples\Tutorial\timing_closure _tutor\PrecisionRTL. 5. Click OK to close the browse dialog box, and click OK again to save the new project. To add the input files to the project: 1. Make sure that the Design Center tab is selected, and then add the dbg_interface files as follows: Right-click the Input Files folder and choose Add Input Files. Navigate to the ..\timing_closure_tutor\dbg_interface folder. Select all Verilog HDL (.v) files except dbg_defines.v and timescale.v.

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Appendix A: Logic Synthesis with Precision RTL

Click Open. 2. Add the onchip_ram files: Right-click the Input File folder and choose Add Input Files. Navigate to the ..\timing_closure_tutor\onchip_ram folder. Select the two Verilog HDL (.v) files. Click Open. 3. Add the or1200 files: Right-click the Input File folder and choose Add Input Files. Navigate to the ..\timing_closure_tutor\or1200 folder. Select all Verilog HDL (.v) files except or1200_defines.v. Click Open. 4. Add the sdr_sdram files: Right-click the Input File folder and choose Add Input Files. Navigate to the ..\timing_closure_tutor\sdr_sdram folder. Select all Verilog HDL (.v) files except sdr_par.v. Click Open. 5. Add the uart16550 files: Right-click the Input File folder and choose Add Input Files. Navigate to the ..\timing_closure_tutor\uart16550 folder. Select all Verilog HDL (.v) files except timescale.v and uart_defines.v. Click Open. 6. Add the remaining files: Right-click the Input File folder and choose Add Input Files. Navigate to the ..\timing_closure_tutor folder. Select the ec_fpga_top.v and tc_top.v files. Click Open. To specify the input file search path for the design files: 1. Choose Tools > Set Options.

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Achieving Timing Closure in FPGA Designs

Appendix A: Logic Synthesis with Precision RTL

2. In the Options dialog box, select Input in the left pane. In the right pane, click the open folder button next to Input File Search Path.

3. In the dialog box, select the timing_closure_tutor folder and click OK. The folder is added to the Input File Search Path list.

4. Repeat Steps 2 and 3 for the following sub-folders: dbg_interface onchip_ram or1200 sdr_sdram uart16550 5. Click OK to accept the sub-folder list. These search paths enable Precision RTL to locate files referred to by the Verilog include compiler directives within sub-modules of the SoC design.

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Achieving Timing Closure in FPGA Designs

Appendix A: Logic Synthesis with Precision RTL

To set up and compile the design: 1. In the Design pane on the left, click Setup Design to open the Project Settings dialog box. 2. Double-click Lattice in the Technology pane, and select Lattice ECP.

3. Select the following settings: Device: LFECP10E Speed Grade: 4 Package: PQFP208 Design Frequency Set Frequency: 66 I/O Constraints Set Delay Input Delay: 10 I/O Constraints Set Delay Output Delay: 10 4. Click OK. 5. In the Design pane, click Compile. The Precision software reads the input files and compiles the design based on the source files, targeted device, and settings.

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Achieving Timing Closure in FPGA Designs

Appendix A: Logic Synthesis with Precision RTL

To set constraints and synthesize the design: 1. Select the Design Center tab. 2. In the Design Hierarchy pane, expand the Clocks folder.

3. Perform the following steps: Right-click clk and select Set Clock Constraints to open the Clock Constraints: Port-clk dialog box.

Specify 15.15 for Period and click OK. Right-click jtag_tck and select Set Clock Constraints. Specify 100 for Period and click OK.

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Achieving Timing Closure in FPGA Designs

Appendix A: Logic Synthesis with Precision RTL

4. Expand the Ports folder, and then perform the following steps: Right-click the Inputs folder and select Set Input Constraints to open the Port Constraints: All Ports dialog box.

Specify 10 for Input Delay and click OK. Right-click the Outputs folder and select Set Output Constraints to open the Port Constraints: All Ports dialog box. Specify 10 for Output Delay and click OK. 5. In the Design Pane, click the Synthesize button. Precision optimizes the design and creates an EDIF netlist, ec_fpga_top.edf, for the implementation. Note
If you want to preserve the original tutorial design files, copy the timing_closure_tutor directory to another location before proceeding.

To save the netlist file 1. From the Project Files pane of the Design Center tab, double-click ec_fpga_top.edf to open the netlist in the text editor. 2. Choose File > Save As, navigate to the ..\timing_closure_tutor folder, and click Save. 3. Click Yes in the message box to replace the EDIF file that already exists.

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Achieving Timing Closure in FPGA Designs

Appendix A: Logic Synthesis with Precision RTL

To examine the timing report: 1. Click the Design Analysis button in the left pane, and then click Report Timing to open the ec_fpga_top_timing.rep file. 2. Locate the Clock Frequency Report section and examine the Min Period (Frequency) estimated by Precision.
Clock Frequency Report Domain -----ClockDomain0 ClockDomain1 Clock Name ---------jtag_tck clk Min Period (Freq) ----------------69.842 (14.318 MHz) 36.732 (27.224 MHz)

3. Choose File > Exit.

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Achieving Timing Closure in FPGA Designs

Appendix B: Command Line Interface Quick Reference

Appendix B: Command Line Interface Quick Reference


This appendix describes the command line usage for key ispLEVER program executables and interactive GUI tools. The first section presents program executables in the typical order of execution as shown in Figure 7 Table 1: ispLEVER Processors and Usage
Design Tool edif2ngd EDIF netlist translator Usage Usage: edif2ngd [-r] {-l <libname>} [-nopropwarn] [-mc] <ediffile> [<ngofile>] where: -r -l <libname>

-d

<edif_file> <ngo_file> ngdbuild build utility

Remove LOC props from the design Design is built from one of the following libraries: LatticeEC LatticeECP LatticeECP2 LatticeECP2M LatticeSC LatticeSCM LatticeXP MachXO Design is translated for a specific device. Device is a combination of the Device Family, Logic Capacity, and Supply Voltage portions of the data sheet Part Number Description. For example: LFEC3E EDIF 2 0 0 format file. Output '.ngo' file. Default is <infile>.ngo.

Usage: ngdbuild [-a|-v <arch>] {-p <searchpath>} [-mc [<modulename>]] [-assemble [{<modulename>}]] <ngo_file[.ngo]>[<ngd_file[.ngd]>] where: -a architecture

-p search_path

Expand design for the given architectures: LatticeEC LatticeECP LatticeECP2 LatticeECP2M LatticeSC LatticeSCM LatticeXP MachXO Add "search_path" to the list of directories to search when resolving NGO/NMC file references

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Achieving Timing Closure in FPGA Designs

Appendix B: Command Line Interface Quick Reference

Table 1: ispLEVER Processors and Usage


Design Tool map design mapper Usage Usage: map [-a <pmname>] [-m] [-p <devicename>] [-t <typename>] [-s <speed>] [-swl [<swlfactor:0,10>]] [-g <guidefile[.ncd]>] [-hier] [-pe] [-c [<packfactor:0,100>]] [-pr <oprffile[.prf]>] [-td [<tdfile[.ncd]>]] [-o <outfile[.ncd]>] <infile[.ngd]> [<prffile[.prf]>] [-retime] where: -a pmname

-c

-f -help -hier -m -o ncd_file -p device_name

-pr pref_file -s speed

-t package_name

-retime

Map design to one of the following architectures: LatticeEC LatticeECP LatticeECP2 LatticeECP2M LatticeSC LatticeSCM LatticeXP MachXO) Without packfactor, map as dense as possible. With packfactor, map to given percentage of PFUs. Use command line arguments from file. Print usage (this message). Use hierarchy information when packing. Produce oversized NCDs. Optional output .ncd file. Map design to device name. The device name is a combination of the Device Family, Logic Capacity, and Supply Voltage portions of the data sheet Part Number Description. For example, LFEC3E. Optional output preference file. Speed grade to use: 3 (slowest) 4 5 (fastest) Package name to use: TQFP100 TQFP144 PQFP208 FPBGA256 FPBGA388 FPBGA484 FPBGA672 FPBGA900 FPBGA896 FPBGA1152 FPBGA1517 FPBGA1704 Perform register retiming.

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Achieving Timing Closure in FPGA Designs

Appendix B: Command Line Interface Quick Reference

Table 1: ispLEVER Processors and Usage


Design Tool par place and route program Usage Usage: par [-k] [-p] [-r] [-i <routepasses:0,2000>] [-c <costpasses:0,20>] [-e|-d <delaypasses:0,100>] [-exp 0|1] [-u <routecost:1,5>] [-q] [-g <guidefile[.ncd]>] [-gv] [-x] [-a] [-l <level:1,5>] [-mf <matchingfactor:0,100>] [-n <iterations:0,100>] [-t <costtable:1,100>] [-sp <speedgrade>] [-s <savebest:1,100>] [-w] [-y] [-m <nodelistfile>] [-exp <explorerstring>] [-mc] [-assemble] [-pe] <infile[.ncd]> <outfile> {<preffile[.prf]>} where: -a

Turn on automatic level skipping for constructive placement. Begins at "-l <1-5>" and automatically skips levels based on completion criteria. The "-n <n>" switch controls the maximum number of iterations per level. Note: "-n <n>", when used with "-a" will be the maximum number of iterations at each level -- not for the total run. -assemble (Modular Design) Assemble top-level design and the implemented modules into one design. -c Run n cleanup passes of the router. Default: 1. -d Run n delay based cleanup passes of the router, n >= 0. Default: 0. -e Run n delay based cleanup passes of the router if there are 0 unrouted, n >= 0. Default: 0. -exp Give shorter routes priority (-ex 1). Default: 0 -f Read par command line arguments & switches from file.

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Achieving Timing Closure in FPGA Designs

Appendix B: Command Line Interface Quick Reference

Table 1: ispLEVER Processors and Usage


Design Tool par place and route program Usage -g Use a guide file to place and route against. 1. Keep matching block names. 2. Keep matching netnames/pins. -gv List matched comps/macros/signals in guided par report file -i = Run n iterations of the router. Default: Run until router decides it will not complete without diverging. -k Skip constructive placement. Run optimize placement, and then enter the router. Note: Use -k -p to do reentrant routing. -l Effort Level. Level 5 is maximum effort. Default: 5. -m Multi task par run. File "<node list file>" contains a list of node names to run the jobs on. -mc (Modular Design) Compile each module. -mf Matching factor. Default: 100 -n Iterations at this level. Use "-n 0" to run until fully routed. See Note under "-a" option. Default: 1. -p Don't run placement. -pe Error out if there are any Preference errors. -q Placer will attempt to minimize overall clock skew. -r Don't run router. -s Save "n" best results for this run. Default: Save All. -sp Change speed grade. Default: Keep Current speed grade. -t Start at this placer cost table entry. Default: 1. -u Use this router cost table entry. Valid range varies by device. Default: 1. -w Overwrite. Allows overwrite of an existing file (including input file). If specified output is a directory, allows files in directory to be overwritten. -x Ignore Timing preferences in preference file. -y Create .dly file and the delay statistics at end of .par file <infile> Name of input NCD file. <outfile> Name of output NCD file or output directory. Use format "<outfile>.ncd" or "<outfile>.dir". <preffile> Name of preference file. Usage: trce [-e|-v [<limit:0,32000>]] [-sp <grade>] [-hld] [-sm <report>][-min] [-max] [-c] [-nmp] [-p] [-o <report[.twr]>] <design[.ncd]>{<preference[.prf]>} where: <design[.ncd]> <preference[.prf]> -c -e [<limit>]

trce static timing analysis

-f <cmd file> -hld -o <report[.twr]> -p -sm <stampfile>

Design input file (no default) Optional preference input file(default design.prf) Print connections not covered by the preference file in the verbose mode Produce detailed error report for timing preferences, optionally limited to the specified number of items Read trce command line arguments & switches from file Perform hold time checking Optional report output file (default design.twr) Print loops in the verbose mode Generate stamp output files

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Achieving Timing Closure in FPGA Designs

Appendix B: Command Line Interface Quick Reference

Table 1: ispLEVER Processors and Usage


Design Tool trce static timing analysis bitgen bitstream generator Usage -sp <speed_grade> -v [<limit>] Enable default speed to be overridden Produce verbose timing report for timing preferences, optionally limited to the specified number of items

Usage: bitgen [-help <arch>] [-J w <infile1.ncd> {<infile2.ncd>}] [-J r] <infile[.ncd]> [<outfile>] [<prffile[.prf]>] Where: -help -J w -J r Valid architectures are: or3t00 MachXO LatticeEC LatticeECP LatticeECP2 LatticeECP2M LatticeSC LatticeSCM LatticeXP MachXO

promgen PROM file generator

Usage: promgen [-b] [-p mcs|exo|tek] [-s <size>] [-t <size>] [-o <outfile>]{-u <hexaddr> <file> {<file>}} {-d <hexaddr> <file> {<file>}} {-n <file>{<file>}} Where: -b -s <size> -t <size>

-p -o -u

-d

-n

Byte wide mode (no bit mirroring) Prom size in K bytes (must be power of 2) Split the into multiple prom files with user-specified size. The resulting files are named as <file>00.<ext>, <file>01.<ext>, <file>02.<ext>, ..., etc. Cannot be used with switch -s, -n, or -d. <format> PROM format (mcs, exo, or tek) <file> Output prom file name (default matches first .bit file) <hexaddr> <file> {<file>} Load .bit or .rbt file(s) up from address. Multiple bit or .rbt files are daisychained to form a single prom load. <hexaddr> <file> {<file>} Load .bit or .rbt file(s) down from address. Multiple .bit or .rbt files are daisychained to form a single prom load. <file> {<file>} Load .bit or .rbt file(s) up or down starting from the next address following previous load. Multiple .bit or .rbt files are daisychained to form a single prom load. Must follow a -u, -d, or -n option.

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Achieving Timing Closure in FPGA Designs

Appendix B: Command Line Interface Quick Reference

Table 1: ispLEVER Processors and Usage


Design Tool ldbanno Timing simulation model writer Usage Usage: ldbanno [-w] [-pre <prfx>] [-neg] [-sup] [-sp <grade>] [-min] [-dis[<del>]] [-sig <sigfile>] [-i] [-n <type>] [-l <libtype>] [-p <prffile>] [-o <netfile>] [<ncdfile>] where: -w Overwrite the output file(s) -sp <grade> Override speed grade for back annotation -pre <prfx> Prefix to add to module name to make them unique for multi-chip simulation -min Override speed grade to minimum timing for hold check -dis <del> Distribute routing delays by splitting the signal and inserting buffers. <del> is the maximum delay (in ps) between each buffer (1000ps by default) -neg Negative setup/hold delay support. Without this option, all negative numbers are set to 0 in SDF -sup Suppress Custom Design MACO blocks SDF output. <sigfile> Contains names for the signals to be split. If not given along with the -dis option, all signals will be processed -i Create a buffer for each block input that has interconnection delay (only valid for Verilog) <type> Netlist type to write out <libtype> Library element type to use <prffile> Preference file <netfile> The name of the output netlist file. The extension on this file will change depending on which type of netlist is being written. Use -h <type>, where <type> is the output netlist type, for more specific information. <ncdfile> Input file '.ncd' Use ldbanno -h <type> for detailed netlist and annotation options. Valid netlist types are: Verilog (generic Verilog format w/ SDF delay file) VHDL (generic VHDL format w/ SDF delay file) Valid library types are: orca - Default for VHDL, Verilog ibisgen IBIS model writer

Usage: ibisgen <padfile> <ibisfile> Write out design IBIS models.

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Achieving Timing Closure in FPGA Designs

Appendix B: Command Line Interface Quick Reference

Table 2: ispLEVER GUI-based Design Tools


Design Tool EPIC - Device Editor Design Planner Usage epic flmainappw [@responsefile] [-inp <NGDfile] [-dir <directory>] [-prj <projectfile>] [-a <arch>] [-p part] [-t <package>] [-lpf <logical_preference_file>] flmainapp [@responsefile] [-inp <NCDfile>] [-dir <directory>] [-prj <projectfile>] [-a <arch>] [-p part] [-t <package>] [-lpf <logical_preference_file>] [-prf <physical_preference_file>] where: -inp loads the specified premap or post-map database file. -dir specifies the path and directory of the database file. -prj specifies the name of the project. -a specifies the device architecture to which the design will be mapped. -p specifies the device part number. -t specifies the device package. -lpf specifies the logical preference file. -prf specifies the physical preference file. -msg specifies the process stage for the database design file. Module/IP Manager Power Calculator Schematic Editor Symbol Editor Text Editor Waveform Stimulus Editor ispmg powerest schem [filename] sym [filename] synedit [filename] wet [filename]

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