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ComputerArchitecture

CacheMemory

ARASHHABIBILASHKARI (April ( April 2010)


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Characteristics
Location Capacity Unitoftransfer Unit of transfer Accessmethod Performance P f Physicaltype Physicalcharacteristics Organisation
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Location
CPU Internal External l

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Capacity
Word size Wordsize
Thenaturalunitoforganisation

Number of words Numberofwords


orBytes

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UnitofTransfer Unit of Transfer


Internal
Usuallygovernedbydatabuswidth

External
Usuallyablockwhichismuchlargerthanaword

Addressable unit Addressableunit


Smallestlocationwhichcanbeuniquely addressed Wordinternally ClusteronM$disks
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AccessMethods(1) Access Methods (1)


Sequential q
Startatthebeginningandreadthroughinorder Accesstimedependsonlocationofdataandprevious location e.g.tape

Direct
Individualblockshaveuniqueaddress Accessisbyjumpingtovicinityplussequentialsearch A Accesstimedependsonlocationandprevious ti d d l ti d i location e.g.disk
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AccessMethods(2) Access Methods (2)


Random
Individualaddressesidentifylocationsexactly Accesstimeisindependentoflocationorprevious access e.g.RAM

Associative
Dataislocatedbyacomparisonwithcontentsofa portionofthestore Access time is independent of location or previous Accesstimeisindependentoflocationorprevious access e.g.cache
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MemoryHierarchy Memory Hierarchy


Registers
InCPU

Internal or Main memory InternalorMainmemory


Mayincludeoneormorelevelsofcache RAM

Externalmemory
Backingstore

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MemoryHierarchy Memory Hierarchy Diagram

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Performance
Access time Accesstime
Timebetweenpresentingtheaddressandgetting thevaliddata

MemoryCycletime
Timemayberequiredforthememoryto recoverbeforenextaccess Cycletimeisaccess+recovery

TransferRate
Rateatwhichdatacanbemoved
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PhysicalTypes Physical Types


Semiconductor
RAM

Magnetic
Disk&Tape

Optical
CD&DVD

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PhysicalCharacteristics Physical Characteristics


Decay Volatility Erasable bl Powerconsumption

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Organisation
Physical arrangement of bits into words Physicalarrangementofbitsintowords Notalwaysobvious e.g.interleaved i l d

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TheBottomLine The Bottom Line


How much? Howmuch?
Capacity

How fast? Howfast?


Timeismoney

Howexpensive?

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HierarchyList Hierarchy List


Registers L1Cache L2Cache L2 Cache Mainmemory Diskcache Di k h Disk Optical Tape
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Soyouwantfast? So you want fast?


It is possible to build a computer which uses Itispossibletobuildacomputerwhichuses onlystaticRAM(seelater) This would be very fast Thiswouldbeveryfast Thiswouldneednocache
Howcanyoucachecache?

Thiswouldcostaverylargeamount

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Cache
Small amount of fast memory Smallamountoffastmemory SitsbetweennormalmainmemoryandCPU MaybelocatedonCPUchipormodule b l d C hi d l

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Cache/MainMemoryStructure Cache/Main Memory Structure

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Cacheoperation Cache operation overview


CPUrequestscontentsofmemorylocation CPU requests contents of memory location Checkcacheforthisdata Ifpresent,getfromcache(fast) f f h (f ) Ifnotpresent,readrequiredblockfrommain memorytocache ThendeliverfromcachetoCPU Cacheincludestagstoidentifywhichblockof mainmemoryisineachcacheslot main memory is in each cache slot
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CacheReadOperation Cache Read Operation Flowchart

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CacheDesign Cache Design


Size MappingFunction ReplacementAlgorithm l l ih WritePolicy BlockSize NumberofCaches Number of Caches

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Sizedoesmatter Size does matter


Cost
Morecacheisexpensive

Speed
Morecacheisfaster(uptoapoint) Checkingcachefordatatakestime

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TypicalCacheOrganization Typical Cache Organization

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MappingFunction Mapping Function


Cache of 64kByte Cacheof64kByte Cacheblockof4bytes
i i.e.cacheis16k(214) li h i 16k (2 )linesof4bytes f4b t

16MBytesmainmemory 24bitaddress
(224=16M)

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WritePolicy Write Policy


Must not overwrite a cache block unless main Mustnotoverwriteacacheblockunlessmain memoryisuptodate Multiple CPUs may have individual caches MultipleCPUsmayhaveindividualcaches I/Omayaddressmainmemorydirectly

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Writethrough Write through


All writes go to main memory as well as cache Allwritesgotomainmemoryaswellascache MultipleCPUscanmonitormainmemory traffictokeeplocal(toCPU)cacheuptodate traffic to keep local (to CPU) cache up to date Lotsoftraffic Slowsdownwrites Rememberboguswritethroughcaches!
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Writeback Write back


Updates initially made in cache only Updatesinitiallymadeincacheonly Updatebitforcacheslotissetwhenupdate occurs Ifblockistobereplaced,writetomain memoryonlyifupdatebitisset l if d bi i Othercachesgetoutofsync I/Omustaccessmainmemorythroughcache N.B.15%ofmemoryreferencesarewrites N B 15% of memory references are writes
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Pentium4Cache Pentium 4 Cache


80386 noonchipcache 80486 8k i 16 b 80486 8kusing16bytelinesandfourwaysetassociative li df i i organization Pentium(allversions) twoonchipL1caches
Data&instructions

PentiumIII L3cacheaddedoffchip Pentium4


L1caches
8k b t 8kbytes 64bytelines fourwaysetassociative

L2cache
FeedingbothL1caches Feeding both L1 caches 256k 128bytelines 8waysetassociative

L3 cache on chip L3cacheonchip


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Pentium4BlockDiagram Pentium 4 Block Diagram

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Questions

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