JOURNAL OF COMPUTING, VOLUME 4, ISSUE 5, MAY 2012, ISSN 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.

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The Fat-Stack in Network-on-chips (NOCs): New Structure for interconnection networks

Reza Kourdy Department of Computer Engineering Islamic Azad University, Khorramabad Branch, Iran Mohammad Reza Nouri rad Department of Computer Engineering Islamic Azad University, Khorramabad Branch, Iran

Abstract this paper shows that a novel network called the fat-stack is efficient and is suitable for use as a baseline distributed network and as crucial benchmark architecture for evaluating the performance of specific distributed networks. The fat-stack structure makes the network scalable to closely represent a distributed network. We show that the fat-stack is efficient by proving it is universal. A requirement for the fat-stack to be universal is that link capacities double up the levels of the network.. Index Terms Networks-on-Chip (NoC), Fat-stack, augmented fat-stack (AFS), general fat-stack (GFS), augmented fat-stack (AFS).

1 INTRODUCTION

etworks-on-Chip (NoC) have been proposed as a promising solution to multi-processor on-chip communication problems. To catalyze the deployment of the NoC paradigm for many high performance computational applications, many challenging research problems of NoC design abstractions need to be addressed at all levels. The active problems in the field of NoC design include: design space exploration of NoC architecture for applications, application scheduling and mapping algorithms, evaluation of switching, topology or routing algorithm for efficient execution of application, and optimization of communication cost, area, and power [1]. The topology of a network determines its efficiency on the first order. Network architecture can be considered as consisting of a distinct topology, varied link capacities, and a specific routing scheme. An architecture resembling practical networks provides not only a working model but also a foundation for studying different networks and contriving novel network services. In this paper we prove analytically that a certain architecture is the best suitable for distributed networking and can be used as a benchmark to evaluate the performance of specific network topologies. The proofs are based on routing results and hardware layouts developed in the context of interconnection networks for parallel computers. It is both theoretically significant and desirable to ensure the proving premises and results to be valid across scales. We show how to scale a VLSI network up to represent a distributed network such that routing properties are retained. An efficient network should move traffic speedily for the computing task and require no excessive hardware to build. We show that the fat-stack is such an efficient network by showing that it is universal, i.e. it can simulate any other network with an overhead of no more than

(some power of) the logarithm of the area A of the hardware containing the network. This universality result implies that the fat-stack performs much better than or as well as most, if not all, of known networks. The choice of the term fat-stack stems from the observation that the network is a construct of identical atomic sub-network units stacked up and tapering upwards fast. The fat-tree is the first proved universal network [2]. But it is universal only under unit wire delay condition; its universality does not hold under non-unit wire delays [3]. The fat-pyramid has been proven to be universal under both unit and non-unit wire delay conditions [3]. The fattree has been used in the CM-5 parallel computer whereas the fat-pyramid has not been adopted for any machine. Another clear advantage of the fat-pyramid over the fattree is its better absolute efficiency due to its hierarchical meshes. But these same meshes of the fat-pyramid increase its wire usage considerably and make it not scalable to represent a distributed network. The fat-stack is relatively simplistic in structure, which makes it scalable to closely represent a distributed network. It can be constructed by stacking up atomic subnetwork units following a fat-tree framework. A subnetwork unit is made of a ring of certain nodes and one or more upward links each from one node of the unit. These links connect to the same node of a sub-network right above the unit. The network is built up recursively. We consider two variants of the fat-stack in this paper. One has only one upward link from a sub-network and the top level node is omitted. This variant is not strictly based on a tree due to the omission of some links. We refer to this variant as the general fat-stack (GFS) which is the main focus of this paper. The second variant has as many up-

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ward links as the number of nodes in the sub-network. We refer to this variant as the augmented fat-stack (AFS).

2 NOC FRAMEWORK
The NoC framework/system consists of five main modules: i) The processing architecture ii) The communication infrastructure iii) The communication paradigm iv) The monitor module v) The traffic generator module. The NoC processing architecture consists of several master/slave processing elements (PEs) that are connected to the communication infrastructure by means of a network adapter. The PEs can be a master PE or slave PE, depending on whether it can initiate a message transfer or only respond to a request. Only master PEs can initiate a message transfer. Slave PEs respond to the requests from master PE either by sending back the requested signals/data or by saving the received information. UART, TIMER, and Instruction/Data Memory all are considered slave PEs, whereas the master PEs used in the design are capable of performing arithmetic and logical operations. The network adapter receives signals from the PEs and generates packets to be sent to the communication infrastructure. Hence, the main function of the adapter module is to transform the data to and from the format required by underlying infrastructure. The data/message is communicated as packets. The entire message can be either generated as a single packet or the packets can be divided into flits before actually transmitted.

for simulation of ordinary networks of computers. As many models of network components are provided, the user can simulate at a high abstraction level. Yet, it is possible to implement new components in the network model. Ns-2 has support for local area networks, mobile networks and even satellite networks. Two computer languages are used in ns-2, namely C++ and OTcl. We would use the tool, Network Simulator ns-2 [9], [10], Which has been extensively used in the research for design and evaluation of public domain computer network, to evaluate various design options for NOC architecture, including the design of router, communication protocol, Routing algorithms. NS-2 is an open source, object-oriented and discrete event driven network simulator written in C++ and OTCL. It is a very common and widely used tool to simulate small and large area networks [11]. All of the topology parameters can be described as a script file; in Tcl. A part of the ns-2 script file about constructing the topology is shown below: #puts "--------Node Index-------------------------" for {set i 0} {$i < $sum} {incr i} { set sw([expr ($i)]) [$ns node] $sw([expr ($i)]) label sw[expr ($i)] if ($i==0) {$sw([expr ($i)]) color blue } if ([expr $i>=1 && $i<=3]) {$sw([expr ($i)]) color red } if ([expr $i>=4 && $i<=12]) {$sw([expr ($i)]) color #00aa00} if ([expr $i>=13 && $i<=39]) {$sw([expr ($i)]) color brown } if ([expr $i>=40 && $i<=120]) {$sw([expr ($i)]) color #696969} if ([expr $i>=121 && $i<=363]) {$sw([expr ($i)]) color #ff8c00} if ([expr $i>=364 && $i<=1092]) {$sw([expr ($i)]) color #000080} } #puts "--------Resource Index-------------------------" for {set i 0} {$i < $sum} {incr i} { set Res([expr ($i)]) [$ns node] $Res([expr ($i)]) label Res[expr ($i)] $Res([expr ($i)]) shape square } #Create links (switches-switches circuilar-links) for {set i 0} {$i < [expr ($sum)/3]} {incr i} { $ns duplex-link $sw([expr ($i*3+1)]) $sw([expr $i*3+2]) 1Mb 10ms DropTail $ns duplex-link $sw([expr ($i*3+2)]) $sw([expr $i*3+3]) 1Mb 10ms DropTail $ns duplex-link $sw([expr ($i*3+3)]) $sw([expr $i*3+1]) 1Mb 10ms DropTail }

3 SYSTEM ARCHITECTURE
Network topology determines the connectivity among nodes and is therefore a first-order determinant of network performance and energy-efficiency. Since the ability of the network to efficiently disseminate information depends largely on the topology, we especially focus on different types of Topologies:

4. SIMULATION METHODOLOGY
In this section, simulation of AFS on-chip interconnects is done by using a simulator developed in [4]. This discrete event driven simulator is based on ns2 [5] that provides many facilities to describe network topology, transmission protocols, routing algorithms, and traffics generation. The main objective of using ns2 is to rapidly explore and evaluate the performance metrics as well as the energy consumption of on-chip interconnects.

4.1. Simulation Details In this paper, we have modeled our architecture concepts with the widely used network simulator ns-2 [6]. NS2 has been widely applied in research related to the design and evaluation of computer networks and to evaluate various design options for architectures [7], including the design of routers, communication protocols, etc. Ns-2 [8] is a discrete event network simulator designed

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5. SIMULATION RESULTS
In this section, we present the Simulation of NoC with different levels with the topology NOC- Fat-Stack and we survey the ability and flexibility of ns2 in NOC-WKrecursive (network-on-chip-WK-recursive) simulations. Figures 2 to 9, show different views of NOC-AFS simulations.

5.2. The 4-levels NOC-AFS Some of the simulations in which the number of nodes is high may have a different view. For example Figures 3 to 5, show different views of 3-levels NOC-AFS topology which each of them consists of 40 nodes.

5.1. The 3-levels NOC-AFS Some of the simulations in which the number of nodes is high may have a different view. For example Figures 1 to 2, show different views of 3-levels NOC-AFS topology which each of them consists of 13 nodes.

Fig.3. the 1st view of the 4-levels NOC-AFS

Fig.1. the 1st view of the 3-levels NOC-AFS

Fig.2. the 2nd view of the 3-levels NOC-AFS

Fig.4. the 2nd view of the 4-levels NOC-AFS

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Fig.5. the 3rd view of the 4-levels NOC-AFS Fig.7. the 2nd view of the 5-levels NOC-AFS

5.3. The 5-levels NOC-AFS Some of the simulations in which the number of nodes is high may have a different view. For example Figures 6 to 9, show different views of 5-levels NOC-AFS topology which each of them consists of 121 nodes

Fig.6. the 1st view of the 5-levels NOC-AFS

Fig.8. the 3rd view of the 5-levels NOC-AFS

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nrg.ee.lbl.gov/ns/ [10] The network simulator-ns-2,available at http://www.isi.edu/nsnam/ns/ [11] M. Ali, M. Welzl, A. Adnan, F. Nadeem , " Using the NS-2 Network Simulator for Evaluating Network on Chips (NoC)" International Conference on Emerging Technologies, pp.506 512, 2006.

Reza Kourdy received his B.Sc. degree in Computer Engineering and his M.Sc. degree in Computer Architecture both from Azad University of Arak, Iran, in 2002 and 2007, respectively. His research interests include Network-On-Chip Architecture and Fault-tolerance.
Mohammad Reza Nouri Rad received his B.Sc. Degree in Computer Engineering Software from Azad University of Najafabad, Iran, in 2001, and his M.Sc. Degree in Computer Software from Azad University of Arak, Iran, in 2010. His research interests include NetworkOn-Chip Architecture and Network Security. He is Program Committee of following conferences : WICT 2011 CSNT 2011 CICN 2011 SocProS 2011 CSNT 2012 CICN 2012 BIC-TA 2012

Fig.9. the 4th view of the 5-levels NOC-AFS

REFERENCES
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