Final&Project&

Figure 1 Image processing system block diagram. Video segmentation refers to the process of extracting regions of interest from image sequences. The course project will consist of developing a key component of a video segmentation syste m designed to detect flesh toned pixels from an image. You will design and implement a skintone detection accelerator. Skintone&Detection&Overview& Consider the problem of finding human faces in an image. To locate faces we can start by applying a 2D face detector of fixed size (i.e. 20 pixels x 20 pixels) at every (x,y) location with in the image. To be sure we do not miss any faces and assuming we have no prior knowledge about the probability of existence of a face at a particular (x,y), the detector should be applied at every (x,y) offset in the im age. In addition, since the size of a face can vary vastly depending on its location in the Field of View (i.e. distan ce from image sensor), the face detector should be applied at varying scales of the image. Even for a conservat ive number of scales, exhaustively searching the image for faces can be prohibitive for real-time imag e processing systems. Segmenting an image by skintone can increase performance by filtering image loca tions that do not contain pixels that are characteristic of human flesh tone. Since skin tone detection i s a per pixel operation the computed skintone score for a given pixel is dependen t only on the pixel in question there is a huge potential for speedup by parallelizing the computation. Your task will be to implement an accelerator for a skin tone detector that computes the skintone score for every pixel in an image. For each pixel in the image, your module will return the Skintone Score the degree of flesh toneness that a pixel exhibits. The module must interface with a provided system platform targeted for the Virtex-6 LXT240 FPGA. A C/C++ software implementation of the skintone detection algorithm is provided. You are required to analyze the code and port the software implementation into a FEASIBLE hardware implement ation. In addition to the skintone detector, you will need to implement a RGB to YCrCb Converter utilizing the Xilinx Coregen tool. Ultimately your design must be integrated into the Router test platform that is provided. Your design criterions include maximizing performance, maximizing accuracy, and minimizing area. Figure 2 Sample application illustrating the result of skintoning. Skintone pix els are colored in Dark Red.

Hardware&System&Overview& Figure 1 is a block diagram of the skin tone detection system. The entire syste m is interconnected via an onchip router that will be provided. The components that must be implemented are conta ined in the dashed box and described in the following sections. Figure 3 gives a logical view of the proce ssing pipeline. The input ARGB pixel is Color Space converted to YCrCb and subsequently processed by the Skinto ne Detector. The output SkinScore replaces the Alpha field of the original ARGB pixel. Figure 3 Skintone Detector logical view

RGB$to$YCrCb Converter datain_valid datain[N51:0] datain_ready dataout_valid dataout[N51:0] dataout_ready Figure 4 RGB to YCrCb Converter. The operation of the RGB to YCrCb Converter is detailed in the Coregen documenta tion. Note that the datain and dataout widths can be set to any size you require to match your particular a rchitecture and performance requirements. You will need to adapt the handshaking interface that is provided by the Coregen module to the handshaking interface that is specified in the Handshaking Protocol section belo w. Skintone( Detector datain_valid datain[N31:0] datain_ready dataout_valid dataout[N31:0] dataout_ready Figure 5 Skintone Detector. A C/C++ software implementation of the skintone detection algorithm is provided. You are required to analyze the code and port the software implementation into a feasible hardware implement ation. You may implement your Detector utilizing Floating-Point or Fixed-Point. If you choose to utilize Floating-Point you may

implement your own Floating-Point arithmetic modules or you may use Coregen to g enerate the required modules. Note, that Floating-Point arithmetic is considerably expensive with re gards to resource utilization and performance. Fixed-Point however is much more efficient with regards to resourc e utilization and performance but requires careful consideration of the particular Fixed-Point format that sho uld be used. If you choose to use Fixed-Point, a tool will be provided to help you determine the appropriate forma t.

Handshaking&Protocol& The YCrCb Converter and Skintone Detector must follow the simple handshaking pro tocol shown in figure X.

Test&Environment& A verilog test environment will be provided. The testbench will generate data t o be processed by your modules. In addition, the testbench will generate expected output. You will need to comp are the output of your module with the expected data. Design&Constraints&and&Timeline& Your%implementation,%which%includes%the%YCrCb%Converter%and%Skintone%detector,%m ay%consume%at%most% 16,000%logic%slices,%32%DSP48s,%and%16%BlockRAMs%as%reported%after%PAR.%%Designs& that&achieve&high& performance&yet&use&fewer&resources&are&overwhelming&preferred.%Your%implementat ion%may%use% fixed%or%floating%point%representation%at%any%precision(s)%that%you%determine%as %suitable.%However,%the% classification%of%skin/noPskin%after&thresholding%should%match%the%software%impl ementation%for%all%test% cases.% % You%are%free%to%make%any%design%choices%that%will%result%in%the%best%performance %possible%within%the% constraints%of%correctness%and%device%utilization%as%specified%in%Table 1.%%Thin gs%to%consider%include%degree% of%parallelization%and%operating%frequency.%%Finally,%try%to%find%optimizations% in%the%C%code%that%will% translate%to%more%efficient%hardware%implementation.%%Hint:&there&exists&an&opti mization&that&can&

reduce&this&project&from&a&4&day&design&effort&to&a&1.5&day&design&effort!&&Will &you&find&it?% % Table 1 Device utilization and performance constraints Maximum # Logic Slices 16,000 Maximum # DSP48 32 Maximum # BlockRAM 16 Performance 1920 x1080 @ 30 fps (0.033 sec/frame) Table 2 Project Timeline Monday 6/25/2012 Project Design Presentation Slide 1: Group members and Group Name Slide 2: Hardware blocks for Skin-tone Module Slide 3: Design performance goals and parameters ( data bit-widths, Fixed-point or Floating Point representation, expected speed) Monday - Thursday HDL Coding and Verification Friday Chipscope Debugging Saturday Onboard Testing