Question No.

1 16 bit processor OPCODE R1 General Purpose Register R2 R3 R4 R5 R6 R7 R8 ALU ADD, SUB, INC, DEC, OR, XOR, AND, NAND, LSHFTR, LSHFTL, ASHFTR, and ASHFTL 4-bits 0-3

4-bits 12-15

8-bits 4-11

Indirect Addressing Instructions OP Code Assembler Format 1001 1010 1011 1100 LOAD STORE ADD SUB Rn, [Rm] Rn, [Rm] Rn, [Rm] Rn, [Rm] Action Rn = Memory [Rm]1 Memory [Rm] = Rn Rn = Rn + Memory [Rm] Rn = Rn Memory [Rm]

Register Addressing Diagram

Register Indirect Addressing Diagram

1. Direct addressing mode: the instruction consist of three byte, byte for the opcode of the instruction followed by two bytes represent the address of the operand Low order bits of the address are in byte 2 High order bits of the address are in byte 3 Ex: LDA 2000h This instruction load the Accumulator is loaded with the 8-bit content of memory location [2000h] 2. Register addressing mode The instruction specifies the register or register pair in which the data is located Ex: MOV A,B Here the content of B register is copied to the Accumulator 3. Register indirect addressing mode The instruction specifies a register pair which contains the memory address where the data is located. Ex. MOV M , A Here the HL register pair is used as a pointer to memory location. The content of Accumulator is copied to that location.
For Example Below program will be placed at 0FH onwards, and the registers allocated as follows: R0 for 'sum', R1 for 'n', R2 for 'addr'

sum = 0 n = 100 addr = 200H loop exit when n <= 0 sum = sum + RAM [addr] addr = addr + 1 n=n-1 end loop ; Result in Register R0

0 1 2 3 ... 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H

0 1 100 200H LOAD LOAD LOAD IFZER IFNEG ADD ADD SUB GOTO STOP R0, [0] R1, [2] R2, [3] R1, 18H R1, 18H R0, [R2] R2, [1] R1, [1] 12H

; Holds 0 ; Holds 1 ; Holds 100 ; Holds 200H ; sum = 0 ; n = 100 ; addr = 200H ; exit when n<=0 ; sum = sum+... ; addr = addr + 1 ;n=n1 ; end loop

Architecture

Question No. 2 Register Register Architecture (Load Store) Special instructions to access memory (load, store) First operand is loaded from the memory into a register Second operand is loaded from the memory into a register Operation is performed on the registers Both operands and location of result are explicit Result is written into a register, and has to be explicitly stored back into memory

Memory-memory architecture: (obsolete) Operation is performed on the memory locations Result is written into the memory Which Architecture Is the Best? Early computers used stack, accumulator, Register-memory and memory-memory Current computers use Register- Register (load-store): Register access is faster Registers can be named with fewer bits than memory Registers allow for compiler optimizations (out of order execution) Registers can be used to hold all the variables relevant for a specific code segment all operations are faster. Base Machine (Register / Register) Op Freq ALU 50% Load 20% Store 10% Branch 20% Typical Mix of instruction type in program

Cycles 1 2 2 2

CPI (i) 0.5 0.4 0.2 0.4 1.5

(% Time) 33% 27% 13% 27%

Question No. 3
In a single-cycle implementation, CPI = 1 and clock-cycle time = latency of slowest instruction

Question 4 U = A + B + D = 10 + 11 + 13 = 34 V = C + D = 12 + 13 = 25 W= B << 3 = 11 X = 7B + B + C+ D = 7*11 + 12 +13 = 77 + 25 = 102 Y = X + V = 102 + 25 = 127 Total = 299 f = 1/cycle length = 1/299

Add instruction provide its results to sub after 3 cycles, to and after 2 and to Or after 1 clock cycles

XOR: No Data Hazard here, as register is read after being written