Chap05 (7 5 06)

Chapter 5 Introduction (7/5/06)
Page 5.0-1.
CHAPTER 5 CMOS AMPLIFIERS

INTRODUCTION
Objective Illustrate the analysis and design of amplifiers using CMOS technology. Topics Introduction and Characterization Inverting Amplifiers Differential Amplifiers Cascode Amplifiers Functional blocks or circuits Current Amplifiers (Perform a complex function) Output Amplifiers
Chapter 5 Blocks or circuits (Combination of primitives, independent)
Sub-blocks or subcircuits (A primitive, not independent)

Fig. 5.0-1
CMOS Analog Circuit Design
P.E. Allen - 2006
Page 5.0-2.
Types of Amplifiers Type of Amplifier Voltage Current Transconductance Transresistance Output Gain = Input Output Voltage Av = Input Voltage Output Current Ai = Input Current Output Current Gm = Input Voltage Output Voltage Rm = Input Current Ideal Input Resistance Infinite Zero Infinite Zero Ideal Output Resistance Zero Infinite Infinite Zero
Most CMOS amplifiers fit naturally into the transconductance amplifier category as they have large input resistance and fairly large output resistance. If the load resistance is high, the CMOS transconductance amplifier is essentially a voltage amplifier.
CMOS Analog Circuit Design P.E. Allen - 2006
Page 5.0-3.
Characterization of an Amplifier 1.) Large signal static characterization: Plot of output versus input (transfer curve) Large signal gain Output and input swing limits 2.) Small signal static characterization: AC gain AC input resistance AC output resistance 3.) Small signal dynamic characterization: Bandwidth Noise Power supply rejection 4.) Large signal dynamic characterization: Slew rate Nonlinearity
Page 5.0-4.
Components of a CMOS Voltage/Transconductance Amplifier 1.) A transconductance stage that converts the input voltage to current. 2.) A transresistance stage (load) that converts the current from the transconductance stage back to voltage.
Transresistance Transconductance Stage Stage Input Output Voltage Voltage-to Current Current-to Voltage Current Voltage Conversion Conversion Voltage Amplifier
060607-01
Input Voltage Voltage Amplifier
Output Voltage
P.E. Allen - 2006
Page 5.0-5.
Illustration of Voltage Amplifier Components

VDD
+ VT+ 2VON + VT+VON -
VCC
+ VEB + VEB + VEC(sat) -
MOS Loads IBias IBias
BJT Loads
IBias
IBias
+ VT+ 2VON - V+ T+VON MOS Transconductors BJT Transconductors
+ VBE + VCE(sat) + VBE Fig320-01
Transconductance stages are in the lower two shaded boxes Transresistance stages (loads) are in the upper two shaded boxes (actually, the transconductance output also serves as a part of the load or transresistance stage)
Page 5.0-6.
Amplifier Notation
Output Voltage
VDD VSS
Output Voltage
VDD
060607-02
Split Power Supplies
Single Power Supply
Simpler notation:
VDD Input Voltage Voltage Amplifier VSS
060607-03
VDD Output Voltage Input Voltage Voltage Amplifier Output Voltage
Split Power Supplies
Single Power Supply
P.E. Allen - 2006
Page 5.0-7.
Inverting and Noninverting Amplifiers The types of amplifiers are based on the various configurations of the actual transistors. If we assume that one terminal of the transistor is grounded, then three possibilities result:
VDD Load vin + vout vin Common Source + VDD Load + vout vin VDD
+ + Load Common Drain vout
060608-01
Common Gate
Note that there are two categories of amplifiers: 1.) Noninverting - Those whose input and output are in phase (common gate and common drain) 2.) Inverting - Those whose input and output are out of phase (common source)
P.E. Allen - 2006
Chapter 5 Section 1 (7/5/06)
Page 5.1-1.
SECTION 5.1 INVERTING AMPLIFIERS

Types of Inverting Amplifiers The inverting amplifier or common source amplifier differs only by the type of load. Possible types of inverting amplifiers are shown below:
VDD Load vout vin vin VDD M2 vout M1 vin VPBias1 VDD M2 vout M1 vin VDD M2 vout M1
060608-02
Class A Amplifiers
Push-Pull Amplifier
Class A amplifiers The current in the load transistor (M2) flows during the entire period of a sinusoidal input. Push-Pull (Class B and Class AB) amplifiers The current flows in each transistor (M1 and M2) for less than the entire period of a sinusoidal input. Class B is 180 and Class AB is between 180 and 360.
Page 5.1-2.
ACTIVE LOAD INVERTER Voltage Transfer Characteristic of the Active Load Inverter
vIN=5.0V vIN=4.5V vIN=4.0V 0.5 vIN=3.5V K JI H vIN=3.0V 0.4
G
5V vIN=2.5V M2 W2 = 1m L2 1m ID + vOUT W1 2m = L1 1m -
ID (mA)
0.3 0.2 0.1
F E
vIN=2.0V
M1 + vIN
M2
D
vIN=1.5V
C A,B
0.0
vOUT
vIN=1.0V 5 4
A B C D
M2 cutoff M2 saturated
vOUT
3 2 1
d ate tur ive a 1 s ct M 1a M E

F G H I J K
Fig. 320-02
0 0
2v 3 IN
The boundary between active and saturation operation for M1 is vOUT vIN - 0.7V vDS1 vGS1 - VTN
Page 5.1-3.
Large-Signal Voltage Swing Limits of the Active Load Inverter Maximum output voltage, vOUT(max): vOUT(max) VDD - |VTP| (ignores subthreshold current influence on the MOSFET) Minimum output voltage, vOUT(min): Assume that M1 is nonsaturated and that VT1 = |VT2| = VT. vDS1 vGS1 - VTN vOUT vIN - 0.7V The current through M1 is (vOUT)2 v and the=current through M2 is DS1 = iD 1 (vGS1 VT)vDS1 (VDD VT)(vOUT ) 1 2 2 2 2 2 iD = 2 (vSG2 VT)2 = 2 (VDD vOUT VT)2 = 2 (vOUT + VT VDD)2 Equating these currents gives the minimum vOUT as, vOUT(min) = VDD VT VDD VT 1 + ( 2/ 1)
2
P.E. Allen - 2006
Page 5.1-4.
Small-Signal Midband Performance of the Active Load Inverter The development of the small-signal model for the active load inverter is shown below:
VDD
S2=B2 rds2 + vout + vin gm1vin Rout + vout Fig. 320-03
ID vIN
gm2vgs2 M2 vOUT G1 D1=D2=G2 + vin gm1vgs1 M1 S1=B1
rds1
rds1
gm2vout
rds2
Sum the currents at the output node to get, gm1vin + gds1vout + gm2vout + gds2vout = 0 Solving for the voltage gain, vout/vin, gives gm1 gm1 K'NW1L2 1/2 vout vin = gds1 + gds2 + gm2 gm2 = K'PL1W2 The small-signal output resistance can also be found from the above by letting vin = 0 to get, 1 1 Rout = gds1 + gds2 + gm2 gm2
Page 5.1-5.
Frequency Response of the MOS Diode Load Inverter Incorporation of the parasitic VDD Cgs2 capacitors into the small-signal M2 model: Cbd2 If we assume the input voltage has a Vout small source resistance, then we can Cgd1 Cbd1 CL write the following: M1 Vin sCM(Vout-Vin) + gmVin Cgs1 + GoutVout + sCoutVout = 0 Vout(Gout + sCM + sCout) = - (gm sCM)Vin -(gm sCM) Vout Vin = Gout+ sCM + sCout = -gmRout where and gm = gm1,
CM + Vin gmVin + Vout -
Rout
Cout
Fig. 320-04
sCM s gmRout 1 - z1 1- gm s 1+ sRout(CM + Cout) = 1 - p1 and gm1 z1 = CM Cout = Cbd1+Cbd2+Cgs2+CL
1 p1 = Rout(Cout+CM) , 1 gm2 ,
Rout = [gds1+gds2+gm2]-1
CM = Cgd1 , and
P.E. Allen - 2006
Page 5.1-6.
Frequency Response of the MOS Diode Load Inverter - Continued If |p1| < z1, then the -3dB frequency is approximately equal to [Rout(Cout+CM)]-1.
dB 20log10(gmRout) z1 |p1| -3dB log10
0512-06-02.EPS
0dB
Observation: The poles in a MOSFET circuit can be found by summing the capacitance connected to a node and multiplying this capacitance times the equivalent resistance from this node to ground and inverting the product. (See Appendix 5A for details on frequency response and Bode plots)
P.E. Allen - 2006
Page 5.1-7.
Example 5.1-1 - Performance of an Active Resistor-Load Inverter Calculate the output-voltage swing limits for VDD = 5 volts, the small-signal gain, the output resistance, and the -3 dB frequency of active load inverter if (W1/L1) is 2 m/1 m and W2/L2 = 1 m/1 m, Cgd1 = 100fF, Cbd1 = 200fF, Cbd2 = 100fF, Cgs2 = 200fF, CL = 1 pF, and ID1 = ID2 = 100A, using the parameters in Table 3.1-2. Solution From the above results we find that: vOUT(max) = 4.3 volts vOUT(min) = 0.418 volts Small-signal voltage gain = -1.92V/V Rout = 9.17 k including gds1 and gds2 and 10 k ignoring gds1 and gds2 z1 = 2.10x109 rads/sec p1 = -64.1x106 rads/sec. Thus, the -3 dB frequency is 10.2 MHz.
P.E. Allen - 2006
Page 5.1-8.
CURRENT SOURCE INVERTER Voltage Transfer Characteristic of the Current Source Inverter
vIN=5.0V vIN=4.5V vIN=4.0V 0.5 vIN=3.5V vIN=3.0V 0.4 5V vIN=2.5V W2 = 2m L2 1m ID + vOUT W1 = 2m L1 1m -
ID (mA)
0.3 0.2 0.1

KJIH F G E
2.5V
vIN=2.0V
M2 M1 + vIN
M2
D C A,B
vIN=1.5V vIN=1.0V 5 A B C 4
D
0.0 0
vOUT
vOUT
M2 active 3 M2 saturated 2
E
ed rat atu tive 1s M 1 ac M

F G H I J K
1 0 0 1 2
vIN Regions of operation for the transistors: M1: vDS1 vGS1 -VTn vOUT vIN - 0.7V M2: vSD2 vSG2 - |VTp| VDD-vOUT VDD -VGG2 - |VTp|
Fig. 5.1-5
vOUT
3.2V
P.E. Allen - 2006
Page 5.1-9.
Large-Signal Voltage Swing Limits of the Current Source Load Inverter Maximum output voltage, vOUT(max): vOUT (max) VDD Minimum output voltage, vOUT(min): Assume that M1 is nonsaturated. The minimum output voltage is, 2 VDD - VGG - |VT2| 2 1- 1 vOUT(min) = vOUT(min) = (VDD - VT1) 1 VDD - VT1 This result assumes that vIN is taken to VDD.
P.E. Allen - 2006
Page 5.1-10.
Small-Signal Midband Performance of the Current Source Load Inverter Small-Signal Model:
VDD M2 vOUT G1 + vin M1 -
S2=B2 rds2 D1=D2 gm1vgs1 S1=B1=G2 + vout + vin gm1vin Rout + vout Fig. 5.1-5B
VGG2
vIN
ID
rds1
rds1
rds2
Midband Performance: gm1 2K'NW1 1/2 vout vin = gds1 + gds2 = L1ID
vout vin Weak Inversion
+ 2
1
D
1 1 !!! and Rout = gds1 + gds2 ID( 1 +
2)
Strong Inversion
1A
log(IBias) 060614-01
P.E. Allen - 2006
Page 5.1-11.
Frequency Response of the Current Source Load Inverter Incorporation of the parasitic VDD Cgs2 capacitors into the small-signal model (x is connected to VGG2): x M2
Cbd2
CM + Vout -
If we assume the input voltage has a small source resistance, then we can write the following: s gmRout 1 - z1 Vout(s) Vin(s) = s 1 - p1 where gm = gm1,
Cgd2 Cgd1 Vin M1
Vout Cbd1 CL
+ Vin gmVin -
Rout
Cout
Fig. 5.1-4
1 p1 = Rout(Cout+CM) ,
gm and z1 = CM
1 and Rout = gds1 + gds2 and Cout = Cgd2 + Cbd1 + Cbd2 + CL CM = Cgd1 Therefore, if |p1|<|z1|, then the 3 dB frequency response can be expressed as gds1 + gds2 1 = Cgd1 + Cgd2 + Cbd1 + Cbd2 + CL -3dB
Page 5.1-12.
VDD Example 5.1-2 - Performance of a Current-Sink Inverter + VSG1 A current-sink inverter is shown in Fig. 5.1-7. Assume vIN M1 that W1 = 2 m, L1 = 1 m, W2 = 1 m, L2 = 1m, VDD = 5 ID vOUT volts, VGG1 = 3 volts, and the parameters of Table 3.1-2 M2 describe M1 and M2. Use the capacitor values of Example VGG1 5.1-1 (Cgd1 = Cgd2). Calculate the output-swing limits and the small-signal performance. Figure 5.1-7 Current sink CMOS inverter. Solution To attain the output signal-swing limitations, we treat Fig. 5.1-7 as a current source CMOS inverter with PMOS parameters for the NMOS and NMOS parameters for the PMOS and use NMOS equations. Using a prime notation to designate the results of the current source CMOS inverter that exchanges the PMOS and NMOS model parameters, 1101 3-0.7 vOUT(max) = 5V and vOUT(min) = (5-0.7) 1 - 1 - 502 5-0-0.7 2 = 0.74V In terms of the current sink CMOS inverter, these limits are subtracted from 5V to get vOUT(max) = 4.26V and v OUT (min) = 0V. To find the small signal performance, first calculate the dc current. The dc current, ID, is KNW1 1101 ID = 2L1 (VGG1-VTN)2 = 21 (3-0.7)2 = 291A vout/vin = 9.2V/V, Rout = 38.1 k , and f-3dB = 2.78 MHz.
Page 5.1-13.
PUSH-PULL INVERTER Voltage Transfer Characteristic of the Push-Pull Inverter

1.0 0.8
vIN=2.0V v =4.5V vIN=5.0V IN vIN=4.0V vIN=3.5V vIN=0.5V vIN=1.0V vIN=1.5V vIN=3.0V
5V W2 = 2m L2 1m ID + vOUT W1 1m = L1 1m -
ID (mA)
0.6
vIN=2.5V
M2
vIN=2.5V E D vIN=2.0V vIN=1.5V vIN=1.0V A B C D E
+ vIN
0.4 0.2 0.0 0

H I G F vIN=3.0V vIN=3.5V vIN=4.5V J,K 1
M1
vOUT
4 C A,B 5
4
vOUT
3 2 1 0 0
e tiv d ac rate 2 M satu 2 M
F
ed rat atu tive 1s M 1 ac M
Note the railto-rail output voltage swing
J K
Regions of operation for M1 and M2: vOUT vIN - 0.7V M1: vDS1 vGS1 - VT1 M2: vSD2 vSG2-|VT2| VDD -vOUT VDD -vIN-|VT2|
2v 3 IN
Fig. 5.1-8
vOUT vIN + 0.7V

P.E. Allen - 2006
Page 5.1-14.
Small-Signal Performance of the Push-Pull Amplifier

5V
CM
M2 + vin M1 + vout
Fig. 5.1-9
+ vin -
gm1vin
rds1
gm2vin
rds2
Cout
+ vout -
Small-signal analysis gives the following results: vout (gm1 + gm2) K'N(W1/L1) + K'P(W2/L2) = gds1 + gds2 = (2/ID) vin 1+ 2 1 Rout = gds1 + gds2 gm1+gm2 gm1+gm2 (gds1 + gds2) z = CM = Cgd1+Cgd2 and p1 = Cgd1 + Cgd2 + Cbd1 + Cbd2 + CL If z1 > |p1|, then gds1 + gds2 = Cgd1 + Cgd2 + Cbd1 + Cbd2 + CL -3dB
P.E. Allen - 2006
Page 5.1-15.
Example 5.1-3 - Performance of a Push-Pull Inverter The performance of a push-pull CMOS inverter is to be examined. Assume that W1 = 1 m, L1 = 1 m, W2 = 2 m, L2 = 1m, VDD = 5 volts, and use the parameters of Table 3.1-2 to model M1 and M2. Use the capacitor values of Example 5.1-1 (Cgd1 = Cgd2). Calculate the output-swing limits and the small-signal performance assuming that ID1 = ID2 = 300A. Solution The output swing is seen to be from 0V to 5V. In order to find the small signal performance, we will make the important assumption that both transistors are operating in the saturation region. Therefore: vout -257S - 245S vin = 12S + 15S = -18.6V/V Rout = 37 k f-3dB = 2.86 MHz and z1 = 399 MHz
P.E. Allen - 2006
Page 5.1-16.
NOISE ANALYSIS OF INVERTING AMPLIFIERS Noise Analysis of Inverting Amplifiers Noise model:
VDD en22 Noise Free MOSFETs eout2 M1 vin VDD M2 eeq2 Noise Free MOSFETs eout2 M1
Fig. 5.1-10
*
en12 vin
M2
Approach: 1.) Assume a mean-square input-voltage-noise spectral density en2 in series with the gate of each MOSFET. (This step assumes that the MOSFET is the common source configuration.) 2.) Calculate the output-voltage-noise spectral density, eout2 (Assume all sources are additive). 3.) Refer the output-voltage-noise spectral density back to the input to get equivalent input noise eeq2. 4.) Substitute the type of noise source, 1/f or thermal.
Page 5.1-17.
Noise Analysis of the Active Load Inverter 1.) See model to the right. Noise Noise VDD VDD Free Free gm1 2 en22 MOSFETs MOSFETs 2.) eout2 = en12 gm2 + en22 M2 M2 * eout2 eout2 gm2 2 en2 2 en12 eeq2 3.) eeq2 = en12 1 + gm1 en1 vin vin M1 M1 * * Up to now, the type of noise is not defined. Fig. 5.1-10 1/f Noise KF B Substituting en2= 2fCoxWLK = fWL , into the above gives, B1 K'2B2 L1 2 B1 1/2 K'2B2 L1 2 1/2 eeq(1/f)2 = fW1L1 1 + K'1B1 L2 eeq(1/f) = fW1L1 1 + K'1B1 L2 To minimize 1/f noise, 1.) Make L2>>L1, 2.) increase the value of W1 and 3.) choose M1 as a PMOS. Thermal Noise 8kT Substituting en2= 3gm into the above gives, W2L1K'2 1/2 1/2 8kT eeq(th) = 3[2K'1(W/L)1I1]1/2 1+ L2W1K'1 To minimize thermal noise, maximize the gain of the inverter.
Page 5.1-18.
Noise Analysis of the Active Load Inverter - Continued When calculating the contribution of en22 to eout2, it was assumed that the gain was unity. To verify this assumption consider the following model:
en22
+ vgs2 -
+ gm2vgs2 rds1 rds2 eout2 _

Fig. 5.1-11
We can show that, eout2 gm2(rds1||rds2) 2 = 1 + g (r ||r ) en2 m2 ds1 ds2
P.E. Allen - 2006
Page 5.1-19.
Noise Analysis of the Current Source Load Inverting Amplifier Model:

VDD en22 Noise Free MOSFETs eout2 M1 vin VDD M2 eeq2 Noise Free MOSFETs eout2 M1
Fig. 5.1-12.
VGG2
vin
*
en12
M2
The output-voltage-noise spectral density of this inverter can be written as, eout2 = (gm1rout)2en12 + (gm2rout)2en22 or (gm2rout)2 gm2 2 en2 2 2=e 2+ 2=e 2 1+ eeq n1 n1 (gm1rout)2en2 gm1 en12 This result is identical with the active load inverter. Thus the noise performance of the two circuits are equivalent although the small-signal voltage gain is significantly different.
P.E. Allen - 2006
Page 5.1-20.
Noise Analysis of the Push-Pull Amplifier Model:

VDD en22 Noise Free MOSFETs eout2 M1
Fig. 5.1-13.
*
vin en12
M2
The equivalent input-voltage-noise spectral density of the push-pull inverter can be found as gm1en1 2 gm2en2 2 + gm1 + gm2 eeq = gm1 + gm2 If the two transconductances are balanced (gm1 = gm2), then the noise contribution of each device is divided by two. The total noise contribution can only be reduced by reducing the noise contribution of each device. (Basically, both M1 and M2 act like the load transistor and input transistor, so there is no defined input transistor that can cause the noise of the load transistor to be insignificant.)
Page 5.1-21.
Summary of CMOS Inverting Amplifiers

Inverter p-channel active load inverter Current source load inverter Push-Pull inverter AC Voltage Gain -gm1 gm2 -gm1 gds1+gds2 -(gm1+gm2) gds1+gds2 AC Output Resistance 1 gm2 1 gds1+gds2 1 gds1+gds2 Bandwidth (CGB=0)
gm2 CBD1+CGS1+CGS2+CBD2 gds1+gds2 CBD1+CGD1+CDG2+CBD2 gds1+gds2 CBD1+CGD1+CGS2+CBD2
Equivalent, input-referred,meansquare noise voltage

en12
gm2 + en22 gm1 2 gm2 + en22 gm1 2
en12
gm1en1 2 gm1en1 2 gm1+ gm2 + gm1+ gm2
P.E. Allen - 2006
Page 5.2-1.
SECTION 5.2 DIFFERENTIAL AMPLIFIERS

CHARACTERIZATION OF A DIFFERENTIAL AMPLIFIER What is a Differential Amplifier? A differential amplifier is an amplifier that amplifies the difference between two voltages and rejects the average or common mode value of the two voltages. Differential and common mode voltages: v1 and v2 are called single-ended voltages. They are voltages referenced to ac ground. The differential-mode input voltage, vID, is the voltage difference between v1 and v2. The common-mode input voltage, vIC, is the average value of v1 and v2 . v1+v2 vID = v1 - v2 and vIC = 2 v1 = vIC + 0.5vID and v2 = vIC - 0.5vID v1 + v2 vID vOUT = AVDvID AVCvIC = AVD(v1 - v2) AVC 2 2 + where + vID vIC AVD = differential-mode voltage gain vOUT 2 AVC = common-mode voltage gain Fig. 5.2-1B
P.E. Allen - 2006
Page 5.2-2.
Differential Amplifier Definitions Common mode rejection rato (CMRR) AVD CMRR = AVC CMRR is a measure of how well the differential amplifier rejects the common-mode input voltage in favor of the differential-input voltage. Input common-mode range (ICMR) The input common-mode range is the range of common-mode voltages over which the differential amplifier continues to sense and amplify the difference signal with the same gain. Typically, the ICMR is defined by the common-mode voltage range over which all MOSFETs remain in the saturation region. Output offset voltage (VOS(out)) The output offset voltage is the voltage which appears at the output of the differential amplifier when the input terminals are connected together. Input offset voltage (VOS(in) = VOS) The input offset voltage is equal to the output offset voltage divided by the differential voltage gain. VOS(out) VOS = AVD
Page 5.2-3.
Transconductance Characteristic of the Differential Amplifier Consider the following n-channel differential amplifier (sometimes called a source-coupled pair): vG1 M1 Where should bulk be connected? Consider a p-well, CMOS technology,
D1 G1 S1 n+ S2 G2 D2 VDD
VDD iD1 iD2 M2 v G2 + vGS2 VBulk

Fig. 5.2-2
n-substrate
y y ; ;
n+ p+ n+ p-well
v IBias ID M4
vGS1
M3 ISS
n+
n+
Fig. 5.2-3
1.) Bulks connected to the sources: No modulation of VT but large common mode parasitic capacitance. 2.) Bulks connected to ground: Smaller common mode parasitic capacitors, but modulation of VT. If the technology is n-well CMOS, there is no choice. The bulks must be connected to ground.
Page 5.2-4.
Transconductance Characteristic of the Differential Amplifier - Continued Defining equations: 2iD1 1/2 2iD2 1/2 vID = vGS1 vGS2 = and ISS = iD1 + iD2 Solution: ISS ISS vID iD1 = 2 + 2 ISS
2 4 2vID 2 4ISS
1/2
and
ISS ISS vID iD2 = 2 2 ISS
4 2vID 2 4ISS
1/2
which are valid for vID < 2(ISS/ )1/2. Illustration of the result:
iD/ISS 1.0 0.8 0.6 0.4 iD1 iD2
Differentiating iD1 (or iD2) 0.2 vID with respect to vID and 0.0 -2.0 -1.414 1.414 2.0 (ISS/)0.5 Fig. 5.2-4 setting VID =0V gives diD1 K'1ISSW1 1/2 (half the gm of an inverting amplifier) gm = dvID(VID = 0) = ( ISS/4)1/2 = 4L1
Page 5.2-5.
Voltage Transfer Characteristic of the Differential Amplifier In order to obtain the voltage transfer characteristic, a load for the differential amplifier must be defined. We will select a current mirror load as illustrated below.
VDD
2m 1m 2m 1m
M3 iD3
2m 1m
M4 iD4 iOUT
2m 1m
iD1 M1
iD2 vGS2 +
+ VDD 2 vOUT
M2 ISS M5
vGS1
vG1 -
2m 1m
vG2 Fig. 5.2-5
VBias
Note that output signal to ground is equivalent to the differential output signal due to the current mirror. The short-circuit, transconductance is given as diOUT K'1ISSW1 1/2 gm = dvID (VID = 0) = ( ISS)1/2 = L1
Page 5.2-6.
Voltage Transfer Function of the Differential Amplifer with a Current Mirror Load
VDD = 5V
2m 1m 2m 1m
5 4
iD3
2m 1m
M3 iD1 M1
M4 iD4 iOUT
2m 1m
M4 active M4 saturated VIC = 2V
iD2
vOUT (Volts)
3 2 1 0 -1 -0.5 0 vID (Volts)
M2 ISS M5
vGS1 -
vG1 VBias
2m 1m
+ - vGS2 vOUT vG2 -
M2 saturated M2 active
0.5 1
060705-01
Regions of operation of the transistors: M2 is saturated when, vOUT-VS1 VIC-0.5vID-VS1-VTN vOUT VIC-VTN vDS2 vGS2-VTN where we have assumed that the region of transition for M2 is close to vID = 0V. M4 is saturated when, vSD4 vSG4 - |VTP| VDD-vOUT VSG4-|VTP| vOUT VDD-VSG4+|VTP| The regions of operations shown on the voltage transfer function assume ISS = 100A. 250 vOUT 5 - 1 - 0.7 + 0.7 = 4V Note: VSG4 = 502 +|VTP| = 1 + |VTP|
Page 5.2-7.
Differential Amplifier Using p-channel Input MOSFETs

VDD M5
VBias
+ vG1
vSG1 + M1 iD1 iD3 M3
IDD M2 vSG2 + iD2 iOUT iD4 M4 +
+ vG2 vOUT Fig. 5.2-7
P.E. Allen - 2006
Page 5.2-8.
Input Common Mode Range (ICMR) 2m 1m ICMR is found by setting vID = 0 and varying vIC M3 until one of the transistors leaves the saturation. iD3 Highest Common Mode Voltage 2m 1m iD1 Path from G1 through M1 and M3 to VDD: M1 + VIC(max) =VG1(max) =VG2(max) vGS1 2m =VDD -VSG3 -VDS1(sat) +VGS1 vG1 1m or VBias VIC(max) = VDD - VSG3 + VTN1 Path from G2 through M2 and M4 to VDD: VIC(max) =VDD -VSD4(sat) -VDS2(sat) +VGS2 =VDD -VSD4(sat) + VTN2 VIC(max) = VDD - VSG3 + VTN1 Lowest Common Mode Voltage (Assume a VSS for generality) VIC(min) = VSS +VDS5(sat) + VGS1 = VSS +VDS5(sat) + VGS2
VDD
2m 1m
M4 iD4 iOUT
2m 1m
iD2 vGS2 +
+ VDD 2 vOUT
M2 ISS M5
vG2 Fig. 330-02
where we have assumed that VGS1 = VGS2 during changes in the input common mode voltage.
Page 5.2-9.
Example 5.2-1 - Small-Signal Analysis of the Differential-Mode of the Diff. Amp A requirement for differential-mode operation is that the differential amplifier is balanced.
VDD M3 iD3 iD1 M1 vid M5 VBias ISS M2 vout M4 iD4 iout iD2 + D1=G3=D3=G4 G1 + vid + vg1 G2 + vg2 C1 rds1 i3 1 gm3 rds3 S3 G2 G1 + vid + + vgs2 vgs1 gm1vgs1 D1=G3=D3=G4 i3 1 rds1 rds3 gm3 C3 C1 gm2vgs2 S1=S2=S3=S4 i3 rds2 rds4 C2 gm1vgs1 C3 S1=S2 rds5 rds2 gm2vgs2 i3 D2=D4 C2 + vout iout' + vout Fig. 330-03
rds4 S4 D2=D4
Differential Transconductance: Assume that the output of the differential amplifier is an ac short. gm1gm3rp1 iout = 1 + gm3rp1 vgs1 gm2vgs2 gm1vgs1 gm2vgs2 = gmdvid where gm1 = gm2 = gmd, rp1 = rds1 rds3 and i'out designates the output current into a short circuit.
It can be shown that the current mirror causes this requirement to be invalid because the drain loads are not matched. However, we will continue to use the assumption regardless. CMOS Analog Circuit Design P.E. Allen - 2006
Page 5.2-10.
Small-Signal Analysis of the Differential-Mode of the Diff. Amplifier - Continued Output Resistance: Differential Voltage Gain: vout gmd 1 rout = gds2 + gds4 = rds2||rds4 Av = vid = gds2 + gds4 If we assume that all transistors are in saturation and replace the small signal parameters of gm and rds in terms of their large-signal model equivalents, we achieve vout (K'1ISSW1/L1)1/2 K'1W1 1/2 1 2 Av = vid = ( 2 + 4)(ISS/2) = 2 + 4 ISSL1 ISS Note that the small-signal gain is inversely vout vin Strong Inversion proportional to the square root of the bias Weak current! InversExample: ion If W1/L1 = 2m/1m and ISS = 50A log(IBias) 1A 060614-01 (10A), then Av(n-channel) = 46.6V/V (104.23V/V) Av(p-channel) = 31.4V/V (70.27V/V)
1 1 rout = gds2 + gds4 = 25A0.09V-1 = 0.444M (2.22M

P.E. Allen - 2006
Page 5.2-11.
Common Mode Analysis for the Current Mirror Load Differential Amplifier The current mirror load differential amplifier is not a good example for common mode analysis because the current mirror rejects the common mode signal.
VDD -M3-M4 M1 M3 M4
+
M2
M1
vic + VBias -
v 0V M2 out
M5
Fig. 5.2-8A
Total common Common mode Common mode mode Output = output due to - output due to due to vic M1-M3-M4 path M2 path Therefore: The common mode output voltage should ideally be zero. Any voltage that exists at the output is due to mismatches in the gain between the two different paths.
P.E. Allen - 2006
Page 5.2-12.
Small-Signal Analysis of the Common-Mode of the Differential Amplifier The common-mode gain of the differential amplifier with a current mirror load is ideally zero. To illustrate the common-mode gain, we need a different type of load so we will consider the following:
VDD VDD VDD
M3
vo1
M4 vo2 M2
vid 2
vo1 v1
M3
M4
vo2 v2
vo1
M3
M4
vo2
M1
vid 2
M1
M2
ISS M5
M2 M1 1 ISS M5x 2 ISS 2 2

vic VBias vic
VBias
Differential-mode circuit
General circuit
Common-mode circuit
Fig. 330-05
Differential-Mode Analysis: gm1 vo2 gm2 vo1 -2gm3 and + 2gm4 vid vid Note that these voltage gains are half of the active load inverter voltage gain.
Page 5.2-13.
Small-Signal Analysis of the Common-Mode of the Differential Amplifier Contd Common-Mode Analysis:
gm1vgs1 + vgs1 Assume that rds1 is large and can be + + ignored (greatly simplifies the 1 2rds5 vic rds1 rds3 gm3 vo1 analysis). vgs1 = vg1-vs1 = vic - 2gm1rds5vgs1 Fig. 330-06 Solving for vgs1 gives vic vgs1 = 1 + 2gm1rds5 The single-ended output voltage, vo1, as a function of vic can be written as gm1[rds3||(1/gm3)] (gm1/gm3) gds5 vo1 - 1 + 2gm1rds5 - 2gm3 vic = - 1 + 2gm1rds5 Common-Mode Rejection Ratio (CMRR): |vo1/vid| gm1/2gm3 CMRR = |vo1/vic| = gds5/2gm3 = gm1rds5 How could you easily increase the CMRR of this differential amplifier?
P.E. Allen - 2006
Page 5.2-14.
Frequency Response of the Differential Amplifier Back to the current mirror load differential amplifier:
Cbd3 Cgd1 vid VDD Cgs3+Cgs4 M4 M3 Cgd4 Cbd1 Cbd2 M1 M5 VBias M2 Cbd4 Cgd2 + vout CL G2 G1 D1=G3=D3=G4 + vid + + i3 C3 vgs2 vgs1 1 gm1vgs1 C1 gm2vgs2 gm3 S1=S2=S3=S4 D2=D4 i3 rds2 rds4 C2 iout' + vout -
Fig. 330-07
Ignore the zeros that occur due to Cgd1, Cgd2 and Cgd4. C2 = Cbd2 +Cbd4+Cgd2+CL C1 = Cgd1+Cbd1+Cbd3+Cgs3+Cgs4, If C3 0, then we can write Vout(s)
gm1
and C3 = Cgd4
gds2 + gds4 gm3 2 Vgs1(s) - Vgs2(s) s + 2 where 2 C2 gds2 + gds4 gm3 + sC1 If we further assume that gm3/C1 >> (gds2+gds4)/C2 = 2 then the frequency response of the differential amplifier reduces to gm1 Vout(s) 2 (A more detailed analysis will be made in Chapter 6) Vid(s) gds2 + gds4 s + 2
Page 5.2-15.
AN INTUITIVE METHOD OF SMALL SIGNAL ANALYSIS Simplification of Small Signal Analysis Small signal analysis is used so often in analog circuit design that it becomes desirable to find faster ways of performing this important analysis. Intuitive Analysis (or Schematic Analysis) Technique: 1.) Identify the transistor(s) that convert the input voltage to current (these transistors are called transconductance transistors). 2.) Trace the currents to where they flow into an equivalent resistance to ground. 3.) Multiply this resistance by the current to get the voltage at this node to ground. 4.) Repeat this process until the output is reached. Simple Example: VDD VDD
R1 gm1vin
vin
M2
vo1 gm2vo1
M1
vout
R2
Fig. 5.2-10C
vo1 = -(gm1vin) R1
vout = -(gm2vo1)R2
vout = (gm1R1gm2R2)vin
P.E. Allen - 2006
Page 5.2-16.
Intuitive Analysis of the Current-Mirror Load Differential Amplifier

VDD M3 gm1vid gm1vid 2 2 M1 gm1vid gm2vid 2 2 + vid 2 M5
VBias
M4 rout + M2 vid vout + 2 Fig. 5.2-11
vid
1.) 2.) 3.)
i1 = 0.5gm1vid and i2 = -0.5gm2vid i3 = i1 = 0.5gm1vid i4 = i3 = 0.5gm1vid
1 4.) The resistance at the output node, rout, is rds2||rds4 or gds2 + gds4 5.) gm1vin gm2vin vout = (0.5gm1vid+0.5gm2vid )rout =gds2+gds4 = gds2+gds4 vout gm1 = gds2+gds4 vin
P.E. Allen - 2006
Page 5.2-17.
Some Concepts to Help Extend the Intuitive Method of Small-Signal Analysis 1.) Approximate the output resistance of any cascode circuit as Rout (gm2rds2)rds1 where M1 is a transistor cascoded by M2. 2.) If there is a resistance, R, in series with the source of the transconductance transistor, let the effective transconductance be gm gm(eff) = 1+gmR Proof:
gm2(eff)vin gm2(eff)vin
gm2vgs2 iout M2 vin + vgs2 rds1 Small-signal model

Fig. 5.2-11A
M2
vin VBias
M1 vin
rds1
vgs2 = vg2 - vs2 = vin - (gm2rds1)vgs2 gm2vin Thus, iout = 1+gm2rds1 = gm2(eff) vin
vin vgs2 = 1+gm2rds1
P.E. Allen - 2006
Page 5.2-18.
FURTHER CONSIDERATIONS OF THE DIFFERENTIAL AMPLIFIER Linearization of the Transconductance Goal: i i

out out
ISS vin -ISS
ISS Linearization vin -ISS
060608-03
Method (degeneration):
M3 VDD M4 iout M1 + vin VNBias1 RS 2 RS 2 M2 VDD 2 M1 or + vin RS M5 M6
060118-10
M3
VDD M4 iout M2 VDD 2
M5
VNBias1
P.E. Allen - 2006
Page 5.2-19.
Linearization with Active Devices

M3 VDD M4 iout M1 + vin VNBias1 VBias M6 M5x1/2 M5x1/2 M2 VDD 2 M1 or + vin VNBias1
060608-05
M3
VDD M4 iout M2 M6 M7 VDD 2
M5
M6
M6 is in deep triode region
M6 and M7 are in the triode region
Note that these transconductors on this slide and the last can all be adjusted by changing the value of ISS.
P.E. Allen - 2006
Page 5.2-20.
Slew Rate of the Differential Amplifier Slew Rate (SR) = Maximum output-voltage rate (either positive or negative) dvOUT It is caused by, iOUT = CL dt . When iOUT is a constant, the rate is a constant. Consider the following current-mirror load, differential amplifiers:
VDD M3 iD3 iD1 + M1 vGS1 ISS M5
VBias
VDD M4 iD4 iOUT iD2 + CL vOUT M5

VBias
M2 -
vGS2 + vG2 -
vSG1 + M1 + iD1 vG1 M3 iD3
IDD M2 vSG2 + iD2 iOUT iD4 M4 CL + + vG2 vOUT Fig. 5.2-11B
vG1 -
Note that slew rate can only occur when the differential input signal is large enough to cause ISS (IDD) to flow through only one of the differential input transistors. ISS IDD SR = CL = CL If CL = 5pF and ISS = 10A, the slew rate is SR = 2V/s. (For the BJT differential amplifier slewing occurs at 100mV whereas for the MOSFET differential amplifier it can be 2V or more.)
Page 5.2-21.
Noise Analysis of the Differential Amplifier

VDD M5 M5
VBias VBias
VDD M5 en22 eeq2
en12
*
M3
M1 en32 en42
M2 ito2
*
M4 Vout
M1
M2 vOUT
M3
M4
Fig. 5.2-11C
Solve for the total output-noise current to get, ito 2 = gm12en12 + gm22en22 + gm32en32 + gm42en42 This output-noise current can be expressed in terms of an equivalent input noise voltage, ito2 = gm12eeq2 eeq2, given as Equating the above two expressions for the total output-noise current gives, gm3 2 eeq2 = en12 + en22 + gm1 en32 + en42 1/f Noise (en12=en22 and en32=en42): Thermal Noise (en12=en22 and en32=en42): 2BP KN BN L1 2 W3L1K'3 1/2 16kT eeq(1/f)= fW1L1 1 + KPBP L3 eeq(th)= 1/2 1+ L3W1K'1 3[2K'1(W/L)1I1]
Page 5.2-22.
DIFFERENTIAL AMPLIFIERS WITH DIFFERENTIAL OUTPUT Current-Source Load Differential Amplifier VDD Gives a truly balanced differential amplifier.
M3 X1 M7 X1 I3 I1 M1 X1 M5 M4 X1 I4 I2 X1 M2 I5 X2
Fig. 5.2-12
Also, the upper input common-mode range is extended.
v3 v1
v4 v2
IBias M6
However, a problem occurs if I1

Current I3 I1
I3 or if I2
Current I3
I4.
X1
I1
0 0
VDS1<VDS(sat) (a.) I1>I3.
VDD
vDS1 0 0
VSD3<VSD(sat) (b.) I3>I1.
VDD
vDS1
Fig. 5.2-13
P.E. Allen - 2006
Page 5.2-23.
A Differential-Output, Differential-Input Amplifier Probably the best way to solve the current mismatch problem is through the use of common-mode feedback. Consider the following solution to the previous problem.
VDD M3 IBias MC3
Commonmode feedback circuit MC4 IC4 MC2A v1 MC2B MC5 MB v3
M4 I3 I4
v4 Selfresistances of M1-M4 v2
IC3
MC1
VCM
M1 M5
M2
VSS
Fig. 5.2-14
Operation: Common mode output voltages are sensed at the gates of MC2A and MC2B and compared to VCM. The current in MC3 provides the negative feedback to drive the common mode output voltage to the desired level. With large values of output voltage, this common mode feedback scheme has flaws.
Page 5.2-24.
Common-Mode Stabilization of the Diff.-Output, Diff.-Input Amplifier - Continued The following circuit avoids the large differential output signal swing problems.
VDD M3 IBias MC3
Commonmode feedback circuit MC4 IC4 MC2 v3 RCM1 RCM2 v1 MC5 MB
M4 I3 I4
v4 Selfresistances of M1-M4 v2
IC3
MC1
VCM
M1 M5
M2
VSS
Fig. 5.2-145
Note that RCM1 and RCM2 must not load the output of the differential amplifier.
P.E. Allen - 2006
Page 5.2-25.
DESIGNING DIFFERENTIAL AMPLIFIERS Design of a CMOS Differential Amplifier with a Current Mirror Load VDD Design Considerations: Constraints Specifications Small-signal gain Power supply M3 M4 Frequency response (CL) Technology vout Temperature ICMR CL Slew rate (CL) + vin M1 M2 Power dissipation Relationships Av = gm1Rout I5 -3dB = 1/RoutCL M5 VBias VIC(max) = VDD - VSG3 + VTN1 ALA20 VSS VIC(min) = VSS +VDS5(sat) + VGS1 = VSS +VDS5(sat) + VGS2 SR = ISS/CL Pdiss = (VDD+|VSS|)xAll dc currents flowing from VDD or to VSS
P.E. Allen - 2006
Page 5.2-26.
Design of a CMOS Differential Amplifier with a Current Mirror Load - Continued

Max. ICMR VSG4 +
VDD
Schematic-wise, the design procedure is illustrated as shown: Procedure: 1.) Pick ISS to satisfy the slew rate knowing CL or the power dissipation 2.) Check to see if Rout will satisfy the frequency response, if not change ISS or modify circuit 3.) Design W3/L3 (W4/L4) to satisfy the upper ICMR 4.) Design W1/L1 (W2/L2) to satisfy the gain 5.) Design W5/L5 to satisfy the lower ICMR 6.) Iterate where necessary
M3
M4
vout
gm1Rout + vin
CL
M2
M1 Min. ICMR
+ VBias -
I5
I5 = SRCL, -3dB, Pdiss
M5 VSS
ALA20
P.E. Allen - 2006
Page 5.2-27.
Example 5.2-2 - Design of a MOS Differential Amp. with a Current Mirror Load Design the currents and W/L values of the current mirror load MOS differential amplifier to satisfy the following specifications: VDD = -VSS = 2.5V, SR 10V/s (CL=5pF), f100kHz (CL=5pF), a small signal gain of 100V/V, -1.5V ICMR 2V and Pdiss 3dB 1mW. Use the parameters of KN=110A/V2, KP=50A/V2, VTN=0.7V, VTP=-0.7V, N=0.04V-1 and P=0.05V-1. Solution 1.) To meet the slew rate, ISS 50A. For maximum Pdiss, ISS 200A. 2 318k . Therefore Rout = ( N+ P)ISS ISS 70A Thus, pick ISS = 100A 2V = 2.5 - VSG3 + 0.7 3.) VIC(max) = VDD - VSG3 + VTN1 250A VSG3 = 1.2V = 50A/V2(W3/L3) + 0.7 2.) f-3dB of 100kHz implies that Rout W3 W4 2 L3 = L4 = (0.5)2 = 8 2110A/V2(W1/L1) gm1 4.) 100=gm1Rout=gds2+gds4 = (0.04+0.05) 50A = 23.31
318k
W1 L1
W1 W2 L1= L2 =18.4
P.E. Allen - 2006
Page 5.2-28.
Example 5.2-2 - Continued 5.) VIC(min) = VSS +VDS5(sat)+VGS1 -1.5 = -2.5+VDS5(sat)+ 250A 110A/V2(18.4) + 0.7
VDS5(sat) = 0.3 - 0.222 = 0.0777
W5 2ISS = K V (sat)2 = 150.6 L5 N DS5
We probably should increase W1/L1 to reduce VGS1. If we choose W1/L1 = 40, then VDS5(sat) = 0.149V and W5/L5 = 41. (Larger than specified gain should be okay.)
P.E. Allen - 2006
Page 5.3-1.
SECTION 5.3 CASCODE (COMMON GATE) AMPLIFIERS

VOLTAGE-DRIVEN COMMON GATE AMPLIFIER Common Gate Amplifier VDD VDD VPBias1 Circuit: R
L
vOUT
M3 vOUT
VNBias2
VNBias2 VNBias1
M2
vIN
IBias
vIN
M1
060609-01
Large Signal Characteristics: VOUT(max) VDD VDS3(sat) VOUT(min) VDS1(sat) + VDS2(sat) Note VDS1(sat) = VON1
vOUT VDD
VON3
VON2 VON1+VON2 VON1

VT2 VNBias2
vIN
060609-02
P.E. Allen - 2006
Page 5.3-2.
Small Signal Performance of the Common Gate Amplifier Small signal model:
rds2 Rin vin rds1 vgs2 gm2vgs2 rds3 + Rout vout vin Rin i1 rds2 Rout vout
060609-03
+ rds1 vs2 gm2vs2 rds3
rds2 gm2rds2rds3 vout = gm2vs2 rds2+rds3 rds3 = rds2+rds3 vin
vout gm2rds2rds3 Av = vin = + rds2+rds3
Rin = Rin||rds1, Rin is found as follows vs2 = (i1 - gm2vs2)rds2 + i1rds3 = i1(rds2 + rds3) - gm2 rds2vs2 vs2 rds2 + rds3 Rin' = i1 = 1 + gm2rds2 Rout rds2||rds3 rds2 + rds3 Rin = rds1||1 + gm2rds2
P.E. Allen - 2006
Page 5.3-3.
Frequency Response of the Common Gate Amplifier Circuit:

VDD VPBias1 Cgd3 Cgd2 VNBias2 VNBias1 M3 rds2 Cbd3 vOUT Cbd2 M2 CL Vin + rds1 Vs2 gm2Vs2 rds3 Vout
Cout
vIN
M1
060609-04
The frequency response can be found by replacing rds3 in the previous slide with, rds3 rds3 where Cout = Cgd2 + Cgd3 + Cbd2 + Cbd3 + CL srds3Cout + 1 Vout gm2rds2rds3 gm2rds2rds3 1 1 = + rds2+rds3 Av(s) = Vin = + rds2+rds3 s rds2rds3Cout 1 - p1 s rds2+rds3 + 1 where -1 p1 = rds2rds3 Cout rds2+rds3
-3dB = |p1|
P.E. Allen - 2006
Page 5.3-4.
VOLTAGE-DRIVEN CASCODE AMPLIFIER Cascode Amplifier

VDD VPBias1 VNBias2 M3 vOUT M2 M1 vIN
060609-05
Advantages of the cascode amplifier: Increases the output resistance and gain (if M3 is cascaded also) Eliminates the Miller effect when the input source resistance is large
P.E. Allen - 2006
Page 5.3-5.
Large-Signal Characteristics of the Cascode Amplifier

vIN=5.0V 0.5 0.4 vIN=4.5V vIN=4.0V vIN=3.5V vIN=3.0V vIN=2.5V
K JIH G F E
2.3V
5V M3 W3 2m = L3 1m ID M2 + W2 = 2m L2 1m vOUT W1 2m = L1 1m -
ID (mA)
0.3 0.2 0.1
M3
D A,B
vIN=2.0V 3.4V M1
C vIN=1.0V
vIN=1.5V
+ vIN
0.0 0
vOUT
5 A B C
D
4
E
vOUT
3 2
M3 active M3 saturated
M2 saturated M2 active F
1
Fig. 5.3-2
G H I J K
0 0
M1 saturated
M1 active
2v 3 IN
M1 sat. when VGG2-VGS2 VGS1-VT vIN 0.5(VGG2+VTN) where VGS1=VGS2 M2 sat. when VDS2 VGS2-VTN vOUT-VDS1 VGG2-VDS1-VTN vOUT VGG2-VTN M3 is saturated when VDD-vOUT VDD - VGG3 - |VTP| vOUT VGG3 + |VTP|
Page 5.3-6.
Large-Signal Voltage Swing Limits of the Cascode Amplifier Maximum output voltage, vOUT(max): vOUT(max) = VDD Minimum output voltage, vOUT(min): Referencing all potentials to the negative power supply (ground in this case), we may express the current through each of the devices, M1 through M3, as iD1 = iD2 = and (V VGG3 |VT3|)2 2 DD where we have also assumed that both vDS1 and vOUT are small, and vIN = VDD. Solving for vOUT by realizing that iD1 = iD2 = iD3 and 1 = 2 we get, vOUT(min) = 2 2 (VDD
vDS1 (VDD - VT1)vDS1 - 2
1(VDD
- VT1)vDS1 (vOUT - vDS1)2 2
2 (VGG2 - vDS1 - VT2)(vOUT - vDS1) 2(VGG2 - vDS1 - VT2)(vOUT - vDS1) 3
iD3 =
VGG3
1 1 |VT3|)2 VGG2 VT2 + VDD VT1

P.E. Allen - 2006
Page 5.3-7.
Example 5.3-1 - Calculation of the Min. Output Voltage for the Cascode Amplifier (a.) Assume the values and parameters used for the cascode configuration plotted in the previous slide on the voltage transfer function and calculate the value of vOUT(min). (b.) Find the value of vOUT(max) and vOUT(min) where all transistors are in saturation. Solution (a.) Using the previous result gives, vOUT(min) = 0.50 volts. We note that simulation gives a value of about 0.75 volts. If we include the influence of the channel modulation on M3 in the previous derivation, the calculated value is 0.62 volts which is closer. The difference is attributable to the assumption that both vDS1 and vOUT are small. (b.) The largest output voltage for which all transistors of the cascode amplifier are in saturation is given as vOUT(max) = VDD - VSD3(sat) and the corresponding minimum output voltage is vOUT(min) = VDS1(sat) + VDS2(sat) . For the cascode amplifier of Fig. 5.3-2, these limits are 3.0V and 2.7V. Consequently, the range over which all transistors are saturated is quite small for a 5V power supply.
Page 5.3-8.
Small-Signal Midband Performance of the Cascode Amplifier Small-signal model:

gm2vgs2= -gm2v1 G1 D2=D3 rds2 + + + vin = v1 rds3 vout vgs1 gm1vgs1 rds1 S1=G2=G3 Small-signal model of cascode amplifier neglecting the bulk effect on M2. C1 rds2 D1=S2 D2=D3 G1 + + + vin 1 v1 gm2v1 gm1vin rds3 C3 vout rds1 gm2 C2 Simplified equivalent model of the above circuit. Fig. 5.3-3 D1=S2
Using nodal analysis, we can write, [gds1 + gds2 + gm2]v1 gds2vout = gm1vin [gds2 + gm2]v1 + (gds2 + gds3)vout = 0 Solving for vout/vin yields vout gm1(gds2 + gm2) = gds1gds2 + gds1gds3 + gds2gds3 + gds3gm2 vin The small-signal output resistance is, rout = [rds1 + rds2 + gm2rds1rds2]||rds3 rds3
gm1 gds3 =
2K'1W1 L1ID 23
P.E. Allen - 2006
Page 5.3-9.
Small-Signal Analysis of the Cascode Amplifier - Continued It is of interest to examine the voltage gain of v1/vin. From the previous nodal equations, v1 gm1(gds2+gds3) 2gm1 gds2+gds3 gm1 W1L2 vin = gds1gds2+gds1gds3+gds2gds3+gds3gm2 gds3 gm2 gm2 = 2 L1W2 If the W/L ratios of M1 and M2 are equal and gds2 = gds3, then v1/vin is approximately 2. Why is this gain -2 instead of -1? gm2vs2 iA Rs2 Consider the small-signal model looking into the i1 iB source of M2: rds3 The voltage loop is written as, vs2 rds2 vs2 = (i1 - gm2vs2)rds2 + i1rds3 Fig. 5.3-4 Solving this equation for the ratio of vs2 to i1 = i1(rds2 + rds3) - gm2 rds2vs2 gives vs2 rds2 + rds3 Rs2 = i1 = 1 + gm2rds2 We see that Rs2 equals 2/gm2 if rds2 rds3. Thus, if gm1 gm2, the voltage gain v1/vin -2. Note that: rds3 =0 that Rs2 1/gm2 or rds3=rds2 that Rs2 2/gm2 or rds3 rds2gmrds that Rs2 rds!!! Principle: The small-signal resistance looking into the source of a MOSFET depends on the resistance connected from the drain of the MOSFET to ac ground.
Page 5.3-10.
Frequency Response of the Cascode Amplifier Small-signal model (RS = 0): C1 rds2 D1=S2 G1 where + + vin C1 = Cgd1, 1 v1 gm2v1 gm1vin rds1 gm2 C2 C2 = Cbd1+Cbs2+Cgs2, and C3 = Cbd2+Cbd3+Cgd2+Cgd3+CL The nodal equations now become: (gm2 + gds1 + gds2 + sC1 + sC2)v1 gds2vout = (gm1 sC1)vin and (gds2 + gm2)v1 + (gds2 + gds3 + sC3)vout = 0 Solving for Vout(s)/Vin(s) gives, (gm1 sC1)(gds2 + gm2) Vout(s) 1 Vin(s) = 1 + as + bs2 gds1gds2 + gds3(gm2 + gds1 + gds2) where C3(gds1 + gds2 + gm2) + C2(gds2 + gds3) + C1(gds2 + gds3) a= gds1gds2 + gds3(gm2 + gds1 + gds2) and C3(C1 + C2) b = gds1gds2 + gds3(gm2 + gds1 + gds2)
D2=D3 rds3 C3 + vout -
Fig. 5.3-4A
P.E. Allen - 2006
Page 5.3-11.
A Simplified Method of Finding an Algebraic Expression for the Two Poles Assume that a general second-order polynomial can be written as: s s s2 1 1 P(s) = 1 + as + bs2 = 1 p1 1 p2 = 1 s p1 + p2 + p1p2 Now if |p2| >> |p1|, then P(s) can be simplified as s2 s P(s) 1 p1 + p1p2 Therefore we may write p1 and p2 in terms of a and b as 1 a p1 = a and p2 = b Applying this to the previous problem gives, [gds1gds2 + gds3(gm2 + gds1 + gds2)] gds3 p1 = C3(gds1 + gds2 + gm2) + C2(gds2 + gds3) + C1(gds2 + gds3) C3 The nondominant root p2 is given as [C3(gds1 + gds2 + gm2) + C2(gds2 + gds3) + C1(gds2 + gds3)] gm2 p2 = C3(C1 + C2) C1 + C2 Assuming C1, C2, and C3 are the same order of magnitude, and gm2 is greater than gds3, then |p1| is smaller than |p2|. Therefore the approximation of |p2| >> |p1| is valid. Note that there is a right-half plane zero at z1 = gm1/C1.
Page 5.3-12.
NON-VOLTAGE DRIVEN CASCODE AMPLIFIER THE MILLER EFFECT Miller Effect Consider the following inverting amplifier:
I1 CM -Av
+
Solve for the input impedance: V1 Zin(s) = I1 Therefore,
V1
V2 = -AvV1
060610-03
I1 = sCM(V1 V2) = sCM(V1 + AvV1) = sCM(1 + Av)V1 V1 V1 1 1 Zin(s) = I1 = sCM(1 + Av)V1 = sCM(1 + Av) = sCeq The Miller effect can take Cgd = 5fF and make it look like a 0.5pF capacitor in parallel with the input of the inverting amplifier (Av -100). If the source resistance is large, this creates a dominant pole at the input.
Page 5.3-13.
Simple Inverting Amplifier Driven with a High Source Resistance VDD C2 Examine the frequency M2 + response of a current-source load + Vin VGG2 vout C3 V1 Vout Rs C1 R3 Rs inverter driven from a high g V - m1 1 M1 resistance source: vin C1 Cgs1 C3 = Cbd1 + Cbd2 + Cgd2 Rs Assuming the input is Iin, the Rs R3 = rds1||rds2 C2 = Cgd1 Fig. 5.3-5 nodal equations are, [G1 + s(C1 + C2)]V1 sC2Vout = Iin and (gm1 sC2)V1+[G3+s(C2+C3)]Vout = 0 where G1 = Gs (=1/Rs), G3 = gds1 + gds2, C1 = Cgs1, C2 = Cgd1 and C3 = Cbd1+Cbd2 + Cgd2. Solving for Vout(s)/Vin(s) gives (sC2 gm1)G1 Vout(s) = G1G3+s[G3(C1+C2)+G1(C2+C3)+gm1C2]+(C1C2+C1C3+C2C3)s2 or, Vin(s) [1 s(C2/gm1)] Vout(s) gm1 = G3 1+[R1(C1+C2)+R3(C2+C3)+gm1R1R3C2]s+(C1C2+C1C3+C2C3)R1R3s2 Vin(s) Assuming that the poles are split allows the use of the previous technique to get, gm1C2 1 1 p1 = R1(C1+C2)+R3(C2+C3)+gm1R1R3C2 gm1R1R3C2 and p2 C1C2+C1C3+C2C3 The Miller effect has caused the input pole, 1/R1C1, to be decreased by a value of gm1R3.
Page 5.3-14.
How Does the Cascode Amplifier Solve the Miller Effect? Cascode amplifier:
VDD
VPBias1 VNBias2
Cgd1 RS
vS + vIN
-
M3
+
M2 Rs2 +
vOUT
060610-02
v1 M1
The Miller effect causes Cgs1 to be increased by the value of 1 + (v1/vin) and appear in parallel with the gate-source of M1 causing a dominant pole to occur. The cascode amplifier eliminates this problem by keeping the value of v1/vin small by making the value of Rs2 approximately 2/gm2.
P.E. Allen - 2006
Page 5.3-15.
Comparison of the Inverting and Cascode Non-Voltage Driven Amplifiers The dominant pole of the inverting amplifier with a large source resistance was found to be 1 p1(inverter) = R1(C1+C2)+R3(C2+C3)+gm1R1R3C2 Now if a cascode amplifier is used, R3, can be approximated as 2/gm of the cascoding transistor (assuming the drain sees an rds to ac ground). p1(cascode) = 1 2 2 R1(C1+C2)+ gm (C2+C3)+gm1R1 gm C2 1 R1(C1+3C2)
1 2 R1(C1+C2)+ gm (C2+C3)+2R1C2 Thus we see that p1(cascode) >> p1(inverter). =
P.E. Allen - 2006
Page 5.3-16.
High Gain and High Output Resistance Cascode Amplifier V M4 DD If the load of the cascode D2=D3 VPBias1 amplifier is a cascode current source, then both VPBias2 M3 gm2v1 gmbs2v1 rds2 gm3v4 vout high output resistance M2 D1=S2 G1 Rout and high voltage gain is VNBias2 + + achieved. M1 vin
vin gm1vin v1 rds1
+ gmbs3v4 rds3 D4=S3 + v4 rds4 060609-07
vout
G2=G3=G4=S1=S4
The output resistance is, rout [gm2rds1rds2] [gm3rds3rds4] = ID

1 2 -1.5 3 4
2K'2(W/L)2 + 2K'3(W/L)3 2K'1(W/L)1ID

1 2 -1 3 4
Knowing rout, the gain is simply Av = gm1rout gm1{[gm2rds1rds2] [gm3rds3rds4]}
2K'2(W/L)2 + 2K'3(W/L)3
P.E. Allen - 2006
Page 5.3-17.
Example 5.3-2 - Comparison of the Cascode Amplifier Performance Calculate the small-signal voltage gain, output resistance, the dominant pole, and the nondominant pole for the low-gain, cascode amplifier and the high-gain, cascode amplifier. Assume that ID = 200 microamperes, that all W/L ratios are 2m/1m, and that the parameters of Table 3.1-2 are valid. The capacitors are assumed to be: Cgd = 3.5 fF, Cgs = 30 fF, Cbsn = Cbdn = 24 fF, Cbsp = Cbdp = 12 fF, and CL = 1 pF. Solution The low-gain, cascode amplifier has the following small-signal performance: Av = 37.1V/V Rout = 125k p1 -gds3/C3 1.22 MHz p2 gm2/(C1+C2) 605 MHz. The high-gain, cascode amplifier has the following small-signal performance: Av = 414V/V Rout = 1.40 M p1 1/RoutC3 108 kHz p2 gm2/(C1+C2) 579 MHz (Note at this frequency, the drain of M2 is shorted to ground by the load capacitance, CL)
Page 5.3-18.
Designing Cascode Amplifiers Pertinent design equations for the simple cascode amplifier.
vOUT(max) = VDD - VSD3(sat) 2I =VDD KP(W3/L3)
I=
KPW3 2 2L3 (VDD - VGG3-|VTP|) VGG3
VDD M3
M2 VGG2 VGG2 = VDS1(sat) + VGS2 + vIN

Fig. 5.3-7
vOUT(min) =VDS1(sat) + VDS2(sat) 2I 2I = + KN(W1/L1) KN(W2/L2)
I M1
vOUT
I = Pdiss = (SR)Cout VDD

-
g |Av| = g m1 = 2KN(W1/L1) ds3 P2I
P.E. Allen - 2006
Page 5.3-19.
Example 5.3-3 - Design of a Cascode Amplifier The specs for a cascode amplifier are Av = -50V/V, vOUT(max) = 4V, vOUT(min) = 1.5V, VDD=5V, and Pdiss=1mW. The slew rate with a 10pF load should be 10V/s or greater. Solution The slew rate requires a current greater than 100A while the power dissipation requires a current less than 200A. Compromise with 150A. Beginning with M3, W3 2I 2150 = K [V -v 2 = 50(1)2 = 6 L3 P DD OUT(max)] 2I 2150 From this find VGG3: VGG3 = VDD - |VTP| - KP(W3/L3) = 5 - 1 506 = 3V W1 (Av )2I (500.05)2(150) = 2.73 2110 L1 = 2KN = To design W2/L2, we will first calculate VDS1(sat) and use the vOUT(min) specification to 2I 2150 VDS1(sat) = KN(W1/L1) = 1104.26 = 0.8V define VDS2(sat). Next, Subtracting this value from 1.5V gives VDS2(sat) = 0.7V. W2 2I 2150 L2 = KNVDS2(sat)2 = 1100.72 = 5.57 2I Finally, VGG2 = VDS1(sat) + KN(W2/L2) + VTN = 0.8V+ 0.7V + 0.7V = 2.2V
P.E. Allen - 2006
Page 5.4-1.
SECTION 5.4 CURRENT AMPLIFIERS

What is a Current Amplifier? An amplifier that has a defined output-input current relationship Low input resistance High output resistance Application of current amplifiers:
ii Ai iS RS io iS RL RS ii + Ai ii io RL
Fig. 5.4-1
Current Amplifier Single-ended input.
Current Amplifier
Differential input.
RS >> Rin
and Rout >> RL
Advantages of current amplifiers: Currents are not restricted by the power supply voltages so that wider dynamic ranges are possible with lower power supply voltages. -3dB bandwidth of a current amplifier using negative feedback is independent of the closed loop gain.
Page 5.4-2.
Frequency Response of a Current Amplifier with Current Feedback R2 Consider the following current amplifier with resistive i2 negative feedback applied. i1 Ai R1 Assuming that the small-signal resistance looking into the current amplifier is much less than R1 or R2, vin io = Ai(i1-i2) = Ai R1 - io Solving for io gives R2 Ai Ai vin vout = R2io = R1 1+Ai vin io = 1+Ai R1 If Ai(s) = s Ao , then 1 Ao s
A +(1+Ao)
vin + -
io
vout
Fig. 5.4-2
+1 A R2 Ao = R1 1+Ao 1 s +1 A(1+Ao)
vout R2 vin = R1
R2 1 = R1 1+ Ai(s) -3dB = A(1+Ao)
P.E. Allen - 2006
Page 5.4-3.
Bandwidth Advantage of a Current Feedback Amplifier The unity-gainbandwidth is, R2 R2 R2Ao GB = |Av(0)| -3dB = R1(1+Ao) A(1+Ao) = R1 Ao A = R1 GBi where GBi is the unity-gainbandwidth of the current amplifier. Note that if GBi is constant, then increasing R2/R1 (the voltage gain) increases GB. Illustration:
R Voltage Amplifier, R2 > K R2 Ao 1 dB R2 R1 1+Ao Voltage Amplifier, R = K >1 1 Ao dB K 1+Ao Current Amplifier Ao dB
(1+Ao)A 0dB
Magnitude dB
GBi
GB1 GB2
log10() Fig. 7.2-10
Note that GB2 > GB1 > GBi The above illustration assumes that the GB of the voltage amplifier realizing the voltage buffer is greater than the GB achieved from the above method.
Page 5.4-4.
Current Amplifier using the Simple Current Mirror

VDD VDD
iin M1
I1 R
I2
iout M2
iin + vin gm1vin C2 rds1 C1 gm2vin rds2 C3
iout RL 0
Fig. 5.4-3
Current Amplifier
W2/L2 1 1 Rin = gm1 Rout = 1Io and Ai = W1/L1 . Frequency response: -(gm1+gds1) -(gm1+gds1) -gm1 p1 = C1+C2 = Cbd1+Cgs1+Cgs2+Cgd2 Cbd1+Cgs1+Cgs2+Cgd2 Note that the bandwidth can be almost doubled by including the resistor, R. (R removes Cgs1 from p1)
P.E. Allen - 2006
Page 5.4-5.
Example 5.4-1- Performance of a Simple Current Mirror as a Current Amplifier Find the small-signal current gain, Ai, the input resistance, Rin, the output resistance, Rout, and the -3dB frequency in Hertz for the current amplifier of Fig. 5.4-3(a) if 10I1 = I2 = 100A and W2/L2 = 10W1/L1 = 10m/1m. Assume that Cbd1 = 10fF, Cgs1 = Cgs2 = 100fF, and Cgs2 = 50fF. Solution Ignoring channel modulation and mismatch effects, the small-signal current gain, W2/L2 Ai = W1/L1 10A/A. The small-signal input resistance, Rin, is approximately 1/gm1 and is 1 1 Rin = 46.9S = 21.3k 2KN(1/1)10A The small-signal output resistance is equal to 1 Rout = NI2 = 250k . The -3dB frequency is 46.9S 6 f-3dB = 28.7 MHz -3dB = 260fF = 180.4x10 radians/sec.
Page 5.4-6.
Wide-Swing, Cascode Current Mirror Implementation of a Current Amplifier

VDD VDD
IIN
iin + VNBias2 vIN M1 M3
IOUT
iout M4 + vOUT M2
060610-01
Rin
gm1,
Rout
rds2gm4rds4,
and
W2/L2 Ai = W1/L1
P.E. Allen - 2006
Page 5.4-7.
Example 5.4 -2 - Current Amplifier Implemented by the Wide-Swing, Cascode Current Mirror Assume that IIN and IOUT of the wide-swing cascode current mirror are 100A. Find the value of Rin, Rout, and Ai if the W/L ratios of all transistors are 182m/1m. Solution The input resistance requires gm1 which is 2110182100 = 2mS Rin 500 From our knowledge of the cascode configuration, the small signal output resistance should be Rout gm4rds4rds2 = (2001S)(250k )(250k ) = 125M Because VDS1 = VDS2, the small-signal current gain is W2/L2 Ai = W1/L1 = 1 Simulation results using the level 1 model for this example give Rin= 497 , Rout = 164.7M and Ai = 1.000 A/A. The value of VON for all transistors is VON =
2100A 110A/V2182 = 0.1V

P.E. Allen - 2006
Page 5.4-8.
Low-Input Resistance Current Amplifier VDD To decrease Rin below 1/gm I1 requires the use of negative, iin shunt feedback. Consider M3 the following example.
M1 I3
VDD I2 iout
iin + vin - gm1vgs1 vgs3 rds1 + gm3vgs3 rds3 i=0 + vgs1 -
M2 VGG3
Fig. 5.4-5
Feedback concept: Input resistance without feedback rds1. gm1 gm3 Loop gain gds1 gds3 assuming that the resistances of I1 and I3 are very large. Rin(no fb.) Rin = 1 + Loop gain rds1 1 gm1rds1gm3rds3 = gm1gm3rds3
Current Amplifier
Small signal analysis: iin = gm1vgs1 - gds1vgs3 and vgs3 = -vin vgs1 = vin - (gm3 vgs3rds3) = vin(1+gm3rds3) iin = gm1(1+gm3rds3)vin + gds1vin
gm1gm3rds3vin
Rin
1 gm1gm3rds3
P.E. Allen - 2006
Page 5.4-9.
Differential-Input, Current Amplifiers Definitions for the differential-mode, iID, and common-mode, iIC, input currents of the differential-input current amplifier.
iIC 2 iID iIC 2 + i1 i2 iO
Fig. 5.4-6
i1+i2 iO = AIDiID AICiIC = AID(i1 - i2) AIC 2 Implementations:

VDD I i1 i2 M1 M2 i2 M3 M4 VDD 2I VDD iO i1-i2 M5 VGG2
Fig. 5.4-7
M3
VDD M4 iO
M1 i1
VGG1
M2 i2 M6
P.E. Allen - 2006
Page 5.4-10.
Summary Current amplifiers have a low input resistance, high output resistance, and a defined output-input current relationship Input resistances less than 1/gm require feedback However, all feedback loops have internal poles that cause the benefits of negative feedback to vanish at high frequencies. In addition, these feedback loops can have a slow time constant from a pole-zero pair. Voltage amplifiers using a current amplifier have high values of gain-bandwidth Current amplifiers are useful at low power supplies and for switched current applications
P.E. Allen - 2006
Page 5.5-1.
SECTION 5.5 - OUTPUT AMPLIFIERS

INTRODUCTION General Considerations of Output Amplifiers Requirements: 1.) Provide sufficient output power in the form of voltage or current. 2.) Avoid signal distortion. 3.) Be efficient 4.) Provide protection from abnormal conditions (short circuit, over temperature, etc.) Types of Output Amplifiers: 1.) Class A amplifiers 2.) Source followers 3.) Push-pull amplifiers 4.) Substrate BJT amplifiers 5.) Amplifiers using negative shunt feedback
VDD f1(vIN) vIN f2(vIN) Buffer Class A i2 VSS i1 i1 iOUT + vOUT -
RL
Current
t i2=IQ Class AB i1 iOUT iOUT t i2 i1 iOUT t i2

P.E. Allen - 2006
Fig. 5.5-005
Current
Current
Class B
Page 5.5-2.
CLASS A AMPLIFIERS Current source load inverter A Class A circuit has current flow in the MOSFETs during the entire period of a sinusoidal signal. Characteristics of Class A amplifiers: Unsymmetrical sinking and sourcing Linear Poor efficiency
VDD M2 iOUT
VDD+|VSS| RL
vOUT
iD
VGG2
IQ iD1
IQ
RL dominates as the load line
vIN
M1CL
RL
VSS VSS
IQRL
IQRL
vOUT VDD
Fig. 5.5-1
vOUT(peak)2 2RL PRL Efficiency = PSupply = (VDD-VSS)IQ =
vOUT(peak)2 2RL vOUT(peak) 2 = VDD -VSS (VDD-VSS) (VDD -VSS) 2RL Maximum efficiency occurs when vOUT(peak) = VDD = |VSS| which gives 25%.
P.E. Allen - 2006
Page 5.5-3.
Optimum Value of Load Resistor Depending on the value of RL, the signal swing can be symmetrical or asymmetrical. (This ignores the limitations of the transistor.)
iD1 Smaller RL VDD+|VSS| RL Minimum RL for maximum swing
IQ
0
Larger RL
VSS
IQRL
IQRL
vDS1 VDD Fig. 040-03
P.E. Allen - 2006
Page 5.5-4.
Specifying the Performance of a Class A Amplifier Output resistance: 1 1 rout = gds1+ gds2 = ( 1+ 2)ID Current: Maximum sinking current is, K'1W1 IOUT= 2L1 (VDD -VSS - VT1)2 - IQ Maximum sourcing current is, K'2W2 + IOUT = 2L2 (VDD - VGG2 - |VT2|)2 IQ
vOUT
Imax due to RL
Requirements: Imax due to CL Want rout << RL t |IOUT| > CLSR vOUT(peak) |IOUT| > RL Imax due to RL 070118-01 The maximum current is determined by both the current required to provide the necessary slew rate (CL) and to provide a voltage across the load resistor (RL).
Page 5.5-5.
Small-Signal Performance of the Class A Amplifier Although we have considered the small-signal performance of the Class A amplifier as the current source load inverter, let us include the influence of the load. The modified small-signal model:
C1 + vin gm1vin rds1 rds2 RL C2 + vout Fig. 5.5-2
The small-signal voltage gain is: -gm1 vout = gds1+gds2+GL vin The small-signal frequency response includes: A zero at gm1 z = Cgd1 and a pole at -(gds1+gds2+GL) p = Cgd1+Cgd2+Cbd1+Cbd2+CL
Page 5.5-6.
Example 5.5-1 - Design of a Simple Class-A Output Stage Use Table 3.1-2 to design the W/L ratios of M1 and M2 so that a voltage swing of 2V and a slew rate of 1 V/s is achieved if RL = 20 k and CL = 1000 pF. Assume VDD = |VSS| = 3V and VGG2 = 0V. Let L = 2 m and assume that Cgd1 = 100fF. Solution Let us first consider the effects of RL and CL. iOUT(peak) = 2V/20k = 100A and CLSR = 10-9106 = 1000A Since the slew rate current is so much larger than the current needed to meet the voltage specification across RL, we can safely assume that all of the current supplied by the inverter is available to charge CL. Using a value of 1 mA, 2(IOUT-+IQ) W1 4000 3m = L1 K (V +|V | -V )2 = 110(5.3)2 2m N DD SS TN and 2IOUT+ W2 2000 15m = L2 = K (V -V 2m P DD GG2-|VTP|)2 50(2.3)2 The small-signal performance is Av = -8.21 V/V (includes RL = 20k ) and rout = 50k The roots are, zero = gm1/Cgd1 .59GHz and pole = 1/[(RL||rout)CL)] -11.14kHz
Page 5.5-7.
Broadband Harmonic Distortion The linearity of an amplifier can be characterized by its influence on a pure sinusoidal input signal. Assume the input is, Vin( ) = Vp sin( t) The output of an amplifier with distortion will be Vout( ) = a1Vp sin ( t) + a2Vp sin (2 t) +...+ anVp sin(n t) Harmonic distortion (HD) for the ith harmonic can be defined as the ratio of the magnitude of the ith harmonic to the magnitude of the fundamental. For example, second-harmonic distortion would be given as a2 HD2 = a1 Total harmonic distortion (THD) is defined as the square root of the ratio of the sum of all of the second and higher harmonics to the magnitude of the first or fundamental [a2 + a3 +...+ an]1/2 Thus, THD can be expressed as THD = a1 The distortion of the class A amplifier is good for small signals and becomes poor at maximum output swings because of the nonlinearity of the voltage transfer curve for large-signal swing
Page 5.5-8.
Class-A Source Follower N-Channel Source Follower with current sink bias:
VDD IQ vIN M1 VSS M3 VSS M2 VSS iOUT vOUT VDD
Voltage transfer curve:

vOUT VDD VDD-VON1 Triode VDD-VGS1
|VSS|+VON2+VGS1
VGS1 VDD-VON1+VGS1
IQRL<|VSS|+VON2 vIN
RL
Fig. 040-01
Triode
|VSS|+VON2 |VSS|
Fig. 040-02
Maximum output voltage swings: vOUT(min) VSS - VON2 (if RL is large) vOUT(max) = VDD - VON1 (if vIN > VDD)
or or
vOUT(min) -IQRL (if RL is small) vOUT(max) VDD - VGS1
P.E. Allen - 2006
Page 5.5-9.
Output Voltage Swing of the Follower The previous results do not include the bulk effect on VT1 of VGS1. Therefore, VT1 = VT01 + [ 2| F| -vBS- 2| F|] vOUT(max)-VSS Define vOUT(max)-VSS = vOUT(max) which gives the quadratic, vOUT(max)+ 1 vOUT(max)-(VDD-VSS -VON1-VT01)=0 Solving the quadratic gives, vOUT(max) If VDD = 2.5V, and vOUT(max) = 3.661-2.5 = 0.8661V 4 - 2
N 1 2 1 1 2+4(V DD-VSS-VON1-VT01) 2+
VT01+
vSB = VT01+ 1 vOUT(max)-VSS

1
VDD-VSS-VON1-VT1 = VDD-VSS-VON1-VT01-
vOUT(max)-VSS
4(VDD-VSS-VON1-VT01) 4
= 0.4V1/2, VTN1= 0.7V, and VON1 = 0.2V, then vOUT(max) = 3.661V
P.E. Allen - 2006
Page 5.5-10.
Maximum Sourcing and Sinking Currents for the Source Follower VDD Maximum Sourcing Current (into a short circuit): VDD We assume that the transistors are in saturation and vIN M1 IQ VDD = -VSS = 2.5V , thus K1W1 IOUT(sourcing) = 2L1 [VDD
VSS
iOUT vOUT
vOUT VT1]2-IQ
M3 VSS
M2 VSS
RL
Fig. 040-01
where vIN is assumed to be equal to VDD. If W1/L1 =10 and if vOUT = 0V, then VT1 = 1.08V IOUT equal to 1.11 mA.
However, as vOUT increases above 0V, the current rapidly decreases. Maximum Sinking Current: For the current sink load, the sinking current is whatever the sink is biased to provide. IOUT(sinking) = IQ
P.E. Allen - 2006
Page 5.5-11.
Efficiency of the Source Follower Assume that the source follower input can swing to power supply. Plotting iD = 2 (vIN - vOUT - VT)2 vOUT and iD = IQ - RL Efficiency = vOUT(peak)2 2RL PRL = (VDD-VSS)IQ = PSupply
vIN VSS -2VT -VT
iD 3VT 4VT I R = VSS VDD Q L
0 VT 2VT
IQRL VSS VSS-VT -3VT -2VT -VT
IQ VT 2VT 3VT
vOUT VDD-VT VDD

Fig. 040-035
vOUT(peak)2 2RL vOUT(peak) 2 = VDD -VSS (VDD-VSS) (VDD -VSS) 2RL Maximum efficiency occurs when vOUT(peak) = VDD = |VSS| which gives 25%. Comments: Maximum efficiency occurs for the minimum value of RL which gives max. swing. Other values of RL result in less efficiency (and smaller signal swings before clipping) We have ignored the fact that the dynamic Q point cannot travel along the full length of the load line because of minimum and maximum voltage limits.
Page 5.5-12.
Small Signal Performance of the Source Follower v + gs1 Small-signal model:

+ vin + + vin C1 gm1vgs1 vgs1 rds1 gm1vout gmbs1vout rds2 RL C2 + vout gmbs1vbs1 rds1 rds2 RL C2 + vout -
C1 gm1vin
Fig. 040-04
gm1 gm1RL Vout gm1 = gds1 + gds2 + gm1 + gmbs1+GL gm1 + gmbs1+GL 1 +gm1RL Vin If VDD = -VSS = 2.5V, Vout = 0V, W1/L1 = 10m/1 m, W2/L2 = 1m/1 m, and ID = 500 A, then For the current sink load follower (RL = ): Vout Vout = 0.869V/V, if the bulk effect were ignored, then Vin = 0.963V/V Vin For a finite load, RL = 1000 : Vout Vin = 0.512V/V
Page 5.5-13.
Small Signal Performance of the Source Follower - Continued The output resistance is: 1 Rout = gm1 + gmbs1 + gds1 + gds2 For the current sink load follower: Rout = 830 The frequency response of the source follower: (gm1 + sC1) Vout(s) Vin(s) = gds1 + gds2 + gm1 + gmbs1 + GL + s(C1 + C2) where C1 = capacitances connected between the input and output CGS1 C2 = Cbs1 +Cbd2 +Cgd2(or Cgs2) + CL gm1 gm1+GL z = - C1 and p - C1+C2 The presence of a LHP zero leads to the possibility that in most cases the pole and zero will provide some degree of cancellation leading to a broadband response.
P.E. Allen - 2006
Page 5.5-14.
PUSH-PULL AMPLIFIERS Push-Pull Source Follower Can both sink and source current and provide a slightly lower output resistance.
vIN VBias VDD M1 VBias VSS iOUT vOUT VDD vIN VGG VSS VDD VDD
M6 M5 M1
VSS iOUT VDD vOUT RL
RL Efficiency: VDD M2 Depends on how the VSS transistors are biased. Class B - one transistor has current flow for only 180 of the sinusoid (half period)
M4 M2 M3
VSS VSS
Fig. 060-01
vOUT(peak)2 2RL PRL vOUT(peak) Efficiency = PVDD = = 2 VDD -VSS 1 2vOUT(peak) (VDD -VSS) 2 RL Maximum efficiency occurs when vOUT(peak) =VDD and is 78.5% Class AB - each transistor has current flow for more than 180 of the sinusoid. Maximum efficiency is between 25% and 78.5%
Page 5.5-15.
Illustration of Class B and Class AB Push-Pull, Source Follower Output current and voltage characteristics of the push-pull, source follower (RL = 1k ):
2V 1V 0V -1V iD2 -2V -2 0 2 1 Vin(V) Class B, push-pull, source follower -1 -1mA -2V -2 -1 vout vG2 vG1 1mA iD1 0mA 2V 1V 0V -1V iD2 0 2 1 Vin(V) Class AB, push-pull, source follower vout vG2 -1mA 0mA vG1 iD1 1mA
Fig. 060-02
Comments: Note that vOUT cannot reach the extreme values of VDD and VSS IOUT+(max) and IOUT-(max) is always less than VDD/RL or VSS/RL For vOUT = 0V, there is quiescent current flowing in M1 and M2 for Class AB Note that there is significant distortion at vIN =0V for the Class B push-pull follower
P.E. Allen - 2006
Page 5.5-16.
Small-Signal Performance of the Push-Pull Follower Model:

+ + vin + + vin vgs1 rds1 rds2 RL C2 + vout C1 gm1vgs1 vgs1 1 RL g gm1vout gmbs1vout rds1 gm2vin gm2vout m2 mbs2vout rds2 g C2 + vout Fig. 060-03
gmbs1vbs1
gm2vgs2 gmbs2vbs2
C1 gm1vin
gm1 + gm2 vout = gds1+gds2+gm1+gmbs1+gm2+gmbs2+GL vin 1 Rout = gds1+gds2+gm1+gmbs1+gm2+gmbs2 (does not include RL) If VDD = -VSS = 2.5V, Vout = 0V, ID1 = ID2 = 500A, and W/L = 20m/2m, Av = 0.787 (RL= ) and Rout = 448 . A zero and pole are located at -(gds1+gds2+gm1+gmbs1+gm2+gmbs2+GL) -(gm1+gm2) p= . z= C1 C1+C2 These roots will be high-frequency because the associated resistances are small.
Page 5.5-17.
Push-Pull, Common Source Amplifiers Similar to the class A but can operate as class B providing higher efficiency.
VDD M2 VTR2 vIN VTR1 M1CL VSS RL
Fig. 060-04
iOUT vOUT
Comments: The batteries VTR1 and VTR2 are necessary to control the bias current in M1 and M2. The efficiency is the same as the push-pull, source follower.
P.E. Allen - 2006
Page 5.5-18.
Practical Implementation of the Push-Pull, Common Source Amplifier Method 1

VDD M5 M1 M3 vIN M2 M4 M7 VSS VGG4 M8
Fig. 060-05
M6 VGG3
iOUT vOUT CL RL
VGG3 and VGG4 can be used to bias this amplifier in class AB or class B operation. Note, that the bias current in M6 and M8 is not dependent upon VDD or VSS (assuming VGG3 and VGG4 are not dependent on VDD and VSS).
P.E. Allen - 2006
Page 5.5-19.
Practical Implementation of the Push-Pull, Common Source Amplifier Method 2

VDD M5 M7 vin+ M8 vinM6 Ib I=2Ib VSS M10
Fig. 060-055
I=2Ib
Ib M1
M3 M4
M9 M2
In steady-state, the current through M5 and M6 is 2Ib. If W4/L4 = W9/L9 and W3/L3 = W8/L8, then the currents in M1 and M2 can be determined by the following relationship: W1/L1 W2/L2 I1 = I2 = Ib W7/L7 = Ib W10/L10 If vin+ goes low, M5 pulls the gates of M1 and M2 high. M4 shuts off causing all of the current flowing through M5 (2Ib) to flow through M3 shutting off M1. The gate of M2 is high allowing the buffer to strongly sink current. If vin- goes high, M6 pulls the gates of M1 and M2 low. As before, this shuts off M2 and turns on M1 allowing strong sourcing.
Page 5.5-20.
Additional Methods of Biasing the Push-Pull Common-Source Amplifier

VDD VDD -VT+VSat VDD -VT+2VSat vOUT VT+2VSat
050423-10
VDD IBias VB2 vIN VB1 vOUT
vIN
050423-08
P.E. Allen - 2006
Page 5.5-21.
Illustration of Class B and Class AB Push-Pull, Inverting Amplifier Output current and voltage characteristics of the push-pull, inverting amplifier (RL = 1k ):
2V 1V 0V -1V -2V -2V 0V 1V 2V vIN Class B, push-pull, inverting amplifier. -1V iD2 vOUT iD1 vG2 iD1 iD2 vG1 2mA 1mA 0mA -1mA -2mA 2V 1V 0V -1V -2V -2V -1V iD2 iD1 vG2 vG1 iD1 iD2 vOUT 2mA 1mA 0mA -1mA -2mA 0V 1V 2V vIN Class AB, push-pull, inverting amplifier. Fig.060-06
Comments: Note that there is significant distortion at vIN =0V for the Class B inverter Note that vOUT cannot reach the extreme values of VDD and VSS IOUT+(max) and IOUT-(max) is always less than VDD/RL or VSS/RL For vOUT = 0V, there is quiescent current flowing in M1 and M2 for Class AB
P.E. Allen - 2006
Page 5.5-22.
BIPOLAR JUNCTION TRANSISTOR OUTPUT AMPLIFIERS What about the use of BJTs?
VDD M3 iB M2 CL VSS p-well CMOS VSS M3 VDD Q1
vout
VDD M2 iB Q1 CL VSS n-well CMOS
vout
Fig. 5.5-8A Comments: Can use either substrate or lateral BJTs. Small-signal output resistance is 1/gm which can easily be less than 100 . Unfortunately, only PNP or NPN BJTs are available but not both on a standard CMOS technology. In order for the BJT to sink (or source) large currents, the base current, iB, must be large. Providing large currents as the voltage gets to extreme values is difficult for MOSFET circuits to accomplish. If one considers the MOSFET driver, the emitter can only pull to within vBE+VON of the power supply rails. This value can be 1V or more. We will consider the BJT as an output stage in more detail in Sec. 7.1.
Page 5.5-23.
USING NEGATIVE FEEDBACK TO REDUCE THE OUTPUT RESISTANCE Concept

VDD
Error Amplifier
vIN + + -
M2 iOUT vOUT CL M1 RL
Fig. 060-07
Error Amplifier
VSS
rds1||rds2 Rout = 1+Loop Gain Comments: Can achieve output resistances as low as 10 . If the error amplifiers are not balanced, it is difficult to control the quiescent current in M1 and M2 Great linearity because of the strong feedback Can be efficient if operated in class B or class AB
Page 5.5-24.
Simple Implementation of Neg., Shunt Feedback to Reduce the Output Resistance

VDD M2
R1
vIN
R2
iOUT vOUT CL M1 RL
Fig. 060-08
VSS
Loop gain Rout =
R1 gm1+gm2 R1+R2 gds1+gds2+GL
rds1||rds2 R1 gm1+gm2 1+ R1+R2 gds1+gds2+GL Let R1 = R2, RL = , IBias = 500A, W1/L1 = 100m/1m and W2/L2 = 200m/1m. Thus, gm1 = 3.316mS, gm2 = 3.162mS, rds1 = 50k and rds2 = 40k . Rout = 50k ||40k 22.22k 3316+3162 = 1+0.5(143.9) = 304 1+0.5 25+20
(Rout = 5.42k
if RL = 1k )
P.E. Allen - 2006
Page 5.5-25.
Summary of Output Amplifiers The objectives are to provide output power in form of voltage and/or current. In addition, the output amplifier should be linear and be efficient. Low output resistance is required to provide power efficiently to a small load resistance. High source/sink currents are required to provide sufficient output voltage rate due to large load capacitances. Types of output amplifiers considered: Class A amplifier Source follower Class B and AB amplifier Use of BJTs Negative shunt feedback
P.E. Allen - 2006
Page 5.6-1.
SECTION 5.7 - SUMMARY

Summary of Chapter Topics Inverting Amplifiers Class A (diode load and current sink/source load) Class AB of B (push-pull) Differential Amplifiers Need good common mode rejection An excellent input stage for integrated circuit amplifiers Cascode Amplifiers Useful for controlling the poles of an amplifier Current Amplifiers Good for low power supplies Output Amplifiers Minimize the output resistance Maximize the current sinking/sourcing capability
P.E. Allen - 2006
Chapter 5 Appendix 5A (7/5/06)
Page 5.7-1.
APPENDIX 5A FREQUENCY RESPONSE BASICS

Complex Frequency (s) Analysis of Circuits The frequency response of linear circuits can be analyzed using the complex frequency variable s which avoids having to solve the circuit in the time domain and then transform into the frequency domain. Passive components in the s domain are: 1 ZR(s) = R ZL(s) = sL and ZC(s) = sC s-domain analysis uses the complex impedance of elements as if they were resistors. C1 Example: s-domain A
+ V1 gmV1 R2 C2 + V2 1/sC1 conversion + V1(s) gmV1(s) R2 + 1 V2(s) sC2
060204-06
Sum currents flowing away from node A to get, sC1(V2 V1) + gmV1 + G2V2 + sC2V2 = 0 Solving for the voltage gain transfer function gives, sC1/gm - 1 -sC1 + gm V2(s) T(s) = V1(s) = s(C1+ C2) + G2 = -gmR2 s(C1+ C2)R2 + 1
Page 5.7-2.
Complex Frequency Plane The complex frequency variable, s, is really a complex number and can be expressed as s= +j where = Re[s] and = Im[s]. Complex frequency plane:
j Positive Imaginary Axis
Negative Real Axis
Positive Real Axis Negative Imaginary Axis
060204-07
It is useful to plot the roots of the transfer function on the complex frequency plane. For the previous T(s), the roots are: The numerator root (zero) is s = z1 = +(gm/C1) The denominator root (pole) is s = p1= -[1/R2(C1+ C2)]
Page 5.7-3.
Frequency Response Frequency response is the result when we replace the complex frequency variable s with j . (This amounts to evaluating T(s) on the imaginary axis of the complex frequency plane.) The frequency response is characterized by the magnitude and phase of T(j ). Example: a 0 + a 1s Assume T(s) = b0 + b1s a02 + ( a1)2 b02 + ( b1)2
s=j
a 0 + a 1j a0 + j a1 T(j ) = b0 + b1j = b0 + j b1 a1 b1 Arg[T(j )] = +tan-1 a0 - tan-1 b0
Since T(j ) is a complex number, we can express the magnitude and phase as, |T(j )| =
For the previous example, the magnitude and phase would be, |T(j )| = gmR2 1 + ( C1/gm)2 1 + [ R2(C1+C2)]2 Note: Because the zero is on the positive real axis, the phase due to the zero is -tan-1( ) rather than +tan-1( ). More about that later.
P.E. Allen - 2006
Arg[T(j )] = -tan-1( C1/gm) - tan-1[ R2(C1+C2)]

Page 5.7-4.
Graphical Illustration of Magnitude and Phase The important concepts of frequency response are communicated through the graphical portrayal of the magnitude and phase. Consider our example, V2(s) sC1/gm - 1 s/z1 - 1 T(s) = V1(s) = -gmR2 s(C1+ C2)R2 + 1 = -T(0) s/p1- 1 where T(0) = gmR2, z1 = +(gm/C1) and p1= -[1/R2(C1+ C2)]. Replacing s with j gives [remember tan-1(-x) = - tan-1(x)], 1 + ( /z1)2 Arg[T(j )] = -tan-1( /z1) - tan-1[ /p2] |T(j )| = T(0) 1 + ( /p )2 and 2 Graphically, we get the following if we assume |p1| = 0.1|z1|,
1.0 0
Phase Shift (Degrees)
Normalized Magnitude |T(j)|/T(0)
0.8 0.707 0.6 0.4 0.2
-20 -40 -60 -80 -100 -120 -140 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 Normalized Frequency (/|p1|)
P.E. Allen - 2006
0.707 frequency 0.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 060205-01 Normalized Frequency (/|p1|)
Page 5.7-5.
Graphical Illustration of Frequency Response Continued If the frequency range is large, it is more useful to use a logarithmic scale for the frequency. In addition, if one expresses the magnitude as 20 log10(|T(j )|, the plots can be closely approximated with straight lines which enables quick analysis by hand. Such plots are called Bode plots.
Normalized Magnitude 20log10[|T(j)|/T(0)] Phase Shift (Degrees)
0 dB -3 dB -5 dB -10 dB -15 dB -3dB frequency
Slope = -20dB/decade
0 -30 -60 -90 -120 -150 -180 0.01 0.1 1.0 10.0 100 1000 Log Normalized Frequency (/|p1|)
-20 dB 0.01
060205-02
0.1 1.0 10.0 100 1000 Log Normalized Frequency (/|p1|)
To construct a Bode asymptotic magnitude plot for a low pass transfer function in the form of products of roots: 1.) Start at a low frequency and plot 20 log10(|T(0)| until you reach the smallest root. 2.) At the frequency equal to magnitude of the smallest root, change to a line with a slope of +20dB/decade if the root is a zero or -20dB/decade if the root is a pole. 3.) Continue increasing in frequency until you have plotted the influence of all roots.
Page 5.7-6.
The Influence of the Complex Frequency Plane on Frequency Response The root locations in the complex frequency plane have a direct influence on the frequency response as illustrated below. Consider the transfer function: s/z1 - 1 s-z1 s-z1 |p1| T(s) = -T(0) s/p1- 1 = - z1 T(0) s-p1 = - 0.1T(0) s-p1 where z1 = 10|p1|
j j10 j8 j6 j4 j2 j0 z1=10 |T(j)|/T(0) 1.0 0.8 j10-p1 j8-p1 j6-p1 j4-p1 j2-p1 j0-p1 p1=-1 j10-z1 j8-z1 j6-z1 j4-z1 j2-z1 j0-z1 0.6 0.4 0.2 0.0 0 1 2 3 4 5 6 7 8 9 10
060205-04
Note: The roots maximally influence the magnitude when is such that the angle between the vector and the horizontal axis is 45. This occurs at j1 for p1 and j10 for z1.
Page 5.7-7.
Bandwidth of a Low-Pass Amplifier One of the most important aspects of frequency analysis is to find the frequency at which the amplitude decreases by -3dB or 1/ 2. This can easily be found from the magnitude the frequency response.
|A(j)|
+
A(0) 0.707A(0) Bandwidth 0 0 A=0.707

060205-03
V1(j)
V2(j)
Amplifier with a Dominant Root: Since the amplifier is low-pass, the poles will be smaller in magnitude than the zeros. If one of the poles is approximately 4-5 times smaller than the next smallest pole, the bandwidth of the amplifier is given as Bandwidth |Smallest pole| Amplifier with no Dominant Root: If there are several poles with roughly the same magnitude, then one should use the graphical method above to find the bandwidth.
Page 5.7-8.
Example of Finding the Bandwidth of an Amplifier Suppose an amplifier has a pole at -10 rads/sec and another at -20 rads/sec. and a zero at +50 radians/sec. Find the bandwidth of this amplifier if the low frequency gain is 100. Solution Since the poles are close together, construct a Bode plot and graphically find the bandwidth.
dB 40 34 30 -3dB 20 Bandwidth 10 6 0 1 2 10 20 3dB -6dB/octave -12dB/octave -6dB/octave 100 200 1000 Frequency (Rad/sec)
060205-05
From the graph, we see that the -3dB bandwidth is close to 11-12 Rad/sec.
P.E. Allen - 2006

Chap05 (7 5 06)

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Sub-blocks or subcircuits (A primitive, not independent)

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Chapter 5 Introduction (7/5/06)

Chapter 5 Introduction (7/5/06)

Chapter 5 Introduction (7/5/06)

Input Voltage Voltage Amplifier

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Chapter 5 Introduction (7/5/06)

Illustration of Voltage Amplifier Components

MOS Loads IBias IBias

+ VT+ 2VON - V+ T+VON MOS Transconductors BJT Transconductors

+ VBE + VCE(sat) + VBE Fig320-01

Chapter 5 Introduction (7/5/06)

Input Voltage Voltage Amplifier

Input Voltage Voltage Amplifier

Split Power Supplies

Single Power Supply

VDD Output Voltage Input Voltage Voltage Amplifier Output Voltage

Split Power Supplies

Single Power Supply

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Chapter 5 Introduction (7/5/06)

+ + Load Common Drain vout

CMOS Analog Circuit Design

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Chapter 5 Section 1 (7/5/06)

SECTION 5.1 INVERTING AMPLIFIERS

Chapter 5 Section 1 (7/5/06)

0.3 0.2 0.1

d ate tur ive a 1 s ct M 1a M E

Chapter 5 Section 1 (7/5/06)

CMOS Analog Circuit Design

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Chapter 5 Section 1 (7/5/06)

S2=B2 rds2 + vout + vin gm1vin Rout + vout Fig. 320-03

gm2vgs2 M2 vOUT G1 D1=D2=G2 + vin gm1vgs1 M1 S1=B1

Chapter 5 Section 1 (7/5/06)

CM + Vin gmVin + Vout -

sCM s gmRout 1 - z1 1- gm s 1+ sRout(CM + Cout) = 1 - p1 and gm1 z1 = CM Cout = Cbd1+Cbd2+Cgs2+CL

CMOS Analog Circuit Design

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Chapter 5 Section 1 (7/5/06)

CMOS Analog Circuit Design

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Chapter 5 Section 1 (7/5/06)

CMOS Analog Circuit Design

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Chapter 5 Section 1 (7/5/06)

0.3 0.2 0.1

ed rat atu tive 1s M 1 ac M

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Chapter 5 Section 1 (7/5/06)

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Chapter 5 Section 1 (7/5/06)

1 1 !!! and Rout = gds1 + gds2 ID( 1 +

CMOS Analog Circuit Design