NAME

H.T.No
YEAR/SEMESTER
DEPARTMENT OF ELECTRONICS &
COMMUNICATION ENGINEERING
1
2
3
S.NO DATE NAME OF THE EXPERIMENT
PAGE
NO REMARKS
INDEX

AIM:
To verify the operation of 741 Op-Amp as
a) Adder
b) Subtractor
c) Comparator
Apparatus :
IC 741 1 No
Resistors: 10k ,
1k
4 Nos
1 No
Potentio meter: 10k 1 No
RPS 2 No.
Functi on Generat or 1 No.
Connecting wires =====
Bread Board 1 No
CRO 1 No
CRO Probes 2 Nos
Digital Multi Meter 1 No.
4
EXP NO:1
OP AMP Applications Adder,
Subtractor, Comparator Circuits
DATE:
Circuit Diagrams:
Inverting Adder
Fig-(a): Inverting Adder
Non-Inverting Adder:
Fig.(b): Non-Inverting Adder:
5
THEORY:
a)ADDER : OP-AMP is used to design a circuit whose output is the
sum of several input signals. Such a circuit is called Summing
amplifier (summer) or adder.
b) SUBTRACTOR: we can also connect signals to both of the inputs at the same time
producing another common type of operational amplifier circuit called a Differential
Amplifier.
By connecting one voltage signal onto one input terminal and another voltage signal onto
the other input terminal the resultant output voltage will be proportional to the
"Difference" between the two input signals of V1 and V2 and this type of circuit can also
be used as a Subtractor.
C) COMPARATOR: In electronics, a comparator is a device which compares two
voltages or currents and switches its output to indicate which is larger.
.
A standard op-amp operating in open loop configuration (without negative feedback) can
be used as a comparator. When the non-inverting input (V+) is at a higher voltage than the
inverting input (V-), the high gain of the op-amp causes it to output the most positive
voltage it can. When the non-inverting input (V+) drops below the inverting input (V-),
the op-amp outputs the most negative voltage it can. Since the output voltage is limited by
the supply voltage, for an op-amp that uses a balanced, split supply, (powered by V
S
)
this action can be written:
V
out
= A
o
(V
1
V
2
)


6
SUBTRACTOR:
Fi g(c) subtractor
Comparator:
Fig.(d) comparator
7
Procedure:
ADDER:
(a) Connect the circuit diagram as shown in the figure (a) for
Inverting Adder and figure
(b) for non - inverting adder
1.
Set V
1
and V
2
for different values
2. Measure the output at pin no.6 and tabulate
3. Compare the practical values with the theoretical values.
b) SUBTRACTOR
1. Connect the circuit diagram as shown in the figure (c).
2. For the different values of V
1
and V
2
measure the out put
voltage V
0
at pin No.6 and tabulate the same.
3. Compare the practical values of V
0
with the theoretical values
by simply subtracting V
2
from V
1
ie.,(V
1-
V
2
).
(c)Comparator:
1. Connect the circuit diagram as shown in the fig (d) and adjust
the 10 k potentiometer so that V
r e f
=+0.5V.
2. Adjust the signal generator so that V
1
= Vpp sine wave at 1 kHz.
3. Using a CRO observe the input and output wave form
simultaneously. Plot the output wave form.
4. Adjust the 10k pot so that V
r e f
= -0.5V and repeat step3.
5. To make a zero crossing detector, set V
r ef
=0V and observe the
output wave forms.
8
Model Wave forms:
For positive reference voltage
For negative reference voltage
9

Tabular columns:
Inverting adder
S.No. V
1
in
volts
V
2
in
volts
Practical value
V
0
=-(V
1
+V
2
)volts
Theoretical value
V
0
=-(V
1
+V
2
)volts
1.
2.
3.
4.
Non-inverting adder
S.No. V
1
in
volts
V
2
in
volts
Practical value
V
0
=+(V
1
+V
2
)
Theoretical value
V
0
=+(V
1
+V
2
)
1.
2.
3.
10
4.
Subtractor
S.No. V
1
in
volts
V
2
in
volts
Practical value
V
0
=(V
1
-V
2
)volts
Theoretical value
V
0
=(V
1
-V
2
)volts
1.
2.
3.
4.
Zero crossing detector
Zero crossing detector
PINDIAGRAM OF IC 741
11
Precautions:
Avoi d t he loose connect ions.
Supply volt age should not exceed + 15V.
Discussions :
1. What is an op-amp?
2. Give the characteristics of an ideal op-amp:
3 How a non-i nvert ing ampli fi er can be convert ed i nt o volt age follower?
4. What i s inverting adder?
5 What i s t he di fference bet ween subt ract or and difference ampli fi er?
6. What i s t he di fference bet ween a basi c comparat or and t he Schmi t t
t ri gger?
Result:
12
13
Aim:
(a)To design a Low Pass Filter and High Pass Filter at a cut off
frequency of 1 KHz with a pass band gain of 2.
(b) To plot the frequency response of the filter in part (a).
Apparatus :
IC 741 1 No
Resistors:10k ,
20k Pot
2 Nos
1 No
Capacitors:0.01 F
1 No
Funct i on Generat or 1 No.
Connecting wires =====
Bread Board 1 No
CRO 1 No
CRO Probes 2 Nos
THEORY:
HPF: A frequency selective electric circuit that passes electric signals of specified band
14
EXP NO:2
FIRST ORDER LOW PASS AND HIGH
PASS FILTERS USING 741 OP-AMP
DATE:
Of frequencies and attenuates the signals of frequencies outside the brand is called an
electric filter. The first order high pass filter consists of a single RC network connected to
the non-inverting input terminal of the operational amplifier. ResistersR1 and RF
determine the gain of the filter in the pass band. The high pass filter has Maximum gain at
f = fl Hz. The frequency range from 0 to Fl is called the stop band the frequency range f >
fl is called the pass band.
LPF: A frequency selective electric circuit that passes electric signals of specified band of
frequencies and attenuates the signals of frequencies outside the brand is called an electric
filter. The first order low pass filter consists of a single RC network connected to the non-
inverting input terminal of the operational amplifier. Resisters Ri and R
F
determine the
gain of the filter in the pass band. The low pass filter as maximum gain at f = 0Hz. The
frequency range from 0 to FH is called the pass band the frequency range f > fh is called
the stop band.
Circuit Diagrams :
Fig (1): Low pass first order Butterworth filter:
Fig.(2): High pass first order Butterworth Filter
15
Design:
Low pass filter:
Let f
h
= 1 KHz A
v
= 2
Choose C = 0.01 F
Since f
h
=
C R 2
1
C f
R
h
2
1

R
( )
( ) KPOT K 20 9 . 15
01 . 0 10 2
1
3

Pass band gain, A

v
=
f i
L
F
R R
R
R
+ 2 1
Let R
i
= R
f
= 10 K .
R = 15.9 K , C = 0.01 F, R
i
= R
f
= 10 K .
High Pass Filter:
Let f
L
= 1 KHz A
v
= 2
16
( )
KHz R R Let
R R
R
R
R
R
A
K R
F L F C Choose
C
R
C R
f
f i
f i
i
f
i
f
v
L
10
2 1
9 . 15
10 01 . 0 10 2
1
1 01 . 0
10 2
1
2
1
6 3
3

+

Model Graph :
Tabular Columns : Low Pass Filter Vi=____V
S.NO.
Frequency
f in Hz
Output
Voltage V
0
in Volts
VOLTAGE G ain
A
V
=| V
0
/V
i
|
Gain in dB
20 log|V
0
/V
i
|
1
100
2
200
3
300
17
4
400
5
500
6
600
7
700
8
800
9
900
10
1k
11
1.5k
12
2k
13
2.5k
14
3k
15
4k
Procedure:
Low Pass Filter
Connect the circuit as shown in figure (1) for Low Pass Filter
and figure (2) for High Pass Filter, with the values of the
components obtained from the design.
Given an input signal V
i
of 1V peak to peak and measure the
output voltage for different input frequencies.
Plot the frequency response 20 log V
0
/V
i
versus input signal
frequency and find the 3 dB frequency from here.
Calculate the theoretical value of upper cutoff frequency f
n
and
the pass band gain A
0
.
18
f
h
=
C R 2
1
. A
0
(dB) = 20 log (1+
i
t
R
R
).
High Pass Filter:
Interchange the resistor R with the capacitor C to make the high
pass filter and repeat step 2 and 3.
Calculate the theoretical value of the lower cutoff frequency f
L
and pass band gain A
0
using that formula.
C R
f
L
2
1
,
( )

,
_

+
L
f
R
R
A
dB
1 log 20
0
High Pass Filter: V
i
=
S.NO.
Frequency
f in Hz
Output Voltage V
0
in Volts
Gain | V
0
/V
i
|
Gain in dB
20 log| V
0
/V
i
|
1
100
2
200
3
300
4 400
5
500
6
600
7
700
8
800
9
900
10
1k
11
1.5k
12
2k
19
13
2.5k
14
3k
15
4k
Precautions:
1. The supply voltage should not exceed t 15 V.
2. Always give +Ve and Ve supply voltage to 7th pin and 4th
pins respectively.
Discussions:
1. What i s an act i ve filt er?
2. Why are act i ve fi lt ers preferred?
3. Li st t he commonly used fi lt ers.
4. What i s t he standard form of t he t ransfer functi on of a fi rst order
low-pass syst em?
5. What i s roll- off rat e of a fi rst order fi lt er?
Result:
20
21
22
Aim:
To construct a triangular wave generator using 741 Operational
Amplifier.
To observe the output waveform and measure their frequency.
Apparatus :
IC 741 2 Nos.
Resistors: 47K,100k, ,22k
10k
Each 1 No.
2 Nos
Capacitors: 0. 047 F,
0.05 F
1 Nos.
1 Nos
RPS 1 No.
DRB /20KPOT 1 No
CRO 1 No
CRO Probes 2 Nos
Connecting wires =====
CIRCUIT DIAGRAM:
23
EX NO:3
FUNCTION GENERATOR
DATE:
Astable multivibrator Integrator
Fig: FUNCTION GENERATOR
24
Theory:
A function generator is a piece of electronic test equipment or
software used to generate electrical waveforms. These waveforms can be
either repetitive, or single-shot in which case some kind of triggering source
is required (internal or external).
Function generator is astable multivibrator followed by an integrator. The
output of the astable multivibrator is Square wave
Triangular wave can be simply obtained by integrating a square wave as
shown in the fig. It is obvious that the frequency of the square wave and
triangular wave is same as shown in the waveform. Although the amplitude
of the square wave is constant at Vsat, the amplitude of the triangular wave
will decrease as the frequency increases. This is because the reactance of
the capacitor in the feedback circuit decreases at high frequencies. The
resistance is connected across the capacitor to avoid the saturation problem
at low frequencies as in the case of practical integrator.
Procedure :
Connect the circuit as per the circuit diagram.
Note that the output of first operational amplifier is a square
wave.
Output of Operational Amplifier1 is given to the inverting
input terminal of operational amplifier.
Observe the output, which is a triangular wave.
Note down the waveforms for different values of R2.
25
TabularColumn:

26
S.No
.
R
2
Theoretical
Time period
t ( ms)
Practical
Time period
t ( ms)
Square wave
output
Vo(volts)
Triangular
wave output
Vo(volts)
1. 10k
2. 22k
3. 47k
Precautions :
Inverting terminal of Operational Amplifier 1 must be
grounded through a capacitor.
For proper operating a voltage compensating network is
connected at non inverting terminal.
Time constant of integrator should be proper.
Calculations :
T= 2 RC ln(1+2(R1/R2))
For R
2
=10K
R=10K, R
1
= 10K, R
2
= 10K, C=0.05F
T=2x 10
4
x 0.05x 10
- 6
ln [1+ ]
T=1.09msec (1msec)
For R
2
=22K
T=
For R
2
=47K
T=
27
Outputwaveform
For R=10k
For R=22k
For R=47k
28
Discussions:
1. What happens if the capacitor at the non-inverting
terminal is removed and what happens if the
capacitor is replaced by a resistor?
2. What changes will occur in amplitude of a
triangular wave as frequency increases?
3. What happens to frequency of oscillation as R
2
increases?
4. What does the factor indicates?
Result:
Conclusion :
29
PINDIAGRAM OF IC 555
30
Aim:
To design an Astable and monostable Multivibrator using IC
555 and observe the output waveforms.
Apparatus:
IC 555 1 No
Resistors:2.2k ,3.9k ,10k Each 1 No
Capacitors:0.1 F,
0.01 F,1F
Each 1 No.
RPS 1 No.
Millimeter 1 No.
Connecting wires =====
DRB 1 No
Bread Board 1 No
CRO 1 No
CRO Probes 2 Nos
31
EX NO:
IC 555 AS AN ASTABLE AND
MONOSTABLE MULTIVIBRATOR
DATE:
Circuit Diagram:
Fig (1) Astable Multivibrator:
Circuit Diagram :
Fig (2) Monostable Multivibrator
THEORY:
The 555 t imer can be used wi t h supply volt age in t he range of +5v t o
+18v and can dri ve up t o 200mAmp. It i s compatible wi th bot h TTL and
CMOS logi c ci rcui t s because of the wi de range of supply volt age t he 555
t i mer i s versat i le and easy t o use i n t he astable multi vi brat or. The t i mer
i s osci llat ed between two threshold level s 1/ 3Vcc and 2/ 3Vcc in order t o
32
generat e a square wave form. No ext ernal si gnal source i s requi red for
such generat i on and hence t hi s i s called as a free runni ng mult i vibrat or
The 555 t imer can be used wi t h supply volt age i n t he range of +5 v
t o+18v and can dri ve up t o 200mAmps. It i s compat ible wit h bot h TTL
and CMOS logi c ci rcui t s because of t he wide range of supply volt age t he
555 t i mer is versat i le and easy t o use i n monost able mult i vi brat or we wi ll
provi de ext ernal t ri ggeri ng i n order t o make the t i mer t o swi t ch over t o
high stat e (unst able). Thi s i s also called as one-shortmult i vi brat or.
Procedure :
Astable Multivibrator
Connect the circuit as per the circuit diagram(1)
Observe the output at the 3rd pin.
Note down the time period and verify the theoretical charging
and discharging periods.
Monostable Multivibrator:
Connect the circuit as per the circuit diagram(2)
Apply the trigger at Pin No 2
Observe the output the 3
r d
pin.
Note down the time period and verify the theoretical values
33
Model Waveforms:
Monostable multivibrator:
Astable multivibrator:
34
Design procedure : (for Monostable Multivibrator)
Pulse width T=1.1 RC;
Let C=1F & T=1msec
1 msec= 1.1 (R) (1 F)=>R=10K
For Astable Multivibrator:
Let f=1.45KHz,C=0.1F
t
c
=0. 0693(R
1
+R
2
)C for charging
t
d
=0.693(R
2
)C for discharging
The total period of output waveform,T = t
c
+ t
d
= 0.693(R
1
+2R
2
)C
Frequency of oscillation f = 1/T =1.45/[(R
1
+2R
2
)C]
1.45=1.45/[(R
1
+2R
2
)C]
(R
1
+2R
2
)=1/[0.01x10
- 6
]
(R
1
+2R
2
) = 10K .. (1)
Let Duty cycle,D =40%
D=R
2
/[R
1
+2R
2
]
0.4= R
2
/[R
1
+2R
2
]
35
From eqn (1),
0.4= R
2
/10K
R
2
=4K
R
1
=2K
Precautions:
Reset pin 4 is connected to V
c c
when it is not used.
Pin 5 is grounded through a capacitor in order to reduce the
noise.
Reset pin is connected to V
CC
when it is not used.
Pin5 is grounded through a capacitor in order to reduce the
noise.
Trigger input is not necessary.
R
1
should not be zero, if R
1
= 0 V
CC
is directly connected to pin
7 and IC may get damage.
36
Discussions:
1. Explain the function of reset
2. What are the modes of operation of timer?
3. What is the expression of time delay of a monostable multivibrator?
4. Discuss some applications of timer in monostable mode.
5. Define duty cycle
6. How is a monostable multivibrator connected into a pulse position modulator?
7. What is the expression of time delay of a astable multivibrator?
Result :
37
38
Aim :
To find the line regulation and load regulations of a given
IC A 723.
Apparatus:
IC A 723
1 N0
Resistors:47 ,680 ,8.2K,
1K ,1KPOT
Each 1 No
Capacitors: 100 pF 2 Nos
RPS 1 No.
Multimeter 1 Nos
Connecting wires =====
DRB 1 No
Bread Board 1 No
Theory:
The limitations of 3 terminal regulators have been overcome
in the 723 general purpose regulators, which can be adjusted
over a wide range of both positive and negative regulated
voltage. This IC is inherently low current device, but can be
boosted to provide 5Amps or more current by connecting
external components. The limitation of 723 is that it has no
inbuilt thermal protection. It also has no short circuit
current limits.
39
EX NO:5
723 AS A VOLTAGE REGULATOR
DATE:
Circuit Diagram: Model Wave Form for Line
regulation:
Regulation:

Fig (1): Line Regulation
Tabular Columns:
Line Regulation:
40
S.No. V
i n
(volts) V
o
( Volts)
1.
2.
3.
4.
5.
5.
7.
8.
9.
10.
Procedure :
For line regulation ;
Connect the circuit as per the circuit diagram.(fig1)
Verify the input voltage and note the corresponding
values of the output voltage.
Plot the graph between the input and output voltage.
For load regulation ;
Connect the circuit diagram as shown in figure2
Increase the value of the potentiometer gradually from
minimum value to a maximum value.
Note down the corresponding values of the load current
and the output voltage.
At some point, we find that the load voltage is being
maintained constant.
Plot a graph between the load current and load voltage.
41
Fig(2) Load Regulation: Model Wave Form for Load
Regulation:
Load Regulation:
S.NO. R
L
I
L
(mA) V
0
(Volts )
1.
2.
3.
4.
5.
6.
7.
8.
9.
42
10.
Precautions:
The 13
t h
pin must be connected to the 4
t h
pin
through a discharging capacitor so as to improve
efficiency.
Discussions:
1 What output volt age range we can obt ain from 723 regulat or?
2. What are t he appli cat i ons of 723 regulat ors?
3. Defi ne li ne regulat i on
4. Defi ne load regulat ion
5 . Defi ne ripple rej ection
Result:
43
44
Aim :
To convert a digital signal to its equivalent analog signal
using 741 operational amplifier.
To verify practical output voltage with theoretical values
for a given binary inputs.
Apparatus:
IC 741 1 No.
Resistors:1K ,5K,10 K
20K ,40K
each 1 No.
RPS 1 No.
Multimeter 1 Nos
Connecting wires =====
THEORY:
Most of t he real world physi cal quant it i es such as volt age current
t emperat ure pressure are avai lable in analog form. It i s very di ffi cult t o
process t he si gnal in analog form; hence ADC and DAC are used. The
DAC i s t o convert di gital si gnal int o analog and hence t he funct i oning of
DAC i s exact ly opposit e t o that of ADC. The DAC i s usually operat ed at
45
EX NO:6
D/A CONVERTER
DATE:
t he same frequency as the ADC. The out put of t he DAC i s commonly
st ai rcase. Thi s stai rcase li ke di gi t al out put i s passed through a smoothi ng
fi l t er t o reduce t he effect of quanti zat i on noi se. There are three t ypes of
DAC t echni ques (i ) Wei ght ed resi st or DAC (ii ) R-2R ladder. (i i i )
Invert ed R-2R ladder. Wi de range of resi stors i s requi red in bi nary
wei ghted resi stor type DAC. Thi s can be avoi ded by usi ng R-2R ladder
t ype DAC where only two values of resist ors are requi red i t i s well sui t ed
for int egrated ci rcui t reali zati on.
Circuit Diagram :
Model Graphs:
46
Procedure:
Connect the circuit as per the circuit diagram.
Give eight different combinations of inputs and note
down the corresponding outputs.
Compare the obtained practical values with the
theoretical values.
Plot the graph.
47
Tabular Columns :
Deci mal
Equi val ent
Bi nary
I nput s
Inputs Outputs
V
1
=
100

th
th P
V
V V
b
3
b
2
b
1
b
0
Theoretica (
V)
Practical (V
P
)
1.
2.
3.
4.
5.
6.
7.
48
Observations :
Output voltage V0

theoretically is
R f
V
R
b
R
b
R
b
R
b
R V
1
]
1

+ + +
8 4 2
0 1 2 3
0
For example;
For b
3
= 1, b
2
= 1, b
1
= 1, b
0
=0
Theoretical output voltage V
0
= 0.75 V
Practical output voltage V
0
=___V.
Precautions :
Take care in selecting the polarity of the reference
voltage, which is chosen in accordance with the type of
switch is used.
The choice of smallest value is reasonable, otherwise
loading effect will occur.
Discussions : .
1. Name t he essent ial part s of a DAC.
2. How many resi st ors are requi red i n 12 bi t wei ghted resi st or DAC?
3. Why i s an invert ed R-2R ladder net work DAC is bet t er t han R-2R
ladder DAC.
4. Defi ne
i ) resolut i on i i ) li neari ty i i i ) monot oni ci ty i v) set t li ng t ime.
5. Define st ep size.
Result :
Theoretical values V
0
= V.
Practical Values V
0
= V.
49
50
51
VHDL LAB PROGRAMS
52
53
54
PINDIAGRAM OF IC74X74:


55
AIM: To simulate D flip-flop ic74x74 using VHDL
APPARATUS: 1.XILINX PROJECT NAVIGATOR.
2. MODELSIM SIMULATOR.
PROGRAM:
VHDL CODE FOR D FLIPFLOP IC74X74
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dfff is
Port ( d: in STD_LOGIC_VECTOR(0 to 1);
clk : in STD_LOGIC_VECTOR(0 to 1);
pr : in STD_LOGIC_VECTOR(0 to 1);
clr : in STD_LOGIC_VECTOR(0 to 1);
q : out STD_LOGIC_VECTOR(0 to 1);
nq :out STD_LOGIC_VECTOR(0 to 1));
end DFFF;
architecture structural of DFFF is
component dff1
port(d1,clk1,pr1,clr1:in std_logic;
q1,nq1:inout std_logic);
end component;
begin
56
EX NO:
IC7474A POSITIVE EDGE TRIGGERING D
FLIP FLOP
DATE:
D1:dff1 port map(d(0),clk(0),pr(0),clr(0),q(0),nq(0));
D2:dff1 port map(d(1),clk(1),pr(1),clr(1),q(1),nq(1));
end structural;
CIRCUIT DIAGRAM:
57
PR-L
CLR-L
CLK
D
Q
QN
LOGIC DIARAM OF D FLIP FLOP
0
1
1
1
0
QN
1
0
1
0
1
Q
x
x
x
0
1
x
1
0
0
1
1
1
0
1
0
1
1
1
x
x
x
1
1
QN Q D CLR_L PR_L CLK
TRUTH TABLE :
VHDL CODE FOR COMPONENT D FLIPFLOP
entity dff1 is
Port ( d1: in STD_LOGIC;
Clk1 : in STD_LOGIC;
Pr1 : in STD_LOGIC;
Clr1 : in STD_LOGIC;
Q1 : inout STD_LOGIC;
Nq1 :inout STD_LOGIC);
end dff1;
architecture Behavioral of dff1 is
begin
process(d1,pr1,clr1,clk1)
begin
if(pr1='0' and clr1='0')then
q1<='1';nq1<='1';
elsif(pr1='0' and clr1='1')then
q1<='1';nq1<='0';
58
elsif(pr1='1' and clr1='0')then
q1<='0';nq1<='1';
elsif(clk1='1' and clk1'event)then
q1<=d1;nq1<=not d1;
end if;

end process;

end Behavioral;
59
OUT PUT WAVEFORMS:
60
VIVA QUESTIONS:
1. Write the behavioral code for the IC 74x74.
2. Write the dataflow code for the IC 74x74.
3. What is a flip-flop?
4. Explain the functions of preset and clear inputs in flip-flop?
5. What is the difference between flip-flop and latch?
6. What are the various methods used for triggering flip-flops?
Result:
61
LOGIC DIAGRAM OF DECADE COUNTER
62
J
K
Q
Q J
K
Q
Q
J
K
Q
Q
J
K Q
Q
CLK_L
Q(0) Q(1) Q(2) Q(3)
CLR_L
CLR_L CLR_L CLR_L
PR_L
PR_L PR_L PR_L
1
1 1
1
1
1
1
1
MR1 MR2
MS1 MS2
AIM:
To write the VHDL code for IC 74x90 decade counter.
APPARATUS: 1. XILINX PROJECT NAVIGATOR.
2. MODELSIM SIMULATOR.
PROGRAM:
V HDL CODE FOR DECADE COUNTER-IC 7490
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decadecount is
Port ( mr1 : in STD_LOGIC;
mr2 : in STD_LOGIC;
ms1 : in STD_LOGIC;
ms2 : in STD_LOGIC;
clk : in STD_LOGIC;
q : inout STD_LOGIC_vector(3 downto 0));
end decadecount;
architecture Behavioral of decadecount is
component jkff is
port(j,k,clk,pr,clr:in std_logic;
q,nq:inout std_logic);
end component;
signal s1,s2,s3,s4,s5,nq:std_logic;
begin
ff1:jkff port map('1','1',clk,s1,s2,q(0),open);
63
EX NO:
IC 74x90 DECADE COUNTER
DATE:
0
0
1
0
0
0
0
0
0
Count
0
0
1
X
L
H
X
L
L
X
L
X
H
L
X
X
L
H
H
L
X
L
X
L
H
H
L
L
X
L
X
Q(3) Q(2) Q(1) Q(0) MS2 MS1 MR2 MR1
TRUTH TABLE:
64
ff2:jkff port map(nq,'1',q(0),'1',s3,q(1),open);
ff3:jkff port map('1','1',q(1),'1',s4,q(2),open);
ff4:jkff port map(s5,'1',q(0),s1,s2,q(3),nq);
s1<=ms1 nand ms2;
s2<=mr1 nand mr2;
s3<=s1 and s2;
s4<=s1 and s2;
s5<=q(1) and q(2);
end Behavioral;
VHDL CODE FOR JK FLIP-FLOP
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jkff is
Port ( j : in STD_LOGIC;
k : in STD_LOGIC;
clk : in STD_LOGIC;
pr:in STD_LOGIC;
clr : in STD_LOGIC;
q : inout STD_LOGIC;
nq : inout STD_LOGIC);
end jkff;
architecture Behavioral of jkff is
begin
process(j,k,clk,pr,clr)
begin

65
OUTPUT WAVE FORM:
66
if(pr='0' and clr='0')then
q<='1';
nq<='1';
elsif(pr='0' and clr='1')then
q<='1';
nq<='0';
elsif(pr='1' and clr='0')then
q<='0';
nq<='1';
elsif(clk='0' and clk'event)then
if(j='0' and k='0')then
q<=q;
nq<=nq;
elsif(j='0' and k='1')then
q<='0';
nq<='1';
elsif(j='1' and k='0')then
q<='1';
nq<='0';
else
q<=nq;
nq<=q;
end if;
elsif(clk='1' and clk'event)then
q<=q;
nq<=nq;
end if;
end process;
end Behavioral;
67
68
VIVA QUESTIONS:
1.Write the behavioral code for IC 74x90.
1.What is a sequential circuit?
2.Differentiate between synchronous and asynchronous counter?
3.How many no. of flip-flops are required for decade counter?
4.What is meant by excitation table?
5.What are the meanings of different types of values in std_ulogic?
6.What are the objects in VHDL?
7.Write the syntax for a signal?
8.Write the difference between signal and variable?
Result:
69
CIRCUIT DIAGRAM:
70
PI N D I AGR AM OF U N IVER SAL SH I FT REG IST ER
IC 7 4LS 19 4
CL R
R IN
A
B
C
D
L IN
G N D
VC C
Q A
Q B
Q C
Q D
CL K
S1
S0
1
2
3
4
5
6
7
8
9
1 0
11
12
13
14
15
16
AIM : To write the structural program for IC 74x95 SHIFT REGISTER.
APPARATUS: 1.XILINX PROJECT NAVIGATOR.
2. MODELSIM SIMULATOR.
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bitregister4 is
Port ( s : in STD_LOGIC;
cp1 : in STD_LOGIC;
cp2 : in STD_LOGIC;
ds : in STD_LOGIC;
d : in STD_LOGIC_vector(0 to 3);
q : input STD_LOGIC_vector(0 to 3));
end bitregister4;
architecture Behavioral of bitregister4 is
begin
process(s,cp1,cp2,ds,d)
begin
if(s='1') then
if(cp2='0' and cp2'event) then
q<=d;
end if;
71
EX NO: IC 74x95 SHIFT REGISTER DATE:
Truth Table:
72
else
if(cp1='0' and cp1'event) then
q<=ds & q(0 to 2);
end if;
end if;
end process;
end Behavioral;
Discussions:
1. Write the behavioral code for IC 74x95.
2. What is a shift register?
3. Write some applications of shift register?
4. Write the syntax for function?
5. Write the syntax for procedure?
6. How to define variable in VHDL?
7. Write the difference between with-select and when-else statement?
Result:
73
PIN DIAGRAM:
CIRCUITDIAGRAM:
74
IC74X138
G1
G2A
G2B
A
B
C
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
G1
G2A_L
G2B_L
A
B
C
Y0_L
Y1_L
Y2_L
Y3_L
Y4_L
Y5_L
Y6_L
Y7_L
G1
G2A_L
G2B_L
A
B
C
Y0_L
Y1_L
Y2_L
Y3_L
Y4_L
Y5_L
Y6_L
Y7_L
AIM: Write a VHDL code for IC74138-3X8 Decoder
APPARATUS: 1.XILINX PROJECT NAVIGATOR.
2. MODELSIM SIMULATOR.
PROGRAM:
VHDL CODE FOR 3 t0 8 DECODER-BEHAVIORAL MODEL IC-
74138
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dec3to8_beh isPort ( g1 : in STD_LOGIC;
g2a_l : in STD_LOGIC;
g2b_l : in STD_LOGIC;
a : in STD_LOGIC_vector(2 downto 0);
y_l : out STD_LOGIC_vector(0 to 7));
end dec3to8_beh;
architecture Behavioral of dec3to8_beh is
TRUTH TABLE:
75
EX NO:
IC 74X138-3x8 DECODER
DATE:
OUTPUT WAVEFORM:
begin
process (g1,g2a_l,g2b_l,a)
76
G1 G2A_L G2B_L C B A Y7_L Y6_L Y5_L Y4_L Y3_L Y2_L Y1_L Y0_L
0 X X X X X 1 1 1 1 1 1 1 1
X 1 X X X X 1 1 1 1 1 1 1 1
X X 1 X X X 1 1 1 1 1 1 1 1
1 0 0 0 0 0 1 1 1 1 1 1 1 0
1 0 0 0 0 1 1 1 1 1 1 1 0 1
1 0 0 0 1 0 1 1 1 1 1 0 1 1
1 0 0 0 1 1 1 1 1 1 0 1 1 1
1 0 0 1 0 0 1 1 1 0 1 1 1 1
1 0 0 1 0 1 1 1 0 1 1 1 1 1
1 0 0 1 1 0 1 0 1 1 1 1 1 1
1 0 0 1 1 1 0 1 1 1 1 1 1 1
begin
if (g1='0' and g2a_l='0' and g2b_l='0')then
y_l<= "11111111";
elsif(g1 ='1' and g2a_l='0' and g2b_l='0') then
if(a="000")then
y_l<="11111110";
elsif(a="001") then
y_l<="11111101";
elsif(a="010")then
y_l<="11111011";
elsif(a="011")then
y_l<="11110111";
elsif(a="100")then
y_l<="11101111";
elsif(a="101")then
y_l<="11011111";
elsif(a="110")then
y_l<="10111111";
elsif(a="111") then
y_l<="01111111;
end if;
end if;
end process;
end Behavioral;
77
78
IC
7
4
x
8
5
DISCUSSIONS:
1. Write the behavioral code for the IC 74x138.
2. Write the VHDL code for the IC 74x138 using CASE statement.
3. What does priority encoder mean?
4. How many decoders are needed to construct 4X16 decoder?
5. What is the difference between decoder and encoder?
Result:
79
IC
7
4
x
8
5
PIN DIAGRAM OF IC74X85:
80
IC
7
4
x
8
5
ALTBIN
AEQBIN
AGTBIN
ALTBOUT
AEQBOUT
AGTBOUT
VCC
A0
B0
A1
B1
A2
B2
A3
B3
GND
AIM: Write a VHDL code for IC 74x85 4-bit comparator.
APPARATUS: 1 .XILINX PROJECT NAVIGATOR.
2. MODELSIM SIMULATOR.
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity comparator is
Port(A,B:in STD_LOGIC;
ALTBIN ,AEQBIN,AGTBIN:INOUT STD_LOGIC;
AGTBOUT,AEQBOUT,ALTBOUT:INOUT STD_LOGIC);
End comparator;
Architecture comparator_b of comparator is
Begin
ALTBIN<=0;AEQBIN<=1;AGTBIN<=0;
Process(A,B)
81
EXP NO:
74x85 8-BIT COMPARATOR
DATE:
LOGIC DIAGRAM:


82
Begin
If(A>B)then
ALTBOUT<=0;
AEQBOUT<=0;
AGTBOUT<=1;
End if;
If(A<B) then
ALTBOUT<=1;
AEQBOUT<=0;
AGTBOUT<=0;
End if;
If(A=B) then
ALTBOUT<=0;
AEQBOUT<=1;
AGTBOUT<=0;
End if;

End process;
End comparator b;
DISCUSSIONS:
1. Write the dataflow model for the IC 74x85.
.
2. Write the VHDL code for the IC 74x85 using WITH statement.
3. Write the VHDL code for the IC 74x85 using WHEN--ELSE statement.
4. Write the structural program for IC 74x85.
5. Design a 2-bit comparator using gates?
Result:

83
LOGIC DIAGRAM OF 8X1 MUX:

A
C
EN_L
D0
D1
D2
D3
D4
D5
D6
D7
B
84
PIN DIAGRAM OF IC 74X151
IC74X151
EN
A
B
C
D0
D1
D2
D3
D4
D5
D6
D7
EN_L
A
B
C
D0
D1
D2
D3
D4
D5
D6
D7
Y_L
Y
Y
Y
TRUTH TABLE
1
D0
D1
D2
D3
D4
D5
D6
D7
0
D0
D1
D2
D3
D4
D5
D6
D7
X
0
1
0
1
0
1
0
1
X
0
0
1
1
0
0
1
1
X
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
Y-L Y S0 S1 S2 EN_L
OUTPUTS INPUTS
AIM: Write a VHDL code for IC741518x1 multiplexer
APPARATUS:1.XILINX PROJECT NAVIGATOR.
2.MODELSIM SIMULATOR.
PROGRAM:
library IEEE;
85
EXp NO:
IC74X151-8x1 MULTIPLEXER
DATE:
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux8_1 is
Port ( en : in STD_LOGIC;
d : in STD_LOGIC_vector(0 to 7);
s : in STD_LOGIC_vector(0 to 2);
y,y_l : out STD_LOGIC);
end mux8_1;
architecture Behavioral of mux8_1 is
begin
process(en,d,s)
begin
if(en='1') then
y<='0';
y_l<='1';
else
case s is
when "000"=>y<=d(0);y_l<=not d(0);
when "001"=>y<=d(1); y_l<=not d(1);
when "010"=>y<=d(2); y_l<=not d(2);
86
when "011"=>y<=d(3); y_l<=not d(3);
when "100"=>y<=d(4); y_l<=not d(4);
when "101"=>y<=d(5); y_l<=not d(5);
when "110"=>y<=d(6); y_l<=not d(6);
when others=>y<=d(7); y_l<=not d(7);
end case;
end if;
end process;
end Behavioral;
VHDL CODE FOR 8 X 1 MULTIPLEXER-IC 74X151
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
87
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux8_1 is
Port ( en : in STD_LOGIC;
d : in STD_LOGIC_vector(0 to 7);
s : in STD_LOGIC_vector(0 to 2);
y,y_l : out STD_LOGIC);
end mux8_1;
architecture Behavioral of mux8_1 is
begin
process(en,d,s)
begin
if(en='1') then
y<='0';
y_l<=1;
else
case s is
OUTPUT WAVEFORM:
88
when "000"=>y<=d(0);y_l<=not d(0);
when "001"=>y<=d(1); y_l<=not d(1);
89
when "010"=>y<=d(2); y_l<=not d(2);
when "011"=>y<=d(3); y_l<=not d(3);
when "100"=>y<=d(4); y_l<=not d(4);
when "101"=>y<=d(5); y_l<=not d(5);
when "110"=>y<=d(6); y_l<=not d(6);
when others=>y<=d(7); y_l<=not d(7);
end case;
end if;
end process;
end behavioral;
VIVA QUESTIONS
1. Write the behavioral code for the IC 74x151.
2. What is meant by multiplexer?
3. What does demultiplexer mean?
4. How many 8X1 multiplexers are needed to construct 16X1 multiplexer?
5. Compare decoder with demultiplexer?
Result:
90