TQP3M9007

W High Linearity LNA Gain Block Applications

Repeaters Mobile Infrastructure LTE / WCDMA / CDMA / EDGE General Purpose Wireless

SOT-89 Package

Product Features
100-4000 MHz 13 dB Gain @ 1.9 GHz 1.3 dB Noise Figure @ 1.9 GHz +41 dBm Output IP3 +23.6 dBm P1dB 50 Ohm Cascadable Gain Block Unconditionally Stable High Input Power Capability +5V Single Supply, 125 mA Current SOT-89 Package

Functional Block Diagram

GND 4

1 RF IN

2 GND

3 RF OUT

General Description
The TQP3M9007 is a high linearity low noise gain block amplifier in a low-cost surface-mount package. At 1.9 GHz, the amplifier typically provides 13 dB gain, +41 dBm OIP3, and 1.3 dB Noise Figure while drawing 125 mA current. The device is housed in a leadfree/green/RoHS-compliant industry-standard SOT89 package. The TQP3M9007 has the benefit of having high linearity while also providing very low noise across a broad range of frequencies. This allows the device to be used in both receive and transmit chains for high performance systems. The amplifier is internally matched using a high performance E-pHEMT process and only requires an external RF choke and blocking/bypass capacitors for operation from a single +5V supply. The internal active bias circuit also enables stable operation over bias and temperature variations. The TQP3M9007 covers the 0.1 - 4 GHz frequency band and is targeted for wireless infrastructure or other applications requiring high linearity and/or low noise figure.

Pin Configuration
Pin #
1 3 2, 4

Symbol
RF IN RF OUT GND

Ordering Information
Part No.
TQP3M9007 TQP3M9007-PCB

Description
High Linearity LNA Gain Block 0.5-4 GHz Evaluation Board

Standard T/R size =1000 pieces on a 7 reel. Data Sheet: Rev D 12/27/11 2011 TriQuint Semiconductor, Inc. - 1 of 9 Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network

TQP3M9007
W High Linearity LNA Gain Block Specifications Absolute Maximum Ratings
Parameter
Storage Temperature RF Input Power,CW,50 ,T=25C Device Voltage,Vdd

Recommended Operating Conditions

Parameter
Vdd Tcase Tj (for>106 hours MTTF)

Rating
-55 to 150 oC +20 dBm +7 V

Min
3 -40

Typ
5

Max Units
5.25 +85 190 V o C o C

Operation of this device outside the parameter ranges given above may cause permanent damage.

Electrical specifications are measured at specified test conditions. Specifications are not guaranteed over all recommended operating conditions.

Electrical Specifications
Test conditions unless otherwise noted: +25C, +5V supply, 50 system.

Parameter
Operational Frequency Range Test Frequency Gain Input Return Loss Output Return Loss Output P1dB Output IP3 Noise Figure Supply Voltage, Vdd Current, Idd Thermal Resistance (jnc to case) jc

Conditions

Min
100

Typical
1900

Max
4000

Units
MHz MHz dB dB dB dBm dBm dB V

11.5

13 18 13 +23.6

14.5

See Note 1.

+37

+41 1.3 +5 125 52 150

mA
o

C/W

Notes: 1. OIP3 is measured with two tones at an output power of 4 dBm / tone separated by 1 MHz. The suppression on the largest IM3 product is used to calculate the OIP3 using 2:1 rule. 2:1 rule gives relative value with respect to fundamental tone.

Data Sheet: Rev D 12/27/11 2011 TriQuint Semiconductor, Inc.

- 2 of 9 -

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TQP3M9007
W High Linearity LNA Gain Block Device Characterization Data
S11
6 0.

S22
Swp Max 6GHz
6 0.

1.0

Swp Max 6GHz

2. 0

0.8

30 25

3.

10.0

10.0

Gain (dB)

20 15

10.0

0.2

0.4

0.6

0.8

1.0

2.0

3.0

4.0

5.0

0.2

0.4

0.6

0.8

1.0

2.0

3.0

4.0

5.0

10 5 0.0

-0

.4

.4 -0

.0

-2

-0 .6

-0.8

-1.0

-0.8

Frequency (GHz)

S-Parameter Data
Vdd = +5 V, Icq = 125 mA, T = +25C, unmatched 50 ohm system, calibrated to device leads

Freq (MHz) 50 100 200 400 800 1000 1200 1500 1900 2000 2200 2500 2600 3000 3500 4000

S11 (dB) -9.21 -9.18 -9.58 -11.09 -13.55 -14.69 -15.31 -16.32 -16.36 -16.44 -16.55 -16.78 -16.83 -17.62 -18.79 -20.11

S11 (ang) -171.69 178.66 168.58 155.91 148.37 147.37 148.14 152.38 155.45 154.43 154.33 153.75 154.69 157.51 154.34 176.37

S21 (dB) 21.92 21.72 21.39 20.71 18.58 17.47 16.33 14.85 13.11 12.73 11.98 10.97 10.59 9.53 8.24 7.01

S21 (ang) 165.87 164.31 154.89 134.86 99.19 84.06 70.48 52.18 30.26 25.52 15.20 0.51 -4.70 -24.26 -48.07 -72.56

S12 (dB) -28.66 -28.54 -28.25 -27.05 -24.58 -23.58 -22.59 -21.45 -19.96 -19.77 -19.13 -18.24 -18.14 -17.17 -16.19 -15.53

S12 (ang) 7.52 8.08 11.48 16.59 17.74 14.87 12.31 6.08 -2.85 -5.72 -12.30 -20.16 -23.60 -36.43 -53.90 -72.99

S22 (dB) -10.26 -10.62 -10.93 -11.61 -12.39 -13.43 -13.72 -14.84 -15.21 -15.43 -16.18 -16.76 -16.24 -16.21 -14.74 -11.54

-1.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Swp Min 0.01GHz

-0 .6

-2

.0

S22 (ang) -177.68 166.81 145.14 112.74 63.78 40.99 23.70 -3.77 -32.08 -42.20 -54.41 -84.02 -91.43 -128.42 -165.72 154.74

Data Sheet: Rev D 12/27/11 2011 TriQuint Semiconductor, Inc.

- 3 of 9 -

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-3 .0

-3

.0

Gain (dB)

Swp Min 0.01GHz

-4 .0 -5. 0

-4 .0 -5. 0

2 -0.

2 -0.

-10.0

0.2

-10.0

0.2

De-embedded S-parameter Vcc = 5V

0 4.
5.0

0. 4

0. 4

Gain and Max Stable Gain

2.

0.8

1.0

3.

0 4.
5.0

10.0

TQP3M9007
W High Linearity LNA Gain Block Application Circuit Configuration
GND J3

C3

C1

Q1
C2 C6

Notes: 1. See PC Board Layout, under Application Information section, for more information. 2. Components shown on the silkscreen but not on the schematic are not used. 3. B1 (0 jumper) may be replaced with copper trace in the target application layout. 4. All components are of 0603 size unless stated on the schematic. 5. C6 and L2 value are critical for linearity performance.

Bill of Material: TQP3M9007-PCB

Reference Desg.
Q1 C2 C6 C1 L2 C3 B1 D1 100 pF 27 pF 0.1 uF 56 nH 4.7 uF 0 Do Not Place

Value

Description
High Linearity LNA Gain Block Cap, Chip, 0603, 50V, NPO, 5% Cap, Chip, 0603, 50V, NPO, 5% Cap, Chip, 0603, 16V, X7R, 10% Ind, Chip, 0603, 5% Res, Chip, 0603, 1/16W, 5%

Manufacturer
TriQuint various various various various various various

Part Number
TQP3M9007

Cap, Chip, 0603, 6.3V, X5R, 20% various

Data Sheet: Rev D 12/27/11 2011 TriQuint Semiconductor, Inc.

- 4 of 9 -

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TQP3M9007
W High Linearity LNA Gain Block Typical Performance TQP3M9007-PCB
Test conditions unless otherwise noted: +25C, +5V, 125 mA, 50 system. The data shown below is measured on TQP3M9007-PCB

Frequency
Gain Input Return Loss Output Return Loss Output P1dB OIP3 [1] Noise Figure [2]

MHz
dB dB dB dBm dBm dB

500
20 11.5 10.5 +22.9 +39.3 1.4

900
18 14 13 +23.3 +40.2 1.2

1900
13 18 13 +23.5 +41.1 1.3

2100
12 17.5 12 +23.8 +42.2 1.4

2600
10 15.5 10.5 +24.0 +42.2 1.8

Notes: 1. OIP3 measured with two tones at an output power of +4 dBm / tone separated by 1 MHz. The suppression on the largest IM3 product is used to calculate the OIP3 using 2:1 rule. 2. Noise figure data shown in the table above is measured on evaluation board and corrected for the board loss of about 0.13 dB @ 1.9 GHz.

Performance Plots
Performance plots data is measured using TQP3M9007-PCB. Noise figure plot has been corrected for evaluation board loss of 0.13 dB @ 1.9 GHz.
24 22 20 18
Gain (dB)

Gain vs. Frequency

Vcc = 5V

0 -5 -10 -15 -20 -25

Input Return Loss vs. Frequency

Vcc = 5V

0 -5 -10 -15 -20 -25

Output Return Loss vs. Frequency

Vcc = 5V

16 14 12 10 8 6 0.0 0.5 1.0 1.5 2.0 2.5

+85C +25C 40C

+85C +25C 40C

3.0

3.5

4.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Output Return Loss (dB)

Input Return Loss (dB)

+85C +25C 40C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Frequency (GHz)
4.0 3.5 3.0
NF (dB)
Vcc = 5 V

Frequency (GHz)
50

Frequency (GHz)
50 +85C +25C 30 C 40C

Noise Figure vs. Frequency

OIP3 vs. Output Power/Tone

+85C +25C 30 C 40C
Freq. = 900 MHz 1MHz Tone Spacing Vcc = 5V

OIP3 vs. Output Power/Tone

Freq. = 1900 MHz 1 MHz Tone Spacing Vcc = 5V

OIP3 (dBm)

2.0 1.5 1.0 0.5 0.0 0.5 1.0

40

OIP3 (dBm)

2.5

+85C +25C 40C

45

45

40

35

35

30 1.5 2.0 2.5 3.0 0 2 4 6 8 10 12

30 0 2 4 6 8 10 12

Frequency (GHz)

Output Power (dBm)

Output Power/Tone (dBm)

Data Sheet: Rev D 12/27/11 2011 TriQuint Semiconductor, Inc.

- 5 of 9 -

Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network

TQP3M9007
W High Linearity LNA Gain Block
50

OIP3 vs. Frequency

1 MHz Tone Spacing Temp. = 25oC Vcc = 5V

25

P1dB vs. Temperature

Vcc = 5V

-30 -35
ACLR1 (dBc)

ACLR vs. Output Power

Single Carrier 1+64DPCH WCDMA, PAR 10.2dB @ 0.01% probability Vcc = 5V

45
OIP3 (dBm) P1dB (dBm)

24

1900 MHz 900 MHz

-40 -45 -50 -55 900 MHz 1900 MHz 10 12 14 16 18 20

40

23

35

30 0.5 1.0 1.5 2.0 2.5

22 -40 -20 0 20 40 60 80

-60

Frequency (GHz)
30 25
Output Power (dBm)
OIP3 (dBm)

Temperature (C)
45 1900MHz 900MHz 40
P1dB (dBm)

Output Power (dBm)

30
Pout/tone = 4dBm Tone spacing = 1MHz

Power Compression Curve

OIP3 vs. Vdd

P1dB vs. Vdd

1900 MHz 900 MHz

25

20 900 MHz 15 10 5 0 5 10 15 20 1900 MHz

35

20

30

15

25 3 4 5 6 7

10 3 4 5 6 7

Input Power (dBm)

130 125 120
Idd (mA)

Vdd (Volts)

Vdd (Volts)

Idd vs Vdd

115 110 105 100 95 3.0 4.0 5.0 6.0 7.0

Vdd (Volts)

Data Sheet: Rev D 12/27/11 2011 TriQuint Semiconductor, Inc.

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TQP3M9007
W High Linearity LNA Gain Block Pin Description
GND 4

1 RF IN

2 GND

3 RF OUT

Pin
1 3 2, 4

Symbol
RF Input Vdd / RFout GND Paddle

Description
Input, matched to 50 ohms. External DC Block is required. Output, matched to 50 ohms, External DC Block is required and supply voltage. Backside Paddle. Multiple vias should be employed to minimize inductance and thermal resistance; see page 7 for mounting configuration.

Applications Information PC Board Layout

Top RF layer is .014 NELCO N4000-13, r = 3.9, 4 total layers (0.062 thick) for mechanical rigidity. Metal layers are 1-oz copper. 50 ohm Microstrip line details: width = .029, spacing = .035 The pad pattern shown has been developed and tested for optimized assembly at TriQuint Semiconductor. The PCB land pattern has been developed to accommodate lead and package tolerances. Since surface mount processes vary from company to company, careful process development is recommended. For further technical information, Refer to www.TriQuint.com

Data Sheet: Rev D 12/27/11 2011 TriQuint Semiconductor, Inc.

- 7 of 9 -

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TQP3M9007
W High Linearity LNA Gain Block Mechanical Information Package Information and Dimensions
Markings: Part number: 3M9007 Assembly code: Y is last digit of part manufacture year. XXX is lot code. 3M9007 YXXX

PCB Mounting Pattern

All dimensions are in millimeters (inches). Angles are in degrees.

Notes: 1. Ground / thermal vias are critical for the proper performance of this device. Vias should use a .35mm (#80 / .0135) diameter drill and have a final plated thru diameter of .25 mm (.010). 2. Add as much copper as possible to inner and outer layers near the part to ensure optimal thermal performance. 3. RF trace width depends upon the PC board material and construction. 4. Use 1 oz. Copper minimum.

Data Sheet: Rev D 12/27/11 2011 TriQuint Semiconductor, Inc.

- 8 of 9 -

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TQP3M9007
W High Linearity LNA Gain Block Product Compliance Information ESD Information Solderability
Compatible with both lead-free (maximum 260C reflow temperature) and lead (maximum 245C reflow temperature) soldering processes. ESD Rating: Value: Test: Standard: ESD Rating: Value: Test: Standard: Class 1A Passes 250 V to < 500 V Human Body Model (HBM) JEDEC Standard JESD22-A114 Class IV Passes 1000 V Charged Device Model (CDM) JEDEC Standard JESD22-C101 This part is compliant with EU 2002/95/EC RoHS directive (Restrictions on the Use of Certain Hazardous Substances in Electrical and Electronic Equipment). This product also has the following attributes: Lead Free Halogen Free (Chlorine, Bromine) Antimony Free TBBP-A (C15H12Br402) Free PFOS Free SVHC Free

MSL Rating
Moisture Sensitivity Level 3 at 260C per JEDEC standard IPC/JEDEC J-STD-020.

Contact Information
For the latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: info-sales@tqs.com For technical questions and application information: Email: sjcapplications.engineering@tqs.com Tel: Fax: +1.503.615.9000 +1.503.615.8902

Important Notice
The information contained herein is believed to be reliable. TriQuint makes no warranties regarding the information contained herein. TriQuint assumes no responsibility or liability whatsoever for any of the information contained herein. TriQuint assumes no responsibility or liability whatsoever for the use of the information contained herein. The information contained herein is provided "AS IS, WHERE IS" and with all faults, and the entire risk associated with such information is entirely with the user. All information contained herein is subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for TriQuint products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by such information. TriQuint products are not warranted or authorized for use as critical components in medical, life-saving, or life-sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death.

Data Sheet: Rev D 12/27/11 2011 TriQuint Semiconductor, Inc.

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