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ReshapingtheSoCpowerdesignflow
AndrewYangandShenLin 2/6/20045:00PMEST
ExistingstaticsignoffflowsfailtocatchpowerproblemsincomplexSoCs,accordingtoApache DesignSolutionsCEOAndrewYangandCTOShenLin.Inthisexclusivefeature,theyoutlineanew physicalpowerflowthatisbasedonpowerprototypingandfullchipdynamicpowersignoff verification.Powerintegrityhasbecomeonethemostcriticalissuesaschipdesignshavetransitionedto 130nmand90nmprocessingtechnologies.Decreasingsupplyvoltages,increasingdevicedensityand leakagecurrents,fasteredgerates,andlowpowerdesigntechniqueshaveallcontributedtoadramatic increaseinpowergroundnoiseandthechanceofdesignfailures. ExistingstaticIRdropsignoffmethodologies,basedon"average"powerandconservativeover designingthepowergrid,havebecomeinadequatetoprotectdesignsfromsupplynoiseinducedlogic andtimingfailures.Furthermore,thelackofaccurateandefficienttoolsforanalyzingthecomplex problemofgroundnoisecouplingbetweentheICandthepackageorboardresultsinincreasingI/O simultaneousswitchingoutput(SSO)failuresforchipswithmanyI/Os. DesignersandEDAtoolvendorsalikehaveconcentratedmostoftheireffortsonachievingtiming closurebetweensynthesisandlayout.Recently,significanteffortshavealsoresultedinsuccessin copingwithsignalintegrity(crosstalk).Fullchippowerintegrity,ontheotherhand,ismorechallenging becausethepowergroundsuppliesconsistoflayersofstronglyinterconnectedmeshnetworks,the dynamicswitchingeventsarelogicandtimingdependent,andtheoffchipenvironmentimpactsonthe systemonchip(SoC)coreduetothecouplingofI/Ogroundnoise. Inthisarticle,wefirstdiscussthelimitationsofexistingpowermethodologiesandtheirimpactonSoC designs.Specifically,weaddressexamplesofpotentialchipfailuresbothinthecoreregionaswellas theI/Oarea,duetodynamicsupplynoise,andexplainwhyexistingstaticsignoffflowsfailtocatch theseproblems.Wethenpresentthenewphysicalpowerflowthatisbasedonpowerprototypingand fullchipdynamicpowersignoffverificationincludingnoiseimpacttotiming. I.Today'spowermethodology overdesign

Intoday'sSoCflow,designersfirstdeterminethecorepowerbudgetbasedonmacro/IPpower estimationandstandardcellblockpower,calculatedfromthestaticnumbersinthecelllibrary(.lib).I/O powerisalsocalculatedusinganestimateofthequantityofsimultaneousswitchingI/Osdrivingthe packagemodel. Powergriddesign Thepowersupplynetworksareusuallydesignedbyaspreadsheetusingrulesbasedonthechippower estimates.Typically,thepowergridsareoverdesignedtoaddsignificantIRdroptoleranceand accommodateanylatestagedesignchanges.Thisprocesscanrepresentmanyweeksofmanualwork andtheendresultisapowergridthatusesexcessmetal,leadingtoroutingcongestionsandlargerdie size.

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"Golden"staticIRdropverification Thenexttimepowerisconsideredisusuallyafterrouting.Anypowerrelatedchangeswillbevery difficultandtimeconsumingatthislatestage.Aspartofthetapeoutflow,astaticanalysisistypically performedtoverifythefullchippowerandIRdropdistribution.As"staticIRdrop"impliesbyits name,theonlythingsbeingtakenintoaccountarethegridresistance(R)timestheaverageamountof current(I)flowingthroughit.Thisaveragecurrentiscalculatedusingan"averagetogglerate",whichis yetanotherruleofthumbmetric. Thissimplisticviewofthepowergridisresponsibleforanumberofweaknesseswiththis"golden"IR dropsignoff.Manyimportantpowerconsiderationsareomittedthatmanifestthemselvesinrealworld chipfailures.Theseomissionsinclude: Simultaneousswitchinganalysisofcorelogicandmacros/IP Capacitiveorinductiveeffects TransientanalysisoftheI/Obufferpackageconcurrenteffects,whichcanbedominant Hence,thestaticIRverificationmethodologycanonlybeusedtoidentifygrossdesignviolationssuch asmissingconnections,missingvias,blockswithinsufficientpowerconnections,ordanglingpower connections. Adhocdecouplingcapacitancemethodology Whengeometrieswerelarger,supplyvoltageshigher,andfrequencieslower,theoverdesign methodologycouldcompensateforthesimplifyingassumptionsandinaccuraciesofstaticIRanalysis. However,itisnotpossibletooverdesignforthepotentialeffectsofspikesofsupplynoise.Hence,on chipdecouplingcapacitors(decaps)canbeusedtoreducethedynamicsupplynoisefromsimultaneous switchingevents. Unfortunately,unlessenoughdecapcellsareplacedincloseproximitytothedynamic"hotspots"ina design,theireffectivenessisgreatlydiminished(seeFigure1).SincestaticIRanalysisdoesnotconsider capacitiveandinductiveeffects,designersgenerallydonothaveaccurateinformationforthelocations andsizeofdecaprequired. Typically,anadhocmethodologyisusedtosimplyfillemptyspaceswithdecaps.Withoutanaccurate andsystematicmeanstoanalyzetheireffectiveness,decapcellscanbeputinplaceswheretheyhave littleornoeffect,contributingonlytoadditionalleakagepowerwhichcouldbecomecritical,especially intoday'slowpowerdesigns.

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Figure1

Decouplingcapacitanceeffectiveness

2.Thefailureofexistingpowermethodologies TheinadequaciesofthestaticIRandtheoverdesignmethodologiesmanifestthemselvesinagrowing numberofchipfailures.VirtuallyeverymajorsemiconductororfablessICmanufacturerdoingcomplex highperformancedesignshasexperiencedoneormoresiliconfailures,inspiteofthedesignpassing their"goldensignoff"verificationflow. Thesefailurestendtoshowupinmoreobscurefashionsandareverydifficulttotrackdown.Theymay beseenonlyincertainmodesofoperationofthechip,orasyieldissueslimitingtheperformanceofthe device.Often,adevicewasdesignedforVddof1.2,butwasonlyfunctionalatmuchhighervoltages. Failuressuchasthesecanbeverycostly,notonlyintermsofmasksetandfabricationcosts,butalsoin thetimeittakestodebuganddevelopafix.Inmanycasesthefixhasmeantasignificantredesign, rangingfrompowergridmodifications(andsubsequentrerouteofthedevice),amodifiedpackage and/orI/Obuffer,orchangingthestructureofthelogictoavoidtoomanygatesswitchingatthesame time.Thecommonelementsofthesepowerrelatedfailuresarecoreand/orI/Osimultaneousswitching. Coresimultaneousswitchingeffects Inthecoreofadevice,simultaneousswitchingeventsfrombussesorevenrandomlogicwithlarge driversmaycauselargespikesofcurrentwithinnarrowtimingwindow,asshowninFigure2.Because today'splacementtoolsarenotawareofpower,theymayplacehighpowercellsclosetoeachotherto minimizedelayorwirelength,whichpotentiallycreatedynamichotspotsthatcannotbeanalyzedby staticIRtools. DesignersmustalsounderstandtheimpactofdynamicsupplynoisecanhaveinalargeSoC.The impactofswitchingonandoffofanyonchipIPsuchasaCPUormemoryneedstobeunderstoodas well.Howdoalltheseblocksinteractduringdeviceoperation?Howmanyareactiveatthesametime? Ifthetransientvoltagedropissignificant,andhappensduringanimportantswitchingwindow,timingof thecellscanbeaffectedandcanpotentiallycausethedevicetofailorrunatslowerspeeds.

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Figure2

Dynamiccurrentprofilefromsimultaneousswitchingevents

I/Osimultaneousswitchingeffects I/Osimultaneousswitchingisanotherareawheremanyfailureshavebeenobserved.Buswidthsare nowaslargeashundredsofbits,sotechniquessuchastheuseofintentionalskewmustbeemployed. Eventhen,hundredsofI/Oscanswitchatthesametime.DependingonthesizeoftheI/Obuffer,this canputasignificantstrainonthepowergridorpackageofadevice. Additionally,theseI/Oswitchingcurrentscauselargegroundbounce,whichimpactstimingatthe outputoftheI/Obuffers,orinsomecases,couplestothecore,causingsurroundingonchiplogictofail. Inonedesign,thegroundbounceattheoutputwasalmost0.5voltsona1.3Vsupply.Theresultant pushoutoftheoutputsignalduetothisgroundbouncecausedthedesigntofailwhencommunicating toanexternalmemoryatthespecifiedvoltageandtiming(seeFigure3). ToaccuratelyanalyzeI/OSSOeffects,theonchipP/Gnetwork,I/Obuffercircuits,aswellasaccurate offchippackagemodelsusingSparametersneedtobeconsidered,basedonrealisticoutputswitching scenarios.

Figure3

I/OsimultaneousswitchingSPICEsimulation

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Lowpowerdesigneffects Powergatingisbecomingmoreandmorecommoninlowpowerdesigns.Thegatingdevicesshut downpartsofthechipincertainmodesinordertosavepower.Understandingtheeffectsofpowering theseblocksbackon,andwhatthepeakcurrentsurgewillbe,iscrucialtosuccessfullowpowerdesign. Manydevicesalsocontaindataretentionnetworksthatsavethestateoftheblockonceitisshutdown. Analyzingtheintegrityoftheseretentionnetworksisveryimportanttothepowerintegrityofthedevice. Basedonthecomplexityoftheproblem,itisnotdifficulttounderstandwhytoday'sstandardofstatic IRdropforfinalverificationisinsufficienttohandlethepowerintegrityproblemsfacingdesigners using150nmandsmallergeometries.Whatisrequiredisanewphysicalpowerflow,whichhasthe abilitytoaddresstheseissuesandassurefullchippowerintegrity. 3.Thenewphysicalpowerflow Inthetraditionalphysicaldesignflow,staticIRdropanalysesareperformedclosetotapeout,whenall physicaldesigninformationisavailable.Asmentionedearlier,theseanalysesdonotcaptureandidentify importantpowerintegrityissuesinadesign.Dynamicpowergridanalysesprovidethemissinglinkin thebackendverificationflow.However,evengreaterbenefitcanbeobtainedbyavoidingtheseissues earlyinthedesignflow,startingwithpowergridplanning. Powergridplanning Powergridplanningneedstobeginearly,oncepowerestimationformacrosandtoplevelblocksis complete.Differentgriddesignsandgridsizesneedtobeexploredautomaticallyasplacementsbecome available.Staticanddynamichotspotscanbeidentifiedanddifferentgridoptionsanddecapsolutions canbedeterminedtoresolvethem. PackageRLCmodelscanbeconsideredalongwithondienetworkstogetarealisticvoltagedrop picture.Differentpadlocationscanbeexploredtoverifytheirusefulnessandeffectiveness.Optionsfor hookingupmacrosandIPtothetoplevelgridcanbeinvestigated. Thepowergridplanningprocessshouldhonorblockagesandspecificroutingrequirements.Itshould automaticallygenerategridsthatmeetpredefinedIRdropbudgetsandallotherdesignconstraints. Engineerscanthenplantheirpowergrid(metalusage,padlocations,anddecapallocation)fromthe verystartofthedesignprocess,alleviatingpowerintegrityissuesandsurprisesjustpriortotapeout. Thenewphysicalpowerflow(seeFigure4)enablesdesignerstoplanandengineertheirpowergrids fromthestartofthedesigncycleandtoincrementallyupdatethemasmoreinformationbecomes available.Thekeyobjectivesaretoundertakeconsistentpoweranalysisfromthestartofthedesign processandtoexploreoptionsforautomaticgriddesign,gridsizing,powerpadanddecapplacement, andsoon,asthedesignevolves. Asthepowernumbersandinitialplacementbecomeavailable,designerscaninitiatepowergrid planning.Differentoptions,suchaspowerringsaroundmacros,globalmeshwithdifferentpitchand designstyles,andpadplacements,canbeexploredautomaticallytomeetspecifiedIRdroptargets.As thedesignevolveswithtrialroutes,designerscanrefinethegridtomeetroutinganddesignconstraints. IRdropanalysiscanbedoneateachstageforverification.Theseanalysesshouldincorporate capabilitieshighlightedinthefollowingsection.Afterinitialplacements,thepowergridplannerwill

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adviseondecapinsertionandgridsizingtoresolvedynamichotspots.Towardsthecloseofthedesign cycleasthecompletedesigninformationbecomesavailable,designerscanverifytheeffectivenessofthe gridwithafullchipdynamicverificationforfinalsignoff.

Figure4

Thenewphysicalpowerflow

Powergridverification Afullchippowergridanalysisbringsseveralchallenges.Itisdifficulttofindworstcasevectors,andit isevenmoredifficulttofindthemearlyinthedesigncycle.Vectorlessdynamicanalysisusesstatistical techniquestofindrealisticworstcasepowerscenariosforbothblocklevelandfullchippowergrid analysis.Thisallowsdesignerstounderstandweaknessesinthegridearlyonandmakechangesbefore routing.Italsoallowsforasensitivityanalysistoexploreweaknessesbeyondthecoverageprovidedby vectorbasedruns. DynamicVoltageDrop(DvD)analysisisatruetransientanalysisofthecompletepowergridwith Spicelikeaccuracy.Atransientanalysisistheonlywaytoaccuratelyunderstandthecapacitiveand inductiveeffectsonthepowergrid,andtoincorporatetheeffectsofexplicitdecouplingcapacitorsand intrinsicdevicecapacitances. Pseudodynamicapproachesofdividingtheclockcycleintomanywindowsandperformingsequential staticanalysisoneachwindowarenotadequateorsufficientlyaccurate.Theflowmustalsobeableto workattheblocklevelinordertoprovideearlyfeedbackforthedesigner.However,thecapacityto performfullchiptransientanalysis(includingallmemoryandIP),inareasonabletime,isalsocriticalto thenewphysicalpowerflow. Withinformationaboutthevoltageataninstanceoverthesimulatedperiodoftime,wecanestimatethe impactoftheloweroperatingvoltageontimingofthatinstance.Alargevoltagedropacrossacellmay nothaveabigeffectonan8Xdriver,whileasmallerdropmightcauseafailureina1xcell.Similarly,a largedropacrossacellinapathwithalargeamountofslackwillhavemarginaleffect,whileasmaller dropacrossacellinapathwithminimalslackmaycauseatimingfailure.

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AnalyzingtheDvD'simpacttotimingisacriticalpartofthenewphysicalpowerflow.Theoutputfor timinganalysisiscomprisedofavoltagewaveformforVddandVssofeachcellfortherealisticworst caseclockcycle.Statictiminganalysis(STA)toolstodayarenotquitereadytohandlethiswaveform information,butcanconsideran"effective"voltageforeachcelloveritsswitchingtimingwindow.This informationcanbederivedfromthevoltagewaveforms.Astimingtoolsadvance,theywillbeableto handlethisinstantaneousbasedwaveforminformationtoaccuratelypredictdelaysandtiming. AsurprisingnumberofdesignfailuresareI/Orelated.WithmanysimultaneousswitchingI/O's,the amountofcurrentbeingdrawncanbestaggering.Groundbouncebecomesasignificantissueandcan pushsignaldelaysoutpastacceptablewindows. ThisisespeciallycriticalformultigigabitI/Os.GroundbounceandasharedVsscandisturbdigital logicintheI/OsorcorecellsneartheI/Obuffers.ThenewphysicalpowerflowneedstosupportSpice accurateanalysisofhundredsofI/Osswitchingtoensureproperoperationofthechip.Thisanalysis needstoencompassnotonlytheI/Obuffermodelbutalsothepowergridparasitics,packagemodel, andloadoftheI/O. Alloftheabovecapabilitiesaremeaninglesswithoutahighlevelofaccuracyinthecelllibrary.As mentionedbefore,manypowertoolsbasetheiranalysisoffthepowernumbersinstandardlibrariessuch asthe.libformat.Thisnumberisthetotalswitchingenergyforthecellanddoesnotrepresenttrue dynamicbehavior. Powernumbersin.libcanbeoffbyasmuchas30%ormore.Theoldadage"garbagein,garbageout" applieshereaswell.ASpicelevelcharacterizationofthedetailedswitchingwaveformsofthecellsin thelibraryistheonlyreliablewaytogetaccuratepowernumbersandtofacilitatesimulations,which shouldbearequirementofanydynamicpowerflow. Integratedsolutions routing,signalintegrity,andpower SomeEDAvendorsandusershaveproposedintegratedsolutionsthatencompassrouting,signal integrity,andpower.Thelimitationoftheseproposedsolutionsisthatpowerintegrityisafullchip phenomenonwhilebothroutingandsignalintegrityissuesarelocalizedproblems. Includingdynamicpoweranalysisintotheinnerprocessofroutingandsignalintegritymakesitalmost intractablebecauseofthecomplexityofeachfullchipsimulation.Thenewphysicalpowerflowsolves theprobleminatopdownfashion,incrementallyimprovingthedesignfromearlyfloorplanningtofinal postrouteverification,eliminatingsurprisespriortotapeoutandensuringpowerintegrity. Conclusion Asgeometriesshrink,thephysicalpowerissuesarebecomingacriticaldesignlimitation.Itisoften difficultfordesignteamstocomprehendthechallengesofmovingfromdesigningin130nmto90nm. Manydesignersaresurprisedwhentheyhavepowerrelatedfailureswhichshouldhavebeenavoided byareshapingthephysicalpowerflow.Movingtothisnewpowerflowprovidedesignersinformation abouttheirdesignsthattheyhaveneverhadbefore.Utilizingthisinformationwillleadtosmaller,faster, andmorerobustdesignswithfastertimetomarketandgreatersiliconyield. And e T.Yangha e eda hechiefe ec i eoffice incehecofo ndedApacheDe ignSol ion in2001.And e ecei edhi Ph.Df om heUni e i ofIllinoi ,U banaChampaignin1989and

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a a en ep ofe o a heUni e i ofWa hing on n il1996.In1993,hefo ndedAnag am, hich a me ged i hA an iin1996.The e,he e eda icep e iden e pon iblefo e ac ion andanal i p od c n il1998.And e ha al obeenaleadin e o andad i o fo an mbe of EDAcompanie incl dingCADMOS,Innologic,Moja e,Sapphi e,andUl ima. ShenLinha e eda hechief echnicaloffice incehecofo ndedApachein2001.Shen ecei ed hi Ph.D.f om heUni e i ofCalifo nia,Be kele in1992and o keda a e ea ch affmembe of heIBMT.J.Wa onRe ea chCen e inYo k o nHeigh n il1995.Shen o keda LSILogic de elopingon hefl ASICde ignme hodologie befo ejoiningHPLab ,PaloAl oin1997foc ing onind c ance ela ed ignalin eg i i e andcon ib ing o heHPIn elIA64mic op oce o de ign.

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