Computer Arithmetic Circuit Design

Chapter 11

Tree and Array Multipliers

Full-Tree Multipliers Alternative Reduction Trees Tree Multipliers for Signed Numbers Partial-Tree Multipliers Array Multipliers Pipelined Tree and Array Multipliers

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Full-Tree Multipliers

Ch 11. Tree and Array Multipliers

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Full-Tree Multipliers
1. All multiples of the multiplicand are produced in parallel. 2. k-input CSA tree is used to reduce them to two operands. 3. A CPA is used to reduce those two to the product. No feedback pipelining is feasible. Different multiplier arrays are distinguished by the designs of the above three elements.
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General Structure of a Full-tree Multiplier

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Radix Tradeoffs
The higher the radix .
The more complex the multiple-forming circuits, and The less complex the reduction tree.

Where is the optimal cost-effectiveness?

Depends on design Depends on technology
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Tradeoffs in CSA Trees

Wallace Tree Multiplier
Combine partial product bits at the earliest opportunity. Leads to fastest possible design.

Dadda Tree Multiplier

Combine as late as possible, while keeping the critical path length (# levels) of the tree minimal. Leads to simpler CSA tree structure, but wider CPA at the end.

Hybrids
Some where in between.
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Two Binary 4 4 Tree Multipliers

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Reduction Tree
Results from chapter 8 apply to the design of partial product reduction trees.
General CSA Trees Generalized Parallel Counters

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CSA for 7 7 Tree Multiplier

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Structure of a CSA Tree

A logarithmic depth reduction trees based on CSAs (e.g. Wallace, Dadda. Etc.)
Have an irregular structure. Make design and layout difficult.

Connections and signal paths of various lengths

Lead to logic hazards and signal skew. Implication for both performance and power consumption.

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Alternative Reduction Trees (n;2) Counters

(more suitable to VLSI)

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A Balanced (11;2) Counter

1. Balanced: All outputs are produced after the same number of delays. 2. All carries produced at evel i enter FAs at level i+1. 3. Can be laid out to occupy a narrow vertical slice. 4. Can be easily expanded to a (18;2) counter.
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Tree Multiplier Based on (4,2) Counters

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Layout of Binary Reduction Tree

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Sign Extension

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Signed Addition

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Baugh-Wooley Arrays

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Partial Tree Multipliers

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Basic Array Multiplier Using a One-Sided CSA Tree

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Unsigned Array Multiplier1

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Unsigned Array Multiplier2

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Baugh-Wooley Signed Multiply

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Signed Multiplier Array

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Mixed Positive and Negative Binary

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Mixed Binary Full Adders

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5 5 Signed Multiplier Using Mixed +/ Numbers

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Include AND Gates in Cells

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Change the Terms of the Problem

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Multiplier Without Final CPA

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Conditional Carry-Save

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Pipelined Partial-Tree Multiplier

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Pipelined Array Multiplier

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