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Instruction set of 8086

Data transfer group Arithmetic group Bit manipulation group String instruction group Program transfer group Process control instruction group

Data transfer group (types)


1.General purpose MOV (move byte r word) PUSH (push word on to stack) POP (pop word off stack) XCHG (exchange byte r word) XLAT (translate byte) 2.Address object LEA (load effective address) LDS (load pointer using DS) LES (load pointer using ES)

3.Input/Output IN (Input byte r word) OUT (output byte r word)

4.Flag transfer LAHF (load AH register from flags) SAHF (store AH in flags) PUSHF (push flags onto stack) POPF (pop flags off stack)

General purpose 1.MOV destination, source


Mnemonics :MOV destination (operand1), source(operand2) Flags: no flags affected Algorithm: destination source (operand1<-operand2) Addressing mode: Register Addressing mode Operation: destinaion =source Examples: MOV [SI],AL MOV AX , Temp result MOV AX,BX MOV COUNT [DI],2DH

Valid destination and source


s.no 1 2 3 4 5 6 7 8 9 10 destination memory accumulator register register memory register memory Seg-reg Seg-reg Reg-16 source accumulator memory register memory register immediate Immediate Reg-16 Mem-16 Seg-reg

PUSH source
Mnemonics :PUSH source Flags: no flags affected Algorithm: sp<--sp-2 Addressing mode: Register Addressing mode Operation: sp=sp-2 Examples: PUSH AX Explanation: copy word from AX reg to the location in (SS) stack segment where (SP) Stack pointer points. SS Data from specifies source

Possible sources of operand in push


General purpose register Flag register Segment register memory

POP destination
Mnemonics :POP destination Flags: no flags affected Algorithm: sp<--sp+2 Addressing mode: Register Addressing mode Operation: sp=sp+2 Examples: POP AX Explanation: SS Data copied to destination .

XCHG destination ,source


Mnemonics :XCHG destination ,source Flags: no flags affected Algorithm: destination source Addressing mode: Implied Addressing mode Operation: destination source Examples: XCHG AX,BX Note : XCHG can not directly exchange the contents of two memory location

XLAT translate (or) replace byte


Mnemonics :XLAT or XLATB Flags: no flags affected Algorithm: AL <--DS:[ BX+unsigned AL] Addressing mode: Implied Addressing mode Operation: AL =DS:[ BX+unsigned AL] Examples: XLAT, XLATB Mostly this is used to convert BCD to Seven segment code.

Input/Output IN copy a data from the port


Mnemonics :IN accumulator, port address Flags: no flags affected Algorithm: AXcontents of port AL contents of port Addressing mode: Direct port Addressing mode Operation: AXcontents of port AL contents of port Examples: IN AL, 02 IN AL, DX (Indirect)

OUT copy a data from the port


Mnemonics :OUT port address,Accmulator Flags: no flags affected Algorithm: AX port address AL port address Addressing mode: indirect port Addressing mode Operation: AX port address AL port address Examples: OUT 02, AL OUT DX, AL

Address object LEA (load effective address) LEA register, source


Mnemonics :LEA register,source Flags: no flags affected Algorithm: register source (Address of the memory (offset)) Addressing mode: Register direct Addressing mode Operation: register=source Examples: LEA AX, count

Mnemonics :LDA register ,source Flags: no flags affected Algorithm: Registersource DS (source+2) Addressing mode: Register direct Addressing mode Operation: Registersource DS (source+2)

LDS (Load pointer with DS) Load register &DS with word from memory

LES (Load pointer with ES) Load register &ES with word from memory
Mnemonics :LEA register ,source Flags: no flags affected Algorithm: Registersource ES (source+2) Addressing mode: Register direct Addressing mode Operation: Registersource ES (source+2)

FLAG transfer LAHF (load AH register from flag) (copy lower byte flag reg to AH)
Mnemonics :LAHF Flags: no flags affected Algorithm: AHflag registers lower byte Addressing mode: implied Addressing mode Operation: AH= flag registers lower byte In this the lower byte 8086 flag register copied to the the AH.

FLAG transfer SAHF (store AH register from flag) (copy content of AH to lower byte of flag register)
Mnemonics :SAHF Flags: all the flags changed Algorithm: AH changed flag registers lower byte Addressing mode: implied Addressing mode Operation: AH= flag registers lower byte

PUSH PUSH flag reg on the stack


Mnemonics :PUSHF Flags: no flags affected Algorithm: SPSP-2 Addressing mode: Register Addressing mode Operation: SP=SP-2

POP PUSH flag off stack


Mnemonics :POPF Flags: no flags affected Algorithm: SPSP+2 Addressing mode: Register Addressing mode Operation: SP=SP+2

ARITHMETIC INSTRUCTION
ADDITION SUBTRACTION MULTIPLICATION DIVISION

ADDITION ADD ADC INC AAA DAA

SUBTRACTION SUB SBB DEC AAS DAS NEG CMP

MULTIPILICATION MUL IMUL AAM

DIVISION DIV IDIV AAD CBW CWD

ADDITION ADD(add byte r word)


Mnemonics: ADD destination,source Flags :all flags affected Algorithm: destination<--destination +source Addressing mode: not specified Operation: destination= destination +source Ex:- ADD AX,BX

Destination n source for ADD &ADC&also for SUB ,SBB


s.no Destination source

1
2 3

register
register memory

register
memory register

4
5 6

register
memory accumulator

immediate
immediate immediate

ADC(add byte r word with carry)


Mnemonics: ADC destination,source Flags :all flags affected Algorithm: destination<--destination +source+CY Addressing mode: register immediate addresing Operation: destination= destination +source+CY EX:-ADC AX,BX

INC(Increment byte r word by 1)


Mnemonics: INC destination Flags: all flags are affected Algorithm: destinationdestination+1 Addressing mode: implied addressing mode Operation: destination=destination+1 Ex:- INC CX INC CL

AAA(ASCII adjust addition)


Mnemonics: AAA Flags: all flags are changed Algorithm: if lower nibble of AL > 9 (or) AF=1 then AL=AL+6 & AH=AH+1 AF=1,CF=1 else AF=0,CF=0 in both d case clear the higher nibble of AL Addressing mode: Implied Operation:

AL =00110101 (5) ascii BL= 00111001 (9) ascii ADD AL&BL 0011 0101 (al) 0011 1001 (bl) 0110 1110 in ascii(al) 0000 0110 0111 0100

DAA(decimal adjust addition)


Mnemonics: DAA Flags: all falgs are changed Algorithm: if lower nibble of AL > 9 (or) AF=1 then AL=AL+6 AF=1 Addressing mode: Implied Operation:

AL =00110101 (5) ascii BL= 00111001 (9) ascii ADD AL&BL 0011 0101 (al) 0011 1001 (bl) 0110 1110 in ascii(al) 0110 [1] 0000 0100

SUBTRACTION SUB(subtract byte r word)


Mnemonics: SUB destination,source Flags :all flags affected Algorithm: destination<--destination source Addressing mode: not specified Operation: destination= destination source Ex:- SUB AX,BX

SBB Subtract byte r word with borrow


Mnemonics: SBB destination,source Flags :all flags affected Algorithm: destination<--destination source-CY Addressing mode: register immediate addresing Operation: destination= destination source-CY EX:-SBB AX,BX

DEC Decrement byte r word by 1


Mnemonics: DEC destination Flags: all flags are affected Algorithm: destinationdestination-1 Addressing mode: implied addressing mode Operation: destination=destination-1 Ex:- DEC CX DEC CL

AAS(ASCII adjust for subtraction)


Mnemonics: AAS Flags: all flags are changed Algorithm: if lower nibble of AL > 9 (or) AF=1 then AL=AL-6 & AH=AH-1 AF=1,CF=1 else AF=0,CF=0 in both d case clear the higher nibble of AL Addressing mode: Implied Operation:

DAS(decimal adjust subtraction)


Mnemonics: DAS Flags: all falgs are changed Algorithm: if lower nibble of AL > 9 (or) AF=1 then AL=AL-6 AF=1 Addressing mode: Implied Operation:

NEG negative byte


Mnemonics: NEG destinaton Flags:all flags are affected Algorithm: invert all bits of operand &add 1 to inverted operand(2s complement) Addressing mode: register addressing mode Operation: 1011 1111 1010 0001 0100 0000 0101 1010 (+) 1 1111 1111 1111 1100

CMP compare byte r word


Mnemonics: CMP destination,source Flags:all the flags are changed Algorithm: destination - source Addressing mode: register addressing mode Operation:

compare

CF ZF SF 0 0 1 1 0 0 Subtraction required borrow so CF=1 No borrow Result of subtraction is zero

Source>desti 1 nation Source<desti 0 nation Source=desti 0 nation

MULTIPLICATION MUL multiply byte

Mnemonics: MUL source Flags: all the flags are change Algorithm: AX=AL*Operand (DX:AX)=AX*Operand Addressing mode: register addressing mode Operation: MUL CX

IMUL
Mnemonics: IMUL source Flags: all the flags are change Algorithm: same as previous Addressing mode: addressing mode Operation:

AAM ASCII adjust for multiplication


Mnemonics: AAM Flags: all the flags are change Algorithm: Quotient of AL/10 Remainder of AL/10 Addressing mode: implied addressing mode Operation: after multiplication u should use this

DIVISION DIV
Mnemonics: DIV source Flags: all the flags are change Algorithm: AL=AX/Operand (quotient) AH=remainder (modulus) AX=(DS:AX)/operand (quotient) DX= remaninder (mod) Addressing mode: addressing mode Operation:

IDIV
Mnemonics: IDIV Flags: all the flags are change Algorithm: same as before Addressing mode: register addressing mode Operation:

AAD ASCII adjust for division


Mnemonics: AAD Flags: all the flags are change Algorithm: AL=(AH*10)+AL Addressing mode: Implied addressing mode Operation:before division u should use this instruction

CBW convert byte to word


Mnemonics: CBW Flags: no flags affected Algorithm: if MSB bit of AL=1 then AH =FF else AH=0 Addressing mode: implied addressing mode Operation

CWD convert word to double word


Mnemonics: CWD Flags: no flags affected Algorithm: if MSB bit of AX=1 then DX =FFFF else DX=0 Addressing mode: implied addressing mode Operation

BIT MAINPULATION INSTRUCTION


Logical instruction Shift instruction Rotations instruction

Logical instruction NOT


Mnemonics: NOT destination Flags: all the flags are change Algorithm: 10 01 Addressing mode: register addressing mode NOT AX

AND
Mnemonics: AND destination, source Flags: all the flags are change Algorithm: destination= destination AND source Addressing mode: register addressing mode AND AL ,BL

OR
Mnemonics: OR destination, source Flags: all the flags are change Algorithm: destination= destination OR source Addressing mode: register addressing mode OR AL ,BL

XOR
Mnemonics: XOR destination, source Flags: all the flags are change Algorithm: destination= destination XOR source Addressing mode: register addressing mode OR AL ,BL

TEST
Mnemonics:TEST destination,source Flags: all the flags are change Algorithm: destination= destination AND source Addressing mode: immediate addressing mode TEST AL ,02 Operation 1 AND 1 =1 1AND 0 =0 0AND 1 =0 0AND 0 =0

Mnemonics: SAL/SHL destination,source Flags: all the flags are change Algorithm: Bn+1Bn Bo 0 CFB7(B15) Addressing mode: immediate addressing mode

SHIFT INSTRUCTIONS SAL/SHL shift arithmetic r logical byte

SHR shift right byte


Mnemonics: SHR destination,source Flags: all the flags are change Algorithm: opposite to the above one Addressing mode: addressing mode Operation:immediate

SAR shift arithmetic right


Mnemonics: SAR destination,count Flags: all the flags are change Algorithm: B7(B15)B7 B6(B14)B7 B0CF Addressing mode: immediate addressing mode Operation:

Mnemonics: ROL destination,source Flags: all the flags are change Algorithm: CFMSBLSB Addressing mode: addressing mode

ROTATE INSTRUCTION ROL rotate left byte

Mnemonics: ROR destination,source Flags: all the flags are change Algorithm: CF MSBLSB Addressing mode: Immediate addressing mode

ROR rotate right byte

RCL rotate through carry left


Mnemonics: RCL destination,count Flags: all the flags are change Algorithm: CFMSBLSB

Addressing mode: immediate addressing mode Operation:

RCL rotate left Through carry


Mnemonics: RCR destination ,source Flags: all the flags are change Algorithm: CFMSLSB Addressing mode: Immediate addressing mode

STRING INSTRUCTION REP


Mnemonics: REPZ/REPE Flags: all the flags are change Algorithm: while CX not equal to 0, ZF=1 repeat this CXCX-1 Addressing mode: string addressing mode Operation:

STRING INSTRUCTION REP


Mnemonics: REPNZ/REPNE Flags: all the flags are change Algorithm: while CX not equal to 0, ZF=0 repeat this CX Addressing mode: string addressing mode Operation:

MOVS
Mnemonics: MOVSB/MOVSW Flags: No flags affected Algorithm: ES:[DI]=DS:[SI] If DF=0 SI=SI+1(SI=SI+2) DI=DI+1(SI=SI+2) Addressing mode: String addressing mode Operation:

CMPS
Mnemonics: CMPSB/CPMSW Flags: all the flags are change Algorithm: DS:[SI]-ES:[DI] Addressing mode: addressing mode Operation:

SCAS scan a string


Mnemonics: SCASB/SCASW Flags: all the flags are change Algorithm: AL-ES:DI Addressing mode: String addressing mode Operation:

LODS Load string byte in AL(AX)


Mnemonics: LODSB/LODSW Flags: No flags Algorithm: ES[DI]=AL If DF is 0 then DI=DI+1(DI=DI+2) IF DF is 1 then DI=DI-1(DI=DI-2) Addressing mode: String addressing mode Operation:

STOS store string byte in AL(AX)


Mnemonics: STOSB/STOSW Flags: No flags Algorithm: AL=DS[SI] If DF is 0 then SI=SI+1(SI=SI+2) IF DF is 1 then SI=SI-1(SI=SI-2) Addressing mode: String addressing mode Operation:

PROCESS CONTROL INSTRUCTIONS


CLC clear carry CMC complement of carry STC set carry CLD clear Direction flag STD set direction flag CLI clear interrupt STI set interupt HLT halt WAIT wait fr TEST pin active ESC esc to external co processor LOCK lock bus during next instruction All are implied addressing mode